51 lines
1.7 KiB
Systemverilog
51 lines
1.7 KiB
Systemverilog
//https://stackoverflow.com/questions/17647819/looking-for-a-crc-implementation-in-systemverilog
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module top;
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function byte calc_crc(byte unsigned cmd[]);
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bit [7:0] crc, d, c;
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int i;
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crc = 0;
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for (i=0; i<cmd.size(); i++) begin
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d = cmd[i];
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c = crc;
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crc[0] = d[7] ^ d[6] ^ d[0] ^ c[0] ^ c[6] ^ c[7];
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crc[1] = d[6] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[6];
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crc[2] = d[6] ^ d[2] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[2] ^ c[6];
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crc[3] = d[7] ^ d[3] ^ d[2] ^ d[1] ^ c[1] ^ c[2] ^ c[3] ^ c[7];
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crc[4] = d[4] ^ d[3] ^ d[2] ^ c[2] ^ c[3] ^ c[4];
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crc[5] = d[5] ^ d[4] ^ d[3] ^ c[3] ^ c[4] ^ c[5];
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crc[6] = d[6] ^ d[5] ^ d[4] ^ c[4] ^ c[5] ^ c[6];
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crc[7] = d[7] ^ d[6] ^ d[5] ^ c[5] ^ c[6] ^ c[7];
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//$display("crc result: %h",crc);
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end
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return crc;
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endfunction
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localparam CRC32POL = 32'hEDB88320; /* Ethernet CRC-32 Polynom, reverse Bits */
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function automatic bit[31:0] genCRC32(input bit [7:0] databyte_stream[]);
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int unsigned i, j;
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bit [31:0] crc32_val = 32'hffffffff; // shiftregister,startvalue
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bit [7:0] data;
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//The result of the loop generate 32-Bit-mirrowed CRC
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for (i = 0; i < databyte_stream.size; i++) // Byte-Stream
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begin
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data = databyte_stream[i];
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for (j=0; j < 8; j++) // Bitwise from LSB to MSB
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begin
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if ((crc32_val[0]) != (data[0])) begin
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crc32_val = (crc32_val >> 1) ^ CRC32POL;
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end else begin
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crc32_val >>= 1;
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end
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data >>= 1;
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end
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end
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crc32_val ^= 32'hffffffff; //invert results
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return crc32_val;
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endfunction : genCRC32
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endmodule |