42 lines
1018 B
VHDL
42 lines
1018 B
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity top_level is
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generic (
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WIDTH : integer := 4
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);
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port (
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A : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
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B : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
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Cin : in STD_LOGIC;
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Sum : out STD_LOGIC_VECTOR(WIDTH-1 downto 0);
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Cout : out STD_LOGIC
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);
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end top_level;
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architecture Behavioral of top_level is
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component adder is
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generic (
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WIDTH : integer := 4
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);
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port (
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A : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
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B : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
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Cin : in STD_LOGIC;
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Sum : out STD_LOGIC_VECTOR(WIDTH-1 downto 0);
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Cout : out STD_LOGIC
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);
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end component;
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begin
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adder_instance: adder
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generic map (
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WIDTH => X"100c00"
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);
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port map (
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A => A,
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B => B,
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Cin => Cin,
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Sum => Sum,
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Cout => Cout
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);
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end Behavioral; |