69505 lines
3.4 MiB
69505 lines
3.4 MiB
<?xml version="1.0" encoding="UTF-8"?>
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<?xml-stylesheet type="text/xsl" href="template.xsl"?>
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<RootFolder label="Verilog" treetype="folder" language="Verilog">
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<Folder label="Device Primitive Instantiation" treetype="folder">
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<SubFolder label="Artix-7" treetype="folder">
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<SubFolder label="Config/BSCAN Components" treetype="folder">
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<Template label="Boundary-Scan User Instruction (BSCANE2)" treetype="template">
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// BSCANE2 : In order to incorporate this function into the design,
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// Verilog : the following instance declaration needs to be placed
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// instance : in the body of the design code. The instance name
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// declaration : (BSCANE2_inst) and/or the port declarations within the
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// code : parenthesis may be changed to properly reference and
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// : connect this function to the design. All inputs
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// : and outputs must be connected.
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// <-----Cut code below this line---->
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// BSCANE2: Boundary-Scan User Instruction
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// Artix-7
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// Xilinx HDL Language Template, version 14.7
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BSCANE2 #(
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.JTAG_CHAIN(1) // Value for USER command.
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)
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BSCANE2_inst (
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.CAPTURE(CAPTURE), // 1-bit output: CAPTURE output from TAP controller.
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.DRCK(DRCK), // 1-bit output: Gated TCK output. When SEL is asserted, DRCK toggles when CAPTURE or
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// SHIFT are asserted.
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.RESET(RESET), // 1-bit output: Reset output for TAP controller.
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.RUNTEST(RUNTEST), // 1-bit output: Output asserted when TAP controller is in Run Test/Idle state.
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.SEL(SEL), // 1-bit output: USER instruction active output.
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.SHIFT(SHIFT), // 1-bit output: SHIFT output from TAP controller.
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.TCK(TCK), // 1-bit output: Test Clock output. Fabric connection to TAP Clock pin.
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.TDI(TDI), // 1-bit output: Test Data Input (TDI) output from TAP controller.
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.TMS(TMS), // 1-bit output: Test Mode Select output. Fabric connection to TAP.
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.UPDATE(UPDATE), // 1-bit output: UPDATE output from TAP controller
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.TDO(TDO) // 1-bit input: Test Data Output (TDO) input for USER function.
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);
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// End of BSCANE2_inst instantiation
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</Template>
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<Template label="Register Capture (CAPTUREE2)" treetype="template">
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// CAPTUREE2 : In order to incorporate this function into the design,
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// Verilog : the following instance declaration needs to be placed
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// instance : in the body of the design code. The instance name
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// declaration : (CAPTUREE2_inst) and/or the port declarations within the
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// code : parenthesis may be changed to properly reference and
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// : connect this function to the design. All inputs
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// : and outputs must be connected.
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// <-----Cut code below this line---->
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// CAPTUREE2: Register Capture
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// Artix-7
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// Xilinx HDL Language Template, version 14.7
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CAPTUREE2 #(
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.ONESHOT("TRUE") // Specifies the procedure for performing single readback per CAP trigger.
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)
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CAPTUREE2_inst (
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.CAP(CAP), // 1-bit input: Capture Input
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.CLK(CLK) // 1-bit input: Clock Input
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);
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// End of CAPTUREE2_inst instantiation
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</Template>
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<Template label="Device DNA Access Port (DNA_PORT)" treetype="template">
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// DNA_PORT : In order to incorporate this function into the design,
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// Verilog : the following instance declaration needs to be placed
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// instance : in the body of the design code. The instance name
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// declaration : (DNA_PORT_inst) and/or the port declarations within the
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// code : parenthesis may be changed to properly reference and
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// : connect this function to the design. All inputs
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// : and outputs must be connected.
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// <-----Cut code below this line---->
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// DNA_PORT: Device DNA Access Port
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// Artix-7
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// Xilinx HDL Language Template, version 14.7
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DNA_PORT #(
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.SIM_DNA_VALUE(57'h000000000000000) // Specifies a sample 57-bit DNA value for simulation
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)
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DNA_PORT_inst (
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.DOUT(DOUT), // 1-bit output: DNA output data.
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.CLK(CLK), // 1-bit input: Clock input.
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.DIN(DIN), // 1-bit input: User data input pin.
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.READ(READ), // 1-bit input: Active high load DNA, active low read input.
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.SHIFT(SHIFT) // 1-bit input: Active high shift enable input.
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);
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// End of DNA_PORT_inst instantiation
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</Template>
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<Template label="32-bit non-volatile design ID (EFUSE_USR)" treetype="template">
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// EFUSE_USR : In order to incorporate this function into the design,
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// Verilog : the following instance declaration needs to be placed
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// instance : in the body of the design code. The instance name
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// declaration : (EFUSE_USR_inst) and/or the port declarations within the
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// code : parenthesis may be changed to properly reference and
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// : connect this function to the design. All inputs
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// : and outputs must be connected.
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// <-----Cut code below this line---->
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// EFUSE_USR: 32-bit non-volatile design ID
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// Artix-7
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// Xilinx HDL Language Template, version 14.7
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EFUSE_USR #(
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.SIM_EFUSE_VALUE(32'h00000000) // Value of the 32-bit non-volatile value used in simulation
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)
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EFUSE_USR_inst (
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.EFUSEUSR(EFUSEUSR) // 32-bit output: User eFUSE register value output
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);
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// End of EFUSE_USR_inst instantiation
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</Template>
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<Template label="Configuration Frame Error Correction (FRAME_ECCE2)" treetype="template">
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// FRAME_ECCE2 : In order to incorporate this function into the design,
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// Verilog : the following instance declaration needs to be placed
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// instance : in the body of the design code. The instance name
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// declaration : (FRAME_ECCE2_inst) and/or the port declarations within the
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// code : parenthesis may be changed to properly reference and
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// : connect this function to the design. All inputs
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// : and outputs must be connected.
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// <-----Cut code below this line---->
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// FRAME_ECCE2: Configuration Frame Error Correction
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// Artix-7
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// Xilinx HDL Language Template, version 14.7
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FRAME_ECCE2 #(
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.FARSRC("EFAR"), // Determines if the output of FAR[25:0] configuration register points to
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// the FAR or EFAR. Sets configuration option register bit CTL0[7].
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.FRAME_RBT_IN_FILENAME("None") // This file is output by the ICAP_E2 model and it contains Frame Data
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// information for the Raw Bitstream (RBT) file. The FRAME_ECCE2 model
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// will parse this file, calculate ECC and output any error conditions.
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)
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FRAME_ECCE2_inst (
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.CRCERROR(CRCERROR), // 1-bit output: Output indicating a CRC error.
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.ECCERROR(ECCERROR), // 1-bit output: Output indicating an ECC error.
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.ECCERRORSINGLE(ECCERRORSINGLE), // 1-bit output: Output Indicating single-bit Frame ECC error detected.
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.FAR(FAR), // 26-bit output: Frame Address Register Value output.
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.SYNBIT(SYNBIT), // 5-bit output: Output bit address of error.
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.SYNDROME(SYNDROME), // 13-bit output: Output location of erroneous bit.
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.SYNDROMEVALID(SYNDROMEVALID), // 1-bit output: Frame ECC output indicating the SYNDROME output is
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// valid.
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.SYNWORD(SYNWORD) // 7-bit output: Word output in the frame where an ECC error has been
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// detected.
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);
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// End of FRAME_ECCE2_inst instantiation
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</Template>
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<Template label="Internal Configuration Access Port (ICAPE2)" treetype="template">
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// ICAPE2 : In order to incorporate this function into the design,
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// Verilog : the following instance declaration needs to be placed
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// instance : in the body of the design code. The instance name
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// declaration : (ICAPE2_inst) and/or the port declarations within the
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// code : parenthesis may be changed to properly reference and
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// : connect this function to the design. All inputs
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// : and outputs must be connected.
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// <-----Cut code below this line---->
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// ICAPE2: Internal Configuration Access Port
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// Artix-7
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// Xilinx HDL Language Template, version 14.7
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ICAPE2 #(
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.DEVICE_ID(0'h3651093), // Specifies the pre-programmed Device ID value to be used for simulation
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// purposes.
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.ICAP_WIDTH("X32"), // Specifies the input and output data width.
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.SIM_CFG_FILE_NAME("None") // Specifies the Raw Bitstream (RBT) file to be parsed by the simulation
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// model.
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)
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ICAPE2_inst (
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.O(O), // 32-bit output: Configuration data output bus
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.CLK(CLK), // 1-bit input: Clock Input
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.CSIB(CSIB), // 1-bit input: Active-Low ICAP Enable
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.I(I), // 32-bit input: Configuration data input bus
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.RDWRB(RDWRB) // 1-bit input: Read/Write Select input
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);
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// End of ICAPE2_inst instantiation
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</Template>
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<Template label="STARTUP Block (STARTUPE2)" treetype="template">
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// STARTUPE2 : In order to incorporate this function into the design,
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// Verilog : the following instance declaration needs to be placed
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// instance : in the body of the design code. The instance name
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// declaration : (STARTUPE2_inst) and/or the port declarations within the
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// code : parenthesis may be changed to properly reference and
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// : connect this function to the design. All inputs
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// : and outputs must be connected.
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// <-----Cut code below this line---->
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// STARTUPE2: STARTUP Block
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// Artix-7
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// Xilinx HDL Language Template, version 14.7
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STARTUPE2 #(
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.PROG_USR("FALSE"), // Activate program event security feature. Requires encrypted bitstreams.
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.SIM_CCLK_FREQ(0.0) // Set the Configuration Clock Frequency(ns) for simulation.
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)
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STARTUPE2_inst (
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.CFGCLK(CFGCLK), // 1-bit output: Configuration main clock output
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.CFGMCLK(CFGMCLK), // 1-bit output: Configuration internal oscillator clock output
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.EOS(EOS), // 1-bit output: Active high output signal indicating the End Of Startup.
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.PREQ(PREQ), // 1-bit output: PROGRAM request to fabric output
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.CLK(CLK), // 1-bit input: User start-up clock input
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.GSR(GSR), // 1-bit input: Global Set/Reset input (GSR cannot be used for the port name)
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.GTS(GTS), // 1-bit input: Global 3-state input (GTS cannot be used for the port name)
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.KEYCLEARB(KEYCLEARB), // 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM)
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.PACK(PACK), // 1-bit input: PROGRAM acknowledge input
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.USRCCLKO(USRCCLKO), // 1-bit input: User CCLK input
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.USRCCLKTS(USRCCLKTS), // 1-bit input: User CCLK 3-state enable input
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.USRDONEO(USRDONEO), // 1-bit input: User DONE pin output control
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.USRDONETS(USRDONETS) // 1-bit input: User DONE 3-state enable output
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);
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// End of STARTUPE2_inst instantiation
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</Template>
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<Template label="Configuration Data Access (USR_ACCESSE2)" treetype="template">
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// USR_ACCESSE2 : In order to incorporate this function into the design,
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// Verilog : the following instance declaration needs to be placed
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// instance : in the body of the design code. The instance name
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// declaration : (USR_ACCESSE2_inst) and/or the port declarations within the
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// code : parenthesis may be changed to properly reference and
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// : connect this function to the design. All inputs
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// : and outputs must be connected.
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// <-----Cut code below this line---->
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// USR_ACCESSE2: Configuration Data Access
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// Artix-7
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// Xilinx HDL Language Template, version 14.7
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USR_ACCESSE2 USR_ACCESSE2_inst (
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.CFGCLK(CFGCLK), // 1-bit output: Configuration Clock output
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.DATA(DATA), // 32-bit output: Configuration Data output
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.DATAVALID(DATAVALID) // 1-bit output: Active high data valid output
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);
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// End of USR_ACCESSE2_inst instantiation
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</Template>
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</SubFolder>
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<SubFolder label="Clock Components" treetype="folder">
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<SubFolder label="Clock Buffers" treetype="folder">
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<Template label="Global Clock Buffer with Clock Enable and Output State 1 (BUFGCE_1)" treetype="template">
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// BUFGCE_1 : In order to incorporate this function into the design,
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// Verilog : the following instance declaration needs to be placed
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// instance : in the body of the design code. The instance name
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// declaration : (BUFGCE_1_inst) and/or the port declarations within the
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// code : parenthesis may be changed to properly reference and
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// : connect this function to the design. All inputs
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// : and outputs must be connected.
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// <-----Cut code below this line---->
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// BUFGCE_1: Global Clock Buffer with Clock Enable and Output State 1
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// Artix-7
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// Xilinx HDL Language Template, version 14.7
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BUFGCE_1 BUFGCE_1_inst (
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.O(O), // 1-bit output: Clock output
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.CE(CE), // 1-bit input: Clock enable input for I0
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.I(I) // 1-bit input: Primary clock
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);
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// End of BUFGCE_1_inst instantiation
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</Template>
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<Template label="Global Clock Buffer with Clock Enable (BUFGCE)" treetype="template">
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// BUFGCE : In order to incorporate this function into the design,
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// Verilog : the following instance declaration needs to be placed
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// instance : in the body of the design code. The instance name
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// declaration : (BUFGCE_inst) and/or the port declarations within the
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// code : parenthesis may be changed to properly reference and
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// : connect this function to the design. All inputs
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// : and outputs must be connected.
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// <-----Cut code below this line---->
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// BUFGCE: Global Clock Buffer with Clock Enable
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// Artix-7
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// Xilinx HDL Language Template, version 14.7
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BUFGCE BUFGCE_inst (
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.O(O), // 1-bit output: Clock output
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.CE(CE), // 1-bit input: Clock enable input for I0
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.I(I) // 1-bit input: Primary clock
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);
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// End of BUFGCE_inst instantiation
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</Template>
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<Template label="Global Clock Simple Buffer (BUFG)" treetype="template">
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// BUFG : In order to incorporate this function into the design,
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// Verilog : the following instance declaration needs to be placed
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// instance : in the body of the design code. The instance name
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// declaration : (BUFG_inst) and/or the port declarations within the
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// code : parenthesis may be changed to properly reference and
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// : connect this function to the design. All inputs
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// : and outputs must be connected.
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// <-----Cut code below this line---->
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// BUFG: Global Clock Simple Buffer
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// Artix-7
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// Xilinx HDL Language Template, version 14.7
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BUFG BUFG_inst (
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.O(O), // 1-bit output: Clock output
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.I(I) // 1-bit input: Clock input
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);
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// End of BUFG_inst instantiation
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</Template>
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<Template label="HROW Clock Buffer with Clock Enable (BUFHCE)" treetype="template">
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// BUFHCE : In order to incorporate this function into the design,
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// Verilog : the following instance declaration needs to be placed
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// instance : in the body of the design code. The instance name
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// declaration : (BUFHCE_inst) and/or the port declarations within the
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// code : parenthesis may be changed to properly reference and
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// : connect this function to the design. All inputs
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// : and outputs must be connected.
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// <-----Cut code below this line---->
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// BUFHCE: HROW Clock Buffer for a Single Clocking Region with Clock Enable
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// Artix-7
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// Xilinx HDL Language Template, version 14.7
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BUFHCE #(
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.CE_TYPE("SYNC"), // "SYNC" (glitchless switching) or "ASYNC" (immediate switch)
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.INIT_OUT(0) // Initial output value (0-1)
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)
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BUFHCE_inst (
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.O(O), // 1-bit output: Clock output
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.CE(CE), // 1-bit input: Active high enable
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.I(I) // 1-bit input: Clock input
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);
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// End of BUFHCE_inst instantiation
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</Template>
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<Template label="HROW Clock Buffer (BUFH)" treetype="template">
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// BUFH : In order to incorporate this function into the design,
|
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// Verilog : the following instance declaration needs to be placed
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// instance : in the body of the design code. The instance name
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// declaration : (BUFH_inst) and/or the port declarations within the
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// code : parenthesis may be changed to properly reference and
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// : connect this function to the design. All inputs
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// : and outputs must be connected.
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// <-----Cut code below this line---->
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// BUFH: HROW Clock Buffer for a Single Clocking Region
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// Artix-7
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// Xilinx HDL Language Template, version 14.7
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BUFH BUFH_inst (
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.O(O), // 1-bit output: Clock output
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.I(I) // 1-bit input: Clock input
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);
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// End of BUFH_inst instantiation
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</Template>
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<Template label="I/O Clock Buffer (BUFIO)" treetype="template">
|
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// BUFIO : In order to incorporate this function into the design,
|
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// Verilog : the following instance declaration needs to be placed
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// instance : in the body of the design code. The instance name
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// declaration : (BUFIO_inst) and/or the port declarations within the
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|
// code : parenthesis may be changed to properly reference and
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|
// : connect this function to the design. All inputs
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// : and outputs must be connected.
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// <-----Cut code below this line---->
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// BUFIO: Local Clock Buffer for I/O
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// Artix-7
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// Xilinx HDL Language Template, version 14.7
|
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BUFIO BUFIO_inst (
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.O(O), // 1-bit output: Clock output (connect to I/O clock loads).
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.I(I) // 1-bit input: Clock input (connect to an IBUF or BUFMR).
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);
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// End of BUFIO_inst instantiation
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</Template>
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<Template label="Multi-Region Clock Buffer with Clock Enable (BUFMRCE)" treetype="template">
|
|
// BUFMRCE : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
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|
// declaration : (BUFMRCE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
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// : and outputs must be connected.
|
|
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|
// <-----Cut code below this line---->
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|
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// BUFMRCE: Multi-Region Clock Buffer with Clock Enable
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// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
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BUFMRCE #(
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.CE_TYPE("SYNC"), // SYNC, ASYNC
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.INIT_OUT(0) // Initial output and stopped polarity, (0-1)
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)
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BUFMRCE_inst (
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.O(O), // 1-bit output: Clock output (connect to BUFIOs/BUFRs)
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.CE(CE), // 1-bit input: Active high buffer enable
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.I(I) // 1-bit input: Clock input (Connect to IBUF)
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);
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// End of BUFMRCE_inst instantiation
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</Template>
|
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<Template label="Multi-Region Clock Buffer (BUFMR)" treetype="template">
|
|
// BUFMR : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFMR_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
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|
// : connect this function to the design. All inputs
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// : and outputs must be connected.
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// <-----Cut code below this line---->
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// BUFMR: Multi-Region Clock Buffer
|
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// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
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BUFMR BUFMR_inst (
|
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.O(O), // 1-bit output: Clock output (connect to BUFIOs/BUFRs)
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.I(I) // 1-bit input: Clock input (Connect to IBUF)
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);
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// End of BUFMR_inst instantiation
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|
</Template>
|
|
<Template label="Regional Clock Buffer (BUFR)" treetype="template">
|
|
// BUFR : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFR_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFR: Regional Clock Buffer for I/O and Logic Resources within a Clock Region
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFR #(
|
|
.BUFR_DIVIDE("BYPASS"), // Values: "BYPASS, 1, 2, 3, 4, 5, 6, 7, 8"
|
|
.SIM_DEVICE(""7SERIES"") // Must be set to "7SERIES"
|
|
)
|
|
BUFR_inst (
|
|
.O(O), // 1-bit output: Clock output port
|
|
.CE(CE), // 1-bit input: Active high, clock enable (Divided modes only)
|
|
.CLR(CLR), // 1-bit input: Active high, asynchronous clear (Divided modes only)
|
|
.I(I) // 1-bit input: Clock buffer input driven by an IBUF, MMCM or local interconnect
|
|
);
|
|
|
|
// End of BUFR_inst instantiation
|
|
</Template>
|
|
<Template label="Single-ended Input Global Clock Buffer (IBUFG)" treetype="template">
|
|
// IBUFG : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFG_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFG: Global Clock Buffer (sourced by an external pin)
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFG #(
|
|
.IBUF_LOW_PWR("TRUE"), // Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
) IBUFG_inst (
|
|
.O(O), // Clock buffer output
|
|
.I(I) // Clock buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUFG_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Input Global Clock Buffer (IBUFGDS)" treetype="template">
|
|
// IBUFGDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFGDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFGDS: Differential Global Clock Buffer (sourced by an external pin)
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFGDS #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination
|
|
.IBUF_LOW_PWR("TRUE"), // Low power="TRUE", Highest performance="FALSE"
|
|
.IOSTANDARD("DEFAULT") // Specifies the I/O standard for this buffer
|
|
) IBUFGDS_inst (
|
|
.O(O), // Clock buffer output
|
|
.I(I), // Diff_p clock buffer input
|
|
.IB(IB) // Diff_n clock buffer input
|
|
);
|
|
|
|
// End of IBUFGDS_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Global Clock Buffer with Differential Output (IBUFGDS_DIFF_OUT)" treetype="template">
|
|
// IBUFGDS_DIFF_OUT : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFGDS_DIFF_OUT_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFGDS_DIFF_OUT: Differential Global Clock Buffer with Differential Output
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFGDS_DIFF_OUT #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination, "TRUE"/"FALSE"
|
|
.IBUF_LOW_PWR("TRUE"), // Low power="TRUE", Highest performance="FALSE"
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
) IBUFGDS_DIFF_OUT_inst (
|
|
.O(O), // Buffer diff_p output
|
|
.OB(OB), // Buffer diff_n output
|
|
.I(I), // Diff_p buffer input (connect directly to top-level port)
|
|
.IB(IB) // Diff_n buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUFGDS_DIFF_OUT_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Clock MUXes" treetype="folder">
|
|
<Template label="Global Clock Control Buffer (BUFGCTRL)" treetype="template">
|
|
// BUFGCTRL : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFGCTRL_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFGCTRL: Global Clock Control Buffer
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFGCTRL #(
|
|
.INIT_OUT(0), // Initial value of BUFGCTRL output ($VALUES;)
|
|
.PRESELECT_I0("FALSE"), // BUFGCTRL output uses I0 input ($VALUES;)
|
|
.PRESELECT_I1("FALSE") // BUFGCTRL output uses I1 input ($VALUES;)
|
|
)
|
|
BUFGCTRL_inst (
|
|
.O(O), // 1-bit output: Clock output
|
|
.CE0(CE0), // 1-bit input: Clock enable input for I0
|
|
.CE1(CE1), // 1-bit input: Clock enable input for I1
|
|
.I0(I0), // 1-bit input: Primary clock
|
|
.I1(I1), // 1-bit input: Secondary clock
|
|
.IGNORE0(IGNORE0), // 1-bit input: Clock ignore input for I0
|
|
.IGNORE1(IGNORE1), // 1-bit input: Clock ignore input for I1
|
|
.S0(S0), // 1-bit input: Clock select for I0
|
|
.S1(S1) // 1-bit input: Clock select for I1
|
|
);
|
|
|
|
// End of BUFGCTRL_inst instantiation
|
|
</Template>
|
|
<Template label="Global Clock Mux Buffer with Output State 1 (BUFGMUX_1)" treetype="template">
|
|
// BUFGMUX_1 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFGMUX_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFGMUX_1: Global Clock Mux Buffer with Output State 1
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFGMUX_1 #(
|
|
)
|
|
BUFGMUX_1_inst (
|
|
.O(O), // 1-bit output: Clock output
|
|
.I0(I0), // 1-bit input: Clock input (S=0)
|
|
.I1(I1), // 1-bit input: Clock input (S=1)
|
|
.S(S) // 1-bit input: Clock select
|
|
);
|
|
|
|
// End of BUFGMUX_1_inst instantiation
|
|
</Template>
|
|
<Template label="2-to-1 Global Clock MUX Buffer (BUFGMUX_CTRL)" treetype="template">
|
|
// BUFGMUX_CTRL : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFGMUX_CTRL_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFGMUX_CTRL: 2-to-1 Global Clock MUX Buffer
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFGMUX_CTRL BUFGMUX_CTRL_inst (
|
|
.O(O), // 1-bit output: Clock output
|
|
.I0(I0), // 1-bit input: Clock input (S=0)
|
|
.I1(I1), // 1-bit input: Clock input (S=1)
|
|
.S(S) // 1-bit input: Clock select
|
|
);
|
|
|
|
// End of BUFGMUX_CTRL_inst instantiation
|
|
</Template>
|
|
<Template label="Global Clock Mux Buffer (BUFGMUX)" treetype="template">
|
|
// BUFGMUX : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFGMUX_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFGMUX: Global Clock Mux Buffer
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFGMUX #(
|
|
)
|
|
BUFGMUX_inst (
|
|
.O(O), // 1-bit output: Clock output
|
|
.I0(I0), // 1-bit input: Clock input (S=0)
|
|
.I1(I1), // 1-bit input: Clock input (S=1)
|
|
.S(S) // 1-bit input: Clock select
|
|
);
|
|
|
|
// End of BUFGMUX_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="MMCM / PLL" treetype="folder">
|
|
<Template label="Advanced Mixed Mode Clock Manager (MMCME2_ADV)" treetype="template">
|
|
// MMCME2_ADV : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MMCME2_ADV_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MMCME2_ADV: Advanced Mixed Mode Clock Manager
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MMCME2_ADV #(
|
|
.BANDWIDTH("OPTIMIZED"), // Jitter programming (OPTIMIZED, HIGH, LOW)
|
|
.CLKFBOUT_MULT_F(5.0), // Multiply value for all CLKOUT (2.000-64.000).
|
|
.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB (-360.000-360.000).
|
|
// CLKIN_PERIOD: Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
|
|
.CLKIN1_PERIOD(0.0),
|
|
.CLKIN2_PERIOD(0.0),
|
|
// CLKOUT0_DIVIDE - CLKOUT6_DIVIDE: Divide amount for CLKOUT (1-128)
|
|
.CLKOUT1_DIVIDE(1),
|
|
.CLKOUT2_DIVIDE(1),
|
|
.CLKOUT3_DIVIDE(1),
|
|
.CLKOUT4_DIVIDE(1),
|
|
.CLKOUT5_DIVIDE(1),
|
|
.CLKOUT6_DIVIDE(1),
|
|
.CLKOUT0_DIVIDE_F(1.0), // Divide amount for CLKOUT0 (1.000-128.000).
|
|
// CLKOUT0_DUTY_CYCLE - CLKOUT6_DUTY_CYCLE: Duty cycle for CLKOUT outputs (0.01-0.99).
|
|
.CLKOUT0_DUTY_CYCLE(0.5),
|
|
.CLKOUT1_DUTY_CYCLE(0.5),
|
|
.CLKOUT2_DUTY_CYCLE(0.5),
|
|
.CLKOUT3_DUTY_CYCLE(0.5),
|
|
.CLKOUT4_DUTY_CYCLE(0.5),
|
|
.CLKOUT5_DUTY_CYCLE(0.5),
|
|
.CLKOUT6_DUTY_CYCLE(0.5),
|
|
// CLKOUT0_PHASE - CLKOUT6_PHASE: Phase offset for CLKOUT outputs (-360.000-360.000).
|
|
.CLKOUT0_PHASE(0.0),
|
|
.CLKOUT1_PHASE(0.0),
|
|
.CLKOUT2_PHASE(0.0),
|
|
.CLKOUT3_PHASE(0.0),
|
|
.CLKOUT4_PHASE(0.0),
|
|
.CLKOUT5_PHASE(0.0),
|
|
.CLKOUT6_PHASE(0.0),
|
|
.CLKOUT4_CASCADE("FALSE"), // Cascade CLKOUT4 counter with CLKOUT6 (FALSE, TRUE)
|
|
.COMPENSATION("ZHOLD"), // ZHOLD, BUF_IN, EXTERNAL, INTERNAL
|
|
.DIVCLK_DIVIDE(1), // Master division value (1-106)
|
|
// REF_JITTER: Reference input jitter in UI (0.000-0.999).
|
|
.REF_JITTER1(0.0),
|
|
.REF_JITTER2(0.0),
|
|
.STARTUP_WAIT("FALSE"), // Delays DONE until MMCM is locked (FALSE, TRUE)
|
|
// Spread Spectrum: Spread Spectrum Attributes
|
|
.SS_EN("FALSE"), // Enables spread spectrum (FALSE, TRUE)
|
|
.SS_MODE("CENTER_HIGH"), // CENTER_HIGH, CENTER_LOW, DOWN_HIGH, DOWN_LOW
|
|
.SS_MOD_PERIOD(10000), // Spread spectrum modulation period (ns) (VALUES)
|
|
// USE_FINE_PS: Fine phase shift enable (TRUE/FALSE)
|
|
.CLKFBOUT_USE_FINE_PS("FALSE"),
|
|
.CLKOUT0_USE_FINE_PS("FALSE"),
|
|
.CLKOUT1_USE_FINE_PS("FALSE"),
|
|
.CLKOUT2_USE_FINE_PS("FALSE"),
|
|
.CLKOUT3_USE_FINE_PS("FALSE"),
|
|
.CLKOUT4_USE_FINE_PS("FALSE"),
|
|
.CLKOUT5_USE_FINE_PS("FALSE"),
|
|
.CLKOUT6_USE_FINE_PS("FALSE")
|
|
)
|
|
MMCME2_ADV_inst (
|
|
// Clock Outputs: 1-bit (each) output: User configurable clock outputs
|
|
.CLKOUT0(CLKOUT0), // 1-bit output: CLKOUT0
|
|
.CLKOUT0B(CLKOUT0B), // 1-bit output: Inverted CLKOUT0
|
|
.CLKOUT1(CLKOUT1), // 1-bit output: CLKOUT1
|
|
.CLKOUT1B(CLKOUT1B), // 1-bit output: Inverted CLKOUT1
|
|
.CLKOUT2(CLKOUT2), // 1-bit output: CLKOUT2
|
|
.CLKOUT2B(CLKOUT2B), // 1-bit output: Inverted CLKOUT2
|
|
.CLKOUT3(CLKOUT3), // 1-bit output: CLKOUT3
|
|
.CLKOUT3B(CLKOUT3B), // 1-bit output: Inverted CLKOUT3
|
|
.CLKOUT4(CLKOUT4), // 1-bit output: CLKOUT4
|
|
.CLKOUT5(CLKOUT5), // 1-bit output: CLKOUT5
|
|
.CLKOUT6(CLKOUT6), // 1-bit output: CLKOUT6
|
|
// DRP Ports: 16-bit (each) output: Dynamic reconfiguration ports
|
|
.DO(DO), // 16-bit output: DRP data
|
|
.DRDY(DRDY), // 1-bit output: DRP ready
|
|
// Dynamic Phase Shift Ports: 1-bit (each) output: Ports used for dynamic phase shifting of the outputs
|
|
.PSDONE(PSDONE), // 1-bit output: Phase shift done
|
|
// Feedback Clocks: 1-bit (each) output: Clock feedback ports
|
|
.CLKFBOUT(CLKFBOUT), // 1-bit output: Feedback clock
|
|
.CLKFBOUTB(CLKFBOUTB), // 1-bit output: Inverted CLKFBOUT
|
|
// Status Ports: 1-bit (each) output: MMCM status ports
|
|
.CLKFBSTOPPED(CLKFBSTOPPED), // 1-bit output: Feedback clock stopped
|
|
.CLKINSTOPPED(CLKINSTOPPED), // 1-bit output: Input clock stopped
|
|
.LOCKED(LOCKED), // 1-bit output: LOCK
|
|
// Clock Inputs: 1-bit (each) input: Clock inputs
|
|
.CLKIN1(CLKIN1), // 1-bit input: Primary clock
|
|
.CLKIN2(CLKIN2), // 1-bit input: Secondary clock
|
|
// Control Ports: 1-bit (each) input: MMCM control ports
|
|
.CLKINSEL(CLKINSEL), // 1-bit input: Clock select, High=CLKIN1 Low=CLKIN2
|
|
.PWRDWN(PWRDWN), // 1-bit input: Power-down
|
|
.RST(RST), // 1-bit input: Reset
|
|
// DRP Ports: 7-bit (each) input: Dynamic reconfiguration ports
|
|
.DADDR(DADDR), // 7-bit input: DRP address
|
|
.DCLK(DCLK), // 1-bit input: DRP clock
|
|
.DEN(DEN), // 1-bit input: DRP enable
|
|
.DI(DI), // 16-bit input: DRP data
|
|
.DWE(DWE), // 1-bit input: DRP write enable
|
|
// Dynamic Phase Shift Ports: 1-bit (each) input: Ports used for dynamic phase shifting of the outputs
|
|
.PSCLK(PSCLK), // 1-bit input: Phase shift clock
|
|
.PSEN(PSEN), // 1-bit input: Phase shift enable
|
|
.PSINCDEC(PSINCDEC), // 1-bit input: Phase shift increment/decrement
|
|
// Feedback Clocks: 1-bit (each) input: Clock feedback ports
|
|
.CLKFBIN(CLKFBIN) // 1-bit input: Feedback clock
|
|
);
|
|
|
|
// End of MMCME2_ADV_inst instantiation
|
|
</Template>
|
|
<Template label="Base Mixed Mode Clock Manager (MMCME2_BASE)" treetype="template">
|
|
// MMCME2_BASE : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MMCME2_BASE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MMCME2_BASE: Base Mixed Mode Clock Manager
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MMCME2_BASE #(
|
|
.BANDWIDTH("OPTIMIZED"), // Jitter programming (OPTIMIZED, HIGH, LOW)
|
|
.CLKFBOUT_MULT_F(5.0), // Multiply value for all CLKOUT (2.000-64.000).
|
|
.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB (-360.000-360.000).
|
|
.CLKIN1_PERIOD(0.0), // Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
|
|
// CLKOUT0_DIVIDE - CLKOUT6_DIVIDE: Divide amount for each CLKOUT (1-128)
|
|
.CLKOUT1_DIVIDE(1),
|
|
.CLKOUT2_DIVIDE(1),
|
|
.CLKOUT3_DIVIDE(1),
|
|
.CLKOUT4_DIVIDE(1),
|
|
.CLKOUT5_DIVIDE(1),
|
|
.CLKOUT6_DIVIDE(1),
|
|
.CLKOUT0_DIVIDE_F(1.0), // Divide amount for CLKOUT0 (1.000-128.000).
|
|
// CLKOUT0_DUTY_CYCLE - CLKOUT6_DUTY_CYCLE: Duty cycle for each CLKOUT (0.01-0.99).
|
|
.CLKOUT0_DUTY_CYCLE(0.5),
|
|
.CLKOUT1_DUTY_CYCLE(0.5),
|
|
.CLKOUT2_DUTY_CYCLE(0.5),
|
|
.CLKOUT3_DUTY_CYCLE(0.5),
|
|
.CLKOUT4_DUTY_CYCLE(0.5),
|
|
.CLKOUT5_DUTY_CYCLE(0.5),
|
|
.CLKOUT6_DUTY_CYCLE(0.5),
|
|
// CLKOUT0_PHASE - CLKOUT6_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
|
|
.CLKOUT0_PHASE(0.0),
|
|
.CLKOUT1_PHASE(0.0),
|
|
.CLKOUT2_PHASE(0.0),
|
|
.CLKOUT3_PHASE(0.0),
|
|
.CLKOUT4_PHASE(0.0),
|
|
.CLKOUT5_PHASE(0.0),
|
|
.CLKOUT6_PHASE(0.0),
|
|
.CLKOUT4_CASCADE("FALSE"), // Cascade CLKOUT4 counter with CLKOUT6 (FALSE, TRUE)
|
|
.DIVCLK_DIVIDE(1), // Master division value (1-106)
|
|
.REF_JITTER1(0.0), // Reference input jitter in UI (0.000-0.999).
|
|
.STARTUP_WAIT("FALSE") // Delays DONE until MMCM is locked (FALSE, TRUE)
|
|
)
|
|
MMCME2_BASE_inst (
|
|
// Clock Outputs: 1-bit (each) output: User configurable clock outputs
|
|
.CLKOUT0(CLKOUT0), // 1-bit output: CLKOUT0
|
|
.CLKOUT0B(CLKOUT0B), // 1-bit output: Inverted CLKOUT0
|
|
.CLKOUT1(CLKOUT1), // 1-bit output: CLKOUT1
|
|
.CLKOUT1B(CLKOUT1B), // 1-bit output: Inverted CLKOUT1
|
|
.CLKOUT2(CLKOUT2), // 1-bit output: CLKOUT2
|
|
.CLKOUT2B(CLKOUT2B), // 1-bit output: Inverted CLKOUT2
|
|
.CLKOUT3(CLKOUT3), // 1-bit output: CLKOUT3
|
|
.CLKOUT3B(CLKOUT3B), // 1-bit output: Inverted CLKOUT3
|
|
.CLKOUT4(CLKOUT4), // 1-bit output: CLKOUT4
|
|
.CLKOUT5(CLKOUT5), // 1-bit output: CLKOUT5
|
|
.CLKOUT6(CLKOUT6), // 1-bit output: CLKOUT6
|
|
// Feedback Clocks: 1-bit (each) output: Clock feedback ports
|
|
.CLKFBOUT(CLKFBOUT), // 1-bit output: Feedback clock
|
|
.CLKFBOUTB(CLKFBOUTB), // 1-bit output: Inverted CLKFBOUT
|
|
// Status Ports: 1-bit (each) output: MMCM status ports
|
|
.LOCKED(LOCKED), // 1-bit output: LOCK
|
|
// Clock Inputs: 1-bit (each) input: Clock input
|
|
.CLKIN1(CLKIN1), // 1-bit input: Clock
|
|
// Control Ports: 1-bit (each) input: MMCM control ports
|
|
.PWRDWN(PWRDWN), // 1-bit input: Power-down
|
|
.RST(RST), // 1-bit input: Reset
|
|
// Feedback Clocks: 1-bit (each) input: Clock feedback ports
|
|
.CLKFBIN(CLKFBIN) // 1-bit input: Feedback clock
|
|
);
|
|
|
|
// End of MMCME2_BASE_inst instantiation
|
|
</Template>
|
|
<Template label="Advanced Phase Locked Loop (PLLE2_ADV)" treetype="template">
|
|
// PLLE2_ADV : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (PLLE2_ADV_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// PLLE2_ADV: Advanced Phase Locked Loop (PLL)
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
PLLE2_ADV #(
|
|
.BANDWIDTH("OPTIMIZED"), // OPTIMIZED, HIGH, LOW
|
|
.CLKFBOUT_MULT(5), // Multiply value for all CLKOUT, (2-64)
|
|
.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB, (-360.000-360.000).
|
|
// CLKIN_PERIOD: Input clock period in nS to ps resolution (i.e. 33.333 is 30 MHz).
|
|
.CLKIN1_PERIOD(0.0),
|
|
.CLKIN2_PERIOD(0.0),
|
|
// CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for CLKOUT (1-128)
|
|
.CLKOUT0_DIVIDE(1),
|
|
.CLKOUT1_DIVIDE(1),
|
|
.CLKOUT2_DIVIDE(1),
|
|
.CLKOUT3_DIVIDE(1),
|
|
.CLKOUT4_DIVIDE(1),
|
|
.CLKOUT5_DIVIDE(1),
|
|
// CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for CLKOUT outputs (0.001-0.999).
|
|
.CLKOUT0_DUTY_CYCLE(0.5),
|
|
.CLKOUT1_DUTY_CYCLE(0.5),
|
|
.CLKOUT2_DUTY_CYCLE(0.5),
|
|
.CLKOUT3_DUTY_CYCLE(0.5),
|
|
.CLKOUT4_DUTY_CYCLE(0.5),
|
|
.CLKOUT5_DUTY_CYCLE(0.5),
|
|
// CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for CLKOUT outputs (-360.000-360.000).
|
|
.CLKOUT0_PHASE(0.0),
|
|
.CLKOUT1_PHASE(0.0),
|
|
.CLKOUT2_PHASE(0.0),
|
|
.CLKOUT3_PHASE(0.0),
|
|
.CLKOUT4_PHASE(0.0),
|
|
.CLKOUT5_PHASE(0.0),
|
|
.COMPENSATION("ZHOLD"), // ZHOLD, BUF_IN, EXTERNAL, INTERNAL
|
|
.DIVCLK_DIVIDE(1), // Master division value (1-56)
|
|
// REF_JITTER: Reference input jitter in UI (0.000-0.999).
|
|
.REF_JITTER1(0.0),
|
|
.REF_JITTER2(0.0),
|
|
.STARTUP_WAIT("FALSE") // Delay DONE until PLL Locks, ("TRUE"/"FALSE")
|
|
)
|
|
PLLE2_ADV_inst (
|
|
// Clock Outputs: 1-bit (each) output: User configurable clock outputs
|
|
.CLKOUT0(CLKOUT0), // 1-bit output: CLKOUT0
|
|
.CLKOUT1(CLKOUT1), // 1-bit output: CLKOUT1
|
|
.CLKOUT2(CLKOUT2), // 1-bit output: CLKOUT2
|
|
.CLKOUT3(CLKOUT3), // 1-bit output: CLKOUT3
|
|
.CLKOUT4(CLKOUT4), // 1-bit output: CLKOUT4
|
|
.CLKOUT5(CLKOUT5), // 1-bit output: CLKOUT5
|
|
// DRP Ports: 16-bit (each) output: Dynamic reconfiguration ports
|
|
.DO(DO), // 16-bit output: DRP data
|
|
.DRDY(DRDY), // 1-bit output: DRP ready
|
|
// Feedback Clocks: 1-bit (each) output: Clock feedback ports
|
|
.CLKFBOUT(CLKFBOUT), // 1-bit output: Feedback clock
|
|
.LOCKED(LOCKED), // 1-bit output: LOCK
|
|
// Clock Inputs: 1-bit (each) input: Clock inputs
|
|
.CLKIN1(CLKIN1), // 1-bit input: Primary clock
|
|
.CLKIN2(CLKIN2), // 1-bit input: Secondary clock
|
|
// Control Ports: 1-bit (each) input: PLL control ports
|
|
.CLKINSEL(CLKINSEL), // 1-bit input: Clock select, High=CLKIN1 Low=CLKIN2
|
|
.PWRDWN(PWRDWN), // 1-bit input: Power-down
|
|
.RST(RST), // 1-bit input: Reset
|
|
// DRP Ports: 7-bit (each) input: Dynamic reconfiguration ports
|
|
.DADDR(DADDR), // 7-bit input: DRP address
|
|
.DCLK(DCLK), // 1-bit input: DRP clock
|
|
.DEN(DEN), // 1-bit input: DRP enable
|
|
.DI(DI), // 16-bit input: DRP data
|
|
.DWE(DWE), // 1-bit input: DRP write enable
|
|
// Feedback Clocks: 1-bit (each) input: Clock feedback ports
|
|
.CLKFBIN(CLKFBIN) // 1-bit input: Feedback clock
|
|
);
|
|
|
|
// End of PLLE2_ADV_inst instantiation
|
|
</Template>
|
|
<Template label="Base Phase Locked Loop (PLLE2_BASE)" treetype="template">
|
|
// PLLE2_BASE : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (PLLE2_BASE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// PLLE2_BASE: Base Phase Locked Loop (PLL)
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
PLLE2_BASE #(
|
|
.BANDWIDTH("OPTIMIZED"), // OPTIMIZED, HIGH, LOW
|
|
.CLKFBOUT_MULT(5), // Multiply value for all CLKOUT, (2-64)
|
|
.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB, (-360.000-360.000).
|
|
.CLKIN1_PERIOD(0.0), // Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
|
|
// CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128)
|
|
.CLKOUT0_DIVIDE(1),
|
|
.CLKOUT1_DIVIDE(1),
|
|
.CLKOUT2_DIVIDE(1),
|
|
.CLKOUT3_DIVIDE(1),
|
|
.CLKOUT4_DIVIDE(1),
|
|
.CLKOUT5_DIVIDE(1),
|
|
// CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for each CLKOUT (0.001-0.999).
|
|
.CLKOUT0_DUTY_CYCLE(0.5),
|
|
.CLKOUT1_DUTY_CYCLE(0.5),
|
|
.CLKOUT2_DUTY_CYCLE(0.5),
|
|
.CLKOUT3_DUTY_CYCLE(0.5),
|
|
.CLKOUT4_DUTY_CYCLE(0.5),
|
|
.CLKOUT5_DUTY_CYCLE(0.5),
|
|
// CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
|
|
.CLKOUT0_PHASE(0.0),
|
|
.CLKOUT1_PHASE(0.0),
|
|
.CLKOUT2_PHASE(0.0),
|
|
.CLKOUT3_PHASE(0.0),
|
|
.CLKOUT4_PHASE(0.0),
|
|
.CLKOUT5_PHASE(0.0),
|
|
.DIVCLK_DIVIDE(1), // Master division value, (1-56)
|
|
.REF_JITTER1(0.0), // Reference input jitter in UI, (0.000-0.999).
|
|
.STARTUP_WAIT("FALSE") // Delay DONE until PLL Locks, ("TRUE"/"FALSE")
|
|
)
|
|
PLLE2_BASE_inst (
|
|
// Clock Outputs: 1-bit (each) output: User configurable clock outputs
|
|
.CLKOUT0(CLKOUT0), // 1-bit output: CLKOUT0
|
|
.CLKOUT1(CLKOUT1), // 1-bit output: CLKOUT1
|
|
.CLKOUT2(CLKOUT2), // 1-bit output: CLKOUT2
|
|
.CLKOUT3(CLKOUT3), // 1-bit output: CLKOUT3
|
|
.CLKOUT4(CLKOUT4), // 1-bit output: CLKOUT4
|
|
.CLKOUT5(CLKOUT5), // 1-bit output: CLKOUT5
|
|
// Feedback Clocks: 1-bit (each) output: Clock feedback ports
|
|
.CLKFBOUT(CLKFBOUT), // 1-bit output: Feedback clock
|
|
.LOCKED(LOCKED), // 1-bit output: LOCK
|
|
.CLKIN1(CLKIN1), // 1-bit input: Input clock
|
|
// Control Ports: 1-bit (each) input: PLL control ports
|
|
.PWRDWN(PWRDWN), // 1-bit input: Power-down
|
|
.RST(RST), // 1-bit input: Reset
|
|
// Feedback Clocks: 1-bit (each) input: Clock feedback ports
|
|
.CLKFBIN(CLKFBIN) // 1-bit input: Feedback clock
|
|
);
|
|
|
|
// End of PLLE2_BASE_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="I/O Components" treetype="folder">
|
|
<Template label="Digitally Controlled Impedance Reset Component (DCIRESET)" treetype="template">
|
|
// DCIRESET : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (DCIRESET_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// DCIRESET: Digitally Controlled Impedance Reset Component
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
DCIRESET DCIRESET_inst (
|
|
.LOCKED(LOCKED), // 1-bit output: LOCK status output
|
|
.RST(RST) // 1-bit input: Active-high asynchronous reset input
|
|
);
|
|
|
|
// End of DCIRESET_inst instantiation
|
|
</Template>
|
|
<SubFolder label="I/O Delay Components" treetype="folder">
|
|
<Template label="Delay Calibration (IDELAYCTRL)" treetype="template">
|
|
// IDELAYCTRL : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IDELAYCTRL_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IDELAYCTRL: IDELAYE2/ODELAYE2 Tap Delay Value Control
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
(* IODELAY_GROUP = <iodelay_group_name> *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTRL
|
|
|
|
IDELAYCTRL IDELAYCTRL_inst (
|
|
.RDY(RDY), // 1-bit output: Ready output
|
|
.REFCLK(REFCLK), // 1-bit input: Reference clock input
|
|
.RST(RST) // 1-bit input: Active high reset input
|
|
);
|
|
|
|
// End of IDELAYCTRL_inst instantiation
|
|
</Template>
|
|
<Template label="Input Delay Element (IDELAYE2)" treetype="template">
|
|
// IDELAYE2 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IDELAYE2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IDELAYE2: Input Fixed or Variable Delay Element
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
(* IODELAY_GROUP = <iodelay_group_name> *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTRL
|
|
|
|
IDELAYE2 #(
|
|
.CINVCTRL_SEL("FALSE"), // Enable dynamic clock inversion (FALSE, TRUE)
|
|
.DELAY_SRC("IDATAIN"), // Delay input (IDATAIN, DATAIN)
|
|
.HIGH_PERFORMANCE_MODE("FALSE"), // Reduced jitter ("TRUE"), Reduced power ("FALSE")
|
|
.IDELAY_TYPE("FIXED"), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
|
|
.IDELAY_VALUE(0), // Input delay tap setting (0-31)
|
|
.PIPE_SEL("FALSE"), // Select pipelined mode, FALSE, TRUE
|
|
.REFCLK_FREQUENCY(200.0), // IDELAYCTRL clock input frequency in MHz (190.0-210.0, 290.0-310.0).
|
|
.SIGNAL_PATTERN("DATA") // DATA, CLOCK input signal
|
|
)
|
|
IDELAYE2_inst (
|
|
.CNTVALUEOUT(CNTVALUEOUT), // 5-bit output: Counter value output
|
|
.DATAOUT(DATAOUT), // 1-bit output: Delayed data output
|
|
.C(C), // 1-bit input: Clock input
|
|
.CE(CE), // 1-bit input: Active high enable increment/decrement input
|
|
.CINVCTRL(CINVCTRL), // 1-bit input: Dynamic clock inversion input
|
|
.CNTVALUEIN(CNTVALUEIN), // 5-bit input: Counter value input
|
|
.DATAIN(DATAIN), // 1-bit input: Internal delay data input
|
|
.IDATAIN(IDATAIN), // 1-bit input: Data input from the I/O
|
|
.INC(INC), // 1-bit input: Increment / Decrement tap delay input
|
|
.LD(LD), // 1-bit input: Load IDELAY_VALUE input
|
|
.LDPIPEEN(LDPIPEEN), // 1-bit input: Enable PIPELINE register to load data input
|
|
.REGRST(REGRST) // 1-bit input: Active-high reset tap-delay input
|
|
);
|
|
|
|
// End of IDELAYE2_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="FIFOs" treetype="folder">
|
|
<Template label="Input FIFO (IN_FIFO)" treetype="template">
|
|
// IN_FIFO : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IN_FIFO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IN_FIFO: Input First-In, First-Out (FIFO)
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IN_FIFO #(
|
|
.ALMOST_EMPTY_VALUE(1), // Almost empty offset (1-2)
|
|
.ALMOST_FULL_VALUE(1), // Almost full offset (1-2)
|
|
.ARRAY_MODE("ARRAY_MODE_4_X_8"), // ARRAY_MODE_4_X_8, ARRAY_MODE_4_X_4
|
|
.SYNCHRONOUS_MODE("FALSE") // Clock synchronous (FALSE)
|
|
)
|
|
IN_FIFO_inst (
|
|
// FIFO Status Flags: 1-bit (each) output: Flags and other FIFO status outputs
|
|
.ALMOSTEMPTY(ALMOSTEMPTY), // 1-bit output: Almost empty
|
|
.ALMOSTFULL(ALMOSTFULL), // 1-bit output: Almost full
|
|
.EMPTY(EMPTY), // 1-bit output: Empty
|
|
.FULL(FULL), // 1-bit output: Full
|
|
// Q0-Q9: 8-bit (each) output: FIFO Outputs
|
|
.Q0(Q0), // 8-bit output: Channel 0
|
|
.Q1(Q1), // 8-bit output: Channel 1
|
|
.Q2(Q2), // 8-bit output: Channel 2
|
|
.Q3(Q3), // 8-bit output: Channel 3
|
|
.Q4(Q4), // 8-bit output: Channel 4
|
|
.Q5(Q5), // 8-bit output: Channel 5
|
|
.Q6(Q6), // 8-bit output: Channel 6
|
|
.Q7(Q7), // 8-bit output: Channel 7
|
|
.Q8(Q8), // 8-bit output: Channel 8
|
|
.Q9(Q9), // 8-bit output: Channel 9
|
|
// D0-D9: 4-bit (each) input: FIFO inputs
|
|
.D0(D0), // 4-bit input: Channel 0
|
|
.D1(D1), // 4-bit input: Channel 1
|
|
.D2(D2), // 4-bit input: Channel 2
|
|
.D3(D3), // 4-bit input: Channel 3
|
|
.D4(D4), // 4-bit input: Channel 4
|
|
.D5(D5), // 8-bit input: Channel 5
|
|
.D6(D6), // 8-bit input: Channel 6
|
|
.D7(D7), // 4-bit input: Channel 7
|
|
.D8(D8), // 4-bit input: Channel 8
|
|
.D9(D9), // 4-bit input: Channel 9
|
|
// FIFO Control Signals: 1-bit (each) input: Clocks, Resets and Enables
|
|
.RDCLK(RDCLK), // 1-bit input: Read clock
|
|
.RDEN(RDEN), // 1-bit input: Read enable
|
|
.RESET(RESET), // 1-bit input: Reset
|
|
.WRCLK(WRCLK), // 1-bit input: Write clock
|
|
.WREN(WREN) // 1-bit input: Write enable
|
|
);
|
|
|
|
// End of IN_FIFO_inst instantiation
|
|
</Template>
|
|
<Template label="Output FIFO (OUT_FIFO)" treetype="template">
|
|
// OUT_FIFO : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OUT_FIFO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OUT_FIFO: Output First-In, First-Out (FIFO) Buffer
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OUT_FIFO #(
|
|
.ALMOST_EMPTY_VALUE(1), // Almost empty offset (1-2)
|
|
.ALMOST_FULL_VALUE(1), // Almost full offset (1-2)
|
|
.ARRAY_MODE("ARRAY_MODE_8_X_4"), // ARRAY_MODE_8_X_4, ARRAY_MODE_4_X_4
|
|
.OUTPUT_DISABLE("FALSE"), // Disable output (FALSE, TRUE)
|
|
.SYNCHRONOUS_MODE("FALSE") // Must always be set to false.
|
|
)
|
|
OUT_FIFO_inst (
|
|
// FIFO Status Flags: 1-bit (each) output: Flags and other FIFO status outputs
|
|
.ALMOSTEMPTY(ALMOSTEMPTY), // 1-bit output: Almost empty flag
|
|
.ALMOSTFULL(ALMOSTFULL), // 1-bit output: Almost full flag
|
|
.EMPTY(EMPTY), // 1-bit output: Empty flag
|
|
.FULL(FULL), // 1-bit output: Full flag
|
|
// Q0-Q9: 4-bit (each) output: FIFO Outputs
|
|
.Q0(Q0), // 4-bit output: Channel 0 output bus
|
|
.Q1(Q1), // 4-bit output: Channel 1 output bus
|
|
.Q2(Q2), // 4-bit output: Channel 2 output bus
|
|
.Q3(Q3), // 4-bit output: Channel 3 output bus
|
|
.Q4(Q4), // 4-bit output: Channel 4 output bus
|
|
.Q5(Q5), // 8-bit output: Channel 5 output bus
|
|
.Q6(Q6), // 8-bit output: Channel 6 output bus
|
|
.Q7(Q7), // 4-bit output: Channel 7 output bus
|
|
.Q8(Q8), // 4-bit output: Channel 8 output bus
|
|
.Q9(Q9), // 4-bit output: Channel 9 output bus
|
|
// D0-D9: 8-bit (each) input: FIFO inputs
|
|
.D0(D0), // 8-bit input: Channel 0 input bus
|
|
.D1(D1), // 8-bit input: Channel 1 input bus
|
|
.D2(D2), // 8-bit input: Channel 2 input bus
|
|
.D3(D3), // 8-bit input: Channel 3 input bus
|
|
.D4(D4), // 8-bit input: Channel 4 input bus
|
|
.D5(D5), // 8-bit input: Channel 5 input bus
|
|
.D6(D6), // 8-bit input: Channel 6 input bus
|
|
.D7(D7), // 8-bit input: Channel 7 input bus
|
|
.D8(D8), // 8-bit input: Channel 8 input bus
|
|
.D9(D9), // 8-bit input: Channel 9 input bus
|
|
// FIFO Control Signals: 1-bit (each) input: Clocks, Resets and Enables
|
|
.RDCLK(RDCLK), // 1-bit input: Read clock
|
|
.RDEN(RDEN), // 1-bit input: Read enable
|
|
.RESET(RESET), // 1-bit input: Active high reset
|
|
.WRCLK(WRCLK), // 1-bit input: Write clock
|
|
.WREN(WREN) // 1-bit input: Write enable
|
|
);
|
|
|
|
// End of OUT_FIFO_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="I/O SERDES" treetype="folder">
|
|
<Template label="Input SERial/DESerializer with Bitslip (ISERDESE2)" treetype="template">
|
|
// ISERDESE2 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ISERDESE2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ISERDESE2: Input SERial/DESerializer with Bitslip
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ISERDESE2 #(
|
|
.DATA_RATE("DDR"), // DDR, SDR
|
|
.DATA_WIDTH(4), // Parallel data width (2-8,10,14)
|
|
.DYN_CLKDIV_INV_EN("FALSE"), // Enable DYNCLKDIVINVSEL inversion (FALSE, TRUE)
|
|
.DYN_CLK_INV_EN("FALSE"), // Enable DYNCLKINVSEL inversion (FALSE, TRUE)
|
|
// INIT_Q1 - INIT_Q4: Initial value on the Q outputs (0/1)
|
|
.INIT_Q1(1'b0),
|
|
.INIT_Q2(1'b0),
|
|
.INIT_Q3(1'b0),
|
|
.INIT_Q4(1'b0),
|
|
.INTERFACE_TYPE("MEMORY"), // MEMORY, MEMORY_DDR3, MEMORY_QDR, NETWORKING, OVERSAMPLE
|
|
.IOBDELAY("NONE"), // NONE, BOTH, IBUF, IFD
|
|
.NUM_CE(2), // Number of clock enables (1,2)
|
|
.OFB_USED("FALSE"), // Select OFB path (FALSE, TRUE)
|
|
.SERDES_MODE("MASTER"), // MASTER, SLAVE
|
|
// SRVAL_Q1 - SRVAL_Q4: Q output values when SR is used (0/1)
|
|
.SRVAL_Q1(1'b0),
|
|
.SRVAL_Q2(1'b0),
|
|
.SRVAL_Q3(1'b0),
|
|
.SRVAL_Q4(1'b0)
|
|
)
|
|
ISERDESE2_inst (
|
|
.O(O), // 1-bit output: Combinatorial output
|
|
// Q1 - Q8: 1-bit (each) output: Registered data outputs
|
|
.Q1(Q1),
|
|
.Q2(Q2),
|
|
.Q3(Q3),
|
|
.Q4(Q4),
|
|
.Q5(Q5),
|
|
.Q6(Q6),
|
|
.Q7(Q7),
|
|
.Q8(Q8),
|
|
// SHIFTOUT1, SHIFTOUT2: 1-bit (each) output: Data width expansion output ports
|
|
.SHIFTOUT1(SHIFTOUT1),
|
|
.SHIFTOUT2(SHIFTOUT2),
|
|
.BITSLIP(BITSLIP), // 1-bit input: The BITSLIP pin performs a Bitslip operation synchronous to
|
|
// CLKDIV when asserted (active High). Subsequently, the data seen on the Q1
|
|
// to Q8 output ports will shift, as in a barrel-shifter operation, one
|
|
// position every time Bitslip is invoked (DDR operation is different from
|
|
// SDR).
|
|
|
|
// CE1, CE2: 1-bit (each) input: Data register clock enable inputs
|
|
.CE1(CE1),
|
|
.CE2(CE2),
|
|
.CLKDIVP(CLKDIVP), // 1-bit input: TBD
|
|
// Clocks: 1-bit (each) input: ISERDESE2 clock input ports
|
|
.CLK(CLK), // 1-bit input: High-speed clock
|
|
.CLKB(CLKB), // 1-bit input: High-speed secondary clock
|
|
.CLKDIV(CLKDIV), // 1-bit input: Divided clock
|
|
.OCLK(OCLK), // 1-bit input: High speed output clock used when INTERFACE_TYPE="MEMORY"
|
|
// Dynamic Clock Inversions: 1-bit (each) input: Dynamic clock inversion pins to switch clock polarity
|
|
.DYNCLKDIVSEL(DYNCLKDIVSEL), // 1-bit input: Dynamic CLKDIV inversion
|
|
.DYNCLKSEL(DYNCLKSEL), // 1-bit input: Dynamic CLK/CLKB inversion
|
|
// Input Data: 1-bit (each) input: ISERDESE2 data input ports
|
|
.D(D), // 1-bit input: Data input
|
|
.DDLY(DDLY), // 1-bit input: Serial data from IDELAYE2
|
|
.OFB(OFB), // 1-bit input: Data feedback from OSERDESE2
|
|
.OCLKB(OCLKB), // 1-bit input: High speed negative edge output clock
|
|
.RST(RST), // 1-bit input: Active high asynchronous reset
|
|
// SHIFTIN1, SHIFTIN2: 1-bit (each) input: Data width expansion input ports
|
|
.SHIFTIN1(SHIFTIN1),
|
|
.SHIFTIN2(SHIFTIN2)
|
|
);
|
|
|
|
// End of ISERDESE2_inst instantiation
|
|
</Template>
|
|
<Template label="Output SERial/DESerializer with bitslip (OSERDESE2)" treetype="template">
|
|
// OSERDESE2 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OSERDESE2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OSERDESE2: Output SERial/DESerializer with bitslip
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OSERDESE2 #(
|
|
.DATA_RATE_OQ("DDR"), // DDR, SDR
|
|
.DATA_RATE_TQ("DDR"), // DDR, BUF, SDR
|
|
.DATA_WIDTH(4), // Parallel data width (2-8,10,14)
|
|
.INIT_OQ(1'b0), // Initial value of OQ output (1'b0,1'b1)
|
|
.INIT_TQ(1'b0), // Initial value of TQ output (1'b0,1'b1)
|
|
.SERDES_MODE("MASTER"), // MASTER, SLAVE
|
|
.SRVAL_OQ(1'b0), // OQ output value when SR is used (1'b0,1'b1)
|
|
.SRVAL_TQ(1'b0), // TQ output value when SR is used (1'b0,1'b1)
|
|
.TBYTE_CTL("FALSE"), // Enable tristate byte operation (FALSE, TRUE)
|
|
.TBYTE_SRC("FALSE"), // Tristate byte source (FALSE, TRUE)
|
|
.TRISTATE_WIDTH(4) // 3-state converter width (1,4)
|
|
)
|
|
OSERDESE2_inst (
|
|
.OFB(OFB), // 1-bit output: Feedback path for data
|
|
.OQ(OQ), // 1-bit output: Data path output
|
|
// SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
|
|
.SHIFTOUT1(SHIFTOUT1),
|
|
.SHIFTOUT2(SHIFTOUT2),
|
|
.TBYTEOUT(TBYTEOUT), // 1-bit output: Byte group tristate
|
|
.TFB(TFB), // 1-bit output: 3-state control
|
|
.TQ(TQ), // 1-bit output: 3-state control
|
|
.CLK(CLK), // 1-bit input: High speed clock
|
|
.CLKDIV(CLKDIV), // 1-bit input: Divided clock
|
|
// D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
|
|
.D1(D1),
|
|
.D2(D2),
|
|
.D3(D3),
|
|
.D4(D4),
|
|
.D5(D5),
|
|
.D6(D6),
|
|
.D7(D7),
|
|
.D8(D8),
|
|
.OCE(OCE), // 1-bit input: Output data clock enable
|
|
.RST(RST), // 1-bit input: Reset
|
|
// SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
|
|
.SHIFTIN1(SHIFTIN1),
|
|
.SHIFTIN2(SHIFTIN2),
|
|
// T1 - T4: 1-bit (each) input: Parallel 3-state inputs
|
|
.T1(T1),
|
|
.T2(T2),
|
|
.T3(T3),
|
|
.T4(T4),
|
|
.TBYTEIN(TBYTEIN), // 1-bit input: Byte group tristate
|
|
.TCE(TCE) // 1-bit input: 3-state clock enable
|
|
);
|
|
|
|
// End of OSERDESE2_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Input Buffers" treetype="folder">
|
|
<Template label="Single-ended Buffer (IBUF)" treetype="template">
|
|
// IBUF : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUF_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUF: Single-ended Input Buffer
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUF #(
|
|
.IBUF_LOW_PWR("TRUE"), // Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
) IBUF_inst (
|
|
.O(O), // Buffer output
|
|
.I(I) // Buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUF_inst instantiation
|
|
</Template>
|
|
<Template label="Single-ended Buffer w/ Disable (IBUF_IBUFDISABLE)" treetype="template">
|
|
// IBUF_IBUFDISABLE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUF_IBUFDISABLE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUF_IBUFDISABLE: Single-ended Input Buffer with Disable
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUF_IBUFDISABLE #(
|
|
.IBUF_LOW_PWR("TRUE"), // Low power ("TRUE") vs. performance ("FALSE") for referenced I/O standards
|
|
.IOSTANDARD("DEFAULT"), // Specify the input I/O standard
|
|
.USE_IBUFDISABLE("TRUE") // Set to "TRUE" to enable IBUFDISABLE feature
|
|
) IBUF_IBUFDISABLE_inst (
|
|
.O(O), // Buffer output
|
|
.I(I), // Buffer input (connect directly to top-level port)
|
|
.IBUFDISABLE(IBUFDISABLE) // Buffer disable input, low=disable
|
|
);
|
|
|
|
// End of IBUF_IBUFDISABLE_inst instantiation
|
|
</Template>
|
|
<Template label="Single-ended Buffer w/ Termination Disable (IBUF_INTERMDISABLE)" treetype="template">
|
|
// IBUF_INTERMDISABLE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUF_INTERMDISABLE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUF_INTERMDISABLE: Single-ended Input Buffer with Termination Input Disable
|
|
// May only be placed in High Range (HR) Banks
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUF_INTERMDISABLE #(
|
|
.IBUF_LOW_PWR("TRUE"), // Low power ("TRUE") vs. performance ("FALSE") for referenced I/O standards
|
|
.IOSTANDARD("DEFAULT"), // Specify the input I/O standard
|
|
.USE_IBUFDISABLE("TRUE") // Set to "TRUE" to enable IBUFDISABLE feature
|
|
) IBUF_INTERMDISABLE_inst (
|
|
.O(O), // Buffer output
|
|
.I(I), // Buffer input (connect directly to top-level port)
|
|
.IBUFDISABLE(IBUFDISABLE), // Buffer disable input, low=disable
|
|
.INTERMDISABLE(INTERMDISABLE) // Input Termination Disable
|
|
);
|
|
|
|
// End of IBUF_INTERMDISABLE_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer (IBUFDS)" treetype="template">
|
|
// IBUFDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFDS: Differential Input Buffer
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFDS #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination
|
|
.IBUF_LOW_PWR("TRUE"), // Low power="TRUE", Highest performance="FALSE"
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
) IBUFDS_inst (
|
|
.O(O), // Buffer output
|
|
.I(I), // Diff_p buffer input (connect directly to top-level port)
|
|
.IB(IB) // Diff_n buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUFDS_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer w/ Disable (IBUFDS_IBUFDISABLE)" treetype="template">
|
|
// IBUFDS_IBUFDISABLE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFDS_IBUFDISABLE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFDS_IBUFDISABLE: Differential Input Buffer with Input Disable
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFDS_IBUFDISABLE #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination
|
|
.IBUF_LOW_PWR("TRUE"), // Low power="TRUE", Highest performance="FALSE"
|
|
.IOSTANDARD("DEFAULT"), // Specify the input I/O standard
|
|
.USE_IBUFDISABLE("TRUE") // Set to "TRUE" to enable IBUFDISABLE feature
|
|
) IBUFDS_IBUFDISABLE_inst (
|
|
.O(O), // Buffer output
|
|
.I(I), // Diff_p buffer input (connect directly to top-level port)
|
|
.IB(IB), // Diff_n buffer input (connect directly to top-level port)
|
|
.IBUFDISABLE(IBUFDISABLE) // Buffer disable input, low=disable
|
|
);
|
|
|
|
// End of IBUFDS_IBUFDISABLE_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer w/ Termination Disable (IBUFDS_INTERMDISABLE)" treetype="template">
|
|
// IBUFDS_INTERMDISABLE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFDS_INTERMDISABLE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFDS_INTERMDISABLE: Differential Input Buffer with Input Termination Disable
|
|
// May only be placed in High Range (HR) Banks
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFDS_INTERMDISABLE #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination
|
|
.IBUF_LOW_PWR("TRUE"), // Low power="TRUE", Highest performance="FALSE"
|
|
.IOSTANDARD("DEFAULT"), // Specify the input I/O standard
|
|
.USE_IBUFDISABLE("TRUE") // Set to "TRUE" to enable IBUFDISABLE feature
|
|
) IBUFDS_INTERMDISABLE_inst (
|
|
.O(O), // Buffer output
|
|
.I(I), // Diff_p buffer input (connect directly to top-level port)
|
|
.IB(IB), // Diff_n buffer input (connect directly to top-level port)
|
|
.IBUFDISABLE(IBUFDISABLE), // Buffer disable input, low=disable
|
|
.INTERMDISABLE(INTERMDISABLE) // Input Termination Disable
|
|
);
|
|
|
|
// End of IBUFDS_INTERMDISABLE_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer with Differential Output (IBUFDS_DIFF_OUT)" treetype="template">
|
|
// IBUFDS_DIFF_OUT : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFDS_DIFF_OUT_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFDS_DIFF_OUT: Differential Input Buffer with Differential Output
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFDS_DIFF_OUT #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination, "TRUE"/"FALSE"
|
|
.IBUF_LOW_PWR("TRUE"), // Low power="TRUE", Highest performance="FALSE"
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
) IBUFDS_DIFF_OUT_inst (
|
|
.O(O), // Buffer diff_p output
|
|
.OB(OB), // Buffer diff_n output
|
|
.I(I), // Diff_p buffer input (connect directly to top-level port)
|
|
.IB(IB) // Diff_n buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUFDS_DIFF_OUT_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer with Differential Output w/ Input Disable (IBUFDS_DIFF_OUT_IBUFDISABLE)" treetype="template">
|
|
// IBUFDS_DIFF_OUT_IBUFDISABLE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFDS_DIFF_OUT_IBUFDISABLE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFDS_DIFF_OUT_IBUFDISABLE: Differential Input Buffer with Differential Output with Input Disable
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFDS_DIFF_OUT_IBUFDISABLE #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination, "TRUE"/"FALSE"
|
|
.IBUF_LOW_PWR("TRUE"), // Low power="TRUE", Highest performance="FALSE"
|
|
.IOSTANDARD("DEFAULT"), // Specify the input I/O standard
|
|
.USE_IBUFDISABLE("TRUE") // Set to "TRUE" to enable IBUFDISABLE feature
|
|
) IBUFDS_DIFF_OUT_IBUFDISABLE_inst (
|
|
.O(O), // Buffer diff_p output
|
|
.OB(OB), // Buffer diff_n output
|
|
.I(I), // Diff_p buffer input (connect directly to top-level port)
|
|
.IB(IB), // Diff_n buffer input (connect directly to top-level port)
|
|
.IBUFDISABLE(IBUFDISABLE) // Buffer disable input, low=disable
|
|
);
|
|
|
|
// End of IBUFDS_DIFF_OUT_IBUFDISABLE_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer with Differential Output w/ Input Termination Disable (IBUFDS_DIFF_OUT_INTERMDISABLE)" treetype="template">
|
|
// IBUFDS_DIFF_OUT_INTERMDISABLE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFDS_DIFF_OUT_INTERMDISABLE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFDS_DIFF_OUT_INTERMDISABLE: Differential Input Buffer with Differential Output with Input Termination Disable
|
|
// May only be placed in High Range (HR) Banks
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFDS_DIFF_OUT_INTERMDISABLE #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination, "TRUE"/"FALSE"
|
|
.IBUF_LOW_PWR("TRUE"), // Low power="TRUE", Highest performance="FALSE"
|
|
.IOSTANDARD("DEFAULT"), // Specify the input I/O standard
|
|
.USE_IBUFDISABLE("TRUE") // Set to "TRUE" to enable IBUFDISABLE feature
|
|
) IBUFDS_DIFF_OUT_INTERMDISABLE_inst (
|
|
.O(O), // Buffer diff_p output
|
|
.OB(OB), // Buffer diff_n output
|
|
.I(I), // Diff_p buffer input (connect directly to top-level port)
|
|
.IB(IB), // Diff_n buffer input (connect directly to top-level port)
|
|
.IBUFDISABLE(IBUFDISABLE), // Buffer disable input, low=disable
|
|
.INTERMDISABLE(INTERMDISABLE) // Input Termination Disable
|
|
);
|
|
|
|
// End of IBUFDS_DIFF_OUT_INTERMDISABLE_inst instantiation
|
|
</Template>
|
|
<Template label="Single-ended Global Clock Buffer (IBUFG)" treetype="template">
|
|
// IBUFG : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFG_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFG: Single-ended global clock input buffer
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFG #(
|
|
.IBUF_LOW_PWR("TRUE"), // Low power="TRUE", Highest performance="FALSE"
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
) IBUFG_inst (
|
|
.O(O), // Clock buffer output
|
|
.I(I) // Clock buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUFG_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Global Clock (IBUFGDS)" treetype="template">
|
|
// IBUFGDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFGDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFGDS: Differential Global Clock Input Buffer
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFGDS #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination
|
|
.IBUF_LOW_PWR("TRUE"), // Low power="TRUE", Highest performance="FALSE"
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
) IBUFGDS_inst (
|
|
.O(O), // Clock buffer output
|
|
.I(I), // Diff_p clock buffer input (connect directly to top-level port)
|
|
.IB(IB) // Diff_n clock buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUFGDS_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Global Clock Buffer with Differential Output (IBUFGDS_DIFF_OUT)" treetype="template">
|
|
// IBUFGDS_DIFF_OUT : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFGDS_DIFF_OUT_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFGDS_DIFF_OUT: Differential Global Clock Buffer with Differential Output
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFGDS_DIFF_OUT #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination, "TRUE"/"FALSE"
|
|
.IBUF_LOW_PWR("TRUE"), // Low power="TRUE", Highest performance="FALSE"
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
) IBUFGDS_DIFF_OUT_inst (
|
|
.O(O), // Buffer diff_p output
|
|
.OB(OB), // Buffer diff_n output
|
|
.I(I), // Diff_p buffer input (connect directly to top-level port)
|
|
.IB(IB) // Diff_n buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUFGDS_DIFF_OUT_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Output Buffers" treetype="folder">
|
|
<Template label="Single-ended Buffer (OBUF)" treetype="template">
|
|
// OBUF : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OBUF_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OBUF: Single-ended Output Buffer
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OBUF #(
|
|
.DRIVE(12), // Specify the output drive strength
|
|
.IOSTANDARD("DEFAULT"), // Specify the output I/O standard
|
|
.SLEW("SLOW") // Specify the output slew rate
|
|
) OBUF_inst (
|
|
.O(O), // Buffer output (connect directly to top-level port)
|
|
.I(I) // Buffer input
|
|
);
|
|
|
|
// End of OBUF_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer (OBUFDS)" treetype="template">
|
|
|
|
// OBUFDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OBUFDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OBUFDS: Differential Output Buffer
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OBUFDS #(
|
|
.IOSTANDARD("DEFAULT"), // Specify the output I/O standard
|
|
.SLEW("SLOW") // Specify the output slew rate
|
|
) OBUFDS_inst (
|
|
.O(O), // Diff_p output (connect directly to top-level port)
|
|
.OB(OB), // Diff_n output (connect directly to top-level port)
|
|
.I(I) // Buffer input
|
|
);
|
|
|
|
// End of OBUFDS_inst instantiation
|
|
</Template>
|
|
<Template label="Single-ended 3-state Buffer (OBUFT)" treetype="template">
|
|
// OBUFT : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OBUFT_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OBUFT: Single-ended 3-state Output Buffer
|
|
// All devices
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OBUFT #(
|
|
.DRIVE(12), // Specify the output drive strength
|
|
.IOSTANDARD("DEFAULT"), // Specify the output I/O standard
|
|
.SLEW("SLOW") // Specify the output slew rate
|
|
) OBUFT_inst (
|
|
.O(O), // Buffer output (connect directly to top-level port)
|
|
.I(I), // Buffer input
|
|
.T(T) // 3-state enable input
|
|
);
|
|
|
|
// End of OBUFT_inst instantiation
|
|
</Template>
|
|
<Template label="Differential 3-state Buffer (OBUFTDS)" treetype="template">
|
|
// OBUFTDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OBUFTDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OBUFTDS: Differential 3-state Output Buffer
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OBUFTDS #(
|
|
.IOSTANDARD("DEFAULT"), // Specify the output I/O standard
|
|
.SLEW("SLOW") // Specify the output slew rate
|
|
) OBUFTDS_inst (
|
|
.O(O), // Diff_p output (connect directly to top-level port)
|
|
.OB(OB), // Diff_n output (connect directly to top-level port)
|
|
.I(I), // Buffer input
|
|
.T(T) // 3-state enable input
|
|
);
|
|
|
|
// End of OBUFTDS_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Bi-directional Buffers" treetype="folder">
|
|
<Template label="Single-ended Buffer (IOBUF)" treetype="template">
|
|
// IOBUF : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IOBUF_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IOBUF: Single-ended Bi-directional Buffer
|
|
// All devices
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IOBUF #(
|
|
.DRIVE(12), // Specify the output drive strength
|
|
.IBUF_LOW_PWR("TRUE"), // Low Power - "TRUE", High Performance = "FALSE"
|
|
.IOSTANDARD("DEFAULT"), // Specify the I/O standard
|
|
.SLEW("SLOW") // Specify the output slew rate
|
|
) IOBUF_inst (
|
|
.O(O), // Buffer output
|
|
.IO(IO), // Buffer inout port (connect directly to top-level port)
|
|
.I(I), // Buffer input
|
|
.T(T) // 3-state enable input, high=input, low=output
|
|
);
|
|
|
|
// End of IOBUF_inst instantiation
|
|
</Template>
|
|
<Template label="Single-ended Buffer w/ input and INTERM disable (IOBUF_INTERMDISABLE)" treetype="template">
|
|
// IOBUF_INTERMDISABLE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IOBUF_INTERMDISABLE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IOBUF_INTERMDISABLE: Single-ended Bi-directional Buffer with Input Termination
|
|
// and Input path enable/disable
|
|
// May only be placed in High Range (HR) Banks
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IOBUF_INTERMDISABLE #(
|
|
.DRIVE(12), // Specify the output drive strength
|
|
.IBUF_LOW_PWR("TRUE"), // Low Power - "TRUE", High Performance = "FALSE"
|
|
.IOSTANDARD("DEFAULT"), // Specify the I/O standard
|
|
.SLEW("SLOW"), // Specify the output slew rate
|
|
.USE_IBUFDISABLE("TRUE") // Use IBUFDISABLE function, "TRUE" or "FALSE"
|
|
) IOBUF_INTERMDISABLE_inst (
|
|
.O(O), // Buffer output
|
|
.IO(IO), // Buffer inout port (connect directly to top-level port)
|
|
.I(I), // Buffer input
|
|
.IBUFDISABLE(IBUFDISABLE), // Input disable input, low=disable
|
|
.INTERMDISABLE(INTERMDISABLE), // Input termination disable input
|
|
.T(T) // 3-state enable input, high=input, low=output
|
|
);
|
|
|
|
// End of IOBUF_INTERMDISABLE_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer (IOBUFDS)" treetype="template">
|
|
// IOBUFDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IOBUFDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IOBUFDS: Differential Bi-directional Buffer
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IOBUFDS #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination ("TRUE"/"FALSE")
|
|
.IBUF_LOW_PWR("TRUE"), // Low Power - "TRUE", High Performance = "FALSE"
|
|
.IOSTANDARD("BLVDS_25"), // Specify the I/O standard
|
|
.SLEW("SLOW") // Specify the output slew rate
|
|
) IOBUFDS_inst (
|
|
.O(O), // Buffer output
|
|
.IO(IO), // Diff_p inout (connect directly to top-level port)
|
|
.IOB(IOB), // Diff_n inout (connect directly to top-level port)
|
|
.I(I), // Buffer input
|
|
.T(T) // 3-state enable input, high=input, low=output
|
|
);
|
|
|
|
// End of IOBUFDS_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer w/ input and input termination disable (IOBUFDS_INTERMDISABLE)" treetype="template">
|
|
// IOBUFDS_INTERMDISABLE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IOBUFDS_INTERMDISABLE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IOBUFDS_INTERMDISABLE: Differential Bi-directional Buffer with Input Termination
|
|
// and Input path enable/disable
|
|
// May only be placed in High Range (HR) Banks
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IOBUFDS_INTERMDISABLE #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination ("TRUE"/"FALSE")
|
|
.IBUF_LOW_PWR("TRUE"), // Low Power - "TRUE", High Performance = "FALSE"
|
|
.IOSTANDARD("BLVDS_25"), // Specify the I/O standard
|
|
.SLEW("SLOW"), // Specify the output slew rate
|
|
.USE_IBUFDISABLE("TRUE") // Use IBUFDISABLE function, "TRUE" or "FALSE"
|
|
) IOBUFDS_INTERMDISABLE_inst (
|
|
.O(O), // Buffer output
|
|
.IO(IO), // Diff_p inout (connect directly to top-level port)
|
|
.IOB(IOB), // Diff_n inout (connect directly to top-level port)
|
|
.I(I), // Buffer input
|
|
.IBUFDISABLE(IBUFDISABLE), // Input disable input, low=disable
|
|
.INTERMDISABLE(INTERMDISABLE), // Input termination disable input
|
|
.T(T) // 3-state enable input, high=input, low=output
|
|
);
|
|
|
|
// End of IOBUFDS_INTERMDISABLE_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer with Differential Output (IOBUFDS_DIFF_OUT)" treetype="template">
|
|
// IOBUFDS_DIFF_OUT : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IOBUFDS_DIFF_OUT_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IOBUFDS_DIFF_OUT: Differential Bi-directional Buffer with Differential Output
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IOBUFDS_DIFF_OUT #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination ("TRUE"/"FALSE")
|
|
.IBUF_LOW_PWR("TRUE"), // Low Power - "TRUE", High Performance = "FALSE"
|
|
.IOSTANDARD("BLVDS_25") // Specify the I/O standard
|
|
) IOBUFDS_DIFF_OUT_inst (
|
|
.O(O), // Buffer p-side output
|
|
.OB(OB), // Buffer n-side output
|
|
.IO(IO), // Diff_p inout (connect directly to top-level port)
|
|
.IOB(IOB), // Diff_n inout (connect directly to top-level port)
|
|
.I(I), // Buffer input
|
|
.TM(TM), // 3-state enable input, high=input, low=output
|
|
.TS(TS) // 3-state enable input, high=output, low=input
|
|
);
|
|
|
|
// End of IOBUFDS_DIFF_OUT_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Global Clock Buffer w/ Differential Output, INTERM and IBUF disable (IOBUFDS_DIFF_OUT_INTERMDISABLE)" treetype="template">
|
|
// IOBUFDS_DIFF_OUT_INTERMDISABLE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IOBUFDS_DIFF_OUT_INTERMDISABLE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IOBUFDS_DIFF_OUT_INTERMDISABLE: Differential Global Clock Buffer with Differential Output
|
|
// Input Termination and Input Path Disable
|
|
// May only be placed in High Range (HR) Banks
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IOBUFDS_DIFF_OUT_INTERMDISABLE #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination, "TRUE"/"FALSE"
|
|
.IBUF_LOW_PWR("TRUE"), // Low power="TRUE", Highest performance="FALSE"
|
|
.IOSTANDARD("DEFAULT"), // Specify the input I/O standard
|
|
.USE_IBUFDISABLE("TRUE") // Set to "TRUE" to enable IBUFDISABLE feature
|
|
) IOBUFDS_DIFF_OUT_INTERMDISABLE_inst (
|
|
.O(O), // Buffer p-side output
|
|
.OB(OB), // Buffer n-side output
|
|
.IO(IO), // Diff_p inout (connect directly to top-level port)
|
|
.IOB(IOB), // Diff_n inout (connect directly to top-level port)
|
|
.I(I), // Buffer input
|
|
.INTERMDISABLE(INTERMDISABLE), // Input termination disable input
|
|
.IBUFDISABLE(IBUFDISABLE), // Input disable input, low=disable
|
|
.TM(TM), // 3-state enable input, high=input, low=output
|
|
.TS(TS) // 3-state enable input, high=output, low=input
|
|
);
|
|
|
|
// End of IOBUFDS_DIFF_OUT_INTERMDISABLE_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Weak drivers" treetype="folder">
|
|
<Template label="PULLUP" treetype="template">
|
|
// PULLUP : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (PULLUP_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design.
|
|
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// PULLUP: I/O Buffer Weak Pull-up
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
PULLUP PULLUP_inst (
|
|
.O(O) // Pullup output (connect directly to top-level port)
|
|
);
|
|
|
|
// End of PULLUP_inst instantiation
|
|
</Template>
|
|
<Template label="PULLDOWN" treetype="template">
|
|
// PULLDOWN : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (PULLDOWN_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// PULLDOWN: I/O Buffer Weak Pull-down
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
PULLDOWN PULLDOWN_inst (
|
|
.O(O) // Pulldown output (connect directly to top-level port)
|
|
);
|
|
|
|
// End of PULLDOWN_inst instantiation
|
|
</Template>
|
|
<Template label="KEEPER" treetype="template">
|
|
// KEEPER : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (KEEPER_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// KEEPER: I/O Buffer Weak Keeper
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
KEEPER KEEPER_inst (
|
|
.O(O) // Keeper output (connect directly to top-level port)
|
|
);
|
|
|
|
// End of KEEPER_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="DDR Registers" treetype="folder">
|
|
<Template label="Dual-Clock, Input DDR Register (IDDR_2CLK)" treetype="template">
|
|
// IDDR_2CLK : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IDDR_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IDDR_2CLK: Dual-Clock, Input Double Data Rate Input Register with
|
|
// Set, Reset and Clock Enable.
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IDDR_2CLK #(
|
|
.DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE", "SAME_EDGE"
|
|
// or "SAME_EDGE_PIPELINED"
|
|
.INIT_Q1(1'b0), // Initial value of Q1: 1'b0 or 1'b1
|
|
.INIT_Q2(1'b0), // Initial value of Q2: 1'b0 or 1'b1
|
|
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
|
|
) IDDR_2CLK_inst (
|
|
.Q1(Q1), // 1-bit output for positive edge of clock
|
|
.Q2(Q2), // 1-bit output for negative edge of clock
|
|
.C(C), // 1-bit primary clock input
|
|
.CB(CB), // 1-bit secondary clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.D(D), // 1-bit DDR data input
|
|
.R(R), // 1-bit reset
|
|
.S(S) // 1-bit set
|
|
);
|
|
|
|
// End of IDDR_2CLK_inst instantiation
|
|
</Template>
|
|
<Template label="Input DDR Register (IDDR)" treetype="template">
|
|
// IDDR : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IDDR_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IDDR: Input Double Data Rate Input Register with Set, Reset
|
|
// and Clock Enable.
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IDDR #(
|
|
.DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE", "SAME_EDGE"
|
|
// or "SAME_EDGE_PIPELINED"
|
|
.INIT_Q1(1'b0), // Initial value of Q1: 1'b0 or 1'b1
|
|
.INIT_Q2(1'b0), // Initial value of Q2: 1'b0 or 1'b1
|
|
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
|
|
) IDDR_inst (
|
|
.Q1(Q1), // 1-bit output for positive edge of clock
|
|
.Q2(Q2), // 1-bit output for negative edge of clock
|
|
.C(C), // 1-bit clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.D(D), // 1-bit DDR data input
|
|
.R(R), // 1-bit reset
|
|
.S(S) // 1-bit set
|
|
);
|
|
|
|
// End of IDDR_inst instantiation
|
|
</Template>
|
|
<Template label="Output DDR Register (ODDR)" treetype="template">
|
|
// ODDR : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ODDR_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ODDR: Output Double Data Rate Output Register with Set, Reset
|
|
// and Clock Enable.
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ODDR #(
|
|
.DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE"
|
|
.INIT(1'b0), // Initial value of Q: 1'b0 or 1'b1
|
|
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
|
|
) ODDR_inst (
|
|
.Q(Q), // 1-bit DDR output
|
|
.C(C), // 1-bit clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.D1(D1), // 1-bit data input (positive edge)
|
|
.D2(D2), // 1-bit data input (negative edge)
|
|
.R(R), // 1-bit reset
|
|
.S(S) // 1-bit set
|
|
);
|
|
|
|
// End of ODDR_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Arithmetic Functions" treetype="folder">
|
|
<Template label="48-bit Multi-Functional Arithmetic Block (DSP48E1)" treetype="template">
|
|
// DSP48E1 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (DSP48E1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// DSP48E1: 48-bit Multi-Functional Arithmetic Block
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
DSP48E1 #(
|
|
// Feature Control Attributes: Data Path Selection
|
|
.A_INPUT("DIRECT"), // Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
|
|
.B_INPUT("DIRECT"), // Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
|
|
.USE_DPORT("FALSE"), // Select D port usage (TRUE or FALSE)
|
|
.USE_MULT("MULTIPLY"), // Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE")
|
|
.USE_SIMD("ONE48"), // SIMD selection ("ONE48", "TWO24", "FOUR12")
|
|
// Pattern Detector Attributes: Pattern Detection Configuration
|
|
.AUTORESET_PATDET("NO_RESET"), // "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH"
|
|
.MASK(48'h3fffffffffff), // 48-bit mask value for pattern detect (1=ignore)
|
|
.PATTERN(48'h000000000000), // 48-bit pattern match for pattern detect
|
|
.SEL_MASK("MASK"), // "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2"
|
|
.SEL_PATTERN("PATTERN"), // Select pattern value ("PATTERN" or "C")
|
|
.USE_PATTERN_DETECT("NO_PATDET"), // Enable pattern detect ("PATDET" or "NO_PATDET")
|
|
// Register Control Attributes: Pipeline Register Configuration
|
|
.ACASCREG(1), // Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2)
|
|
.ADREG(1), // Number of pipeline stages for pre-adder (0 or 1)
|
|
.ALUMODEREG(1), // Number of pipeline stages for ALUMODE (0 or 1)
|
|
.AREG(1), // Number of pipeline stages for A (0, 1 or 2)
|
|
.BCASCREG(1), // Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2)
|
|
.BREG(1), // Number of pipeline stages for B (0, 1 or 2)
|
|
.CARRYINREG(1), // Number of pipeline stages for CARRYIN (0 or 1)
|
|
.CARRYINSELREG(1), // Number of pipeline stages for CARRYINSEL (0 or 1)
|
|
.CREG(1), // Number of pipeline stages for C (0 or 1)
|
|
.DREG(1), // Number of pipeline stages for D (0 or 1)
|
|
.INMODEREG(1), // Number of pipeline stages for INMODE (0 or 1)
|
|
.MREG(1), // Number of multiplier pipeline stages (0 or 1)
|
|
.OPMODEREG(1), // Number of pipeline stages for OPMODE (0 or 1)
|
|
.PREG(1) // Number of pipeline stages for P (0 or 1)
|
|
)
|
|
DSP48E1_inst (
|
|
// Cascade: 30-bit (each) output: Cascade Ports
|
|
.ACOUT(ACOUT), // 30-bit output: A port cascade output
|
|
.BCOUT(BCOUT), // 18-bit output: B port cascade output
|
|
.CARRYCASCOUT(CARRYCASCOUT), // 1-bit output: Cascade carry output
|
|
.MULTSIGNOUT(MULTSIGNOUT), // 1-bit output: Multiplier sign cascade output
|
|
.PCOUT(PCOUT), // 48-bit output: Cascade output
|
|
// Control: 1-bit (each) output: Control Inputs/Status Bits
|
|
.OVERFLOW(OVERFLOW), // 1-bit output: Overflow in add/acc output
|
|
.PATTERNBDETECT(PATTERNBDETECT), // 1-bit output: Pattern bar detect output
|
|
.PATTERNDETECT(PATTERNDETECT), // 1-bit output: Pattern detect output
|
|
.UNDERFLOW(UNDERFLOW), // 1-bit output: Underflow in add/acc output
|
|
// Data: 4-bit (each) output: Data Ports
|
|
.CARRYOUT(CARRYOUT), // 4-bit output: Carry output
|
|
.P(P), // 48-bit output: Primary data output
|
|
// Cascade: 30-bit (each) input: Cascade Ports
|
|
.ACIN(ACIN), // 30-bit input: A cascade data input
|
|
.BCIN(BCIN), // 18-bit input: B cascade input
|
|
.CARRYCASCIN(CARRYCASCIN), // 1-bit input: Cascade carry input
|
|
.MULTSIGNIN(MULTSIGNIN), // 1-bit input: Multiplier sign input
|
|
.PCIN(PCIN), // 48-bit input: P cascade input
|
|
// Control: 4-bit (each) input: Control Inputs/Status Bits
|
|
.ALUMODE(ALUMODE), // 4-bit input: ALU control input
|
|
.CARRYINSEL(CARRYINSEL), // 3-bit input: Carry select input
|
|
.CLK(CLK), // 1-bit input: Clock input
|
|
.INMODE(INMODE), // 5-bit input: INMODE control input
|
|
.OPMODE(OPMODE), // 7-bit input: Operation mode input
|
|
// Data: 30-bit (each) input: Data Ports
|
|
.A(A), // 30-bit input: A data input
|
|
.B(B), // 18-bit input: B data input
|
|
.C(C), // 48-bit input: C data input
|
|
.CARRYIN(CARRYIN), // 1-bit input: Carry input signal
|
|
.D(D), // 25-bit input: D data input
|
|
// Reset/Clock Enable: 1-bit (each) input: Reset/Clock Enable Inputs
|
|
.CEA1(CEA1), // 1-bit input: Clock enable input for 1st stage AREG
|
|
.CEA2(CEA2), // 1-bit input: Clock enable input for 2nd stage AREG
|
|
.CEAD(CEAD), // 1-bit input: Clock enable input for ADREG
|
|
.CEALUMODE(CEALUMODE), // 1-bit input: Clock enable input for ALUMODE
|
|
.CEB1(CEB1), // 1-bit input: Clock enable input for 1st stage BREG
|
|
.CEB2(CEB2), // 1-bit input: Clock enable input for 2nd stage BREG
|
|
.CEC(CEC), // 1-bit input: Clock enable input for CREG
|
|
.CECARRYIN(CECARRYIN), // 1-bit input: Clock enable input for CARRYINREG
|
|
.CECTRL(CECTRL), // 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
|
|
.CED(CED), // 1-bit input: Clock enable input for DREG
|
|
.CEINMODE(CEINMODE), // 1-bit input: Clock enable input for INMODEREG
|
|
.CEM(CEM), // 1-bit input: Clock enable input for MREG
|
|
.CEP(CEP), // 1-bit input: Clock enable input for PREG
|
|
.RSTA(RSTA), // 1-bit input: Reset input for AREG
|
|
.RSTALLCARRYIN(RSTALLCARRYIN), // 1-bit input: Reset input for CARRYINREG
|
|
.RSTALUMODE(RSTALUMODE), // 1-bit input: Reset input for ALUMODEREG
|
|
.RSTB(RSTB), // 1-bit input: Reset input for BREG
|
|
.RSTC(RSTC), // 1-bit input: Reset input for CREG
|
|
.RSTCTRL(RSTCTRL), // 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
|
|
.RSTD(RSTD), // 1-bit input: Reset input for DREG and ADREG
|
|
.RSTINMODE(RSTINMODE), // 1-bit input: Reset input for INMODEREG
|
|
.RSTM(RSTM), // 1-bit input: Reset input for MREG
|
|
.RSTP(RSTP) // 1-bit input: Reset input for PREG
|
|
);
|
|
|
|
// End of DSP48E1_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="RAM/ROM" treetype="folder">
|
|
<SubFolder label="FIFO" treetype="folder">
|
|
<Template label="18Kb First-In-First-Out (FIFO) Buffer Memory (FIFO18E1)" treetype="template">
|
|
// FIFO18E1 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FIFO18E1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FIFO18E1: 18Kb FIFO (First-In-First-Out) Block RAM Memory
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FIFO18E1 #(
|
|
.ALMOST_EMPTY_OFFSET(13'h0080), // Sets the almost empty threshold
|
|
.ALMOST_FULL_OFFSET(13'h0080), // Sets almost full threshold
|
|
.DATA_WIDTH(4), // Sets data width to 4-36
|
|
.DO_REG(1), // Enable output register (1-0) Must be 1 if EN_SYN = FALSE
|
|
.EN_SYN("FALSE"), // Specifies FIFO as dual-clock (FALSE) or Synchronous (TRUE)
|
|
.FIFO_MODE("FIFO18"), // Sets mode to FIFO18 or FIFO18_36
|
|
.FIRST_WORD_FALL_THROUGH("FALSE"), // Sets the FIFO FWFT to FALSE, TRUE
|
|
.INIT(36'h000000000), // Initial values on output port
|
|
.SIM_DEVICE("7SERIES"), // Must be set to "7SERIES" for simulation behavior
|
|
.SRVAL(36'h000000000) // Set/Reset value for output port
|
|
)
|
|
FIFO18E1_inst (
|
|
// Read Data: 32-bit (each) output: Read output data
|
|
.DO(DO), // 32-bit output: Data output
|
|
.DOP(DOP), // 4-bit output: Parity data output
|
|
// Status: 1-bit (each) output: Flags and other FIFO status outputs
|
|
.ALMOSTEMPTY(ALMOSTEMPTY), // 1-bit output: Almost empty flag
|
|
.ALMOSTFULL(ALMOSTFULL), // 1-bit output: Almost full flag
|
|
.EMPTY(EMPTY), // 1-bit output: Empty flag
|
|
.FULL(FULL), // 1-bit output: Full flag
|
|
.RDCOUNT(RDCOUNT), // 12-bit output: Read count
|
|
.RDERR(RDERR), // 1-bit output: Read error
|
|
.WRCOUNT(WRCOUNT), // 12-bit output: Write count
|
|
.WRERR(WRERR), // 1-bit output: Write error
|
|
// Read Control Signals: 1-bit (each) input: Read clock, enable and reset input signals
|
|
.RDCLK(RDCLK), // 1-bit input: Read clock
|
|
.RDEN(RDEN), // 1-bit input: Read enable
|
|
.REGCE(REGCE), // 1-bit input: Clock enable
|
|
.RST(RST), // 1-bit input: Asynchronous Reset
|
|
.RSTREG(RSTREG), // 1-bit input: Output register set/reset
|
|
// Write Control Signals: 1-bit (each) input: Write clock and enable input signals
|
|
.WRCLK(WRCLK), // 1-bit input: Write clock
|
|
.WREN(WREN), // 1-bit input: Write enable
|
|
// Write Data: 32-bit (each) input: Write input data
|
|
.DI(DI), // 32-bit input: Data input
|
|
.DIP(DIP) // 4-bit input: Parity input
|
|
);
|
|
|
|
// End of FIFO18E1_inst instantiation
|
|
</Template>
|
|
<Template label="36Kb First-In-First-Out (FIFO) Buffer Memory (FIFO36E1)" treetype="template">
|
|
// FIFO36E1 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FIFO36E1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FIFO36E1: 36Kb FIFO (First-In-First-Out) Block RAM Memory
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FIFO36E1 #(
|
|
.ALMOST_EMPTY_OFFSET(13'h0080), // Sets the almost empty threshold
|
|
.ALMOST_FULL_OFFSET(13'h0080), // Sets almost full threshold
|
|
.DATA_WIDTH(4), // Sets data width to 4-72
|
|
.DO_REG(1), // Enable output register (1-0) Must be 1 if EN_SYN = FALSE
|
|
.EN_ECC_READ("FALSE"), // Enable ECC decoder, FALSE, TRUE
|
|
.EN_ECC_WRITE("FALSE"), // Enable ECC encoder, FALSE, TRUE
|
|
.EN_SYN("FALSE"), // Specifies FIFO as Asynchronous (FALSE) or Synchronous (TRUE)
|
|
.FIFO_MODE("FIFO36"), // Sets mode to "FIFO36" or "FIFO36_72"
|
|
.FIRST_WORD_FALL_THROUGH("FALSE"), // Sets the FIFO FWFT to FALSE, TRUE
|
|
.INIT(72'h000000000000000000), // Initial values on output port
|
|
.SIM_DEVICE("7SERIES"), // Must be set to "7SERIES" for simulation behavior
|
|
.SRVAL(72'h000000000000000000) // Set/Reset value for output port
|
|
)
|
|
FIFO36E1_inst (
|
|
// ECC Signals: 1-bit (each) output: Error Correction Circuitry ports
|
|
.DBITERR(DBITERR), // 1-bit output: Double bit error status
|
|
.ECCPARITY(ECCPARITY), // 8-bit output: Generated error correction parity
|
|
.SBITERR(SBITERR), // 1-bit output: Single bit error status
|
|
// Read Data: 64-bit (each) output: Read output data
|
|
.DO(DO), // 64-bit output: Data output
|
|
.DOP(DOP), // 8-bit output: Parity data output
|
|
// Status: 1-bit (each) output: Flags and other FIFO status outputs
|
|
.ALMOSTEMPTY(ALMOSTEMPTY), // 1-bit output: Almost empty flag
|
|
.ALMOSTFULL(ALMOSTFULL), // 1-bit output: Almost full flag
|
|
.EMPTY(EMPTY), // 1-bit output: Empty flag
|
|
.FULL(FULL), // 1-bit output: Full flag
|
|
.RDCOUNT(RDCOUNT), // 13-bit output: Read count
|
|
.RDERR(RDERR), // 1-bit output: Read error
|
|
.WRCOUNT(WRCOUNT), // 13-bit output: Write count
|
|
.WRERR(WRERR), // 1-bit output: Write error
|
|
// ECC Signals: 1-bit (each) input: Error Correction Circuitry ports
|
|
.INJECTDBITERR(INJECTDBITERR), // 1-bit input: Inject a double bit error input
|
|
.INJECTSBITERR(INJECTSBITERR),
|
|
// Read Control Signals: 1-bit (each) input: Read clock, enable and reset input signals
|
|
.RDCLK(RDCLK), // 1-bit input: Read clock
|
|
.RDEN(RDEN), // 1-bit input: Read enable
|
|
.REGCE(REGCE), // 1-bit input: Clock enable
|
|
.RST(RST), // 1-bit input: Reset
|
|
.RSTREG(RSTREG), // 1-bit input: Output register set/reset
|
|
// Write Control Signals: 1-bit (each) input: Write clock and enable input signals
|
|
.WRCLK(WRCLK), // 1-bit input: Rising edge write clock.
|
|
.WREN(WREN), // 1-bit input: Write enable
|
|
// Write Data: 64-bit (each) input: Write input data
|
|
.DI(DI), // 64-bit input: Data input
|
|
.DIP(DIP) // 8-bit input: Parity input
|
|
);
|
|
|
|
// End of FIFO36E1_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="BlockRAM" treetype="folder">
|
|
<Template label="18Kb Block RAM Memory (RAMB18E1)" treetype="template">
|
|
// RAMB18E1 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB18E1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB18E1: 18K-bit Configurable Synchronous Block RAM
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB18E1 #(
|
|
// Address Collision Mode: "PERFORMANCE" or "DELAYED_WRITE"
|
|
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
|
|
// Collision check: Values ("ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE")
|
|
.SIM_COLLISION_CHECK("ALL"),
|
|
// DOA_REG, DOB_REG: Optional output register (0 or 1)
|
|
.DOA_REG(0),
|
|
.DOB_REG(0),
|
|
// INITP_00 to INITP_07: Initial contents of parity memory array
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// INIT_00 to INIT_3F: Initial contents of data memory array
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// INIT_A, INIT_B: Initial values on output ports
|
|
.INIT_A(18'h00000),
|
|
.INIT_B(18'h00000),
|
|
// Initialization File: RAM initialization file
|
|
.INIT_FILE("NONE"),
|
|
// RAM Mode: "SDP" or "TDP"
|
|
.RAM_MODE("TDP"),
|
|
// READ_WIDTH_A/B, WRITE_WIDTH_A/B: Read/write width per port
|
|
.READ_WIDTH_A(0), // 0-72
|
|
.READ_WIDTH_B(0), // 0-18
|
|
.WRITE_WIDTH_A(0), // 0-18
|
|
.WRITE_WIDTH_B(0), // 0-72
|
|
// RSTREG_PRIORITY_A, RSTREG_PRIORITY_B: Reset or enable priority ("RSTREG" or "REGCE")
|
|
.RSTREG_PRIORITY_A("RSTREG"),
|
|
.RSTREG_PRIORITY_B("RSTREG"),
|
|
// SRVAL_A, SRVAL_B: Set/reset value for output
|
|
.SRVAL_A(18'h00000),
|
|
.SRVAL_B(18'h00000),
|
|
// Simulation Device: Must be set to "7SERIES" for simulation behavior
|
|
.SIM_DEVICE("7SERIES"),
|
|
// WriteMode: Value on output upon a write ("WRITE_FIRST", "READ_FIRST", or "NO_CHANGE")
|
|
.WRITE_MODE_A("WRITE_FIRST"),
|
|
.WRITE_MODE_B("WRITE_FIRST")
|
|
)
|
|
RAMB18E1_inst (
|
|
// Port A Data: 16-bit (each) output: Port A data
|
|
.DOADO(DOADO), // 16-bit output: A port data/LSB data
|
|
.DOPADOP(DOPADOP), // 2-bit output: A port parity/LSB parity
|
|
// Port B Data: 16-bit (each) output: Port B data
|
|
.DOBDO(DOBDO), // 16-bit output: B port data/MSB data
|
|
.DOPBDOP(DOPBDOP), // 2-bit output: B port parity/MSB parity
|
|
// Port A Address/Control Signals: 14-bit (each) input: Port A address and control signals (read port
|
|
// when RAM_MODE="SDP")
|
|
.ADDRARDADDR(ADDRARDADDR), // 14-bit input: A port address/Read address
|
|
.CLKARDCLK(CLKARDCLK), // 1-bit input: A port clock/Read clock
|
|
.ENARDEN(ENARDEN), // 1-bit input: A port enable/Read enable
|
|
.REGCEAREGCE(REGCEAREGCE), // 1-bit input: A port register enable/Register enable
|
|
.RSTRAMARSTRAM(RSTRAMARSTRAM), // 1-bit input: A port set/reset
|
|
.RSTREGARSTREG(RSTREGARSTREG), // 1-bit input: A port register set/reset
|
|
.WEA(WEA), // 2-bit input: A port write enable
|
|
// Port A Data: 16-bit (each) input: Port A data
|
|
.DIADI(DIADI), // 16-bit input: A port data/LSB data
|
|
.DIPADIP(DIPADIP), // 2-bit input: A port parity/LSB parity
|
|
// Port B Address/Control Signals: 14-bit (each) input: Port B address and control signals (write port
|
|
// when RAM_MODE="SDP")
|
|
.ADDRBWRADDR(ADDRBWRADDR), // 14-bit input: B port address/Write address
|
|
.CLKBWRCLK(CLKBWRCLK), // 1-bit input: B port clock/Write clock
|
|
.ENBWREN(ENBWREN), // 1-bit input: B port enable/Write enable
|
|
.REGCEB(REGCEB), // 1-bit input: B port register enable
|
|
.RSTRAMB(RSTRAMB), // 1-bit input: B port set/reset
|
|
.RSTREGB(RSTREGB), // 1-bit input: B port register set/reset
|
|
.WEBWE(WEBWE), // 4-bit input: B port write enable/Write enable
|
|
// Port B Data: 16-bit (each) input: Port B data
|
|
.DIBDI(DIBDI), // 16-bit input: B port data/MSB data
|
|
.DIPBDIP(DIPBDIP) // 2-bit input: B port parity/MSB parity
|
|
);
|
|
|
|
// End of RAMB18E1_inst instantiation
|
|
</Template>
|
|
<Template label="36Kb Block RAM Memory (RAMB36E1)" treetype="template">
|
|
// RAMB36E1 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB36E1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB36E1: 36K-bit Configurable Synchronous Block RAM
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB36E1 #(
|
|
// Address Collision Mode: "PERFORMANCE" or "DELAYED_WRITE"
|
|
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
|
|
// Collision check: Values ("ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE")
|
|
.SIM_COLLISION_CHECK("ALL"),
|
|
// DOA_REG, DOB_REG: Optional output register (0 or 1)
|
|
.DOA_REG(0),
|
|
.DOB_REG(0),
|
|
.EN_ECC_READ("FALSE"), // Enable ECC decoder,
|
|
// FALSE, TRUE
|
|
.EN_ECC_WRITE("FALSE"), // Enable ECC encoder,
|
|
// FALSE, TRUE
|
|
// INITP_00 to INITP_0F: Initial contents of the parity memory array
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// INIT_00 to INIT_7F: Initial contents of the data memory array
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// INIT_A, INIT_B: Initial values on output ports
|
|
.INIT_A(36'h000000000),
|
|
.INIT_B(36'h000000000),
|
|
// Initialization File: RAM initialization file
|
|
.INIT_FILE("NONE"),
|
|
// RAM Mode: "SDP" or "TDP"
|
|
.RAM_MODE("TDP"),
|
|
// RAM_EXTENSION_A, RAM_EXTENSION_B: Selects cascade mode ("UPPER", "LOWER", or "NONE")
|
|
.RAM_EXTENSION_A("NONE"),
|
|
.RAM_EXTENSION_B("NONE"),
|
|
// READ_WIDTH_A/B, WRITE_WIDTH_A/B: Read/write width per port
|
|
.READ_WIDTH_A(0), // 0-72
|
|
.READ_WIDTH_B(0), // 0-36
|
|
.WRITE_WIDTH_A(0), // 0-36
|
|
.WRITE_WIDTH_B(0), // 0-72
|
|
// RSTREG_PRIORITY_A, RSTREG_PRIORITY_B: Reset or enable priority ("RSTREG" or "REGCE")
|
|
.RSTREG_PRIORITY_A("RSTREG"),
|
|
.RSTREG_PRIORITY_B("RSTREG"),
|
|
// SRVAL_A, SRVAL_B: Set/reset value for output
|
|
.SRVAL_A(36'h000000000),
|
|
.SRVAL_B(36'h000000000),
|
|
// Simulation Device: Must be set to "7SERIES" for simulation behavior
|
|
.SIM_DEVICE("7SERIES"),
|
|
// WriteMode: Value on output upon a write ("WRITE_FIRST", "READ_FIRST", or "NO_CHANGE")
|
|
.WRITE_MODE_A("WRITE_FIRST"),
|
|
.WRITE_MODE_B("WRITE_FIRST")
|
|
)
|
|
RAMB36E1_inst (
|
|
// Cascade Signals: 1-bit (each) output: BRAM cascade ports (to create 64kx1)
|
|
.CASCADEOUTA(CASCADEOUTA), // 1-bit output: A port cascade
|
|
.CASCADEOUTB(CASCADEOUTB), // 1-bit output: B port cascade
|
|
// ECC Signals: 1-bit (each) output: Error Correction Circuitry ports
|
|
.DBITERR(DBITERR), // 1-bit output: Double bit error status
|
|
.ECCPARITY(ECCPARITY), // 8-bit output: Generated error correction parity
|
|
.RDADDRECC(RDADDRECC), // 9-bit output: ECC read address
|
|
.SBITERR(SBITERR), // 1-bit output: Single bit error status
|
|
// Port A Data: 32-bit (each) output: Port A data
|
|
.DOADO(DOADO), // 32-bit output: A port data/LSB data
|
|
.DOPADOP(DOPADOP), // 4-bit output: A port parity/LSB parity
|
|
// Port B Data: 32-bit (each) output: Port B data
|
|
.DOBDO(DOBDO), // 32-bit output: B port data/MSB data
|
|
.DOPBDOP(DOPBDOP), // 4-bit output: B port parity/MSB parity
|
|
// Cascade Signals: 1-bit (each) input: BRAM cascade ports (to create 64kx1)
|
|
.CASCADEINA(CASCADEINA), // 1-bit input: A port cascade
|
|
.CASCADEINB(CASCADEINB), // 1-bit input: B port cascade
|
|
// ECC Signals: 1-bit (each) input: Error Correction Circuitry ports
|
|
.INJECTDBITERR(INJECTDBITERR), // 1-bit input: Inject a double bit error
|
|
.INJECTSBITERR(INJECTSBITERR), // 1-bit input: Inject a single bit error
|
|
// Port A Address/Control Signals: 16-bit (each) input: Port A address and control signals (read port
|
|
// when RAM_MODE="SDP")
|
|
.ADDRARDADDR(ADDRARDADDR), // 16-bit input: A port address/Read address
|
|
.CLKARDCLK(CLKARDCLK), // 1-bit input: A port clock/Read clock
|
|
.ENARDEN(ENARDEN), // 1-bit input: A port enable/Read enable
|
|
.REGCEAREGCE(REGCEAREGCE), // 1-bit input: A port register enable/Register enable
|
|
.RSTRAMARSTRAM(RSTRAMARSTRAM), // 1-bit input: A port set/reset
|
|
.RSTREGARSTREG(RSTREGARSTREG), // 1-bit input: A port register set/reset
|
|
.WEA(WEA), // 4-bit input: A port write enable
|
|
// Port A Data: 32-bit (each) input: Port A data
|
|
.DIADI(DIADI), // 32-bit input: A port data/LSB data
|
|
.DIPADIP(DIPADIP), // 4-bit input: A port parity/LSB parity
|
|
// Port B Address/Control Signals: 16-bit (each) input: Port B address and control signals (write port
|
|
// when RAM_MODE="SDP")
|
|
.ADDRBWRADDR(ADDRBWRADDR), // 16-bit input: B port address/Write address
|
|
.CLKBWRCLK(CLKBWRCLK), // 1-bit input: B port clock/Write clock
|
|
.ENBWREN(ENBWREN), // 1-bit input: B port enable/Write enable
|
|
.REGCEB(REGCEB), // 1-bit input: B port register enable
|
|
.RSTRAMB(RSTRAMB), // 1-bit input: B port set/reset
|
|
.RSTREGB(RSTREGB), // 1-bit input: B port register set/reset
|
|
.WEBWE(WEBWE), // 8-bit input: B port write enable/Write enable
|
|
// Port B Data: 32-bit (each) input: Port B data
|
|
.DIBDI(DIBDI), // 32-bit input: B port data/MSB data
|
|
.DIPBDIP(DIPBDIP) // 4-bit input: B port parity/MSB parity
|
|
);
|
|
|
|
// End of RAMB36E1_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Distributed ROM" treetype="folder">
|
|
<Template label="32 X 1 (ROM32X1)" treetype="template">
|
|
// ROM32X1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ROM32X1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ROM32X1: 32 x 1 Asynchronous Distributed (LUT) ROM (Mapped to a SliceM LUT6)
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ROM32X1 #(
|
|
.INIT(32'h00000000) // Contents of ROM
|
|
) ROM32X1_inst (
|
|
.O(O), // ROM output
|
|
.A0(A0), // ROM address[0]
|
|
.A1(A1), // ROM address[1]
|
|
.A2(A2), // ROM address[2]
|
|
.A3(A3), // ROM address[3]
|
|
.A4(A4) // ROM address[4]
|
|
);
|
|
|
|
// End of ROM32X1_inst instantiation
|
|
</Template>
|
|
<Template label="64 X 1 (ROM64X1)" treetype="template">
|
|
// ROM64X1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ROM64X1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ROM64X1: 64 x 1 Asynchronous Distributed (LUT) ROM (Mapped to a SliceM LUT6)
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ROM64X1 #(
|
|
.INIT(64'h0000000000000000) // Contents of ROM
|
|
) ROM64X1_inst (
|
|
.O(O), // ROM output
|
|
.A0(A0), // ROM address[0]
|
|
.A1(A1), // ROM address[1]
|
|
.A2(A2), // ROM address[2]
|
|
.A3(A3), // ROM address[3]
|
|
.A4(A4), // ROM address[4]
|
|
.A5(A5) // ROM address[5]
|
|
);
|
|
|
|
// End of ROM64X1_inst instantiation
|
|
</Template>
|
|
<Template label="128 X 1 (ROM128X1)" treetype="template">
|
|
// ROM128X1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ROM128X1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ROM128X1: 128 x 1 Asynchronous Distributed (LUT) ROM (Mapped to two SliceM LUT6s)
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ROM128X1 #(
|
|
.INIT(128'h00000000000000000000000000000000) // Contents of ROM
|
|
) ROM128X1_inst (
|
|
.O(O), // ROM output
|
|
.A0(A0), // ROM address[0]
|
|
.A1(A1), // ROM address[1]
|
|
.A2(A2), // ROM address[2]
|
|
.A3(A3), // ROM address[3]
|
|
.A4(A4), // ROM address[4]
|
|
.A5(A5), // ROM address[5]
|
|
.A6(A6) // ROM address[6]
|
|
);
|
|
|
|
// End of ROM128X1_inst instantiation
|
|
</Template>
|
|
<Template label="256 X 1 (ROM256X1)" treetype="template">
|
|
// ROM256X1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ROM256X1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ROM256X1: 256 x 1 Asynchronous Distributed (LUT) ROM (Mapped to four SliceM LUT6s)
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ROM256X1 #(
|
|
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000) // Contents of ROM
|
|
) ROM256X1_inst (
|
|
.O(O), // ROM output
|
|
.A0(A0), // ROM address[0]
|
|
.A1(A1), // ROM address[1]
|
|
.A2(A2), // ROM address[2]
|
|
.A3(A3), // ROM address[3]
|
|
.A4(A4), // ROM address[4]
|
|
.A5(A5), // ROM address[5]
|
|
.A6(A6), // ROM address[6]
|
|
.A7(A7) // ROM address[7]
|
|
);
|
|
|
|
// End of ROM256X1_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Distributed RAM" treetype="folder">
|
|
<SubFolder label="Single-Port" treetype="folder">
|
|
<SubFolder label="32 Deep (5-bit address)" treetype="folder">
|
|
<Template label="32 x 1 posedge write (RAM32X1S)" treetype="template">
|
|
// RAM32X1S : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM32X1S_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM32X1S: 32 x 1 posedge write distributed (LUT) RAM (Mapped to a SliceM LUT6)
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM32X1S #(
|
|
.INIT(32'h00000000) // Initial contents of RAM
|
|
) RAM32X1S_inst (
|
|
.O(O), // RAM output
|
|
.A0(A0), // RAM address[0] input
|
|
.A1(A1), // RAM address[1] input
|
|
.A2(A2), // RAM address[2] input
|
|
.A3(A3), // RAM address[3] input
|
|
.A4(A4), // RAM address[4] input
|
|
.D(D), // RAM data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM32X1S_inst instantiation
|
|
</Template>
|
|
<Template label="32 x 1 negedge write (RAM32X1S_1)" treetype="template">
|
|
// RAM32X1S_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM32X1S_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM32X1S_1: 32 x 1 negedge write distributed (LUT) RAM (Mapped to a SliceM LUT6)
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM32X1S_1 #(
|
|
.INIT(32'h00000000) // Initial contents of RAM
|
|
)RAM32X1S_1_inst (
|
|
.O(O), // RAM output
|
|
.A0(A0), // RAM address[0] input
|
|
.A1(A1), // RAM address[1] input
|
|
.A2(A2), // RAM address[2] input
|
|
.A3(A3), // RAM address[3] input
|
|
.A4(A4), // RAM address[4] input
|
|
.D(D), // RAM data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM32X1S_1_inst instantiation
|
|
</Template>
|
|
<Template label="32 x 2 posedge write (RAM32X2S)" treetype="template">
|
|
// RAM32X2S : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM16X2S_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM32X2S: 32 x 2 posedge write distributed (LUT) RAM (Mapped to a SliceM LUT6)
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM32X2S #(
|
|
.INIT_00(32'h00000000), // INIT for bit 0 of RAM
|
|
.INIT_01(32'h00000000) // INIT for bit 1 of RAM
|
|
) RAM32X2S_inst (
|
|
.O0(O0), // RAM data[0] output
|
|
.O1(O1), // RAM data[1] output
|
|
.A0(A0), // RAM address[0] input
|
|
.A1(A1), // RAM address[1] input
|
|
.A2(A2), // RAM address[2] input
|
|
.A3(A3), // RAM address[3] input
|
|
.A4(A4), // RAM address[4] input
|
|
.D0(D0), // RAM data[0] input
|
|
.D1(D1), // RAM data[1] input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM32X2S_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="64 Deep (6-bit address)" treetype="folder">
|
|
<Template label="64 X 1 posedge write (RAM64X1S)" treetype="template">
|
|
// RAM64X1S : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM64X1S_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM64X1S: 64 x 1 positive edge write, asynchronous read single-port distributed RAM (Mapped to a SliceM LUT6)
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM64X1S #(
|
|
.INIT(64'h0000000000000000) // Initial contents of RAM
|
|
) RAM64X1S_inst (
|
|
.O(O), // 1-bit data output
|
|
.A0(A0), // Address[0] input bit
|
|
.A1(A1), // Address[1] input bit
|
|
.A2(A2), // Address[2] input bit
|
|
.A3(A3), // Address[3] input bit
|
|
.A4(A4), // Address[4] input bit
|
|
.A5(A5), // Address[5] input bit
|
|
.D(D), // 1-bit data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM64X1S_inst instantiation
|
|
</Template>
|
|
<Template label="64 X 1 negedge write (RAM64X1S_1)" treetype="template">
|
|
// RAM64X1S_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM64X1S_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM64X1S_1: 64 x 1 negative edge write, asynchronous read single-port distributed RAM (Mapped to a SliceM LUT6)
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM64X1S_1 #(
|
|
.INIT(64'h0000000000000000) // Initial contents of RAM
|
|
) RAM64X1S_1_inst (
|
|
.O(O), // 1-bit data output
|
|
.A0(A0), // Address[0] input bit
|
|
.A1(A1), // Address[1] input bit
|
|
.A2(A2), // Address[2] input bit
|
|
.A3(A3), // Address[3] input bit
|
|
.A4(A4), // Address[4] input bit
|
|
.A5(A5), // Address[5] input bit
|
|
.D(D), // 1-bit data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM64X1S_1_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="128 Deep (7-bit address)" treetype="folder">
|
|
<Template label="128 X 1 posedge write (RAM128X1S)" treetype="template">
|
|
// RAM128X1S : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM128X1S_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM128X1S: 128 x 1 positive edge write, asynchronous read single-port distributed RAM (Mapped to two SliceM LUT6s)
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM128X1S #(
|
|
.INIT(128'h00000000000000000000000000000000) // Initial contents of RAM
|
|
) RAM128X1S_inst (
|
|
.O(O), // 1-bit data output
|
|
.A0(A0), // Address[0] input bit
|
|
.A1(A1), // Address[1] input bit
|
|
.A2(A2), // Address[2] input bit
|
|
.A3(A3), // Address[3] input bit
|
|
.A4(A4), // Address[4] input bit
|
|
.A5(A5), // Address[5] input bit
|
|
.A6(A6), // Address[6] input bit
|
|
.D(D), // 1-bit data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM128X1S_inst instantiation
|
|
</Template>
|
|
<Template label="128 X 1 negedge write (RAM128X1S_1)" treetype="template">
|
|
// RAM128X1S_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM128X1S_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM128X1S_1: 128 x 1 negative edge write, asynchronous read single-port distributed RAM (Mapped to two SliceM LUT6s)
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM128X1S_1 #(
|
|
.INIT(128'h00000000000000000000000000000000) // Initial contents of RAM
|
|
) RAM128X1S_1_inst (
|
|
.O(O), // 1-bit data output
|
|
.A0(A0), // Address[0] input bit
|
|
.A1(A1), // Address[1] input bit
|
|
.A2(A2), // Address[2] input bit
|
|
.A3(A3), // Address[3] input bit
|
|
.A4(A4), // Address[4] input bit
|
|
.A5(A5), // Address[5] input bit
|
|
.A6(A6), // Address[6] input bit
|
|
.D(D), // 1-bit data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM128X1S_1_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="256 Deep (8-bit address)" treetype="folder">
|
|
<Template label="256 X 1 posedge write (RAM256X1S)" treetype="template">
|
|
// RAM256X1S : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM256X1S_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM256X1S: 256-deep by 1-wide positive edge write, asynchronous read (Mapped to four SliceM LUT6s)
|
|
// single-port distributed LUT RAM
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM256X1S #(
|
|
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAM256X1S_inst (
|
|
.O(O), // Read/write port 1-bit output
|
|
.A(A), // Read/write port 8-bit address input
|
|
.WE(WE), // Write enable input
|
|
.WCLK(WCLK), // Write clock input
|
|
.D(D) // RAM data input
|
|
);
|
|
|
|
// End of RAM256X1S_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Dual-Port" treetype="folder">
|
|
<Template label="32 X 1 posedge write (RAM32X1D)" treetype="template">
|
|
// RAM32X1D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM32X1D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM32X1D: 32 x 1 positive edge write, asynchronous read dual-port distributed RAM (Mapped to a SliceM LUT6)
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM32X1D #(
|
|
.INIT(32'h00000000) // Initial contents of RAM
|
|
) RAM32X1D_inst (
|
|
.DPO(DPO), // Read-only 1-bit data output
|
|
.SPO(SPO), // Rw/ 1-bit data output
|
|
.A0(A0), // Rw/ address[0] input bit
|
|
.A1(A1), // Rw/ address[1] input bit
|
|
.A2(A2), // Rw/ address[2] input bit
|
|
.A3(A3), // Rw/ address[3] input bit
|
|
.A4(A4), // Rw/ address[4] input bit
|
|
.D(D), // Write 1-bit data input
|
|
.DPRA0(DPRA0), // Read-only address[0] input bit
|
|
.DPRA1(DPRA1), // Read-only address[1] input bit
|
|
.DPRA2(DPRA2), // Read-only address[2] input bit
|
|
.DPRA3(DPRA3), // Read-only address[3] input bit
|
|
.DPRA4(DPRA4), // Read-only address[4] input bit
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM32X1D_inst instantiation
|
|
</Template>
|
|
<Template label="32 X 1 negedge write (RAM32X1D_1)" treetype="template">
|
|
// RAM32X1D_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM32X1D_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM32X1D_1: 32 x 1 negative edge write, asynchronous read dual-port distributed RAM (Mapped to a SliceM LUT6)
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM32X1D_1 #(
|
|
.INIT(32'h00000000) // Initial contents of RAM
|
|
) RAM32X1D_1_inst (
|
|
.DPO(DPO), // Read-only 1-bit data output
|
|
.SPO(SPO), // Rw/ 1-bit data output
|
|
.A0(A0), // Rw/ address[0] input bit
|
|
.A1(A1), // Rw/ address[1] input bit
|
|
.A2(A2), // Rw/ address[2] input bit
|
|
.A3(A3), // Rw/ address[3] input bit
|
|
.A4(A4), // Rw/ address[4] input bit
|
|
.D(D), // Write 1-bit data input
|
|
.DPRA0(DPRA0), // Read-only address[0] input bit
|
|
.DPRA1(DPRA1), // Read-only address[1] input bit
|
|
.DPRA2(DPRA2), // Read-only address[2] input bit
|
|
.DPRA3(DPRA3), // Read-only address[3] input bit
|
|
.DPRA4(DPRA4), // Read-only address[4] input bit
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM32X1D_1_inst instantiation
|
|
</Template>
|
|
<Template label="64 X 1 posedge write (RAM64X1D)" treetype="template">
|
|
// RAM64X1D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM64X1D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM64X1D: 64 x 1 positive edge write, asynchronous read dual-port distributed RAM (Mapped to a SliceM LUT6)
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM64X1D #(
|
|
.INIT(64'h0000000000000000) // Initial contents of RAM
|
|
) RAM64X1D_inst (
|
|
.DPO(DPO), // Read-only 1-bit data output
|
|
.SPO(SPO), // Rw/ 1-bit data output
|
|
.A0(A0), // Rw/ address[0] input bit
|
|
.A1(A1), // Rw/ address[1] input bit
|
|
.A2(A2), // Rw/ address[2] input bit
|
|
.A3(A3), // Rw/ address[3] input bit
|
|
.A4(A4), // Rw/ address[4] input bit
|
|
.A5(A5), // Rw/ address[5] input bit
|
|
.D(D), // Write 1-bit data input
|
|
.DPRA0(DPRA0), // Read-only address[0] input bit
|
|
.DPRA1(DPRA1), // Read-only address[1] input bit
|
|
.DPRA2(DPRA2), // Read-only address[2] input bit
|
|
.DPRA3(DPRA3), // Read-only address[3] input bit
|
|
.DPRA4(DPRA4), // Read-only address[4] input bit
|
|
.DPRA5(DPRA5), // Read-only address[5] input bit
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM64X1D_inst instantiation
|
|
</Template>
|
|
<Template label="128 X 1 posedge write (RAM128X1D)" treetype="template">
|
|
// RAM128X1D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM128X1D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM128X1D: 128-deep by 1-wide positive edge write, asynchronous read (Mapped to two SliceM LUT6s)
|
|
// dual-port distributed LUT RAM
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM128X1D #(
|
|
.INIT(128'h00000000000000000000000000000000)
|
|
) RAM128X1D_inst (
|
|
.DPO(DPO), // Read port 1-bit output
|
|
.SPO(SPO), // Read/write port 1-bit output
|
|
.A(A), // Read/write port 7-bit address input
|
|
.D(D), // RAM data input
|
|
.DPRA(DPRA), // Read port 7-bit address input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM128X1D_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Multi-Port" treetype="folder">
|
|
<Template label="32 X 8 (RAM32M)" treetype="template">
|
|
// RAM32M : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM32M_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM32M: 32-deep by 8-wide Multi Port LUT RAM (Mapped to four SliceM LUT6s)
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM32M #(
|
|
.INIT_A(64'h0000000000000000), // Initial contents of A Port
|
|
.INIT_B(64'h0000000000000000), // Initial contents of B Port
|
|
.INIT_C(64'h0000000000000000), // Initial contents of C Port
|
|
.INIT_D(64'h0000000000000000) // Initial contents of D Port
|
|
) RAM32M_inst (
|
|
.DOA(DOA), // Read port A 2-bit output
|
|
.DOB(DOB), // Read port B 2-bit output
|
|
.DOC(DOC), // Read port C 2-bit output
|
|
.DOD(DOD), // Read/write port D 2-bit output
|
|
.ADDRA(ADDRA), // Read port A 5-bit address input
|
|
.ADDRB(ADDRB), // Read port B 5-bit address input
|
|
.ADDRC(ADDRC), // Read port C 5-bit address input
|
|
.ADDRD(ADDRD), // Read/write port D 5-bit address input
|
|
.DIA(DIA), // RAM 2-bit data write input addressed by ADDRD,
|
|
// read addressed by ADDRA
|
|
.DIB(DIB), // RAM 2-bit data write input addressed by ADDRD,
|
|
// read addressed by ADDRB
|
|
.DIC(DIC), // RAM 2-bit data write input addressed by ADDRD,
|
|
// read addressed by ADDRC
|
|
.DID(DID), // RAM 2-bit data write input addressed by ADDRD,
|
|
// read addressed by ADDRD
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM32M_inst instantiation
|
|
</Template>
|
|
<Template label="64 X 4 (RAM64M)" treetype="template">
|
|
// RAM64M : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM64M_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM64M: 64-deep by 4-wide Multi Port LUT RAM (Mapped to four SliceM LUT6s)
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM64M #(
|
|
.INIT_A(64'h0000000000000000), // Initial contents of A Port
|
|
.INIT_B(64'h0000000000000000), // Initial contents of B Port
|
|
.INIT_C(64'h0000000000000000), // Initial contents of C Port
|
|
.INIT_D(64'h0000000000000000) // Initial contents of D Port
|
|
) RAM64M_inst (
|
|
.DOA(DOA), // Read port A 1-bit output
|
|
.DOB(DOB), // Read port B 1-bit output
|
|
.DOC(DOC), // Read port C 1-bit output
|
|
.DOD(DOD), // Read/write port D 1-bit output
|
|
.DIA(DIA), // RAM 1-bit data write input addressed by ADDRD,
|
|
// read addressed by ADDRA
|
|
.DIB(DIB), // RAM 1-bit data write input addressed by ADDRD,
|
|
// read addressed by ADDRB
|
|
.DIC(DIC), // RAM 1-bit data write input addressed by ADDRD,
|
|
// read addressed by ADDRC
|
|
.DID(DID), // RAM 1-bit data write input addressed by ADDRD,
|
|
// read addressed by ADDRD
|
|
.ADDRA(ADDRA), // Read port A 6-bit address input
|
|
.ADDRB(ADDRB), // Read port B 6-bit address input
|
|
.ADDRC(ADDRC), // Read port C 6-bit address input
|
|
.ADDRD(ADDRD), // Read/write port D 6-bit address input
|
|
.WE(WE), // Write enable input
|
|
.WCLK(WCLK) // Write clock input
|
|
);
|
|
|
|
// End of RAM64M_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Advanced" treetype="folder">
|
|
<Template label="Gigabit Transceiver Buffer (IBUFDS_GTE2)" treetype="template">
|
|
// IBUFDS_GTE2 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFDS_GTE2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFDS_GTE2: Gigabit Transceiver Buffer
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFDS_GTE2 #(
|
|
.CLKCM_CFG("TRUE"), // Refer to Transceiver User Guide
|
|
.CLKRCV_TRST("TRUE"), // Refer to Transceiver User Guide
|
|
.CLKSWING_CFG(2'b11) // Refer to Transceiver User Guide
|
|
)
|
|
IBUFDS_GTE2_inst (
|
|
.O(O), // 1-bit output: Refer to Transceiver User Guide
|
|
.ODIV2(ODIV2), // 1-bit output: Refer to Transceiver User Guide
|
|
.CEB(CEB), // 1-bit input: Refer to Transceiver User Guide
|
|
.I(I), // 1-bit input: Refer to Transceiver User Guide
|
|
.IB(IB) // 1-bit input: Refer to Transceiver User Guide
|
|
);
|
|
|
|
// End of IBUFDS_GTE2_inst instantiation
|
|
</Template>
|
|
<Template label="Xilinx Analog-to-Digital Converter (XADC)" treetype="template">
|
|
// XADC : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (XADC_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// XADC: Dual 12-Bit 1MSPS Analog-to-Digital Converter
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
XADC #(
|
|
// INIT_40 - INIT_42: XADC configuration registers
|
|
.INIT_40(16'h0000),
|
|
.INIT_41(16'h0000),
|
|
.INIT_42(16'h0800),
|
|
// INIT_48 - INIT_4F: Sequence Registers
|
|
.INIT_48(16'h0000),
|
|
.INIT_49(16'h0000),
|
|
.INIT_4A(16'h0000),
|
|
.INIT_4B(16'h0000),
|
|
.INIT_4C(16'h0000),
|
|
.INIT_4D(16'h0000),
|
|
.INIT_4F(16'h0000),
|
|
.INIT_4E(16'h0000), // Sequence register 6
|
|
// INIT_50 - INIT_58, INIT5C: Alarm Limit Registers
|
|
.INIT_50(16'h0000),
|
|
.INIT_51(16'h0000),
|
|
.INIT_52(16'h0000),
|
|
.INIT_53(16'h0000),
|
|
.INIT_54(16'h0000),
|
|
.INIT_55(16'h0000),
|
|
.INIT_56(16'h0000),
|
|
.INIT_57(16'h0000),
|
|
.INIT_58(16'h0000),
|
|
.INIT_5C(16'h0000),
|
|
// Simulation attributes: Set for proper simulation behavior
|
|
.SIM_DEVICE("7SERIES"), // Select target device (values)
|
|
.SIM_MONITOR_FILE(""design.txt"") // Analog simulation data file name
|
|
)
|
|
XADC_inst (
|
|
// ALARMS: 8-bit (each) output: ALM, OT
|
|
.ALM(ALM), // 8-bit output: Output alarm for temp, Vccint, Vccaux and Vccbram
|
|
.OT(OT), // 1-bit output: Over-Temperature alarm
|
|
// Dynamic Reconfiguration Port (DRP): 16-bit (each) output: Dynamic Reconfiguration Ports
|
|
.DO(DO), // 16-bit output: DRP output data bus
|
|
.DRDY(DRDY), // 1-bit output: DRP data ready
|
|
// STATUS: 1-bit (each) output: XADC status ports
|
|
.BUSY(BUSY), // 1-bit output: ADC busy output
|
|
.CHANNEL(CHANNEL), // 5-bit output: Channel selection outputs
|
|
.EOC(EOC), // 1-bit output: End of Conversion
|
|
.EOS(EOS), // 1-bit output: End of Sequence
|
|
.JTAGBUSY(JTAGBUSY), // 1-bit output: JTAG DRP transaction in progress output
|
|
.JTAGLOCKED(JTAGLOCKED), // 1-bit output: JTAG requested DRP port lock
|
|
.JTAGMODIFIED(JTAGMODIFIED), // 1-bit output: JTAG Write to the DRP has occurred
|
|
.MUXADDR(MUXADDR), // 5-bit output: External MUX channel decode
|
|
// Auxiliary Analog-Input Pairs: 16-bit (each) input: VAUXP[15:0], VAUXN[15:0]
|
|
.VAUXN(VAUXN), // 16-bit input: N-side auxiliary analog input
|
|
.VAUXP(VAUXP), // 16-bit input: P-side auxiliary analog input
|
|
// CONTROL and CLOCK: 1-bit (each) input: Reset, conversion start and clock inputs
|
|
.CONVST(CONVST), // 1-bit input: Convert start input
|
|
.CONVSTCLK(CONVSTCLK), // 1-bit input: Convert start input
|
|
.RESET(RESET), // 1-bit input: Active-high reset
|
|
// Dedicated Analog Input Pair: 1-bit (each) input: VP/VN
|
|
.VN(VN), // 1-bit input: N-side analog input
|
|
.VP(VP), // 1-bit input: P-side analog input
|
|
// Dynamic Reconfiguration Port (DRP): 7-bit (each) input: Dynamic Reconfiguration Ports
|
|
.DADDR(DADDR), // 7-bit input: DRP address bus
|
|
.DCLK(DCLK), // 1-bit input: DRP clock
|
|
.DEN(DEN), // 1-bit input: DRP enable signal
|
|
.DI(DI), // 16-bit input: DRP input data bus
|
|
.DWE(DWE) // 1-bit input: DRP write enable
|
|
);
|
|
|
|
// End of XADC_inst instantiation
|
|
</Template>
|
|
<Template label="XADC Simulation File" treetype="template">
|
|
// Must use valid headers on all columns
|
|
// Comments can be added to the stimulus file using '//'
|
|
|
|
TIME TEMP VCCAUX VCCINT VBRAM VP VN VAUXP[0] VAUXN[0]
|
|
00000 45 1.8 1.0 1.0 0.5 0.0 0.7 0.0
|
|
05000 85 1.77 1.01 1.01 0.3 0.0 0.2 0.0
|
|
|
|
// Time stamp data is in nano seconds (ns)
|
|
// Temperature is recorded in C (degrees centigrade)
|
|
// All other channels are recorded as V (Volts)
|
|
// Valid column headers are:
|
|
// TIME, TEMP, VCCAUX, VCCINT, VBRAM, VCCPINT, VCCPAUX, VCCDDRO, VP, VN,
|
|
// VAUXP[0], VAUXN[0],...............VAUXP[15], VAUXN[15]
|
|
// External analog inputs are differential so VP = 0.5 and VN = 0.1 the
|
|
// input on channel VP/VN in 0.5 - 0.1 = 0.4V
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Slice/CLB Primitives" treetype="folder">
|
|
<SubFolder label="MUXFx" treetype="folder">
|
|
<Template label="MUXF7" treetype="template">
|
|
// MUXF7 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF7_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF7: CLB MUX to tie two LUT6's together with general output
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF7 MUXF7_inst (
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie to LUT6 O6 pin)
|
|
.I1(I1), // Input (tie to LUT6 O6 pin)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF7_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF7_L" treetype="template">
|
|
// MUXF7_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF7_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF7_L: CLB MUX to tie two LUT6's together with local output
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF7_L MUXF7_L_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.I0(I0), // Input (tie to LUT6 O6 pin)
|
|
.I1(I1), // Input (tie to LUT6 O6 pin)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF7_L_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF7_D" treetype="template">
|
|
// MUXF7_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF7_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF7_D: CLB MUX to tie two LUT6's together with general and local outputs
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF7_D MUXF7_D_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie to LUT6 O6 pin)
|
|
.I1(I1), // Input (tie to LUT6 O6 pin)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF7_D_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF8" treetype="template">
|
|
// MUXF8 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF8_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF8: CLB MUX to tie two MUXF7's together with general output
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF8 MUXF8_inst (
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie to MUXF7 L/LO out)
|
|
.I1(I1), // Input (tie to MUXF7 L/LO out)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF8_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF8_L" treetype="template">
|
|
// MUXF8_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF8_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF8_L: CLB MUX to tie two MUXF7's together with local output
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF8_L MUXF8_L_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.I0(I0), // Input (tie to MUXF7 L/LO out)
|
|
.I1(I1), // Input (tie to MUXF7 L/LO out)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF8_L_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF8_D" treetype="template">
|
|
// MUXF8_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF8_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF8_D: CLB MUX to tie two MUXF7's together with general and local outputs
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF8_D MUXF8_D_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie to MUXF7 L/LO out)
|
|
.I1(I1), // Input (tie to MUXF7 L/LO out)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF8_D_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="LUTs" treetype="folder">
|
|
<SubFolder label="Info" treetype="folder">
|
|
<Template label="Info (LUT INIT)" treetype="template">
|
|
// The INIT parameter for the FPGA LUT primitive is what gives the LUT its
|
|
// logical value. By default this value is zero thus driving the output to a
|
|
// zero regardless of the input values (acting as a ground) however in most
|
|
// cases an new INIT value must be determined in order to specify the logic
|
|
// function for the LUT primitive. There are a few methods in which the LUT
|
|
// value can be determined and two of those methods will be discussed here.
|
|
//
|
|
// The Truth Table Method
|
|
// ----------------------
|
|
//
|
|
// A common method to determine the desired INIT value for a LUT is using a
|
|
// truth table. To do so, simply create a binary truth table of all possible
|
|
// inputs, specify the desired logic value of the output and then create the
|
|
// INIT string from those output values. An example is shown below:
|
|
//
|
|
// Example of determining an XOR INIT equation for a LUT4:
|
|
//
|
|
// _________________
|
|
// | I3 I2 I1 I0 | O |
|
|
// |-----------------|
|
|
// | 0 0 0 0 | 0 |\
|
|
// | 0 0 0 1 | 1 | \ = 4'b0110 = 4'h6 ---------------+
|
|
// | 0 0 1 0 | 1 | / |
|
|
// | 0 0 1 1 | 0 |/ |
|
|
// |-------------|---| |
|
|
// | 0 1 0 0 | 1 |\ |
|
|
// | 0 1 0 1 | 0 | \ = 4'b1001 = 4'h9 |
|
|
// | 0 1 1 0 | 0 | / |
|
|
// | 0 1 1 1 | 1 |/ |
|
|
// |-------------|---| INIT = 16'h6996
|
|
// | 1 0 0 0 | 1 |\ |
|
|
// | 1 0 0 1 | 0 | \ = 4'b0110 = 4'h9 |
|
|
// | 1 0 1 0 | 0 | / |
|
|
// | 1 0 1 1 | 1 |/ |
|
|
// |-------------|---| |
|
|
// | 1 1 0 0 | 0 |\ |
|
|
// | 1 1 0 1 | 1 | \ = 4'b1001 = 4'h6 ------------+
|
|
// | 1 1 1 0 | 1 | /
|
|
// | 1 1 1 1 | 0 |/
|
|
// -------------------
|
|
//
|
|
// Example of determining a 3-input AND gate:
|
|
//
|
|
// ______________
|
|
// | I2 I1 I0 | O |
|
|
// |--------------|
|
|
// | 0 0 0 | 0 |\
|
|
// | 0 0 1 | 0 | \ = 4'b0000 = 4'h0 --------------+
|
|
// | 0 1 0 | 0 | / |
|
|
// | 0 1 1 | 0 |/ |
|
|
// |----------|---| INIT = 8'h80
|
|
// | 1 0 0 | 0 |\ |
|
|
// | 1 0 1 | 0 | \ = 4'b1000 = 4'h8 -------------+
|
|
// | 1 1 0 | 0 | /
|
|
// | 1 1 1 | 1 |/
|
|
// ----------------
|
|
//
|
|
// The Equation Method
|
|
// -------------------
|
|
//
|
|
// Another method to determine the LUT value is to define parameters for each
|
|
// input to the LUT that correspond to their listed truth value and use those to
|
|
// build the logic equation you are after. This method is easier to understand
|
|
// once you have grasped the concept and more self-documenting that the above
|
|
// method however does require the code to first specify the appropriate
|
|
// parameters. See the example below.
|
|
//
|
|
// Example of specifying the equation (A and B) or (C and D) for a LUT4:
|
|
//
|
|
// The forllowing parameters are defined to allow for
|
|
// equation-based INIT specification.
|
|
parameter I0 = 16'haaaa;
|
|
parameter I1 = 16'hcccc;
|
|
parameter I2 = 16'hf0f0;
|
|
parameter I3 = 16'hff00;
|
|
|
|
// LUT4: 4-input Look-Up Table with general output (Mapped to a LUT6)
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT4 #(
|
|
.INIT((I0&I1)|(I2&I3)) // Specify LUT Contents
|
|
) LUT4_inst (
|
|
.O(O_LUT), // LUT general output
|
|
.I0(A), // LUT input
|
|
.I1(B), // LUT input
|
|
.I2(C), // LUT input
|
|
.I3(D) // LUT input
|
|
);
|
|
|
|
// End of LUT4_inst instantiation
|
|
|
|
// With the parameters specifying all possible cases for the truth table, a
|
|
// Verilog equation can be written to determine the end INIT value.
|
|
</Template>
|
|
<SubFolder label="INIT Parameters" treetype="folder">
|
|
<Template label="LUT1" treetype="template">
|
|
// The forllowing parameter is defined to allow for
|
|
// equation-based INIT specification for a LUT1.
|
|
parameter I0 = 2'b10;
|
|
</Template>
|
|
<Template label="LUT2" treetype="template">
|
|
// The forllowing parameters are defined to allow for
|
|
// equation-based INIT specification for a LUT2.
|
|
parameter I0 = 4'ha;
|
|
parameter I1 = 4'hc;
|
|
</Template>
|
|
<Template label="LUT3" treetype="template">
|
|
// The forllowing parameters are defined to allow for
|
|
// equation-based INIT specification for a LUT3.
|
|
parameter I0 = 8'haa;
|
|
parameter I1 = 8'hcc;
|
|
parameter I2 = 8'hf0;
|
|
</Template>
|
|
<Template label="LUT4" treetype="template">
|
|
// The forllowing parameters are defined to allow for
|
|
// equation-based INIT specification for a LUT4.
|
|
parameter I0 = 16'haaaa;
|
|
parameter I1 = 16'hcccc;
|
|
parameter I2 = 16'hf0f0;
|
|
parameter I3 = 16'hff00;
|
|
</Template>
|
|
<Template label="LUT5" treetype="template">
|
|
// The forllowing parameters are defined to allow for
|
|
// equation-based INIT specification for a LUT5.
|
|
parameter I0 = 32'haaaaaaaa;
|
|
parameter I1 = 32'hcccccccc;
|
|
parameter I2 = 32'hf0f0f0f0;
|
|
parameter I3 = 32'hff00ff00;
|
|
parameter I4 = 32'hffff0000;
|
|
</Template>
|
|
<Template label="LUT6" treetype="template">
|
|
// The forllowing parameters are defined to allow for
|
|
// equation-based INIT specification for a LUT6.
|
|
parameter I0 = 64'haaaaaaaaaaaaaaaa;
|
|
parameter I1 = 64'hcccccccccccccccc;
|
|
parameter I2 = 64'hf0f0f0f0f0f0f0f0;
|
|
parameter I3 = 64'hff00ff00ff00ff00;
|
|
parameter I4 = 64'hffff0000ffff0000;
|
|
parameter I5 = 64'hffffffff00000000;
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="INIT Truth Tables" treetype="folder">
|
|
<Template label="LUT1" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT1
|
|
// ________
|
|
// | I0 | O |
|
|
// |--------|
|
|
// | 0 | ? |\
|
|
// | 1 | ? |/ = 2'b??
|
|
// ----------
|
|
</Template>
|
|
<Template label="LUT2" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT2
|
|
// ______________
|
|
// | I2 I1 I0 | O |
|
|
// |--------------|
|
|
// | 0 0 0 | ? |\
|
|
// | 0 0 1 | ? | \ = INIT = 4'b???? = 4'h?
|
|
// | 0 1 0 | ? | /
|
|
// | 0 1 1 | ? |/
|
|
// ---------- ---
|
|
</Template>
|
|
<Template label="LUT3" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT3
|
|
// ______________
|
|
// | I2 I1 I0 | O |
|
|
// |--------------|
|
|
// | 0 0 0 | ? |\
|
|
// | 0 0 1 | ? | \ = 4'b???? = 4'h? --------------+
|
|
// | 0 1 0 | ? | / |
|
|
// | 0 1 1 | ? |/ |
|
|
// |----------|---| INIT = 8'h??
|
|
// | 1 0 0 | ? |\ |
|
|
// | 1 0 1 | ? | \ = 4'b???? = 4'h? -------------+
|
|
// | 1 1 0 | ? | /
|
|
// | 1 1 1 | ? |/
|
|
// ----------------
|
|
</Template>
|
|
<Template label="LUT4" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT4
|
|
// _________________
|
|
// | I3 I2 I1 I0 | O |
|
|
// |-----------------|
|
|
// | 0 0 0 0 | ? |\
|
|
// | 0 0 0 1 | ? | \ = 4'b???? = 4'h? ---------------+
|
|
// | 0 0 1 0 | ? | / |
|
|
// | 0 0 1 1 | ? |/ |
|
|
// |-------------|---| |
|
|
// | 0 1 0 0 | ? |\ |
|
|
// | 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 1 0 | ? | / |
|
|
// | 0 1 1 1 | ? |/ |
|
|
// |-------------|---| INIT = 16'h????
|
|
// | 1 0 0 0 | ? |\ |
|
|
// | 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 1 0 | ? | / |
|
|
// | 1 0 1 1 | ? |/ |
|
|
// |-------------|---| |
|
|
// | 1 1 0 0 | ? |\ |
|
|
// | 1 1 0 1 | ? | \ = 4'b???? = 4'h? ------------+
|
|
// | 1 1 1 0 | ? | /
|
|
// | 1 1 1 1 | ? |/
|
|
// -------------------
|
|
</Template>
|
|
<Template label="LUT5" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT5
|
|
// ____________________
|
|
// | I4 I3 I2 I1 I0 | O |
|
|
// |--------------------|
|
|
// | 0 0 0 0 0 | ? |\
|
|
// | 0 0 0 0 1 | ? | \ = 4'b???? = 4'h? -------------------+
|
|
// | 0 0 0 1 0 | ? | / |
|
|
// | 0 0 0 1 1 | ? |/ |
|
|
// |----------------|---| |
|
|
// | 0 0 1 0 0 | ? |\ |
|
|
// | 0 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 0 1 1 0 | ? | / |
|
|
// | 0 0 1 1 1 | ? |/ |
|
|
// |----------------|---| |
|
|
// | 0 1 0 0 0 | ? |\ |
|
|
// | 0 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 0 1 0 | ? | / |
|
|
// | 0 1 0 1 1 | ? |/ |
|
|
// |----------------|---| |
|
|
// | 0 1 1 0 0 | ? |\ |
|
|
// | 0 1 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 1 1 0 | ? | / |
|
|
// | 0 1 1 1 1 | ? |/ |
|
|
// ---------------------- INIT = 32'h????????
|
|
// | 1 0 0 0 0 | ? |\ |
|
|
// | 1 0 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 0 1 0 | ? | / |
|
|
// | 1 0 0 1 1 | ? |/ |
|
|
// |----------------|---| |
|
|
// | 1 0 1 0 0 | ? |\ |
|
|
// | 1 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 1 1 0 | ? | / |
|
|
// | 1 0 1 1 1 | ? |/ |
|
|
// |----------------|---| |
|
|
// | 1 1 0 0 0 | ? |\ |
|
|
// | 1 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 1 0 1 0 | ? | / |
|
|
// | 1 1 0 1 1 | ? |/ |
|
|
// |----------------|---| |
|
|
// | 1 1 1 0 0 | ? |\ |
|
|
// | 1 1 1 0 1 | ? | \ = 4'b???? = 4'h? ------------+
|
|
// | 1 1 1 1 0 | ? | /
|
|
// | 1 1 1 1 1 | ? |/
|
|
// ----------------------
|
|
</Template>
|
|
<Template label="LUT6" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT6
|
|
// _______________________
|
|
// | I5 I4 I3 I2 I1 I0 | O |
|
|
// |-----------------------|
|
|
// | 0 0 0 0 0 0 | ? |\
|
|
// | 0 0 0 0 0 1 | ? | \ = 4'b???? = 4'h? -------------------+
|
|
// | 0 0 0 0 1 0 | ? | / |
|
|
// | 0 0 0 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 0 0 0 1 0 0 | ? |\ |
|
|
// | 0 0 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 0 0 1 1 0 | ? | / |
|
|
// | 0 0 0 1 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 0 0 1 0 0 0 | ? |\ |
|
|
// | 0 0 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 0 1 0 1 0 | ? | / |
|
|
// | 0 0 1 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 0 0 1 1 0 0 | ? |\ |
|
|
// | 0 0 1 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 0 1 1 1 0 | ? | / |
|
|
// | 0 0 1 1 1 1 | ? |/ |
|
|
// ------------------------- |
|
|
// | 0 1 0 0 0 0 | ? |\ |
|
|
// | 0 1 0 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 0 0 1 0 | ? | / |
|
|
// | 0 1 0 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 0 1 0 1 0 0 | ? |\ |
|
|
// | 0 1 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 0 1 1 0 | ? | / |
|
|
// | 0 1 0 1 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 0 1 1 0 0 0 | ? |\ |
|
|
// | 0 1 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 1 0 1 0 | ? | / |
|
|
// | 0 1 1 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 0 1 1 1 0 0 | ? |\ |
|
|
// | 0 1 1 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 1 1 1 0 | ? | / |
|
|
// | 0 1 1 1 1 1 | ? |/ |
|
|
// ------------------------ INIT = 64'h????????????????
|
|
// | 1 0 0 0 0 0 | ? |\ |
|
|
// | 1 0 0 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 0 0 1 0 | ? | / |
|
|
// | 1 0 0 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 0 0 1 0 0 | ? |\ |
|
|
// | 1 0 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 0 1 1 0 | ? | / |
|
|
// | 1 0 0 1 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 0 1 0 0 0 | ? |\ |
|
|
// | 1 0 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 1 0 1 0 | ? | / |
|
|
// | 1 0 1 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 0 1 1 0 0 | ? |\ |
|
|
// | 1 0 1 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 1 1 1 0 | ? | / |
|
|
// | 1 0 1 1 1 1 | ? |/ |
|
|
// ------------------------- |
|
|
// | 1 1 0 0 0 0 | ? |\ |
|
|
// | 1 1 0 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 1 0 0 1 0 | ? | / |
|
|
// | 1 1 0 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 1 0 1 0 0 | ? |\ |
|
|
// | 1 1 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 1 0 1 1 0 | ? | / |
|
|
// | 1 1 0 1 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 1 1 0 0 0 | ? |\ |
|
|
// | 1 1 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 1 1 0 1 0 | ? | / |
|
|
// | 1 1 1 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 1 1 1 0 0 | ? |\ |
|
|
// | 1 1 1 1 0 1 | ? | \ = 4'b???? = 4'h? ----+
|
|
// | 1 1 1 1 1 0 | ? | /
|
|
// | 1 1 1 1 1 1 | ? |/
|
|
// ------------------------
|
|
</Template>
|
|
<Template label="LUT6_2" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT6_2
|
|
// _____________________________
|
|
// | I5 I4 I3 I2 I1 I0 | O6 | O5 |
|
|
// |-----------------------------|
|
|
// | 0 0 0 0 0 0 | ? |\
|
|
// | 0 0 0 0 0 1 | ? | \ = 4'b???? = 4'h? -------------+
|
|
// | 0 0 0 0 1 0 | ? | / |
|
|
// | 0 0 0 0 1 1 | ? |/ |
|
|
// |-------------------|---------| |
|
|
// | 0 0 0 1 0 0 | ? |\ |
|
|
// | 0 0 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 0 0 1 1 0 | ? | / |
|
|
// | 0 0 0 1 1 1 | ? |/ |
|
|
// |-------------------|---------| |
|
|
// | 0 0 1 0 0 0 | ? |\ |
|
|
// | 0 0 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 0 1 0 1 0 | ? | / |
|
|
// | 0 0 1 0 1 1 | ? |/ |
|
|
// |-------------------|---------| |
|
|
// | 0 0 1 1 0 0 | ? |\ |
|
|
// | 0 0 1 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 0 1 1 1 0 | ? | / |
|
|
// | 0 0 1 1 1 1 | ? |/ |
|
|
// ------------------------------- |
|
|
// | 0 1 0 0 0 0 | ? |\ |
|
|
// | 0 1 0 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 0 0 1 0 | ? | / |
|
|
// | 0 1 0 0 1 1 | ? |/ |
|
|
// |-------------------|---------| |
|
|
// | 0 1 0 1 0 0 | ? |\ |
|
|
// | 0 1 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 0 1 1 0 | ? | / |
|
|
// | 0 1 0 1 1 1 | ? |/ |
|
|
// |-------------------|---------| |
|
|
// | 0 1 1 0 0 0 | ? |\ |
|
|
// | 0 1 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 1 0 1 0 | ? | / |
|
|
// | 0 1 1 0 1 1 | ? |/ |
|
|
// |-------------------|---------| |
|
|
// | 0 1 1 1 0 0 | ? |\ |
|
|
// | 0 1 1 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 1 1 1 0 | ? | / |
|
|
// | 0 1 1 1 1 1 | ? |/ |
|
|
// ------------------------------ INIT = 64'h????????????????
|
|
// | 1 0 0 0 0 0 | ? |\ |
|
|
// | 1 0 0 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 0 0 1 0 | ? | / |
|
|
// | 1 0 0 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 0 0 1 0 0 | ? |\ |
|
|
// | 1 0 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 0 1 1 0 | ? | / |
|
|
// | 1 0 0 1 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 0 1 0 0 0 | ? |\ |
|
|
// | 1 0 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 1 0 1 0 | ? | / |
|
|
// | 1 0 1 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 0 1 1 0 0 | ? |\ |
|
|
// | 1 0 1 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 1 1 1 0 | ? | / |
|
|
// | 1 0 1 1 1 1 | ? |/ |
|
|
// ------------------------- |
|
|
// | 1 1 0 0 0 0 | ? |\ |
|
|
// | 1 1 0 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 1 0 0 1 0 | ? | / |
|
|
// | 1 1 0 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 1 0 1 0 0 | ? |\ |
|
|
// | 1 1 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 1 0 1 1 0 | ? | / |
|
|
// | 1 1 0 1 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 1 1 0 0 0 | ? |\ |
|
|
// | 1 1 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 1 1 0 1 0 | ? | / |
|
|
// | 1 1 1 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 1 1 1 0 0 | ? |\ |
|
|
// | 1 1 1 1 0 1 | ? | \ = 4'b???? = 4'h? ----+
|
|
// | 1 1 1 1 1 0 | ? | /
|
|
// | 1 1 1 1 1 1 | ? |/
|
|
// ------------------------
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<Template label="LUT4" treetype="template">
|
|
// LUT4 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT4_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT4: 4-input Look-Up Table with general output (Mapped to a LUT6)
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT4 #(
|
|
.INIT(16'h0000) // Specify LUT Contents
|
|
) LUT4_inst (
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3) // LUT input
|
|
);
|
|
|
|
// End of LUT4_inst instantiation
|
|
</Template>
|
|
<Template label="LUT4_L" treetype="template">
|
|
// LUT4_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT4_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT4_L: 4-input Look-Up Table with local output (Mapped to a LUT6)
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT4_L #(
|
|
.INIT(16'h0000) // Specify LUT Contents
|
|
) LUT4_L_inst (
|
|
.LO(LO), // LUT local output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3) // LUT input
|
|
);
|
|
|
|
// End of LUT4_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT4_D" treetype="template">
|
|
// LUT4_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT4_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT4_D: 4-input Look-Up Table with general and local outputs (Mapped to a LUT6)
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT4_D #(
|
|
.INIT(16'h0000) // Specify LUT Contents
|
|
) LUT4_D_inst (
|
|
.LO(LO), // LUT local output
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3) // LUT input
|
|
);
|
|
|
|
// End of LUT4_D_inst instantiation
|
|
</Template>
|
|
<Template label="LUT3" treetype="template">
|
|
// LUT3 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT3_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT3: 3-input Look-Up Table with general output (Mapped to a LUT6)
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT3 #(
|
|
.INIT(8'h00) // Specify LUT Contents
|
|
) LUT3_inst (
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2) // LUT input
|
|
);
|
|
|
|
// End of LUT3_inst instantiation
|
|
</Template>
|
|
<Template label="LUT3_L" treetype="template">
|
|
// LUT3_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT3_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT3_L: 3-input Look-Up Table with local output (Mapped to a LUT6)
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT3_L #(
|
|
.INIT(8'h00) // Specify LUT Contents
|
|
) LUT3_L_inst (
|
|
.LO(LO), // LUT local output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2) // LUT input
|
|
);
|
|
|
|
// End of LUT3_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT3_D" treetype="template">
|
|
// LUT3_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT3_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT3_D: 3-input Look-Up Table with general and local outputs (Mapped to a LUT6)
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT3_D #(
|
|
.INIT(8'h00) // Specify LUT Contents
|
|
) LUT3_D_inst (
|
|
.LO(LO), // LUT local output
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2) // LUT input
|
|
);
|
|
|
|
// End of LUT3_D_inst instantiation
|
|
</Template>
|
|
<Template label="LUT2" treetype="template">
|
|
// LUT2 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT2: 2-input Look-Up Table with general output (Mapped to a LUT6)
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT2 #(
|
|
.INIT(4'h0) // Specify LUT Contents
|
|
) LUT2_inst (
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1) // LUT input
|
|
);
|
|
|
|
// End of LUT2_inst instantiation
|
|
</Template>
|
|
<Template label="LUT2_L" treetype="template">
|
|
// LUT2_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT2_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT2_L: 2-input Look-Up Table with local output (Mapped to a LUT6)
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT2_L #(
|
|
.INIT(4'h0) // Specify LUT Contents
|
|
) LUT2_L_inst (
|
|
.LO(LO), // LUT local output
|
|
.I0(I0), // LUT input
|
|
.I1(I1) // LUT input
|
|
);
|
|
|
|
// End of LUT2_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT2_D" treetype="template">
|
|
// LUT2_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT2_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT2_D: 2-input Look-Up Table with general and local outputs (Mapped to a LUT6)
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT2_D #(
|
|
.INIT(4'h0) // Specify LUT Contents
|
|
) LUT2_D_inst (
|
|
.LO(LO), // LUT local output
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1) // LUT input
|
|
);
|
|
|
|
// End of LUT2_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT1" treetype="template">
|
|
// LUT1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT1: 1-input Look-Up Table with general output (Mapped to a LUT6)
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT1 #(
|
|
.INIT(2'b00) // Specify LUT Contents
|
|
) LUT1_inst (
|
|
.O(O), // LUT general output
|
|
.I0(I0) // LUT input
|
|
);
|
|
|
|
// End of LUT1_inst instantiation
|
|
</Template>
|
|
<Template label="LUT1_L" treetype="template">
|
|
// LUT1_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT1_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT1_L: 1-input Look-Up Table with local output (Mapped to a LUT6)
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT1_L #(
|
|
.INIT(2'b00) // Specify LUT Contents
|
|
) LUT1_L_inst (
|
|
.LO(LO), // LUT local output
|
|
.I0(I0) // LUT input
|
|
);
|
|
|
|
// End of LUT1_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT1_D" treetype="template">
|
|
// LUT1_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT1_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT1_D: 1-input Look-Up Table with general and local outputs (Mapped to a LUT6)
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT1_D #(
|
|
.INIT(2'b00) // Specify LUT Contents
|
|
) LUT1_D_inst (
|
|
.LO(LO), // LUT local output
|
|
.O(O), // LUT general output
|
|
.I0(I0) // LUT input
|
|
);
|
|
|
|
// End of LUT1_D_inst instantiation
|
|
</Template>
|
|
<Template label="Reconfigurable LUT (CFGLUT5)" treetype="template">
|
|
// CFGLUT5 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (CFGLUT5_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// CFGLUT5: Reconfigurable 5-input LUT (Mapped to a SliceM LUT6)
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
CFGLUT5 #(
|
|
.INIT(32'h00000000) // Specify initial LUT contents
|
|
) CFGLUT5_inst (
|
|
.CDO(CDO), // Reconfiguration cascade output
|
|
.O5(O5), // 4-LUT output
|
|
.O6(O6), // 5-LUT output
|
|
.CDI(CDI), // Reconfiguration data input
|
|
.CE(CE), // Reconfiguration enable input
|
|
.CLK(CLK), // Clock input
|
|
.I0(I0), // Logic data input
|
|
.I1(I1), // Logic data input
|
|
.I2(I2), // Logic data input
|
|
.I3(I3), // Logic data input
|
|
.I4(I4) // Logic data input
|
|
);
|
|
|
|
// End of CFGLUT5_inst instantiation
|
|
</Template>
|
|
<Template label="LUT5" treetype="template">
|
|
// LUT5 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT5_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT5: 5-input Look-Up Table with general output (Mapped to a LUT6)
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT5 #(
|
|
.INIT(32'h00000000) // Specify LUT Contents
|
|
) LUT5_inst (
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3), // LUT input
|
|
.I4(I4) // LUT input
|
|
);
|
|
|
|
// End of LUT5_inst instantiation
|
|
</Template>
|
|
<Template label="LUT5_L" treetype="template">
|
|
// LUT5_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT5_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT5_L: 5-input Look-Up Table with local output (Mapped to a LUT6)
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT5_L #(
|
|
.INIT(32'h0000000) // Specify LUT Contents
|
|
) LUT5_L_inst (
|
|
.LO(LO), // LUT local output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3), // LUT input
|
|
.I4(I4) // LUT input
|
|
);
|
|
|
|
// End of LUT5_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT5_D" treetype="template">
|
|
// LUT5_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT5_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT5_D: 5-input Look-Up Table with general and local outputs (Mapped to a LUT6)
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT5_D #(
|
|
.INIT(32'h0000000) // Specify LUT Contents
|
|
) LUT5_D_inst (
|
|
.LO(LO), // LUT local output
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3), // LUT input
|
|
.I4(I4) // LUT input
|
|
);
|
|
|
|
// End of LUT5_D_inst instantiation
|
|
</Template>
|
|
<Template label="LUT6" treetype="template">
|
|
// LUT6 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT6_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT6: 6-input Look-Up Table with general output
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT6 #(
|
|
.INIT(64'h0000000000000000) // Specify LUT Contents
|
|
) LUT6_inst (
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3), // LUT input
|
|
.I4(I4), // LUT input
|
|
.I5(I5) // LUT input
|
|
);
|
|
|
|
// End of LUT6_inst instantiation
|
|
</Template>
|
|
<Template label="LUT6_L" treetype="template">
|
|
// LUT6_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT6_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT6_L: 6-input Look-Up Table with local output
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT6_L #(
|
|
.INIT(64'h0000000000000000) // Specify LUT Contents
|
|
) LUT6_L_inst (
|
|
.LO(LO), // LUT local output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3), // LUT input
|
|
.I4(I4), // LUT input
|
|
.I5(I5) // LUT input
|
|
);
|
|
|
|
// End of LUT6_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT6_D" treetype="template">
|
|
// LUT6_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT6_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT6_D: 6-input Look-Up Table with general and local outputs
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT6_D #(
|
|
.INIT(64'h0000000000000000) // Specify LUT Contents
|
|
) LUT6_D_inst (
|
|
.LO(LO), // LUT local output
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3), // LUT input
|
|
.I4(I4), // LUT input
|
|
.I5(I5) // LUT input
|
|
);
|
|
|
|
// End of LUT6_D_inst instantiation
|
|
</Template>
|
|
<Template label="LUT6_2" treetype="template">
|
|
// LUT6_2 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT6_2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT6_2: 6-input, 2 output Look-Up Table
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT6_2 #(
|
|
.INIT(64'h0000000000000000) // Specify LUT Contents
|
|
) LUT6_2_inst (
|
|
.O6(O6), // 1-bit LUT6 output
|
|
.O5(O5), // 1-bit lower LUT5 output
|
|
.I0(I0), // 1-bit LUT input
|
|
.I1(I1), // 1-bit LUT input
|
|
.I2(I2), // 1-bit LUT input
|
|
.I3(I3), // 1-bit LUT input
|
|
.I4(I4), // 1-bit LUT input
|
|
.I5(I5) // 1-bit LUT input (fast MUX select only available to O6 output)
|
|
);
|
|
|
|
// End of LUT6_2_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Shift Register LUT" treetype="folder">
|
|
<Template label="16-bit w/ CE posedge SR (SRL16E)" treetype="template">
|
|
// SRL16E : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SRL16E_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SRL16E: 16-bit shift register LUT with clock enable operating on posedge of clock (Mapped to a SliceM LUT6)
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SRL16E #(
|
|
.INIT(16'h0000) // Initial Value of Shift Register
|
|
) SRL16E_inst (
|
|
.Q(Q), // SRL data output
|
|
.A0(A0), // Select[0] input
|
|
.A1(A1), // Select[1] input
|
|
.A2(A2), // Select[2] input
|
|
.A3(A3), // Select[3] input
|
|
.CE(CE), // Clock enable input
|
|
.CLK(CLK), // Clock input
|
|
.D(D) // SRL data input
|
|
);
|
|
|
|
// End of SRL16E_inst instantiation
|
|
</Template>
|
|
<Template label="32-bit w/ CE posedge SR (SRLC32E)" treetype="template">
|
|
// SRLC32E : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SRL32E_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SRLC32E: 32-bit variable length cascadable shift register LUT (Mapped to a SliceM LUT6)
|
|
// with clock enable
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SRLC32E #(
|
|
.INIT(32'h00000000) // Initial Value of Shift Register
|
|
) SRLC32E_inst (
|
|
.Q(Q), // SRL data output
|
|
.Q31(Q31), // SRL cascade output pin
|
|
.A(A), // 5-bit shift depth select input
|
|
.CE(CE), // Clock enable input
|
|
.CLK(CLK), // Clock input
|
|
.D(D) // SRL data input
|
|
);
|
|
|
|
// End of SRLC32E_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<Template label="Carry (CARRY4)" treetype="template">
|
|
// CARRY4 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (CARRY4_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs and
|
|
// : and outputs of this primitive should be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// CARRY4: Fast Carry Logic Component
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
CARRY4 CARRY4_inst (
|
|
.CO(CO), // 4-bit carry out
|
|
.O(O), // 4-bit carry chain XOR data out
|
|
.CI(CI), // 1-bit carry cascade input
|
|
.CYINIT(CYINIT), // 1-bit carry initialization
|
|
.DI(DI), // 4-bit carry-MUX data in
|
|
.S(S) // 4-bit carry-MUX select input
|
|
);
|
|
|
|
// End of CARRY4_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Registers & Latches" treetype="folder">
|
|
<SubFolder label="Single Data Rate" treetype="folder">
|
|
<Template label="Posedge D-FF w/ Async Clear and CE (FDCE)" treetype="template">
|
|
// FDCE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FDCE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FDCE: Single Data Rate D Flip-Flop with Asynchronous Clear and
|
|
// Clock Enable (posedge clk).
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FDCE #(
|
|
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
|
|
) FDCE_inst (
|
|
.Q(Q), // 1-bit Data output
|
|
.C(C), // 1-bit Clock input
|
|
.CE(CE), // 1-bit Clock enable input
|
|
.CLR(CLR), // 1-bit Asynchronous clear input
|
|
.D(D) // 1-bit Data input
|
|
);
|
|
|
|
// End of FDCE_inst instantiation
|
|
</Template>
|
|
<Template label="Posedge D-FF w/ Async Preset and CE (FDPE)" treetype="template">
|
|
// FDPE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FDPE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FDPE: Single Data Rate D Flip-Flop with Asynchronous Preset and
|
|
// Clock Enable (posedge clk).
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FDPE #(
|
|
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
|
|
) FDPE_inst (
|
|
.Q(Q), // 1-bit Data output
|
|
.C(C), // 1-bit Clock input
|
|
.CE(CE), // 1-bit Clock enable input
|
|
.PRE(PRE), // 1-bit Asynchronous preset input
|
|
.D(D) // 1-bit Data input
|
|
);
|
|
|
|
// End of FDPE_inst instantiation
|
|
</Template>
|
|
<Template label="Posedge D-FF w/ Sync Reset and CE (FDRE)" treetype="template">
|
|
// FDRE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FDRE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FDRE: Single Data Rate D Flip-Flop with Synchronous Reset and
|
|
// Clock Enable (posedge clk).
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FDRE #(
|
|
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
|
|
) FDRE_inst (
|
|
.Q(Q), // 1-bit Data output
|
|
.C(C), // 1-bit Clock input
|
|
.CE(CE), // 1-bit Clock enable input
|
|
.R(R), // 1-bit Synchronous reset input
|
|
.D(D) // 1-bit Data input
|
|
);
|
|
|
|
// End of FDRE_inst instantiation
|
|
</Template>
|
|
<Template label="Posedge D-FF w/ Sync Set and CE (FDSE)" treetype="template">
|
|
// FDSE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FDSE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FDSE: Single Data Rate D Flip-Flop with Synchronous Set and
|
|
// Clock Enable (posedge clk).
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FDSE #(
|
|
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
|
|
) FDSE_inst (
|
|
.Q(Q), // 1-bit Data output
|
|
.C(C), // 1-bit Clock input
|
|
.CE(CE), // 1-bit Clock enable input
|
|
.S(S), // 1-bit Synchronous set input
|
|
.D(D) // 1-bit Data input
|
|
);
|
|
|
|
// End of FDSE_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Transparent Latch" treetype="folder">
|
|
<Template label="Latch with Async Reset and Gate Enable (LDCE)" treetype="template">
|
|
// LDCE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LDCE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LDCE: Transparent latch with Asynchronous Reset and Gate Enable.
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LDCE #(
|
|
.INIT(1'b0) // Initial value of latch (1'b0 or 1'b1)
|
|
) LDCE_inst (
|
|
.Q(Q), // Data output
|
|
.CLR(CLR), // Asynchronous clear/reset input
|
|
.D(D), // Data input
|
|
.G(G), // Gate input
|
|
.GE(GE) // Gate enable input
|
|
);
|
|
|
|
// End of LDCE_inst instantiation
|
|
</Template>
|
|
<Template label="Latch with Async Set and Gate Enable (LDPE)" treetype="template">
|
|
// LDPE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LDPE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LDPE: Transparent latch with Asynchronous Preset and Gate Enable.
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LDPE #(
|
|
.INIT(1'b1) // Initial value of latch (1'b0 or 1'b1)
|
|
) LDPE_inst (
|
|
.Q(Q), // Data output
|
|
.PRE(PRE), // Asynchronous preset/set input
|
|
.D(D), // Data input
|
|
.G(G), // Gate input
|
|
.GE(GE) // Gate enable input
|
|
);
|
|
|
|
// End of LDPE_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Double Data Rate" treetype="folder">
|
|
<Template label="Dual-Clock, Input DDR Register (IDDR_2CLK)" treetype="template">
|
|
// IDDR_2CLK : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IDDR_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IDDR_2CLK: Dual-Clock, Input Double Data Rate Input Register with
|
|
// Set, Reset and Clock Enable.
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IDDR_2CLK #(
|
|
.DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE", "SAME_EDGE"
|
|
// or "SAME_EDGE_PIPELINED"
|
|
.INIT_Q1(1'b0), // Initial value of Q1: 1'b0 or 1'b1
|
|
.INIT_Q2(1'b0), // Initial value of Q2: 1'b0 or 1'b1
|
|
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
|
|
) IDDR_2CLK_inst (
|
|
.Q1(Q1), // 1-bit output for positive edge of clock
|
|
.Q2(Q2), // 1-bit output for negative edge of clock
|
|
.C(C), // 1-bit primary clock input
|
|
.CB(CB), // 1-bit secondary clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.D(D), // 1-bit DDR data input
|
|
.R(R), // 1-bit reset
|
|
.S(S) // 1-bit set
|
|
);
|
|
|
|
// End of IDDR_2CLK_inst instantiation
|
|
</Template>
|
|
<Template label="Input DDR Register (IDDR)" treetype="template">
|
|
// IDDR : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IDDR_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IDDR: Input Double Data Rate Input Register with Set, Reset
|
|
// and Clock Enable.
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IDDR #(
|
|
.DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE", "SAME_EDGE"
|
|
// or "SAME_EDGE_PIPELINED"
|
|
.INIT_Q1(1'b0), // Initial value of Q1: 1'b0 or 1'b1
|
|
.INIT_Q2(1'b0), // Initial value of Q2: 1'b0 or 1'b1
|
|
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
|
|
) IDDR_inst (
|
|
.Q1(Q1), // 1-bit output for positive edge of clock
|
|
.Q2(Q2), // 1-bit output for negative edge of clock
|
|
.C(C), // 1-bit clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.D(D), // 1-bit DDR data input
|
|
.R(R), // 1-bit reset
|
|
.S(S) // 1-bit set
|
|
);
|
|
|
|
// End of IDDR_inst instantiation
|
|
</Template>
|
|
<Template label="Output DDR Register (ODDR)" treetype="template">
|
|
// ODDR : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ODDR_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ODDR: Output Double Data Rate Output Register with Set, Reset
|
|
// and Clock Enable.
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ODDR #(
|
|
.DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE"
|
|
.INIT(1'b0), // Initial value of Q: 1'b0 or 1'b1
|
|
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
|
|
) ODDR_inst (
|
|
.Q(Q), // 1-bit DDR output
|
|
.C(C), // 1-bit clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.D1(D1), // 1-bit data input (positive edge)
|
|
.D2(D2), // 1-bit data input (negative edge)
|
|
.R(R), // 1-bit reset
|
|
.S(S) // 1-bit set
|
|
);
|
|
|
|
// End of ODDR_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="CPLD" treetype="folder">
|
|
<SubFolder label="Clock Components" treetype="folder">
|
|
<SubFolder label="Clock Buffers" treetype="folder">
|
|
<Template label="Global Clock Buffer (BUFG)" treetype="template">
|
|
// BUFG : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFG_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFG: Global Clock Buffer (source by an internal signal)
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFG BUFG_inst (
|
|
.O(O), // Clock buffer output
|
|
.I(I) // Clock buffer input
|
|
);
|
|
|
|
// End of BUFG_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="CR-II Clock Divider" treetype="folder">
|
|
<SubFolder label="Divide by 2" treetype="folder">
|
|
<Template label="Simple Divider (CLK_DIV2)" treetype="template">
|
|
// CLK_DIV2 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (CLK_DIV2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// CLK_DIV2: Simple clock Divide by 2
|
|
// CoolRunner-II
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
CLK_DIV2 CLK_DIV2_inst (
|
|
.CLKDV(CLKDV), // Divided clock output
|
|
.CLKIN(CLKIN) // Clock input
|
|
);
|
|
|
|
// End of CLK_DIV2_inst instantiation
|
|
</Template>
|
|
<Template label="Divider w/ reset (CLK_DIV2R)" treetype="template">
|
|
// CLK_DIV2R : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (CLK_DIV2R_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// CLK_DIV2R: Clock Divide by 2 with synchronous reset
|
|
// CoolRunner-II
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
CLK_DIV2R CLK_DIV2R_inst (
|
|
.CLKDV(CLKDV), // Divided clock output
|
|
.CDRST(CDRST), // Synchronous reset input
|
|
.CLKIN(CLKIN) // Clock input
|
|
);
|
|
|
|
// End of CLK_DIV2R_inst instantiation
|
|
</Template>
|
|
<Template label="Divider w/ start delay (CLK_DIV2SD)" treetype="template">
|
|
// CLK_DIV2SD : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (CLK_DIV2SD_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// CLK_DIV2SD: Clock Divide by 2 with start delay
|
|
// CoolRunner-II
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
CLK_DIV2SD #(
|
|
.DIVIDER_DELAY(1) // Number of clock cycles to delay before starting
|
|
) CLK_DIV2SD_inst (
|
|
.CLKDV(CLKDV), // Divided clock output
|
|
.CDRST(CDRST), // Synchronous reset input
|
|
.CLKIN(CLKIN) // Clock input
|
|
);
|
|
|
|
// End of CLK_DIV2SD_inst instantiation
|
|
</Template>
|
|
<Template label="Divider w/ reset and delay (CLK_DIV2RSD)" treetype="template">
|
|
// CLK_DIV2RSD : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (CLK_DIV2RSD_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// CLK_DIV2RSD: Clock Divide by 2 with synchronous reset and start delay
|
|
// CoolRunner-II
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
CLK_DIV2RSD #(
|
|
.DIVIDER_DELAY(1) // Number of clock cycles to delay before starting
|
|
) CLK_DIV2RSD_inst (
|
|
.CLKDV(CLKDV), // Divided clock output
|
|
.CDRST(CDRST), // Synchronous reset input
|
|
.CLKIN(CLKIN) // Clock input
|
|
);
|
|
|
|
// End of CLK_DIV2RSD_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Divide by 4" treetype="folder">
|
|
<Template label="Simple Divider (CLK_DIV4)" treetype="template">
|
|
// CLK_DIV4 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (CLK_DIV4_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// CLK_DIV4: Simple clock Divide by 4
|
|
// CoolRunner-II
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
CLK_DIV4 CLK_DIV4_inst (
|
|
.CLKDV(CLKDV), // Divided clock output
|
|
.CLKIN(CLKIN) // Clock input
|
|
);
|
|
|
|
// End of CLK_DIV4_inst instantiation
|
|
</Template>
|
|
<Template label="Divider w/ reset (CLK_DIV4R)" treetype="template">
|
|
// CLK_DIV4R : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (CLK_DIV4R_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// CLK_DIV4R: Clock Divide by 4 with synchronous reset
|
|
// CoolRunner-II
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
CLK_DIV4R CLK_DIV4R_inst (
|
|
.CLKDV(CLKDV), // Divided clock output
|
|
.CDRST(CDRST), // Synchronous reset input
|
|
.CLKIN(CLKIN) // Clock input
|
|
);
|
|
|
|
// End of CLK_DIV4R_inst instantiation
|
|
</Template>
|
|
<Template label="Divider w/ start delay (CLK_DIV4SD)" treetype="template">
|
|
// CLK_DIV4SD : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (CLK_DIV4SD_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// CLK_DIV4SD: Clock Divide by 4 with start delay
|
|
// CoolRunner-II
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
CLK_DIV4SD #(
|
|
.DIVIDER_DELAY(1) // Number of clock cycles to delay before starting
|
|
) CLK_DIV4SD_inst (
|
|
.CLKDV(CLKDV), // Divided clock output
|
|
.CDRST(CDRST), // Synchronous reset input
|
|
.CLKIN(CLKIN) // Clock input
|
|
);
|
|
|
|
// End of CLK_DIV4SD_inst instantiation
|
|
</Template>
|
|
<Template label="Divider w/ reset and delay (CLK_DIV4RSD)" treetype="template">
|
|
// CLK_DIV4RSD : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (CLK_DIV4RSD_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// CLK_DIV4RSD: Clock Divide by 4 with synchronous reset and start delay
|
|
// CoolRunner-II
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
CLK_DIV4RSD #(
|
|
.DIVIDER_DELAY(1) // Number of clock cycles to delay before starting
|
|
) CLK_DIV4RSD_inst (
|
|
.CLKDV(CLKDV), // Divided clock output
|
|
.CDRST(CDRST), // Synchronous reset input
|
|
.CLKIN(CLKIN) // Clock input
|
|
);
|
|
|
|
// End of CLK_DIV4RSD_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Divide by 6" treetype="folder">
|
|
<Template label="Simple Divider (CLK_DIV6)" treetype="template">
|
|
// CLK_DIV6 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (CLK_DIV6_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// CLK_DIV6: Simple clock Divide by 6
|
|
// CoolRunner-II
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
CLK_DIV6 CLK_DIV6_inst (
|
|
.CLKDV(CLKDV), // Divided clock output
|
|
.CLKIN(CLKIN) // Clock input
|
|
);
|
|
|
|
// End of CLK_DIV6_inst instantiation
|
|
</Template>
|
|
<Template label="Divider w/ reset (CLK_DIV6R)" treetype="template">
|
|
// CLK_DIV6R : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (CLK_DIV6R_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// CLK_DIV6R: Clock Divide by 6 with synchronous reset
|
|
// CoolRunner-II
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
CLK_DIV6R CLK_DIV6R_inst (
|
|
.CLKDV(CLKDV), // Divided clock output
|
|
.CDRST(CDRST), // Synchronous reset input
|
|
.CLKIN(CLKIN) // Clock input
|
|
);
|
|
|
|
// End of CLK_DIV6R_inst instantiation
|
|
|
|
</Template>
|
|
<Template label="Divider w/ start delay (CLK_DIV6SD)" treetype="template">
|
|
// CLK_DIV6SD : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (CLK_DIV6SD_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// CLK_DIV6SD: Clock Divide by 6 with start delay
|
|
// CoolRunner-II
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
CLK_DIV6SD #(
|
|
.DIVIDER_DELAY(1) // Number of clock cycles to delay before starting
|
|
) CLK_DIV6SD_inst (
|
|
.CLKDV(CLKDV), // Divided clock output
|
|
.CDRST(CDRST), // Synchronous reset input
|
|
.CLKIN(CLKIN) // Clock input
|
|
);
|
|
|
|
// End of CLK_DIV6SD_inst instantiation
|
|
</Template>
|
|
<Template label="Divider w/ reset and delay (CLK_DIV6RSD)" treetype="template">
|
|
// CLK_DIV6RSD : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (CLK_DIV6RSD_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// CLK_DIV6RSD: Clock Divide by 6 with synchronous reset and start delay
|
|
// CoolRunner-II
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
CLK_DIV6RSD #(
|
|
.DIVIDER_DELAY(1) // Number of clock cycles to delay before starting
|
|
) CLK_DIV6RSD_inst (
|
|
.CLKDV(CLKDV), // Divided clock output
|
|
.CDRST(CDRST), // Synchronous reset input
|
|
.CLKIN(CLKIN) // Clock input
|
|
);
|
|
|
|
// End of CLK_DIV6RSD_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Divide by 8" treetype="folder">
|
|
<Template label="Simple Divider (CLK_DIV8)" treetype="template">
|
|
// CLK_DIV8 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (CLK_DIV8_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// CLK_DIV8: Simple clock Divide by 8
|
|
// CoolRunner-II
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
CLK_DIV8 CLK_DIV8_inst (
|
|
.CLKDV(CLKDV), // Divided clock output
|
|
.CLKIN(CLKIN) // Clock input
|
|
);
|
|
|
|
// End of CLK_DIV8_inst instantiation
|
|
</Template>
|
|
<Template label="Divider w/ reset (CLK_DIV8R)" treetype="template">
|
|
// CLK_DIV8R : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (CLK_DIV8R_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// CLK_DIV8R: Clock Divide by 8 with synchronous reset
|
|
// CoolRunner-II
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
CLK_DIV8R CLK_DIV8R_inst (
|
|
.CLKDV(CLKDV), // Divided clock output
|
|
.CDRST(CDRST), // Synchronous reset input
|
|
.CLKIN(CLKIN) // Clock input
|
|
);
|
|
|
|
// End of CLK_DIV8R_inst instantiation
|
|
</Template>
|
|
<Template label="Divider w/ start delay (CLK_DIV8SD)" treetype="template">
|
|
// CLK_DIV8SD : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (CLK_DIV8SD_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// CLK_DIV8SD: Clock Divide by 8 with start delay
|
|
// CoolRunner-II
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
CLK_DIV8SD #(
|
|
.DIVIDER_DELAY(1) // Number of clock cycles to delay before starting
|
|
) CLK_DIV8SD_inst (
|
|
.CLKDV(CLKDV), // Divided clock output
|
|
.CDRST(CDRST), // Synchronous reset input
|
|
.CLKIN(CLKIN) // Clock input
|
|
);
|
|
|
|
// End of CLK_DIV8SD_inst instantiation
|
|
</Template>
|
|
<Template label="Divider w/ reset and delay (CLK_DIV8RSD)" treetype="template">
|
|
// CLK_DIV8RSD : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (CLK_DIV8RSD_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// CLK_DIV8RSD: Clock Divide by 8 with synchronous reset and start delay
|
|
// CoolRunner-II
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
CLK_DIV8RSD #(
|
|
.DIVIDER_DELAY(1) // Number of clock cycles to delay before starting
|
|
) CLK_DIV8RSD_inst (
|
|
.CLKDV(CLKDV), // Divided clock output
|
|
.CDRST(CDRST), // Synchronous reset input
|
|
.CLKIN(CLKIN) // Clock input
|
|
);
|
|
|
|
// End of CLK_DIV8RSD_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Divide by 10" treetype="folder">
|
|
<Template label="Simple Divider (CLK_DIV10)" treetype="template">
|
|
// CLK_DIV10 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (CLK_DIV10_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// CLK_DIV10: Simple clock Divide by 10
|
|
// CoolRunner-II
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
CLK_DIV10 CLK_DIV10_inst (
|
|
.CLKDV(CLKDV), // Divided clock output
|
|
.CLKIN(CLKIN) // Clock input
|
|
);
|
|
|
|
// End of CLK_DIV10_inst instantiation
|
|
</Template>
|
|
<Template label="Divider w/ reset (CLK_DIV10R)" treetype="template">
|
|
// CLK_DIV10R : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (CLK_DIV10R_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// CLK_DIV10R: Clock Divide by 10 with synchronous reset
|
|
// CoolRunner-II
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
CLK_DIV10R CLK_DIV10R_inst (
|
|
.CLKDV(CLKDV), // Divided clock output
|
|
.CDRST(CDRST), // Synchronous reset input
|
|
.CLKIN(CLKIN) // Clock input
|
|
);
|
|
|
|
// End of CLK_DIV10R_inst instantiation
|
|
</Template>
|
|
<Template label="Divider w/ start delay (CLK_DIV10SD)" treetype="template">
|
|
// CLK_DIV10SD : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (CLK_DIV10SD_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// CLK_DIV10SD: Clock Divide by 10 with start delay
|
|
// CoolRunner-II
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
CLK_DIV10SD #(
|
|
.DIVIDER_DELAY(1) // Number of clock cycles to delay before starting
|
|
) CLK_DIV10SD_inst (
|
|
.CLKDV(CLKDV), // Divided clock output
|
|
.CDRST(CDRST), // Synchronous reset input
|
|
.CLKIN(CLKIN) // Clock input
|
|
);
|
|
|
|
// End of CLK_DIV10SD_inst instantiation
|
|
</Template>
|
|
<Template label="Divider w/ reset and delay (CLK_DIV10RSD)" treetype="template">
|
|
// CLK_DIV10RSD : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (CLK_DIV10RSD_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// CLK_DIV10RSD: Clock Divide by 10 with synchronous reset and start delay
|
|
// CoolRunner-II
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
CLK_DIV10RSD #(
|
|
.DIVIDER_DELAY(1) // Number of clock cycles to delay before starting
|
|
) CLK_DIV10RSD_inst (
|
|
.CLKDV(CLKDV), // Divided clock output
|
|
.CDRST(CDRST), // Synchronous reset input
|
|
.CLKIN(CLKIN) // Clock input
|
|
);
|
|
|
|
// End of CLK_DIV10RSD_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Divide by 12" treetype="folder">
|
|
<Template label="Simple Divider (CLK_DIV12)" treetype="template">
|
|
|
|
// CLK_DIV12 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (CLK_DIV12_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// CLK_DIV12: Simple clock Divide by 12
|
|
// CoolRunner-II
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
CLK_DIV12 CLK_DIV12_inst (
|
|
.CLKDV(CLKDV), // Divided clock output
|
|
.CLKIN(CLKIN) // Clock input
|
|
);
|
|
|
|
// End of CLK_DIV12_inst instantiation
|
|
</Template>
|
|
<Template label="Divider w/ reset (CLK_DIV12R)" treetype="template">
|
|
// CLK_DIV12R : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (CLK_DIV12R_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// CLK_DIV12R: Clock Divide by 12 with synchronous reset
|
|
// CoolRunner-II
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
CLK_DIV12R CLK_DIV12R_inst (
|
|
.CLKDV(CLKDV), // Divided clock output
|
|
.CDRST(CDRST), // Synchronous reset input
|
|
.CLKIN(CLKIN) // Clock input
|
|
);
|
|
|
|
// End of CLK_DIV12R_inst instantiation
|
|
</Template>
|
|
<Template label="Divider w/ start delay (CLK_DIV12SD)" treetype="template">
|
|
// CLK_DIV12SD : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (CLK_DIV12SD_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// CLK_DIV12SD: Clock Divide by 12 with start delay
|
|
// CoolRunner-II
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
CLK_DIV12SD #(
|
|
.DIVIDER_DELAY(1) // Number of clock cycles to delay before starting
|
|
) CLK_DIV12SD_inst (
|
|
.CLKDV(CLKDV), // Divided clock output
|
|
.CDRST(CDRST), // Synchronous reset input
|
|
.CLKIN(CLKIN) // Clock input
|
|
);
|
|
|
|
// End of CLK_DIV12SD_inst instantiation
|
|
</Template>
|
|
<Template label="Divider w/ reset and delay (CLK_DIV12RSD)" treetype="template">
|
|
// CLK_DIV12RSD : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (CLK_DIV12RSD_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// CLK_DIV12RSD: Clock Divide by 12 with synchronous reset and start delay
|
|
// CoolRunner-II
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
CLK_DIV12RSD #(
|
|
.DIVIDER_DELAY(1) // Number of clock cycles to delay before starting
|
|
) CLK_DIV12RSD_inst (
|
|
.CLKDV(CLKDV), // Divided clock output
|
|
.CDRST(CDRST), // Synchronous reset input
|
|
.CLKIN(CLKIN) // Clock input
|
|
);
|
|
|
|
// End of CLK_DIV12RSD_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Divide by 14" treetype="folder">
|
|
<Template label="Simple Divider (CLK_DIV14)" treetype="template">
|
|
// CLK_DIV14 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (CLK_DIV14_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// CLK_DIV14: Simple clock Divide by 14
|
|
// CoolRunner-II
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
CLK_DIV14 CLK_DIV14_inst (
|
|
.CLKDV(CLKDV), // Divided clock output
|
|
.CLKIN(CLKIN) // Clock input
|
|
);
|
|
|
|
// End of CLK_DIV14_inst instantiation
|
|
</Template>
|
|
<Template label="Divider w/ reset (CLK_DIV14R)" treetype="template">
|
|
// CLK_DIV14R : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (CLK_DIV14R_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// CLK_DIV14R: Clock Divide by 14 with synchronous reset
|
|
// CoolRunner-II
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
CLK_DIV14R CLK_DIV14R_inst (
|
|
.CLKDV(CLKDV), // Divided clock output
|
|
.CDRST(CDRST), // Synchronous reset input
|
|
.CLKIN(CLKIN) // Clock input
|
|
);
|
|
|
|
// End of CLK_DIV14R_inst instantiation
|
|
</Template>
|
|
<Template label="Divider w/ start delay (CLK_DIV14SD)" treetype="template">
|
|
// CLK_DIV14SD : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (CLK_DIV14SD_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// CLK_DIV14SD: Clock Divide by 14 with start delay
|
|
// CoolRunner-II
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
CLK_DIV14SD #(
|
|
.DIVIDER_DELAY(1) // Number of clock cycles to delay before starting
|
|
) CLK_DIV14SD_inst (
|
|
.CLKDV(CLKDV), // Divided clock output
|
|
.CDRST(CDRST), // Synchronous reset input
|
|
.CLKIN(CLKIN) // Clock input
|
|
);
|
|
|
|
// End of CLK_DIV14SD_inst instantiation
|
|
</Template>
|
|
<Template label="Divider w/ reset and delay (CLK_DIV14RSD)" treetype="template">
|
|
// CLK_DIV14RSD : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (CLK_DIV14RSD_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// CLK_DIV14RSD: Clock Divide by 14 with synchronous reset and start delay
|
|
// CoolRunner-II
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
CLK_DIV14RSD #(
|
|
.DIVIDER_DELAY(1) // Number of clock cycles to delay before starting
|
|
) CLK_DIV14RSD_inst (
|
|
.CLKDV(CLKDV), // Divided clock output
|
|
.CDRST(CDRST), // Synchronous reset input
|
|
.CLKIN(CLKIN) // Clock input
|
|
);
|
|
|
|
// End of CLK_DIV14RSD_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Divide by 16" treetype="folder">
|
|
<Template label="Simple Divider (CLK_DIV16)" treetype="template">
|
|
// CLK_DIV16 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (CLK_DIV16_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// CLK_DIV16: Simple clock Divide by 16
|
|
// CoolRunner-II
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
CLK_DIV16 CLK_DIV16_inst (
|
|
.CLKDV(CLKDV), // Divided clock output
|
|
.CLKIN(CLKIN) // Clock input
|
|
);
|
|
|
|
// End of CLK_DIV16_inst instantiation
|
|
</Template>
|
|
<Template label="Divider w/ reset (CLK_DIV16R)" treetype="template">
|
|
// CLK_DIV16R : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (CLK_DIV16R_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// CLK_DIV16R: Clock Divide by 16 with synchronous reset
|
|
// CoolRunner-II
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
CLK_DIV16R CLK_DIV16R_inst (
|
|
.CLKDV(CLKDV), // Divided clock output
|
|
.CDRST(CDRST), // Synchronous reset input
|
|
.CLKIN(CLKIN) // Clock input
|
|
);
|
|
|
|
// End of CLK_DIV16R_inst instantiation
|
|
</Template>
|
|
<Template label="Divider w/ start delay (CLK_DIV16SD)" treetype="template">
|
|
// CLK_DIV16SD : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (CLK_DIV16SD_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// CLK_DIV16SD: Clock Divide by 16 with start delay
|
|
// CoolRunner-II
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
CLK_DIV16SD #(
|
|
.DIVIDER_DELAY(1) // Number of clock cycles to delay before starting
|
|
) CLK_DIV16SD_inst (
|
|
.CLKDV(CLKDV), // Divided clock output
|
|
.CDRST(CDRST), // Synchronous reset input
|
|
.CLKIN(CLKIN) // Clock input
|
|
);
|
|
// End of CLK_DIV16SD_inst instantiation
|
|
</Template>
|
|
<Template label="Divider w/ reset and delay (CLK_DIV16RSD)" treetype="template">
|
|
// CLK_DIV16RSD : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (CLK_DIV16RSD_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// CLK_DIV16RSD: Clock Divide by 16 with synchronous reset and start delay
|
|
// CoolRunner-II
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
CLK_DIV16RSD #(
|
|
.DIVIDER_DELAY(1) // Number of clock cycles to delay before starting
|
|
) CLK_DIV16RSD_inst (
|
|
.CLKDV(CLKDV), // Divided clock output
|
|
.CDRST(CDRST), // Synchronous reset input
|
|
.CLKIN(CLKIN) // Clock input
|
|
);
|
|
|
|
// End of CLK_DIV16RSD_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="I/O Components" treetype="folder">
|
|
<SubFolder label="Input" treetype="folder">
|
|
<Template label="Single-ended Buffer (IBUF)" treetype="template">
|
|
// IBUF : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUF_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUF: Single-ended Input Buffer
|
|
// All devices
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUF #(
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
) IBUF_inst (
|
|
.O(O), // Buffer output
|
|
.I(I) // Buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUF_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Output" treetype="folder">
|
|
<Template label="Single-ended Buffer (OBUF)" treetype="template">
|
|
// OBUF : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OBUF_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OBUF: Single-ended Output Buffer
|
|
// All devices
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OBUF #(
|
|
.SLEW("SLOW") // Specify the output slew rate
|
|
) OBUF_inst (
|
|
.O(O), // Buffer output (connect directly to top-level port)
|
|
.I(I) // Buffer input
|
|
);
|
|
|
|
// End of OBUF_inst instantiation
|
|
</Template>
|
|
<Template label="Single-ended 3-state Buffer (OBUFT)" treetype="template">
|
|
// OBUFT : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OBUFT_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OBUFT: Single-ended 3-state Output Buffer
|
|
// All devices
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OBUFT OBUFT_inst (
|
|
.O(O), // Buffer output (connect directly to top-level port)
|
|
.I(I), // Buffer input
|
|
.T(T) // 3-state enable input
|
|
);
|
|
|
|
// End of OBUFT_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Bi-directional" treetype="folder">
|
|
<Template label="Single-ended Buffer (IOBUFE)" treetype="template">
|
|
// IOBUFE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IOBUFE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IOBUFE: Single-ended Bi-directional Buffer
|
|
// CPLDs
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IOBUFE IOBUFE_inst (
|
|
.O(O), // Buffer output
|
|
.IO(IO), // Buffer inout port (connect directly to top-level port)
|
|
.I(I), // Buffer input
|
|
.E(E) // 3-state enable input
|
|
);
|
|
|
|
// End of IOBUFE_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Weak drivers" treetype="folder">
|
|
<Template label="PULLUP" treetype="template">
|
|
// PULLUP : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (PULLUP_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// PULLUP: I/O Buffer Weak Pull-up
|
|
// All FPGA, CoolRunner-II
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
PULLUP PULLUP_inst (
|
|
.O(O) // Pullup output (connect directly to top-level port)
|
|
);
|
|
|
|
// End of PULLUP_inst instantiation
|
|
</Template>
|
|
<Template label="KEEPER" treetype="template">
|
|
// KEEPER : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (KEEPER_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// KEEPER: I/O Buffer Weak Keeper
|
|
// All FPGA, CoolRunner-II
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
KEEPER KEEPER_inst (
|
|
.O(O) // Keeper output (connect directly to top-level port)
|
|
);
|
|
|
|
// End of KEEPER_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Registers & Latches" treetype="folder">
|
|
<SubFolder label="Double Data Rate (CR-II)" treetype="folder">
|
|
<Template label="D-FF w/ Async Clear, Set and CE (FDDCPE)" treetype="template">
|
|
// FDDCPE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FDDCPE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FDDCPE: Double Data Rate Register with Asynchronous Clear and Set
|
|
// and Clock Enable (Clear has priority).
|
|
// CoolRunner-II
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FDDCPE FDDCPE_inst (
|
|
.Q(Q), // Data output
|
|
.C(C), // Clock input
|
|
.CE(CE), // Clock enable input
|
|
.CLR(CLR), // Asynchronous clear input
|
|
.D(D), // Data input
|
|
.PRE(PRE) // Asynchronous set input
|
|
);
|
|
|
|
// End of FDDCPE_inst instantiation
|
|
</Template>
|
|
<Template label="T-FF w/ Async Clear, Set, Load and CE (FTDCPLE)" treetype="template">
|
|
// FTDCPLE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FTDCPLE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FTDCPLE: Double Data Rate T Flip-Flop with Asynchronous Clear, Set,
|
|
// Load and Clock Enable (Clear has priority).
|
|
// CoolRunner-II
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FTDCPLE FTDCPLE_inst (
|
|
.Q(Q), // Data output
|
|
.C(C), // Clock input
|
|
.CE(CE), // Clock enable input
|
|
.CLR(CLR), // Asynchronous clear input
|
|
.D(D), // Load data input
|
|
.L(L), // Load enable input
|
|
.PRE(PRE), // Asynchronous set input
|
|
.T(T) // T data input
|
|
);
|
|
|
|
// End of FTDCPLE_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Single Data Rate" treetype="folder">
|
|
<Template label="Posedge D-FF w/ Async Clear, Set and CE (FDCPE)" treetype="template">
|
|
// FDCPE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FDCPE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FDCPE: Single Data Rate D Flip-Flop with Asynchronous Clear, Set and
|
|
// Clock Enable (posedge clk).
|
|
// Virtex-4/5, Spartan-3/3E/3A/3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FDCPE #(
|
|
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
|
|
) FDCPE_inst (
|
|
.Q(Q), // Data output
|
|
.C(C), // Clock input
|
|
.CE(CE), // Clock enable input
|
|
.CLR(CLR), // Asynchronous clear input
|
|
.D(D), // Data input
|
|
.PRE(PRE) // Asynchronous set input
|
|
);
|
|
|
|
// End of FDCPE_inst instantiation
|
|
</Template>
|
|
<Template label="Posedge D-FF w/ Async Clear, and CE (FDCE)" treetype="template">
|
|
// FDCE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FDCE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FDCE: Single Data Rate D Flip-Flop with Asynchronous Clear and
|
|
// Clock Enable (posedge clk).
|
|
// All families.
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FDCE #(
|
|
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
|
|
) FDCE_inst (
|
|
.Q(Q), // Data output
|
|
.C(C), // Clock input
|
|
.CE(CE), // Clock enable input
|
|
.CLR(CLR), // Asynchronous clear input
|
|
.D(D) // Data input
|
|
);
|
|
|
|
// End of FDCE_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Kintex-7" treetype="folder">
|
|
<SubFolder label="Config/BSCAN Components" treetype="folder">
|
|
<Template label="Boundary-Scan User Instruction (BSCANE2)" treetype="template">
|
|
// BSCANE2 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BSCANE2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BSCANE2: Boundary-Scan User Instruction
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BSCANE2 #(
|
|
.JTAG_CHAIN(1) // Value for USER command.
|
|
)
|
|
BSCANE2_inst (
|
|
.CAPTURE(CAPTURE), // 1-bit output: CAPTURE output from TAP controller.
|
|
.DRCK(DRCK), // 1-bit output: Gated TCK output. When SEL is asserted, DRCK toggles when CAPTURE or
|
|
// SHIFT are asserted.
|
|
|
|
.RESET(RESET), // 1-bit output: Reset output for TAP controller.
|
|
.RUNTEST(RUNTEST), // 1-bit output: Output asserted when TAP controller is in Run Test/Idle state.
|
|
.SEL(SEL), // 1-bit output: USER instruction active output.
|
|
.SHIFT(SHIFT), // 1-bit output: SHIFT output from TAP controller.
|
|
.TCK(TCK), // 1-bit output: Test Clock output. Fabric connection to TAP Clock pin.
|
|
.TDI(TDI), // 1-bit output: Test Data Input (TDI) output from TAP controller.
|
|
.TMS(TMS), // 1-bit output: Test Mode Select output. Fabric connection to TAP.
|
|
.UPDATE(UPDATE), // 1-bit output: UPDATE output from TAP controller
|
|
.TDO(TDO) // 1-bit input: Test Data Output (TDO) input for USER function.
|
|
);
|
|
|
|
// End of BSCANE2_inst instantiation
|
|
</Template>
|
|
<Template label="Register Capture (CAPTUREE2)" treetype="template">
|
|
// CAPTUREE2 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (CAPTUREE2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// CAPTUREE2: Register Capture
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
CAPTUREE2 #(
|
|
.ONESHOT("TRUE") // Specifies the procedure for performing single readback per CAP trigger.
|
|
)
|
|
CAPTUREE2_inst (
|
|
.CAP(CAP), // 1-bit input: Capture Input
|
|
.CLK(CLK) // 1-bit input: Clock Input
|
|
);
|
|
|
|
// End of CAPTUREE2_inst instantiation
|
|
</Template>
|
|
<Template label="Device DNA Access Port (DNA_PORT)" treetype="template">
|
|
// DNA_PORT : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (DNA_PORT_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// DNA_PORT: Device DNA Access Port
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
DNA_PORT #(
|
|
.SIM_DNA_VALUE(57'h000000000000000) // Specifies a sample 57-bit DNA value for simulation
|
|
)
|
|
DNA_PORT_inst (
|
|
.DOUT(DOUT), // 1-bit output: DNA output data.
|
|
.CLK(CLK), // 1-bit input: Clock input.
|
|
.DIN(DIN), // 1-bit input: User data input pin.
|
|
.READ(READ), // 1-bit input: Active high load DNA, active low read input.
|
|
.SHIFT(SHIFT) // 1-bit input: Active high shift enable input.
|
|
);
|
|
|
|
// End of DNA_PORT_inst instantiation
|
|
</Template>
|
|
<Template label="32-bit non-volatile design ID (EFUSE_USR)" treetype="template">
|
|
// EFUSE_USR : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (EFUSE_USR_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// EFUSE_USR: 32-bit non-volatile design ID
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
EFUSE_USR #(
|
|
.SIM_EFUSE_VALUE(32'h00000000) // Value of the 32-bit non-volatile value used in simulation
|
|
)
|
|
EFUSE_USR_inst (
|
|
.EFUSEUSR(EFUSEUSR) // 32-bit output: User eFUSE register value output
|
|
);
|
|
|
|
// End of EFUSE_USR_inst instantiation
|
|
</Template>
|
|
<Template label="Configuration Frame Error Correction (FRAME_ECCE2)" treetype="template">
|
|
// FRAME_ECCE2 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FRAME_ECCE2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FRAME_ECCE2: Configuration Frame Error Correction
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FRAME_ECCE2 #(
|
|
.FARSRC("EFAR"), // Determines if the output of FAR[25:0] configuration register points to
|
|
// the FAR or EFAR. Sets configuration option register bit CTL0[7].
|
|
.FRAME_RBT_IN_FILENAME("None") // This file is output by the ICAP_E2 model and it contains Frame Data
|
|
// information for the Raw Bitstream (RBT) file. The FRAME_ECCE2 model
|
|
// will parse this file, calculate ECC and output any error conditions.
|
|
)
|
|
FRAME_ECCE2_inst (
|
|
.CRCERROR(CRCERROR), // 1-bit output: Output indicating a CRC error.
|
|
.ECCERROR(ECCERROR), // 1-bit output: Output indicating an ECC error.
|
|
.ECCERRORSINGLE(ECCERRORSINGLE), // 1-bit output: Output Indicating single-bit Frame ECC error detected.
|
|
.FAR(FAR), // 26-bit output: Frame Address Register Value output.
|
|
.SYNBIT(SYNBIT), // 5-bit output: Output bit address of error.
|
|
.SYNDROME(SYNDROME), // 13-bit output: Output location of erroneous bit.
|
|
.SYNDROMEVALID(SYNDROMEVALID), // 1-bit output: Frame ECC output indicating the SYNDROME output is
|
|
// valid.
|
|
|
|
.SYNWORD(SYNWORD) // 7-bit output: Word output in the frame where an ECC error has been
|
|
// detected.
|
|
|
|
);
|
|
|
|
// End of FRAME_ECCE2_inst instantiation
|
|
</Template>
|
|
<Template label="Internal Configuration Access Port (ICAPE2)" treetype="template">
|
|
// ICAPE2 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ICAPE2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ICAPE2: Internal Configuration Access Port
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ICAPE2 #(
|
|
.DEVICE_ID(0'h3651093), // Specifies the pre-programmed Device ID value to be used for simulation
|
|
// purposes.
|
|
.ICAP_WIDTH("X32"), // Specifies the input and output data width.
|
|
.SIM_CFG_FILE_NAME("None") // Specifies the Raw Bitstream (RBT) file to be parsed by the simulation
|
|
// model.
|
|
)
|
|
ICAPE2_inst (
|
|
.O(O), // 32-bit output: Configuration data output bus
|
|
.CLK(CLK), // 1-bit input: Clock Input
|
|
.CSIB(CSIB), // 1-bit input: Active-Low ICAP Enable
|
|
.I(I), // 32-bit input: Configuration data input bus
|
|
.RDWRB(RDWRB) // 1-bit input: Read/Write Select input
|
|
);
|
|
|
|
// End of ICAPE2_inst instantiation
|
|
</Template>
|
|
<Template label="STARTUP Block (STARTUPE2)" treetype="template">
|
|
// STARTUPE2 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (STARTUPE2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// STARTUPE2: STARTUP Block
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
STARTUPE2 #(
|
|
.PROG_USR("FALSE"), // Activate program event security feature. Requires encrypted bitstreams.
|
|
.SIM_CCLK_FREQ(0.0) // Set the Configuration Clock Frequency(ns) for simulation.
|
|
)
|
|
STARTUPE2_inst (
|
|
.CFGCLK(CFGCLK), // 1-bit output: Configuration main clock output
|
|
.CFGMCLK(CFGMCLK), // 1-bit output: Configuration internal oscillator clock output
|
|
.EOS(EOS), // 1-bit output: Active high output signal indicating the End Of Startup.
|
|
.PREQ(PREQ), // 1-bit output: PROGRAM request to fabric output
|
|
.CLK(CLK), // 1-bit input: User start-up clock input
|
|
.GSR(GSR), // 1-bit input: Global Set/Reset input (GSR cannot be used for the port name)
|
|
.GTS(GTS), // 1-bit input: Global 3-state input (GTS cannot be used for the port name)
|
|
.KEYCLEARB(KEYCLEARB), // 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM)
|
|
.PACK(PACK), // 1-bit input: PROGRAM acknowledge input
|
|
.USRCCLKO(USRCCLKO), // 1-bit input: User CCLK input
|
|
.USRCCLKTS(USRCCLKTS), // 1-bit input: User CCLK 3-state enable input
|
|
.USRDONEO(USRDONEO), // 1-bit input: User DONE pin output control
|
|
.USRDONETS(USRDONETS) // 1-bit input: User DONE 3-state enable output
|
|
);
|
|
|
|
// End of STARTUPE2_inst instantiation
|
|
</Template>
|
|
<Template label="Configuration Data Access (USR_ACCESSE2)" treetype="template">
|
|
// USR_ACCESSE2 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (USR_ACCESSE2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// USR_ACCESSE2: Configuration Data Access
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
USR_ACCESSE2 USR_ACCESSE2_inst (
|
|
.CFGCLK(CFGCLK), // 1-bit output: Configuration Clock output
|
|
.DATA(DATA), // 32-bit output: Configuration Data output
|
|
.DATAVALID(DATAVALID) // 1-bit output: Active high data valid output
|
|
);
|
|
|
|
// End of USR_ACCESSE2_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Clock Components" treetype="folder">
|
|
<SubFolder label="Clock Buffers" treetype="folder">
|
|
<Template label="Global Clock Buffer with Clock Enable and Output State 1 (BUFGCE_1)" treetype="template">
|
|
// BUFGCE_1 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFGCE_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFGCE_1: Global Clock Buffer with Clock Enable and Output State 1
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFGCE_1 BUFGCE_1_inst (
|
|
.O(O), // 1-bit output: Clock output
|
|
.CE(CE), // 1-bit input: Clock enable input for I0
|
|
.I(I) // 1-bit input: Primary clock
|
|
);
|
|
|
|
// End of BUFGCE_1_inst instantiation
|
|
</Template>
|
|
<Template label="Global Clock Buffer with Clock Enable (BUFGCE)" treetype="template">
|
|
// BUFGCE : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFGCE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFGCE: Global Clock Buffer with Clock Enable
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFGCE BUFGCE_inst (
|
|
.O(O), // 1-bit output: Clock output
|
|
.CE(CE), // 1-bit input: Clock enable input for I0
|
|
.I(I) // 1-bit input: Primary clock
|
|
);
|
|
|
|
// End of BUFGCE_inst instantiation
|
|
</Template>
|
|
<Template label="Global Clock Simple Buffer (BUFG)" treetype="template">
|
|
// BUFG : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFG_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFG: Global Clock Simple Buffer
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFG BUFG_inst (
|
|
.O(O), // 1-bit output: Clock output
|
|
.I(I) // 1-bit input: Clock input
|
|
);
|
|
|
|
// End of BUFG_inst instantiation
|
|
</Template>
|
|
<Template label="HROW Clock Buffer with Clock Enable (BUFHCE)" treetype="template">
|
|
// BUFHCE : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFHCE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFHCE: HROW Clock Buffer for a Single Clocking Region with Clock Enable
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFHCE #(
|
|
.CE_TYPE("SYNC"), // "SYNC" (glitchless switching) or "ASYNC" (immediate switch)
|
|
.INIT_OUT(0) // Initial output value (0-1)
|
|
)
|
|
BUFHCE_inst (
|
|
.O(O), // 1-bit output: Clock output
|
|
.CE(CE), // 1-bit input: Active high enable
|
|
.I(I) // 1-bit input: Clock input
|
|
);
|
|
|
|
// End of BUFHCE_inst instantiation
|
|
</Template>
|
|
<Template label="HROW Clock Buffer (BUFH)" treetype="template">
|
|
// BUFH : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFH_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFH: HROW Clock Buffer for a Single Clocking Region
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFH BUFH_inst (
|
|
.O(O), // 1-bit output: Clock output
|
|
.I(I) // 1-bit input: Clock input
|
|
);
|
|
|
|
// End of BUFH_inst instantiation
|
|
</Template>
|
|
<Template label="I/O Clock Buffer (BUFIO)" treetype="template">
|
|
// BUFIO : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFIO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFIO: Local Clock Buffer for I/O
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFIO BUFIO_inst (
|
|
.O(O), // 1-bit output: Clock output (connect to I/O clock loads).
|
|
.I(I) // 1-bit input: Clock input (connect to an IBUF or BUFMR).
|
|
);
|
|
|
|
// End of BUFIO_inst instantiation
|
|
</Template>
|
|
<Template label="Multi-Region Clock Buffer with Clock Enable (BUFMRCE)" treetype="template">
|
|
// BUFMRCE : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFMRCE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFMRCE: Multi-Region Clock Buffer with Clock Enable
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFMRCE #(
|
|
.CE_TYPE("SYNC"), // SYNC, ASYNC
|
|
.INIT_OUT(0) // Initial output and stopped polarity, (0-1)
|
|
)
|
|
BUFMRCE_inst (
|
|
.O(O), // 1-bit output: Clock output (connect to BUFIOs/BUFRs)
|
|
.CE(CE), // 1-bit input: Active high buffer enable
|
|
.I(I) // 1-bit input: Clock input (Connect to IBUF)
|
|
);
|
|
|
|
// End of BUFMRCE_inst instantiation
|
|
</Template>
|
|
<Template label="Multi-Region Clock Buffer (BUFMR)" treetype="template">
|
|
// BUFMR : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFMR_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFMR: Multi-Region Clock Buffer
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFMR BUFMR_inst (
|
|
.O(O), // 1-bit output: Clock output (connect to BUFIOs/BUFRs)
|
|
.I(I) // 1-bit input: Clock input (Connect to IBUF)
|
|
);
|
|
|
|
// End of BUFMR_inst instantiation
|
|
</Template>
|
|
<Template label="Regional Clock Buffer (BUFR)" treetype="template">
|
|
// BUFR : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFR_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFR: Regional Clock Buffer for I/O and Logic Resources within a Clock Region
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFR #(
|
|
.BUFR_DIVIDE("BYPASS"), // Values: "BYPASS, 1, 2, 3, 4, 5, 6, 7, 8"
|
|
.SIM_DEVICE(""7SERIES"") // Must be set to "7SERIES"
|
|
)
|
|
BUFR_inst (
|
|
.O(O), // 1-bit output: Clock output port
|
|
.CE(CE), // 1-bit input: Active high, clock enable (Divided modes only)
|
|
.CLR(CLR), // 1-bit input: Active high, asynchronous clear (Divided modes only)
|
|
.I(I) // 1-bit input: Clock buffer input driven by an IBUF, MMCM or local interconnect
|
|
);
|
|
|
|
// End of BUFR_inst instantiation
|
|
</Template>
|
|
<Template label="Single-ended Input Global Clock Buffer (IBUFG)" treetype="template">
|
|
// IBUFG : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFG_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFG: Global Clock Buffer (sourced by an external pin)
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFG #(
|
|
.IBUF_LOW_PWR("TRUE"), // Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
) IBUFG_inst (
|
|
.O(O), // Clock buffer output
|
|
.I(I) // Clock buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUFG_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Input Global Clock Buffer (IBUFGDS)" treetype="template">
|
|
// IBUFGDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFGDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFGDS: Differential Global Clock Buffer (sourced by an external pin)
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFGDS #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination
|
|
.IBUF_LOW_PWR("TRUE"), // Low power="TRUE", Highest performance="FALSE"
|
|
.IOSTANDARD("DEFAULT") // Specifies the I/O standard for this buffer
|
|
) IBUFGDS_inst (
|
|
.O(O), // Clock buffer output
|
|
.I(I), // Diff_p clock buffer input
|
|
.IB(IB) // Diff_n clock buffer input
|
|
);
|
|
|
|
// End of IBUFGDS_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Global Clock Buffer with Differential Output (IBUFGDS_DIFF_OUT)" treetype="template">
|
|
// IBUFGDS_DIFF_OUT : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFGDS_DIFF_OUT_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFGDS_DIFF_OUT: Differential Global Clock Buffer with Differential Output
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFGDS_DIFF_OUT #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination, "TRUE"/"FALSE"
|
|
.IBUF_LOW_PWR("TRUE"), // Low power="TRUE", Highest performance="FALSE"
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
) IBUFGDS_DIFF_OUT_inst (
|
|
.O(O), // Buffer diff_p output
|
|
.OB(OB), // Buffer diff_n output
|
|
.I(I), // Diff_p buffer input (connect directly to top-level port)
|
|
.IB(IB) // Diff_n buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUFGDS_DIFF_OUT_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Clock MUXes" treetype="folder">
|
|
<Template label="Global Clock Control Buffer (BUFGCTRL)" treetype="template">
|
|
// BUFGCTRL : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFGCTRL_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFGCTRL: Global Clock Control Buffer
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFGCTRL #(
|
|
.INIT_OUT(0), // Initial value of BUFGCTRL output ($VALUES;)
|
|
.PRESELECT_I0("FALSE"), // BUFGCTRL output uses I0 input ($VALUES;)
|
|
.PRESELECT_I1("FALSE") // BUFGCTRL output uses I1 input ($VALUES;)
|
|
)
|
|
BUFGCTRL_inst (
|
|
.O(O), // 1-bit output: Clock output
|
|
.CE0(CE0), // 1-bit input: Clock enable input for I0
|
|
.CE1(CE1), // 1-bit input: Clock enable input for I1
|
|
.I0(I0), // 1-bit input: Primary clock
|
|
.I1(I1), // 1-bit input: Secondary clock
|
|
.IGNORE0(IGNORE0), // 1-bit input: Clock ignore input for I0
|
|
.IGNORE1(IGNORE1), // 1-bit input: Clock ignore input for I1
|
|
.S0(S0), // 1-bit input: Clock select for I0
|
|
.S1(S1) // 1-bit input: Clock select for I1
|
|
);
|
|
|
|
// End of BUFGCTRL_inst instantiation
|
|
</Template>
|
|
<Template label="Global Clock Mux Buffer with Output State 1 (BUFGMUX_1)" treetype="template">
|
|
// BUFGMUX_1 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFGMUX_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFGMUX_1: Global Clock Mux Buffer with Output State 1
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFGMUX_1 #(
|
|
)
|
|
BUFGMUX_1_inst (
|
|
.O(O), // 1-bit output: Clock output
|
|
.I0(I0), // 1-bit input: Clock input (S=0)
|
|
.I1(I1), // 1-bit input: Clock input (S=1)
|
|
.S(S) // 1-bit input: Clock select
|
|
);
|
|
|
|
// End of BUFGMUX_1_inst instantiation
|
|
</Template>
|
|
<Template label="2-to-1 Global Clock MUX Buffer (BUFGMUX_CTRL)" treetype="template">
|
|
// BUFGMUX_CTRL : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFGMUX_CTRL_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFGMUX_CTRL: 2-to-1 Global Clock MUX Buffer
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFGMUX_CTRL BUFGMUX_CTRL_inst (
|
|
.O(O), // 1-bit output: Clock output
|
|
.I0(I0), // 1-bit input: Clock input (S=0)
|
|
.I1(I1), // 1-bit input: Clock input (S=1)
|
|
.S(S) // 1-bit input: Clock select
|
|
);
|
|
|
|
// End of BUFGMUX_CTRL_inst instantiation
|
|
</Template>
|
|
<Template label="Global Clock Mux Buffer (BUFGMUX)" treetype="template">
|
|
// BUFGMUX : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFGMUX_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFGMUX: Global Clock Mux Buffer
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFGMUX #(
|
|
)
|
|
BUFGMUX_inst (
|
|
.O(O), // 1-bit output: Clock output
|
|
.I0(I0), // 1-bit input: Clock input (S=0)
|
|
.I1(I1), // 1-bit input: Clock input (S=1)
|
|
.S(S) // 1-bit input: Clock select
|
|
);
|
|
|
|
// End of BUFGMUX_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="MMCM / PLL" treetype="folder">
|
|
<Template label="Advanced Mixed Mode Clock Manager (MMCME2_ADV)" treetype="template">
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// MMCME2_ADV : In order to incorporate this function into the design,
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// Verilog : the following instance declaration needs to be placed
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// instance : in the body of the design code. The instance name
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// declaration : (MMCME2_ADV_inst) and/or the port declarations within the
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// code : parenthesis may be changed to properly reference and
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// : connect this function to the design. All inputs
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// : and outputs must be connected.
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// <-----Cut code below this line---->
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// MMCME2_ADV: Advanced Mixed Mode Clock Manager
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// Kintex-7
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// Xilinx HDL Language Template, version 14.7
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MMCME2_ADV #(
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.BANDWIDTH("OPTIMIZED"), // Jitter programming (OPTIMIZED, HIGH, LOW)
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.CLKFBOUT_MULT_F(5.0), // Multiply value for all CLKOUT (2.000-64.000).
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.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB (-360.000-360.000).
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// CLKIN_PERIOD: Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
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.CLKIN1_PERIOD(0.0),
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.CLKIN2_PERIOD(0.0),
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// CLKOUT0_DIVIDE - CLKOUT6_DIVIDE: Divide amount for CLKOUT (1-128)
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.CLKOUT1_DIVIDE(1),
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.CLKOUT2_DIVIDE(1),
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.CLKOUT3_DIVIDE(1),
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.CLKOUT4_DIVIDE(1),
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.CLKOUT5_DIVIDE(1),
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.CLKOUT6_DIVIDE(1),
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.CLKOUT0_DIVIDE_F(1.0), // Divide amount for CLKOUT0 (1.000-128.000).
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// CLKOUT0_DUTY_CYCLE - CLKOUT6_DUTY_CYCLE: Duty cycle for CLKOUT outputs (0.01-0.99).
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.CLKOUT0_DUTY_CYCLE(0.5),
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.CLKOUT1_DUTY_CYCLE(0.5),
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.CLKOUT2_DUTY_CYCLE(0.5),
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.CLKOUT3_DUTY_CYCLE(0.5),
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.CLKOUT4_DUTY_CYCLE(0.5),
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.CLKOUT5_DUTY_CYCLE(0.5),
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.CLKOUT6_DUTY_CYCLE(0.5),
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// CLKOUT0_PHASE - CLKOUT6_PHASE: Phase offset for CLKOUT outputs (-360.000-360.000).
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.CLKOUT0_PHASE(0.0),
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.CLKOUT1_PHASE(0.0),
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.CLKOUT2_PHASE(0.0),
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.CLKOUT3_PHASE(0.0),
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.CLKOUT4_PHASE(0.0),
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.CLKOUT5_PHASE(0.0),
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.CLKOUT6_PHASE(0.0),
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.CLKOUT4_CASCADE("FALSE"), // Cascade CLKOUT4 counter with CLKOUT6 (FALSE, TRUE)
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.COMPENSATION("ZHOLD"), // ZHOLD, BUF_IN, EXTERNAL, INTERNAL
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.DIVCLK_DIVIDE(1), // Master division value (1-106)
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// REF_JITTER: Reference input jitter in UI (0.000-0.999).
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.REF_JITTER1(0.0),
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.REF_JITTER2(0.0),
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.STARTUP_WAIT("FALSE"), // Delays DONE until MMCM is locked (FALSE, TRUE)
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// Spread Spectrum: Spread Spectrum Attributes
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.SS_EN("FALSE"), // Enables spread spectrum (FALSE, TRUE)
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.SS_MODE("CENTER_HIGH"), // CENTER_HIGH, CENTER_LOW, DOWN_HIGH, DOWN_LOW
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.SS_MOD_PERIOD(10000), // Spread spectrum modulation period (ns) (VALUES)
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// USE_FINE_PS: Fine phase shift enable (TRUE/FALSE)
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.CLKFBOUT_USE_FINE_PS("FALSE"),
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.CLKOUT0_USE_FINE_PS("FALSE"),
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.CLKOUT1_USE_FINE_PS("FALSE"),
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.CLKOUT2_USE_FINE_PS("FALSE"),
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.CLKOUT3_USE_FINE_PS("FALSE"),
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.CLKOUT4_USE_FINE_PS("FALSE"),
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.CLKOUT5_USE_FINE_PS("FALSE"),
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.CLKOUT6_USE_FINE_PS("FALSE")
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)
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MMCME2_ADV_inst (
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// Clock Outputs: 1-bit (each) output: User configurable clock outputs
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.CLKOUT0(CLKOUT0), // 1-bit output: CLKOUT0
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.CLKOUT0B(CLKOUT0B), // 1-bit output: Inverted CLKOUT0
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.CLKOUT1(CLKOUT1), // 1-bit output: CLKOUT1
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.CLKOUT1B(CLKOUT1B), // 1-bit output: Inverted CLKOUT1
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.CLKOUT2(CLKOUT2), // 1-bit output: CLKOUT2
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.CLKOUT2B(CLKOUT2B), // 1-bit output: Inverted CLKOUT2
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.CLKOUT3(CLKOUT3), // 1-bit output: CLKOUT3
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.CLKOUT3B(CLKOUT3B), // 1-bit output: Inverted CLKOUT3
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.CLKOUT4(CLKOUT4), // 1-bit output: CLKOUT4
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.CLKOUT5(CLKOUT5), // 1-bit output: CLKOUT5
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.CLKOUT6(CLKOUT6), // 1-bit output: CLKOUT6
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// DRP Ports: 16-bit (each) output: Dynamic reconfiguration ports
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.DO(DO), // 16-bit output: DRP data
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.DRDY(DRDY), // 1-bit output: DRP ready
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// Dynamic Phase Shift Ports: 1-bit (each) output: Ports used for dynamic phase shifting of the outputs
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.PSDONE(PSDONE), // 1-bit output: Phase shift done
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// Feedback Clocks: 1-bit (each) output: Clock feedback ports
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.CLKFBOUT(CLKFBOUT), // 1-bit output: Feedback clock
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.CLKFBOUTB(CLKFBOUTB), // 1-bit output: Inverted CLKFBOUT
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// Status Ports: 1-bit (each) output: MMCM status ports
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.CLKFBSTOPPED(CLKFBSTOPPED), // 1-bit output: Feedback clock stopped
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.CLKINSTOPPED(CLKINSTOPPED), // 1-bit output: Input clock stopped
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.LOCKED(LOCKED), // 1-bit output: LOCK
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// Clock Inputs: 1-bit (each) input: Clock inputs
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.CLKIN1(CLKIN1), // 1-bit input: Primary clock
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.CLKIN2(CLKIN2), // 1-bit input: Secondary clock
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// Control Ports: 1-bit (each) input: MMCM control ports
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.CLKINSEL(CLKINSEL), // 1-bit input: Clock select, High=CLKIN1 Low=CLKIN2
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.PWRDWN(PWRDWN), // 1-bit input: Power-down
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.RST(RST), // 1-bit input: Reset
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// DRP Ports: 7-bit (each) input: Dynamic reconfiguration ports
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.DADDR(DADDR), // 7-bit input: DRP address
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.DCLK(DCLK), // 1-bit input: DRP clock
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.DEN(DEN), // 1-bit input: DRP enable
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.DI(DI), // 16-bit input: DRP data
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.DWE(DWE), // 1-bit input: DRP write enable
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// Dynamic Phase Shift Ports: 1-bit (each) input: Ports used for dynamic phase shifting of the outputs
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.PSCLK(PSCLK), // 1-bit input: Phase shift clock
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.PSEN(PSEN), // 1-bit input: Phase shift enable
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.PSINCDEC(PSINCDEC), // 1-bit input: Phase shift increment/decrement
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// Feedback Clocks: 1-bit (each) input: Clock feedback ports
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.CLKFBIN(CLKFBIN) // 1-bit input: Feedback clock
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);
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// End of MMCME2_ADV_inst instantiation
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</Template>
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<Template label="Base Mixed Mode Clock Manager (MMCME2_BASE)" treetype="template">
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// MMCME2_BASE : In order to incorporate this function into the design,
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// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
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|
// declaration : (MMCME2_BASE_inst) and/or the port declarations within the
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|
// code : parenthesis may be changed to properly reference and
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|
// : connect this function to the design. All inputs
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// : and outputs must be connected.
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// <-----Cut code below this line---->
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// MMCME2_BASE: Base Mixed Mode Clock Manager
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// Kintex-7
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// Xilinx HDL Language Template, version 14.7
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MMCME2_BASE #(
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.BANDWIDTH("OPTIMIZED"), // Jitter programming (OPTIMIZED, HIGH, LOW)
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.CLKFBOUT_MULT_F(5.0), // Multiply value for all CLKOUT (2.000-64.000).
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.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB (-360.000-360.000).
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.CLKIN1_PERIOD(0.0), // Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
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// CLKOUT0_DIVIDE - CLKOUT6_DIVIDE: Divide amount for each CLKOUT (1-128)
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.CLKOUT1_DIVIDE(1),
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.CLKOUT2_DIVIDE(1),
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.CLKOUT3_DIVIDE(1),
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.CLKOUT4_DIVIDE(1),
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.CLKOUT5_DIVIDE(1),
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.CLKOUT6_DIVIDE(1),
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.CLKOUT0_DIVIDE_F(1.0), // Divide amount for CLKOUT0 (1.000-128.000).
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// CLKOUT0_DUTY_CYCLE - CLKOUT6_DUTY_CYCLE: Duty cycle for each CLKOUT (0.01-0.99).
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.CLKOUT0_DUTY_CYCLE(0.5),
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.CLKOUT1_DUTY_CYCLE(0.5),
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.CLKOUT2_DUTY_CYCLE(0.5),
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.CLKOUT3_DUTY_CYCLE(0.5),
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.CLKOUT4_DUTY_CYCLE(0.5),
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.CLKOUT5_DUTY_CYCLE(0.5),
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.CLKOUT6_DUTY_CYCLE(0.5),
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// CLKOUT0_PHASE - CLKOUT6_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
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.CLKOUT0_PHASE(0.0),
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.CLKOUT1_PHASE(0.0),
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.CLKOUT2_PHASE(0.0),
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.CLKOUT3_PHASE(0.0),
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.CLKOUT4_PHASE(0.0),
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.CLKOUT5_PHASE(0.0),
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.CLKOUT6_PHASE(0.0),
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.CLKOUT4_CASCADE("FALSE"), // Cascade CLKOUT4 counter with CLKOUT6 (FALSE, TRUE)
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.DIVCLK_DIVIDE(1), // Master division value (1-106)
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.REF_JITTER1(0.0), // Reference input jitter in UI (0.000-0.999).
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.STARTUP_WAIT("FALSE") // Delays DONE until MMCM is locked (FALSE, TRUE)
|
|
)
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MMCME2_BASE_inst (
|
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// Clock Outputs: 1-bit (each) output: User configurable clock outputs
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.CLKOUT0(CLKOUT0), // 1-bit output: CLKOUT0
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.CLKOUT0B(CLKOUT0B), // 1-bit output: Inverted CLKOUT0
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.CLKOUT1(CLKOUT1), // 1-bit output: CLKOUT1
|
|
.CLKOUT1B(CLKOUT1B), // 1-bit output: Inverted CLKOUT1
|
|
.CLKOUT2(CLKOUT2), // 1-bit output: CLKOUT2
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.CLKOUT2B(CLKOUT2B), // 1-bit output: Inverted CLKOUT2
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.CLKOUT3(CLKOUT3), // 1-bit output: CLKOUT3
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.CLKOUT3B(CLKOUT3B), // 1-bit output: Inverted CLKOUT3
|
|
.CLKOUT4(CLKOUT4), // 1-bit output: CLKOUT4
|
|
.CLKOUT5(CLKOUT5), // 1-bit output: CLKOUT5
|
|
.CLKOUT6(CLKOUT6), // 1-bit output: CLKOUT6
|
|
// Feedback Clocks: 1-bit (each) output: Clock feedback ports
|
|
.CLKFBOUT(CLKFBOUT), // 1-bit output: Feedback clock
|
|
.CLKFBOUTB(CLKFBOUTB), // 1-bit output: Inverted CLKFBOUT
|
|
// Status Ports: 1-bit (each) output: MMCM status ports
|
|
.LOCKED(LOCKED), // 1-bit output: LOCK
|
|
// Clock Inputs: 1-bit (each) input: Clock input
|
|
.CLKIN1(CLKIN1), // 1-bit input: Clock
|
|
// Control Ports: 1-bit (each) input: MMCM control ports
|
|
.PWRDWN(PWRDWN), // 1-bit input: Power-down
|
|
.RST(RST), // 1-bit input: Reset
|
|
// Feedback Clocks: 1-bit (each) input: Clock feedback ports
|
|
.CLKFBIN(CLKFBIN) // 1-bit input: Feedback clock
|
|
);
|
|
|
|
// End of MMCME2_BASE_inst instantiation
|
|
</Template>
|
|
<Template label="Advanced Phase Locked Loop (PLLE2_ADV)" treetype="template">
|
|
// PLLE2_ADV : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (PLLE2_ADV_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// PLLE2_ADV: Advanced Phase Locked Loop (PLL)
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
PLLE2_ADV #(
|
|
.BANDWIDTH("OPTIMIZED"), // OPTIMIZED, HIGH, LOW
|
|
.CLKFBOUT_MULT(5), // Multiply value for all CLKOUT, (2-64)
|
|
.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB, (-360.000-360.000).
|
|
// CLKIN_PERIOD: Input clock period in nS to ps resolution (i.e. 33.333 is 30 MHz).
|
|
.CLKIN1_PERIOD(0.0),
|
|
.CLKIN2_PERIOD(0.0),
|
|
// CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for CLKOUT (1-128)
|
|
.CLKOUT0_DIVIDE(1),
|
|
.CLKOUT1_DIVIDE(1),
|
|
.CLKOUT2_DIVIDE(1),
|
|
.CLKOUT3_DIVIDE(1),
|
|
.CLKOUT4_DIVIDE(1),
|
|
.CLKOUT5_DIVIDE(1),
|
|
// CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for CLKOUT outputs (0.001-0.999).
|
|
.CLKOUT0_DUTY_CYCLE(0.5),
|
|
.CLKOUT1_DUTY_CYCLE(0.5),
|
|
.CLKOUT2_DUTY_CYCLE(0.5),
|
|
.CLKOUT3_DUTY_CYCLE(0.5),
|
|
.CLKOUT4_DUTY_CYCLE(0.5),
|
|
.CLKOUT5_DUTY_CYCLE(0.5),
|
|
// CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for CLKOUT outputs (-360.000-360.000).
|
|
.CLKOUT0_PHASE(0.0),
|
|
.CLKOUT1_PHASE(0.0),
|
|
.CLKOUT2_PHASE(0.0),
|
|
.CLKOUT3_PHASE(0.0),
|
|
.CLKOUT4_PHASE(0.0),
|
|
.CLKOUT5_PHASE(0.0),
|
|
.COMPENSATION("ZHOLD"), // ZHOLD, BUF_IN, EXTERNAL, INTERNAL
|
|
.DIVCLK_DIVIDE(1), // Master division value (1-56)
|
|
// REF_JITTER: Reference input jitter in UI (0.000-0.999).
|
|
.REF_JITTER1(0.0),
|
|
.REF_JITTER2(0.0),
|
|
.STARTUP_WAIT("FALSE") // Delay DONE until PLL Locks, ("TRUE"/"FALSE")
|
|
)
|
|
PLLE2_ADV_inst (
|
|
// Clock Outputs: 1-bit (each) output: User configurable clock outputs
|
|
.CLKOUT0(CLKOUT0), // 1-bit output: CLKOUT0
|
|
.CLKOUT1(CLKOUT1), // 1-bit output: CLKOUT1
|
|
.CLKOUT2(CLKOUT2), // 1-bit output: CLKOUT2
|
|
.CLKOUT3(CLKOUT3), // 1-bit output: CLKOUT3
|
|
.CLKOUT4(CLKOUT4), // 1-bit output: CLKOUT4
|
|
.CLKOUT5(CLKOUT5), // 1-bit output: CLKOUT5
|
|
// DRP Ports: 16-bit (each) output: Dynamic reconfiguration ports
|
|
.DO(DO), // 16-bit output: DRP data
|
|
.DRDY(DRDY), // 1-bit output: DRP ready
|
|
// Feedback Clocks: 1-bit (each) output: Clock feedback ports
|
|
.CLKFBOUT(CLKFBOUT), // 1-bit output: Feedback clock
|
|
.LOCKED(LOCKED), // 1-bit output: LOCK
|
|
// Clock Inputs: 1-bit (each) input: Clock inputs
|
|
.CLKIN1(CLKIN1), // 1-bit input: Primary clock
|
|
.CLKIN2(CLKIN2), // 1-bit input: Secondary clock
|
|
// Control Ports: 1-bit (each) input: PLL control ports
|
|
.CLKINSEL(CLKINSEL), // 1-bit input: Clock select, High=CLKIN1 Low=CLKIN2
|
|
.PWRDWN(PWRDWN), // 1-bit input: Power-down
|
|
.RST(RST), // 1-bit input: Reset
|
|
// DRP Ports: 7-bit (each) input: Dynamic reconfiguration ports
|
|
.DADDR(DADDR), // 7-bit input: DRP address
|
|
.DCLK(DCLK), // 1-bit input: DRP clock
|
|
.DEN(DEN), // 1-bit input: DRP enable
|
|
.DI(DI), // 16-bit input: DRP data
|
|
.DWE(DWE), // 1-bit input: DRP write enable
|
|
// Feedback Clocks: 1-bit (each) input: Clock feedback ports
|
|
.CLKFBIN(CLKFBIN) // 1-bit input: Feedback clock
|
|
);
|
|
|
|
// End of PLLE2_ADV_inst instantiation
|
|
</Template>
|
|
<Template label="Base Phase Locked Loop (PLLE2_BASE)" treetype="template">
|
|
// PLLE2_BASE : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (PLLE2_BASE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// PLLE2_BASE: Base Phase Locked Loop (PLL)
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
PLLE2_BASE #(
|
|
.BANDWIDTH("OPTIMIZED"), // OPTIMIZED, HIGH, LOW
|
|
.CLKFBOUT_MULT(5), // Multiply value for all CLKOUT, (2-64)
|
|
.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB, (-360.000-360.000).
|
|
.CLKIN1_PERIOD(0.0), // Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
|
|
// CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128)
|
|
.CLKOUT0_DIVIDE(1),
|
|
.CLKOUT1_DIVIDE(1),
|
|
.CLKOUT2_DIVIDE(1),
|
|
.CLKOUT3_DIVIDE(1),
|
|
.CLKOUT4_DIVIDE(1),
|
|
.CLKOUT5_DIVIDE(1),
|
|
// CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for each CLKOUT (0.001-0.999).
|
|
.CLKOUT0_DUTY_CYCLE(0.5),
|
|
.CLKOUT1_DUTY_CYCLE(0.5),
|
|
.CLKOUT2_DUTY_CYCLE(0.5),
|
|
.CLKOUT3_DUTY_CYCLE(0.5),
|
|
.CLKOUT4_DUTY_CYCLE(0.5),
|
|
.CLKOUT5_DUTY_CYCLE(0.5),
|
|
// CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
|
|
.CLKOUT0_PHASE(0.0),
|
|
.CLKOUT1_PHASE(0.0),
|
|
.CLKOUT2_PHASE(0.0),
|
|
.CLKOUT3_PHASE(0.0),
|
|
.CLKOUT4_PHASE(0.0),
|
|
.CLKOUT5_PHASE(0.0),
|
|
.DIVCLK_DIVIDE(1), // Master division value, (1-56)
|
|
.REF_JITTER1(0.0), // Reference input jitter in UI, (0.000-0.999).
|
|
.STARTUP_WAIT("FALSE") // Delay DONE until PLL Locks, ("TRUE"/"FALSE")
|
|
)
|
|
PLLE2_BASE_inst (
|
|
// Clock Outputs: 1-bit (each) output: User configurable clock outputs
|
|
.CLKOUT0(CLKOUT0), // 1-bit output: CLKOUT0
|
|
.CLKOUT1(CLKOUT1), // 1-bit output: CLKOUT1
|
|
.CLKOUT2(CLKOUT2), // 1-bit output: CLKOUT2
|
|
.CLKOUT3(CLKOUT3), // 1-bit output: CLKOUT3
|
|
.CLKOUT4(CLKOUT4), // 1-bit output: CLKOUT4
|
|
.CLKOUT5(CLKOUT5), // 1-bit output: CLKOUT5
|
|
// Feedback Clocks: 1-bit (each) output: Clock feedback ports
|
|
.CLKFBOUT(CLKFBOUT), // 1-bit output: Feedback clock
|
|
.LOCKED(LOCKED), // 1-bit output: LOCK
|
|
.CLKIN1(CLKIN1), // 1-bit input: Input clock
|
|
// Control Ports: 1-bit (each) input: PLL control ports
|
|
.PWRDWN(PWRDWN), // 1-bit input: Power-down
|
|
.RST(RST), // 1-bit input: Reset
|
|
// Feedback Clocks: 1-bit (each) input: Clock feedback ports
|
|
.CLKFBIN(CLKFBIN) // 1-bit input: Feedback clock
|
|
);
|
|
|
|
// End of PLLE2_BASE_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="I/O Components" treetype="folder">
|
|
<Template label="Digitally Controlled Impedance Reset Component (DCIRESET)" treetype="template">
|
|
// DCIRESET : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (DCIRESET_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// DCIRESET: Digitally Controlled Impedance Reset Component
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
DCIRESET DCIRESET_inst (
|
|
.LOCKED(LOCKED), // 1-bit output: LOCK status output
|
|
.RST(RST) // 1-bit input: Active-high asynchronous reset input
|
|
);
|
|
|
|
// End of DCIRESET_inst instantiation
|
|
</Template>
|
|
<SubFolder label="I/O Delay Components" treetype="folder">
|
|
<Template label="Delay Calibration (IDELAYCTRL)" treetype="template">
|
|
// IDELAYCTRL : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IDELAYCTRL_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IDELAYCTRL: IDELAYE2/ODELAYE2 Tap Delay Value Control
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
(* IODELAY_GROUP = <iodelay_group_name> *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTRL
|
|
|
|
IDELAYCTRL IDELAYCTRL_inst (
|
|
.RDY(RDY), // 1-bit output: Ready output
|
|
.REFCLK(REFCLK), // 1-bit input: Reference clock input
|
|
.RST(RST) // 1-bit input: Active high reset input
|
|
);
|
|
|
|
// End of IDELAYCTRL_inst instantiation
|
|
</Template>
|
|
<Template label="Input Delay Element (IDELAYE2)" treetype="template">
|
|
// IDELAYE2 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IDELAYE2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IDELAYE2: Input Fixed or Variable Delay Element
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
(* IODELAY_GROUP = <iodelay_group_name> *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTRL
|
|
|
|
IDELAYE2 #(
|
|
.CINVCTRL_SEL("FALSE"), // Enable dynamic clock inversion (FALSE, TRUE)
|
|
.DELAY_SRC("IDATAIN"), // Delay input (IDATAIN, DATAIN)
|
|
.HIGH_PERFORMANCE_MODE("FALSE"), // Reduced jitter ("TRUE"), Reduced power ("FALSE")
|
|
.IDELAY_TYPE("FIXED"), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
|
|
.IDELAY_VALUE(0), // Input delay tap setting (0-31)
|
|
.PIPE_SEL("FALSE"), // Select pipelined mode, FALSE, TRUE
|
|
.REFCLK_FREQUENCY(200.0), // IDELAYCTRL clock input frequency in MHz (190.0-210.0, 290.0-310.0).
|
|
.SIGNAL_PATTERN("DATA") // DATA, CLOCK input signal
|
|
)
|
|
IDELAYE2_inst (
|
|
.CNTVALUEOUT(CNTVALUEOUT), // 5-bit output: Counter value output
|
|
.DATAOUT(DATAOUT), // 1-bit output: Delayed data output
|
|
.C(C), // 1-bit input: Clock input
|
|
.CE(CE), // 1-bit input: Active high enable increment/decrement input
|
|
.CINVCTRL(CINVCTRL), // 1-bit input: Dynamic clock inversion input
|
|
.CNTVALUEIN(CNTVALUEIN), // 5-bit input: Counter value input
|
|
.DATAIN(DATAIN), // 1-bit input: Internal delay data input
|
|
.IDATAIN(IDATAIN), // 1-bit input: Data input from the I/O
|
|
.INC(INC), // 1-bit input: Increment / Decrement tap delay input
|
|
.LD(LD), // 1-bit input: Load IDELAY_VALUE input
|
|
.LDPIPEEN(LDPIPEEN), // 1-bit input: Enable PIPELINE register to load data input
|
|
.REGRST(REGRST) // 1-bit input: Active-high reset tap-delay input
|
|
);
|
|
|
|
// End of IDELAYE2_inst instantiation
|
|
</Template>
|
|
<Template label="Output Delay Element (ODELAYE2)" treetype="template">
|
|
// ODELAYE2 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ODELAYE2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ODELAYE2: Output Fixed or Variable Delay Element
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
(* IODELAY_GROUP = <iodelay_group_name> *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTRL
|
|
|
|
ODELAYE2 #(
|
|
.CINVCTRL_SEL("FALSE"), // Enable dynamic clock inversion (FALSE, TRUE)
|
|
.DELAY_SRC("ODATAIN"), // Delay input (ODATAIN, CLKIN)
|
|
.HIGH_PERFORMANCE_MODE("FALSE"), // Reduced jitter ("TRUE"), Reduced power ("FALSE")
|
|
.ODELAY_TYPE("FIXED"), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
|
|
.ODELAY_VALUE(0), // Output delay tap setting (0-31)
|
|
.PIPE_SEL("FALSE"), // Select pipelined mode, FALSE, TRUE
|
|
.REFCLK_FREQUENCY(200.0), // IDELAYCTRL clock input frequency in MHz (190.0-210.0, 290.0-310.0).
|
|
.SIGNAL_PATTERN("DATA") // DATA, CLOCK input signal
|
|
)
|
|
ODELAYE2_inst (
|
|
.CNTVALUEOUT(CNTVALUEOUT), // 5-bit output: Counter value output
|
|
.DATAOUT(DATAOUT), // 1-bit output: Delayed data/clock output
|
|
.C(C), // 1-bit input: Clock input
|
|
.CE(CE), // 1-bit input: Active high enable increment/decrement input
|
|
.CINVCTRL(CINVCTRL), // 1-bit input: Dynamic clock inversion input
|
|
.CLKIN(CLKIN), // 1-bit input: Clock delay input
|
|
.CNTVALUEIN(CNTVALUEIN), // 5-bit input: Counter value input
|
|
.INC(INC), // 1-bit input: Increment / Decrement tap delay input
|
|
.LD(LD), // 1-bit input: Loads ODELAY_VALUE tap delay in VARIABLE mode, in VAR_LOAD or
|
|
// VAR_LOAD_PIPE mode, loads the value of CNTVALUEIN
|
|
|
|
.LDPIPEEN(LDPIPEEN), // 1-bit input: Enables the pipeline register to load data
|
|
.ODATAIN(ODATAIN), // 1-bit input: Output delay data input
|
|
.REGRST(REGRST) // 1-bit input: Active-high reset tap-delay input
|
|
);
|
|
|
|
// End of ODELAYE2_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="FIFOs" treetype="folder">
|
|
<Template label="Input FIFO (IN_FIFO)" treetype="template">
|
|
// IN_FIFO : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IN_FIFO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IN_FIFO: Input First-In, First-Out (FIFO)
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IN_FIFO #(
|
|
.ALMOST_EMPTY_VALUE(1), // Almost empty offset (1-2)
|
|
.ALMOST_FULL_VALUE(1), // Almost full offset (1-2)
|
|
.ARRAY_MODE("ARRAY_MODE_4_X_8"), // ARRAY_MODE_4_X_8, ARRAY_MODE_4_X_4
|
|
.SYNCHRONOUS_MODE("FALSE") // Clock synchronous (FALSE)
|
|
)
|
|
IN_FIFO_inst (
|
|
// FIFO Status Flags: 1-bit (each) output: Flags and other FIFO status outputs
|
|
.ALMOSTEMPTY(ALMOSTEMPTY), // 1-bit output: Almost empty
|
|
.ALMOSTFULL(ALMOSTFULL), // 1-bit output: Almost full
|
|
.EMPTY(EMPTY), // 1-bit output: Empty
|
|
.FULL(FULL), // 1-bit output: Full
|
|
// Q0-Q9: 8-bit (each) output: FIFO Outputs
|
|
.Q0(Q0), // 8-bit output: Channel 0
|
|
.Q1(Q1), // 8-bit output: Channel 1
|
|
.Q2(Q2), // 8-bit output: Channel 2
|
|
.Q3(Q3), // 8-bit output: Channel 3
|
|
.Q4(Q4), // 8-bit output: Channel 4
|
|
.Q5(Q5), // 8-bit output: Channel 5
|
|
.Q6(Q6), // 8-bit output: Channel 6
|
|
.Q7(Q7), // 8-bit output: Channel 7
|
|
.Q8(Q8), // 8-bit output: Channel 8
|
|
.Q9(Q9), // 8-bit output: Channel 9
|
|
// D0-D9: 4-bit (each) input: FIFO inputs
|
|
.D0(D0), // 4-bit input: Channel 0
|
|
.D1(D1), // 4-bit input: Channel 1
|
|
.D2(D2), // 4-bit input: Channel 2
|
|
.D3(D3), // 4-bit input: Channel 3
|
|
.D4(D4), // 4-bit input: Channel 4
|
|
.D5(D5), // 8-bit input: Channel 5
|
|
.D6(D6), // 8-bit input: Channel 6
|
|
.D7(D7), // 4-bit input: Channel 7
|
|
.D8(D8), // 4-bit input: Channel 8
|
|
.D9(D9), // 4-bit input: Channel 9
|
|
// FIFO Control Signals: 1-bit (each) input: Clocks, Resets and Enables
|
|
.RDCLK(RDCLK), // 1-bit input: Read clock
|
|
.RDEN(RDEN), // 1-bit input: Read enable
|
|
.RESET(RESET), // 1-bit input: Reset
|
|
.WRCLK(WRCLK), // 1-bit input: Write clock
|
|
.WREN(WREN) // 1-bit input: Write enable
|
|
);
|
|
|
|
// End of IN_FIFO_inst instantiation
|
|
</Template>
|
|
<Template label="Output FIFO (OUT_FIFO)" treetype="template">
|
|
// OUT_FIFO : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OUT_FIFO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OUT_FIFO: Output First-In, First-Out (FIFO) Buffer
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OUT_FIFO #(
|
|
.ALMOST_EMPTY_VALUE(1), // Almost empty offset (1-2)
|
|
.ALMOST_FULL_VALUE(1), // Almost full offset (1-2)
|
|
.ARRAY_MODE("ARRAY_MODE_8_X_4"), // ARRAY_MODE_8_X_4, ARRAY_MODE_4_X_4
|
|
.OUTPUT_DISABLE("FALSE"), // Disable output (FALSE, TRUE)
|
|
.SYNCHRONOUS_MODE("FALSE") // Must always be set to false.
|
|
)
|
|
OUT_FIFO_inst (
|
|
// FIFO Status Flags: 1-bit (each) output: Flags and other FIFO status outputs
|
|
.ALMOSTEMPTY(ALMOSTEMPTY), // 1-bit output: Almost empty flag
|
|
.ALMOSTFULL(ALMOSTFULL), // 1-bit output: Almost full flag
|
|
.EMPTY(EMPTY), // 1-bit output: Empty flag
|
|
.FULL(FULL), // 1-bit output: Full flag
|
|
// Q0-Q9: 4-bit (each) output: FIFO Outputs
|
|
.Q0(Q0), // 4-bit output: Channel 0 output bus
|
|
.Q1(Q1), // 4-bit output: Channel 1 output bus
|
|
.Q2(Q2), // 4-bit output: Channel 2 output bus
|
|
.Q3(Q3), // 4-bit output: Channel 3 output bus
|
|
.Q4(Q4), // 4-bit output: Channel 4 output bus
|
|
.Q5(Q5), // 8-bit output: Channel 5 output bus
|
|
.Q6(Q6), // 8-bit output: Channel 6 output bus
|
|
.Q7(Q7), // 4-bit output: Channel 7 output bus
|
|
.Q8(Q8), // 4-bit output: Channel 8 output bus
|
|
.Q9(Q9), // 4-bit output: Channel 9 output bus
|
|
// D0-D9: 8-bit (each) input: FIFO inputs
|
|
.D0(D0), // 8-bit input: Channel 0 input bus
|
|
.D1(D1), // 8-bit input: Channel 1 input bus
|
|
.D2(D2), // 8-bit input: Channel 2 input bus
|
|
.D3(D3), // 8-bit input: Channel 3 input bus
|
|
.D4(D4), // 8-bit input: Channel 4 input bus
|
|
.D5(D5), // 8-bit input: Channel 5 input bus
|
|
.D6(D6), // 8-bit input: Channel 6 input bus
|
|
.D7(D7), // 8-bit input: Channel 7 input bus
|
|
.D8(D8), // 8-bit input: Channel 8 input bus
|
|
.D9(D9), // 8-bit input: Channel 9 input bus
|
|
// FIFO Control Signals: 1-bit (each) input: Clocks, Resets and Enables
|
|
.RDCLK(RDCLK), // 1-bit input: Read clock
|
|
.RDEN(RDEN), // 1-bit input: Read enable
|
|
.RESET(RESET), // 1-bit input: Active high reset
|
|
.WRCLK(WRCLK), // 1-bit input: Write clock
|
|
.WREN(WREN) // 1-bit input: Write enable
|
|
);
|
|
|
|
// End of OUT_FIFO_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="I/O SERDES" treetype="folder">
|
|
<Template label="Input SERial/DESerializer with Bitslip (ISERDESE2)" treetype="template">
|
|
// ISERDESE2 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ISERDESE2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ISERDESE2: Input SERial/DESerializer with Bitslip
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ISERDESE2 #(
|
|
.DATA_RATE("DDR"), // DDR, SDR
|
|
.DATA_WIDTH(4), // Parallel data width (2-8,10,14)
|
|
.DYN_CLKDIV_INV_EN("FALSE"), // Enable DYNCLKDIVINVSEL inversion (FALSE, TRUE)
|
|
.DYN_CLK_INV_EN("FALSE"), // Enable DYNCLKINVSEL inversion (FALSE, TRUE)
|
|
// INIT_Q1 - INIT_Q4: Initial value on the Q outputs (0/1)
|
|
.INIT_Q1(1'b0),
|
|
.INIT_Q2(1'b0),
|
|
.INIT_Q3(1'b0),
|
|
.INIT_Q4(1'b0),
|
|
.INTERFACE_TYPE("MEMORY"), // MEMORY, MEMORY_DDR3, MEMORY_QDR, NETWORKING, OVERSAMPLE
|
|
.IOBDELAY("NONE"), // NONE, BOTH, IBUF, IFD
|
|
.NUM_CE(2), // Number of clock enables (1,2)
|
|
.OFB_USED("FALSE"), // Select OFB path (FALSE, TRUE)
|
|
.SERDES_MODE("MASTER"), // MASTER, SLAVE
|
|
// SRVAL_Q1 - SRVAL_Q4: Q output values when SR is used (0/1)
|
|
.SRVAL_Q1(1'b0),
|
|
.SRVAL_Q2(1'b0),
|
|
.SRVAL_Q3(1'b0),
|
|
.SRVAL_Q4(1'b0)
|
|
)
|
|
ISERDESE2_inst (
|
|
.O(O), // 1-bit output: Combinatorial output
|
|
// Q1 - Q8: 1-bit (each) output: Registered data outputs
|
|
.Q1(Q1),
|
|
.Q2(Q2),
|
|
.Q3(Q3),
|
|
.Q4(Q4),
|
|
.Q5(Q5),
|
|
.Q6(Q6),
|
|
.Q7(Q7),
|
|
.Q8(Q8),
|
|
// SHIFTOUT1, SHIFTOUT2: 1-bit (each) output: Data width expansion output ports
|
|
.SHIFTOUT1(SHIFTOUT1),
|
|
.SHIFTOUT2(SHIFTOUT2),
|
|
.BITSLIP(BITSLIP), // 1-bit input: The BITSLIP pin performs a Bitslip operation synchronous to
|
|
// CLKDIV when asserted (active High). Subsequently, the data seen on the Q1
|
|
// to Q8 output ports will shift, as in a barrel-shifter operation, one
|
|
// position every time Bitslip is invoked (DDR operation is different from
|
|
// SDR).
|
|
|
|
// CE1, CE2: 1-bit (each) input: Data register clock enable inputs
|
|
.CE1(CE1),
|
|
.CE2(CE2),
|
|
.CLKDIVP(CLKDIVP), // 1-bit input: TBD
|
|
// Clocks: 1-bit (each) input: ISERDESE2 clock input ports
|
|
.CLK(CLK), // 1-bit input: High-speed clock
|
|
.CLKB(CLKB), // 1-bit input: High-speed secondary clock
|
|
.CLKDIV(CLKDIV), // 1-bit input: Divided clock
|
|
.OCLK(OCLK), // 1-bit input: High speed output clock used when INTERFACE_TYPE="MEMORY"
|
|
// Dynamic Clock Inversions: 1-bit (each) input: Dynamic clock inversion pins to switch clock polarity
|
|
.DYNCLKDIVSEL(DYNCLKDIVSEL), // 1-bit input: Dynamic CLKDIV inversion
|
|
.DYNCLKSEL(DYNCLKSEL), // 1-bit input: Dynamic CLK/CLKB inversion
|
|
// Input Data: 1-bit (each) input: ISERDESE2 data input ports
|
|
.D(D), // 1-bit input: Data input
|
|
.DDLY(DDLY), // 1-bit input: Serial data from IDELAYE2
|
|
.OFB(OFB), // 1-bit input: Data feedback from OSERDESE2
|
|
.OCLKB(OCLKB), // 1-bit input: High speed negative edge output clock
|
|
.RST(RST), // 1-bit input: Active high asynchronous reset
|
|
// SHIFTIN1, SHIFTIN2: 1-bit (each) input: Data width expansion input ports
|
|
.SHIFTIN1(SHIFTIN1),
|
|
.SHIFTIN2(SHIFTIN2)
|
|
);
|
|
|
|
// End of ISERDESE2_inst instantiation
|
|
</Template>
|
|
<Template label="Output SERial/DESerializer with bitslip (OSERDESE2)" treetype="template">
|
|
// OSERDESE2 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OSERDESE2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OSERDESE2: Output SERial/DESerializer with bitslip
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OSERDESE2 #(
|
|
.DATA_RATE_OQ("DDR"), // DDR, SDR
|
|
.DATA_RATE_TQ("DDR"), // DDR, BUF, SDR
|
|
.DATA_WIDTH(4), // Parallel data width (2-8,10,14)
|
|
.INIT_OQ(1'b0), // Initial value of OQ output (1'b0,1'b1)
|
|
.INIT_TQ(1'b0), // Initial value of TQ output (1'b0,1'b1)
|
|
.SERDES_MODE("MASTER"), // MASTER, SLAVE
|
|
.SRVAL_OQ(1'b0), // OQ output value when SR is used (1'b0,1'b1)
|
|
.SRVAL_TQ(1'b0), // TQ output value when SR is used (1'b0,1'b1)
|
|
.TBYTE_CTL("FALSE"), // Enable tristate byte operation (FALSE, TRUE)
|
|
.TBYTE_SRC("FALSE"), // Tristate byte source (FALSE, TRUE)
|
|
.TRISTATE_WIDTH(4) // 3-state converter width (1,4)
|
|
)
|
|
OSERDESE2_inst (
|
|
.OFB(OFB), // 1-bit output: Feedback path for data
|
|
.OQ(OQ), // 1-bit output: Data path output
|
|
// SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
|
|
.SHIFTOUT1(SHIFTOUT1),
|
|
.SHIFTOUT2(SHIFTOUT2),
|
|
.TBYTEOUT(TBYTEOUT), // 1-bit output: Byte group tristate
|
|
.TFB(TFB), // 1-bit output: 3-state control
|
|
.TQ(TQ), // 1-bit output: 3-state control
|
|
.CLK(CLK), // 1-bit input: High speed clock
|
|
.CLKDIV(CLKDIV), // 1-bit input: Divided clock
|
|
// D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
|
|
.D1(D1),
|
|
.D2(D2),
|
|
.D3(D3),
|
|
.D4(D4),
|
|
.D5(D5),
|
|
.D6(D6),
|
|
.D7(D7),
|
|
.D8(D8),
|
|
.OCE(OCE), // 1-bit input: Output data clock enable
|
|
.RST(RST), // 1-bit input: Reset
|
|
// SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
|
|
.SHIFTIN1(SHIFTIN1),
|
|
.SHIFTIN2(SHIFTIN2),
|
|
// T1 - T4: 1-bit (each) input: Parallel 3-state inputs
|
|
.T1(T1),
|
|
.T2(T2),
|
|
.T3(T3),
|
|
.T4(T4),
|
|
.TBYTEIN(TBYTEIN), // 1-bit input: Byte group tristate
|
|
.TCE(TCE) // 1-bit input: 3-state clock enable
|
|
);
|
|
|
|
// End of OSERDESE2_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Input Buffers" treetype="folder">
|
|
<Template label="Single-ended Buffer (IBUF)" treetype="template">
|
|
// IBUF : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUF_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUF: Single-ended Input Buffer
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUF #(
|
|
.IBUF_LOW_PWR("TRUE"), // Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
) IBUF_inst (
|
|
.O(O), // Buffer output
|
|
.I(I) // Buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUF_inst instantiation
|
|
</Template>
|
|
<Template label="Single-ended Buffer w/ Disable (IBUF_IBUFDISABLE)" treetype="template">
|
|
// IBUF_IBUFDISABLE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUF_IBUFDISABLE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUF_IBUFDISABLE: Single-ended Input Buffer with Disable
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUF_IBUFDISABLE #(
|
|
.IBUF_LOW_PWR("TRUE"), // Low power ("TRUE") vs. performance ("FALSE") for referenced I/O standards
|
|
.IOSTANDARD("DEFAULT"), // Specify the input I/O standard
|
|
.USE_IBUFDISABLE("TRUE") // Set to "TRUE" to enable IBUFDISABLE feature
|
|
) IBUF_IBUFDISABLE_inst (
|
|
.O(O), // Buffer output
|
|
.I(I), // Buffer input (connect directly to top-level port)
|
|
.IBUFDISABLE(IBUFDISABLE) // Buffer disable input, low=disable
|
|
);
|
|
|
|
// End of IBUF_IBUFDISABLE_inst instantiation
|
|
</Template>
|
|
<Template label="Single-ended Buffer w/ Termination Disable (IBUF_INTERMDISABLE)" treetype="template">
|
|
// IBUF_INTERMDISABLE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUF_INTERMDISABLE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUF_INTERMDISABLE: Single-ended Input Buffer with Termination Input Disable
|
|
// May only be placed in High Range (HR) Banks
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUF_INTERMDISABLE #(
|
|
.IBUF_LOW_PWR("TRUE"), // Low power ("TRUE") vs. performance ("FALSE") for referenced I/O standards
|
|
.IOSTANDARD("DEFAULT"), // Specify the input I/O standard
|
|
.USE_IBUFDISABLE("TRUE") // Set to "TRUE" to enable IBUFDISABLE feature
|
|
) IBUF_INTERMDISABLE_inst (
|
|
.O(O), // Buffer output
|
|
.I(I), // Buffer input (connect directly to top-level port)
|
|
.IBUFDISABLE(IBUFDISABLE), // Buffer disable input, low=disable
|
|
.INTERMDISABLE(INTERMDISABLE) // Input Termination Disable
|
|
);
|
|
|
|
// End of IBUF_INTERMDISABLE_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer (IBUFDS)" treetype="template">
|
|
// IBUFDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFDS: Differential Input Buffer
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFDS #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination
|
|
.IBUF_LOW_PWR("TRUE"), // Low power="TRUE", Highest performance="FALSE"
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
) IBUFDS_inst (
|
|
.O(O), // Buffer output
|
|
.I(I), // Diff_p buffer input (connect directly to top-level port)
|
|
.IB(IB) // Diff_n buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUFDS_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer w/ Disable (IBUFDS_IBUFDISABLE)" treetype="template">
|
|
// IBUFDS_IBUFDISABLE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFDS_IBUFDISABLE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFDS_IBUFDISABLE: Differential Input Buffer with Input Disable
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFDS_IBUFDISABLE #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination
|
|
.IBUF_LOW_PWR("TRUE"), // Low power="TRUE", Highest performance="FALSE"
|
|
.IOSTANDARD("DEFAULT"), // Specify the input I/O standard
|
|
.USE_IBUFDISABLE("TRUE") // Set to "TRUE" to enable IBUFDISABLE feature
|
|
) IBUFDS_IBUFDISABLE_inst (
|
|
.O(O), // Buffer output
|
|
.I(I), // Diff_p buffer input (connect directly to top-level port)
|
|
.IB(IB), // Diff_n buffer input (connect directly to top-level port)
|
|
.IBUFDISABLE(IBUFDISABLE) // Buffer disable input, low=disable
|
|
);
|
|
|
|
// End of IBUFDS_IBUFDISABLE_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer w/ Termination Disable (IBUFDS_INTERMDISABLE)" treetype="template">
|
|
// IBUFDS_INTERMDISABLE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFDS_INTERMDISABLE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFDS_INTERMDISABLE: Differential Input Buffer with Input Termination Disable
|
|
// May only be placed in High Range (HR) Banks
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFDS_INTERMDISABLE #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination
|
|
.IBUF_LOW_PWR("TRUE"), // Low power="TRUE", Highest performance="FALSE"
|
|
.IOSTANDARD("DEFAULT"), // Specify the input I/O standard
|
|
.USE_IBUFDISABLE("TRUE") // Set to "TRUE" to enable IBUFDISABLE feature
|
|
) IBUFDS_INTERMDISABLE_inst (
|
|
.O(O), // Buffer output
|
|
.I(I), // Diff_p buffer input (connect directly to top-level port)
|
|
.IB(IB), // Diff_n buffer input (connect directly to top-level port)
|
|
.IBUFDISABLE(IBUFDISABLE), // Buffer disable input, low=disable
|
|
.INTERMDISABLE(INTERMDISABLE) // Input Termination Disable
|
|
);
|
|
|
|
// End of IBUFDS_INTERMDISABLE_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer with Differential Output (IBUFDS_DIFF_OUT)" treetype="template">
|
|
// IBUFDS_DIFF_OUT : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFDS_DIFF_OUT_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFDS_DIFF_OUT: Differential Input Buffer with Differential Output
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFDS_DIFF_OUT #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination, "TRUE"/"FALSE"
|
|
.IBUF_LOW_PWR("TRUE"), // Low power="TRUE", Highest performance="FALSE"
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
) IBUFDS_DIFF_OUT_inst (
|
|
.O(O), // Buffer diff_p output
|
|
.OB(OB), // Buffer diff_n output
|
|
.I(I), // Diff_p buffer input (connect directly to top-level port)
|
|
.IB(IB) // Diff_n buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUFDS_DIFF_OUT_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer with Differential Output w/ Input Disable (IBUFDS_DIFF_OUT_IBUFDISABLE)" treetype="template">
|
|
// IBUFDS_DIFF_OUT_IBUFDISABLE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFDS_DIFF_OUT_IBUFDISABLE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFDS_DIFF_OUT_IBUFDISABLE: Differential Input Buffer with Differential Output with Input Disable
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFDS_DIFF_OUT_IBUFDISABLE #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination, "TRUE"/"FALSE"
|
|
.IBUF_LOW_PWR("TRUE"), // Low power="TRUE", Highest performance="FALSE"
|
|
.IOSTANDARD("DEFAULT"), // Specify the input I/O standard
|
|
.USE_IBUFDISABLE("TRUE") // Set to "TRUE" to enable IBUFDISABLE feature
|
|
) IBUFDS_DIFF_OUT_IBUFDISABLE_inst (
|
|
.O(O), // Buffer diff_p output
|
|
.OB(OB), // Buffer diff_n output
|
|
.I(I), // Diff_p buffer input (connect directly to top-level port)
|
|
.IB(IB), // Diff_n buffer input (connect directly to top-level port)
|
|
.IBUFDISABLE(IBUFDISABLE) // Buffer disable input, low=disable
|
|
);
|
|
|
|
// End of IBUFDS_DIFF_OUT_IBUFDISABLE_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer with Differential Output w/ Input Termination Disable (IBUFDS_DIFF_OUT_INTERMDISABLE)" treetype="template">
|
|
// IBUFDS_DIFF_OUT_INTERMDISABLE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFDS_DIFF_OUT_INTERMDISABLE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFDS_DIFF_OUT_INTERMDISABLE: Differential Input Buffer with Differential Output with Input Termination Disable
|
|
// May only be placed in High Range (HR) Banks
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFDS_DIFF_OUT_INTERMDISABLE #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination, "TRUE"/"FALSE"
|
|
.IBUF_LOW_PWR("TRUE"), // Low power="TRUE", Highest performance="FALSE"
|
|
.IOSTANDARD("DEFAULT"), // Specify the input I/O standard
|
|
.USE_IBUFDISABLE("TRUE") // Set to "TRUE" to enable IBUFDISABLE feature
|
|
) IBUFDS_DIFF_OUT_INTERMDISABLE_inst (
|
|
.O(O), // Buffer diff_p output
|
|
.OB(OB), // Buffer diff_n output
|
|
.I(I), // Diff_p buffer input (connect directly to top-level port)
|
|
.IB(IB), // Diff_n buffer input (connect directly to top-level port)
|
|
.IBUFDISABLE(IBUFDISABLE), // Buffer disable input, low=disable
|
|
.INTERMDISABLE(INTERMDISABLE) // Input Termination Disable
|
|
);
|
|
|
|
// End of IBUFDS_DIFF_OUT_INTERMDISABLE_inst instantiation
|
|
</Template>
|
|
<Template label="Single-ended Global Clock Buffer (IBUFG)" treetype="template">
|
|
// IBUFG : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFG_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFG: Single-ended global clock input buffer
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFG #(
|
|
.IBUF_LOW_PWR("TRUE"), // Low power="TRUE", Highest performance="FALSE"
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
) IBUFG_inst (
|
|
.O(O), // Clock buffer output
|
|
.I(I) // Clock buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUFG_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Global Clock (IBUFGDS)" treetype="template">
|
|
// IBUFGDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFGDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFGDS: Differential Global Clock Input Buffer
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFGDS #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination
|
|
.IBUF_LOW_PWR("TRUE"), // Low power="TRUE", Highest performance="FALSE"
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
) IBUFGDS_inst (
|
|
.O(O), // Clock buffer output
|
|
.I(I), // Diff_p clock buffer input (connect directly to top-level port)
|
|
.IB(IB) // Diff_n clock buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUFGDS_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Global Clock Buffer with Differential Output (IBUFGDS_DIFF_OUT)" treetype="template">
|
|
// IBUFGDS_DIFF_OUT : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFGDS_DIFF_OUT_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFGDS_DIFF_OUT: Differential Global Clock Buffer with Differential Output
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFGDS_DIFF_OUT #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination, "TRUE"/"FALSE"
|
|
.IBUF_LOW_PWR("TRUE"), // Low power="TRUE", Highest performance="FALSE"
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
) IBUFGDS_DIFF_OUT_inst (
|
|
.O(O), // Buffer diff_p output
|
|
.OB(OB), // Buffer diff_n output
|
|
.I(I), // Diff_p buffer input (connect directly to top-level port)
|
|
.IB(IB) // Diff_n buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUFGDS_DIFF_OUT_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Output Buffers" treetype="folder">
|
|
<Template label="Single-ended Buffer (OBUF)" treetype="template">
|
|
// OBUF : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OBUF_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OBUF: Single-ended Output Buffer
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OBUF #(
|
|
.DRIVE(12), // Specify the output drive strength
|
|
.IOSTANDARD("DEFAULT"), // Specify the output I/O standard
|
|
.SLEW("SLOW") // Specify the output slew rate
|
|
) OBUF_inst (
|
|
.O(O), // Buffer output (connect directly to top-level port)
|
|
.I(I) // Buffer input
|
|
);
|
|
|
|
// End of OBUF_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer (OBUFDS)" treetype="template">
|
|
|
|
// OBUFDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OBUFDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OBUFDS: Differential Output Buffer
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OBUFDS #(
|
|
.IOSTANDARD("DEFAULT"), // Specify the output I/O standard
|
|
.SLEW("SLOW") // Specify the output slew rate
|
|
) OBUFDS_inst (
|
|
.O(O), // Diff_p output (connect directly to top-level port)
|
|
.OB(OB), // Diff_n output (connect directly to top-level port)
|
|
.I(I) // Buffer input
|
|
);
|
|
|
|
// End of OBUFDS_inst instantiation
|
|
</Template>
|
|
<Template label="Single-ended 3-state Buffer (OBUFT)" treetype="template">
|
|
// OBUFT : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OBUFT_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OBUFT: Single-ended 3-state Output Buffer
|
|
// All devices
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OBUFT #(
|
|
.DRIVE(12), // Specify the output drive strength
|
|
.IOSTANDARD("DEFAULT"), // Specify the output I/O standard
|
|
.SLEW("SLOW") // Specify the output slew rate
|
|
) OBUFT_inst (
|
|
.O(O), // Buffer output (connect directly to top-level port)
|
|
.I(I), // Buffer input
|
|
.T(T) // 3-state enable input
|
|
);
|
|
|
|
// End of OBUFT_inst instantiation
|
|
</Template>
|
|
<Template label="Differential 3-state Buffer (OBUFTDS)" treetype="template">
|
|
// OBUFTDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OBUFTDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OBUFTDS: Differential 3-state Output Buffer
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OBUFTDS #(
|
|
.IOSTANDARD("DEFAULT"), // Specify the output I/O standard
|
|
.SLEW("SLOW") // Specify the output slew rate
|
|
) OBUFTDS_inst (
|
|
.O(O), // Diff_p output (connect directly to top-level port)
|
|
.OB(OB), // Diff_n output (connect directly to top-level port)
|
|
.I(I), // Buffer input
|
|
.T(T) // 3-state enable input
|
|
);
|
|
|
|
// End of OBUFTDS_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Bi-directional Buffers" treetype="folder">
|
|
<Template label="Single-ended Buffer (IOBUF)" treetype="template">
|
|
// IOBUF : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IOBUF_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IOBUF: Single-ended Bi-directional Buffer
|
|
// All devices
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IOBUF #(
|
|
.DRIVE(12), // Specify the output drive strength
|
|
.IBUF_LOW_PWR("TRUE"), // Low Power - "TRUE", High Performance = "FALSE"
|
|
.IOSTANDARD("DEFAULT"), // Specify the I/O standard
|
|
.SLEW("SLOW") // Specify the output slew rate
|
|
) IOBUF_inst (
|
|
.O(O), // Buffer output
|
|
.IO(IO), // Buffer inout port (connect directly to top-level port)
|
|
.I(I), // Buffer input
|
|
.T(T) // 3-state enable input, high=input, low=output
|
|
);
|
|
|
|
// End of IOBUF_inst instantiation
|
|
</Template>
|
|
<Template label="Single-ended Buffer w/ input and DCI disable (IOBUF_DCIEN)" treetype="template">
|
|
// IOBUF_DCIEN : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IOBUF_DCIEN_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IOBUF_DCIEN: Single-ended Bi-directional Buffer with Digital Controlled Impedance (DCI)
|
|
// and Input path enable/disable
|
|
// May only be placed in High Performance (HP) Banks
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IOBUF_DCIEN #(
|
|
.DRIVE(12), // Specify the output drive strength
|
|
.IBUF_LOW_PWR("TRUE"), // Low Power - "TRUE", High Performance = "FALSE"
|
|
.IOSTANDARD("DEFAULT"), // Specify the I/O standard
|
|
.SLEW("SLOW"), // Specify the output slew rate
|
|
.USE_IBUFDISABLE("TRUE") // Use IBUFDISABLE function, "TRUE" or "FALSE"
|
|
) IOBUF_DCIEN_inst (
|
|
.O(O), // Buffer output
|
|
.IO(IO), // Buffer inout port (connect directly to top-level port)
|
|
.DCITERMDISABLE(DCITERMDISABLE), // DCI Termination enable input
|
|
.I(I), // Buffer input
|
|
.IBUFDISABLE(IBUFDISABLE), // Input disable input, low=disable
|
|
.T(T) // 3-state enable input, high=input, low=output
|
|
);
|
|
|
|
// End of IOBUF_DCIEN_inst instantiation
|
|
</Template>
|
|
<Template label="Single-ended Buffer w/ input and INTERM disable (IOBUF_INTERMDISABLE)" treetype="template">
|
|
// IOBUF_INTERMDISABLE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IOBUF_INTERMDISABLE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IOBUF_INTERMDISABLE: Single-ended Bi-directional Buffer with Input Termination
|
|
// and Input path enable/disable
|
|
// May only be placed in High Range (HR) Banks
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IOBUF_INTERMDISABLE #(
|
|
.DRIVE(12), // Specify the output drive strength
|
|
.IBUF_LOW_PWR("TRUE"), // Low Power - "TRUE", High Performance = "FALSE"
|
|
.IOSTANDARD("DEFAULT"), // Specify the I/O standard
|
|
.SLEW("SLOW"), // Specify the output slew rate
|
|
.USE_IBUFDISABLE("TRUE") // Use IBUFDISABLE function, "TRUE" or "FALSE"
|
|
) IOBUF_INTERMDISABLE_inst (
|
|
.O(O), // Buffer output
|
|
.IO(IO), // Buffer inout port (connect directly to top-level port)
|
|
.I(I), // Buffer input
|
|
.IBUFDISABLE(IBUFDISABLE), // Input disable input, low=disable
|
|
.INTERMDISABLE(INTERMDISABLE), // Input termination disable input
|
|
.T(T) // 3-state enable input, high=input, low=output
|
|
);
|
|
|
|
// End of IOBUF_INTERMDISABLE_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer (IOBUFDS)" treetype="template">
|
|
// IOBUFDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IOBUFDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IOBUFDS: Differential Bi-directional Buffer
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IOBUFDS #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination ("TRUE"/"FALSE")
|
|
.IBUF_LOW_PWR("TRUE"), // Low Power - "TRUE", High Performance = "FALSE"
|
|
.IOSTANDARD("BLVDS_25"), // Specify the I/O standard
|
|
.SLEW("SLOW") // Specify the output slew rate
|
|
) IOBUFDS_inst (
|
|
.O(O), // Buffer output
|
|
.IO(IO), // Diff_p inout (connect directly to top-level port)
|
|
.IOB(IOB), // Diff_n inout (connect directly to top-level port)
|
|
.I(I), // Buffer input
|
|
.T(T) // 3-state enable input, high=input, low=output
|
|
);
|
|
|
|
// End of IOBUFDS_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer w/ input and DCI disable (IOBUFDS_DCIEN)" treetype="template">
|
|
// IOBUFDS_DCIEN : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IOBUFDS_DCIEN_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IOBUFDS_DCIEN: Differential Bi-directional Buffer with Digital Controlled Impedance (DCI)
|
|
// and Input path enable/disable
|
|
// May only be placed in High Performance (HP) Banks
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IOBUFDS_DCIEN #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination ("TRUE"/"FALSE")
|
|
.IBUF_LOW_PWR("TRUE"), // Low Power - "TRUE", High Performance = "FALSE"
|
|
.IOSTANDARD("BLVDS_25"), // Specify the I/O standard
|
|
.SLEW("SLOW"), // Specify the output slew rate
|
|
.USE_IBUFDISABLE("TRUE") // Use IBUFDISABLE function, "TRUE" or "FALSE"
|
|
) IOBUFDS_DCIEN_inst (
|
|
.O(O), // Buffer output
|
|
.IO(IO), // Diff_p inout (connect directly to top-level port)
|
|
.IOB(IOB), // Diff_n inout (connect directly to top-level port)
|
|
.DCITERMDISABLE(DCITERMDISABLE), // DCI Termination enable input
|
|
.I(I), // Buffer input
|
|
.IBUFDISABLE(IBUFDISABLE), // Input disable input, low=disable
|
|
.T(T) // 3-state enable input, high=input, low=output
|
|
);
|
|
|
|
// End of IOBUFDS_DCIEN_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer w/ input and input termination disable (IOBUFDS_INTERMDISABLE)" treetype="template">
|
|
// IOBUFDS_INTERMDISABLE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IOBUFDS_INTERMDISABLE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IOBUFDS_INTERMDISABLE: Differential Bi-directional Buffer with Input Termination
|
|
// and Input path enable/disable
|
|
// May only be placed in High Range (HR) Banks
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IOBUFDS_INTERMDISABLE #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination ("TRUE"/"FALSE")
|
|
.IBUF_LOW_PWR("TRUE"), // Low Power - "TRUE", High Performance = "FALSE"
|
|
.IOSTANDARD("BLVDS_25"), // Specify the I/O standard
|
|
.SLEW("SLOW"), // Specify the output slew rate
|
|
.USE_IBUFDISABLE("TRUE") // Use IBUFDISABLE function, "TRUE" or "FALSE"
|
|
) IOBUFDS_INTERMDISABLE_inst (
|
|
.O(O), // Buffer output
|
|
.IO(IO), // Diff_p inout (connect directly to top-level port)
|
|
.IOB(IOB), // Diff_n inout (connect directly to top-level port)
|
|
.I(I), // Buffer input
|
|
.IBUFDISABLE(IBUFDISABLE), // Input disable input, low=disable
|
|
.INTERMDISABLE(INTERMDISABLE), // Input termination disable input
|
|
.T(T) // 3-state enable input, high=input, low=output
|
|
);
|
|
|
|
// End of IOBUFDS_INTERMDISABLE_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer with Differential Output (IOBUFDS_DIFF_OUT)" treetype="template">
|
|
// IOBUFDS_DIFF_OUT : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IOBUFDS_DIFF_OUT_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IOBUFDS_DIFF_OUT: Differential Bi-directional Buffer with Differential Output
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IOBUFDS_DIFF_OUT #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination ("TRUE"/"FALSE")
|
|
.IBUF_LOW_PWR("TRUE"), // Low Power - "TRUE", High Performance = "FALSE"
|
|
.IOSTANDARD("BLVDS_25") // Specify the I/O standard
|
|
) IOBUFDS_DIFF_OUT_inst (
|
|
.O(O), // Buffer p-side output
|
|
.OB(OB), // Buffer n-side output
|
|
.IO(IO), // Diff_p inout (connect directly to top-level port)
|
|
.IOB(IOB), // Diff_n inout (connect directly to top-level port)
|
|
.I(I), // Buffer input
|
|
.TM(TM), // 3-state enable input, high=input, low=output
|
|
.TS(TS) // 3-state enable input, high=output, low=input
|
|
);
|
|
|
|
// End of IOBUFDS_DIFF_OUT_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer w/ Differential Output, input and DCI disable (IOBUFDS_DIFF_OUT_DCIEN)" treetype="template">
|
|
// IOBUFDS_DIFF_OUT_DCIEN : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IOBUFDS_DIFF_OUT_DCIEN_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IOBUFDS_DIFF_OUT_DCIEN: Differential Bi-directional Buffer with Differential Output,
|
|
// Digital Controlled Impedance (DCI)and Input path enable/disable
|
|
// May only be placed in High Performance (HP) Banks
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IOBUFDS_DIFF_OUT_DCIEN #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination ("TRUE"/"FALSE")
|
|
.IBUF_LOW_PWR("TRUE"), // Low Power - "TRUE", High Performance = "FALSE"
|
|
.IOSTANDARD("BLVDS_25"), // Specify the I/O standard
|
|
.USE_IBUFDISABLE("TRUE") // Use IBUFDISABLE function, "TRUE" or "FALSE"
|
|
) IOBUFDS_DIFF_OUT_DCIEN_inst (
|
|
.O(O), // Buffer p-side output
|
|
.OB(OB), // Buffer n-side output
|
|
.IO(IO), // Diff_p inout (connect directly to top-level port)
|
|
.IOB(IOB), // Diff_n inout (connect directly to top-level port)
|
|
.DCITERMDISABLE(DCITERMDISABLE), // DCI Termination enable input
|
|
.I(I), // Buffer input
|
|
.IBUFDISABLE(IBUFDISABLE), // Input disable input, low=disable
|
|
.TM(TM), // 3-state enable input, high=input, low=output
|
|
.TS(TS) // 3-state enable input, high=output, low=input
|
|
);
|
|
|
|
// End of IOBUFDS_DIFF_OUT_DCIEN_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Global Clock Buffer w/ Differential Output, INTERM and IBUF disable (IOBUFDS_DIFF_OUT_INTERMDISABLE)" treetype="template">
|
|
// IOBUFDS_DIFF_OUT_INTERMDISABLE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IOBUFDS_DIFF_OUT_INTERMDISABLE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IOBUFDS_DIFF_OUT_INTERMDISABLE: Differential Global Clock Buffer with Differential Output
|
|
// Input Termination and Input Path Disable
|
|
// May only be placed in High Range (HR) Banks
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IOBUFDS_DIFF_OUT_INTERMDISABLE #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination, "TRUE"/"FALSE"
|
|
.IBUF_LOW_PWR("TRUE"), // Low power="TRUE", Highest performance="FALSE"
|
|
.IOSTANDARD("DEFAULT"), // Specify the input I/O standard
|
|
.USE_IBUFDISABLE("TRUE") // Set to "TRUE" to enable IBUFDISABLE feature
|
|
) IOBUFDS_DIFF_OUT_INTERMDISABLE_inst (
|
|
.O(O), // Buffer p-side output
|
|
.OB(OB), // Buffer n-side output
|
|
.IO(IO), // Diff_p inout (connect directly to top-level port)
|
|
.IOB(IOB), // Diff_n inout (connect directly to top-level port)
|
|
.I(I), // Buffer input
|
|
.INTERMDISABLE(INTERMDISABLE), // Input termination disable input
|
|
.IBUFDISABLE(IBUFDISABLE), // Input disable input, low=disable
|
|
.TM(TM), // 3-state enable input, high=input, low=output
|
|
.TS(TS) // 3-state enable input, high=output, low=input
|
|
);
|
|
|
|
// End of IOBUFDS_DIFF_OUT_INTERMDISABLE_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Weak drivers" treetype="folder">
|
|
<Template label="PULLUP" treetype="template">
|
|
// PULLUP : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (PULLUP_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design.
|
|
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// PULLUP: I/O Buffer Weak Pull-up
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
PULLUP PULLUP_inst (
|
|
.O(O) // Pullup output (connect directly to top-level port)
|
|
);
|
|
|
|
// End of PULLUP_inst instantiation
|
|
</Template>
|
|
<Template label="PULLDOWN" treetype="template">
|
|
// PULLDOWN : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (PULLDOWN_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// PULLDOWN: I/O Buffer Weak Pull-down
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
PULLDOWN PULLDOWN_inst (
|
|
.O(O) // Pulldown output (connect directly to top-level port)
|
|
);
|
|
|
|
// End of PULLDOWN_inst instantiation
|
|
</Template>
|
|
<Template label="KEEPER" treetype="template">
|
|
// KEEPER : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (KEEPER_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// KEEPER: I/O Buffer Weak Keeper
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
KEEPER KEEPER_inst (
|
|
.O(O) // Keeper output (connect directly to top-level port)
|
|
);
|
|
|
|
// End of KEEPER_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="DDR Registers" treetype="folder">
|
|
<Template label="Dual-Clock, Input DDR Register (IDDR_2CLK)" treetype="template">
|
|
// IDDR_2CLK : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IDDR_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IDDR_2CLK: Dual-Clock, Input Double Data Rate Input Register with
|
|
// Set, Reset and Clock Enable.
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IDDR_2CLK #(
|
|
.DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE", "SAME_EDGE"
|
|
// or "SAME_EDGE_PIPELINED"
|
|
.INIT_Q1(1'b0), // Initial value of Q1: 1'b0 or 1'b1
|
|
.INIT_Q2(1'b0), // Initial value of Q2: 1'b0 or 1'b1
|
|
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
|
|
) IDDR_2CLK_inst (
|
|
.Q1(Q1), // 1-bit output for positive edge of clock
|
|
.Q2(Q2), // 1-bit output for negative edge of clock
|
|
.C(C), // 1-bit primary clock input
|
|
.CB(CB), // 1-bit secondary clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.D(D), // 1-bit DDR data input
|
|
.R(R), // 1-bit reset
|
|
.S(S) // 1-bit set
|
|
);
|
|
|
|
// End of IDDR_2CLK_inst instantiation
|
|
</Template>
|
|
<Template label="Input DDR Register (IDDR)" treetype="template">
|
|
// IDDR : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IDDR_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IDDR: Input Double Data Rate Input Register with Set, Reset
|
|
// and Clock Enable.
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IDDR #(
|
|
.DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE", "SAME_EDGE"
|
|
// or "SAME_EDGE_PIPELINED"
|
|
.INIT_Q1(1'b0), // Initial value of Q1: 1'b0 or 1'b1
|
|
.INIT_Q2(1'b0), // Initial value of Q2: 1'b0 or 1'b1
|
|
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
|
|
) IDDR_inst (
|
|
.Q1(Q1), // 1-bit output for positive edge of clock
|
|
.Q2(Q2), // 1-bit output for negative edge of clock
|
|
.C(C), // 1-bit clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.D(D), // 1-bit DDR data input
|
|
.R(R), // 1-bit reset
|
|
.S(S) // 1-bit set
|
|
);
|
|
|
|
// End of IDDR_inst instantiation
|
|
</Template>
|
|
<Template label="Output DDR Register (ODDR)" treetype="template">
|
|
// ODDR : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ODDR_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ODDR: Output Double Data Rate Output Register with Set, Reset
|
|
// and Clock Enable.
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ODDR #(
|
|
.DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE"
|
|
.INIT(1'b0), // Initial value of Q: 1'b0 or 1'b1
|
|
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
|
|
) ODDR_inst (
|
|
.Q(Q), // 1-bit DDR output
|
|
.C(C), // 1-bit clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.D1(D1), // 1-bit data input (positive edge)
|
|
.D2(D2), // 1-bit data input (negative edge)
|
|
.R(R), // 1-bit reset
|
|
.S(S) // 1-bit set
|
|
);
|
|
|
|
// End of ODDR_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Arithmetic Functions" treetype="folder">
|
|
<Template label="48-bit Multi-Functional Arithmetic Block (DSP48E1)" treetype="template">
|
|
// DSP48E1 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (DSP48E1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// DSP48E1: 48-bit Multi-Functional Arithmetic Block
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
DSP48E1 #(
|
|
// Feature Control Attributes: Data Path Selection
|
|
.A_INPUT("DIRECT"), // Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
|
|
.B_INPUT("DIRECT"), // Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
|
|
.USE_DPORT("FALSE"), // Select D port usage (TRUE or FALSE)
|
|
.USE_MULT("MULTIPLY"), // Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE")
|
|
.USE_SIMD("ONE48"), // SIMD selection ("ONE48", "TWO24", "FOUR12")
|
|
// Pattern Detector Attributes: Pattern Detection Configuration
|
|
.AUTORESET_PATDET("NO_RESET"), // "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH"
|
|
.MASK(48'h3fffffffffff), // 48-bit mask value for pattern detect (1=ignore)
|
|
.PATTERN(48'h000000000000), // 48-bit pattern match for pattern detect
|
|
.SEL_MASK("MASK"), // "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2"
|
|
.SEL_PATTERN("PATTERN"), // Select pattern value ("PATTERN" or "C")
|
|
.USE_PATTERN_DETECT("NO_PATDET"), // Enable pattern detect ("PATDET" or "NO_PATDET")
|
|
// Register Control Attributes: Pipeline Register Configuration
|
|
.ACASCREG(1), // Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2)
|
|
.ADREG(1), // Number of pipeline stages for pre-adder (0 or 1)
|
|
.ALUMODEREG(1), // Number of pipeline stages for ALUMODE (0 or 1)
|
|
.AREG(1), // Number of pipeline stages for A (0, 1 or 2)
|
|
.BCASCREG(1), // Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2)
|
|
.BREG(1), // Number of pipeline stages for B (0, 1 or 2)
|
|
.CARRYINREG(1), // Number of pipeline stages for CARRYIN (0 or 1)
|
|
.CARRYINSELREG(1), // Number of pipeline stages for CARRYINSEL (0 or 1)
|
|
.CREG(1), // Number of pipeline stages for C (0 or 1)
|
|
.DREG(1), // Number of pipeline stages for D (0 or 1)
|
|
.INMODEREG(1), // Number of pipeline stages for INMODE (0 or 1)
|
|
.MREG(1), // Number of multiplier pipeline stages (0 or 1)
|
|
.OPMODEREG(1), // Number of pipeline stages for OPMODE (0 or 1)
|
|
.PREG(1) // Number of pipeline stages for P (0 or 1)
|
|
)
|
|
DSP48E1_inst (
|
|
// Cascade: 30-bit (each) output: Cascade Ports
|
|
.ACOUT(ACOUT), // 30-bit output: A port cascade output
|
|
.BCOUT(BCOUT), // 18-bit output: B port cascade output
|
|
.CARRYCASCOUT(CARRYCASCOUT), // 1-bit output: Cascade carry output
|
|
.MULTSIGNOUT(MULTSIGNOUT), // 1-bit output: Multiplier sign cascade output
|
|
.PCOUT(PCOUT), // 48-bit output: Cascade output
|
|
// Control: 1-bit (each) output: Control Inputs/Status Bits
|
|
.OVERFLOW(OVERFLOW), // 1-bit output: Overflow in add/acc output
|
|
.PATTERNBDETECT(PATTERNBDETECT), // 1-bit output: Pattern bar detect output
|
|
.PATTERNDETECT(PATTERNDETECT), // 1-bit output: Pattern detect output
|
|
.UNDERFLOW(UNDERFLOW), // 1-bit output: Underflow in add/acc output
|
|
// Data: 4-bit (each) output: Data Ports
|
|
.CARRYOUT(CARRYOUT), // 4-bit output: Carry output
|
|
.P(P), // 48-bit output: Primary data output
|
|
// Cascade: 30-bit (each) input: Cascade Ports
|
|
.ACIN(ACIN), // 30-bit input: A cascade data input
|
|
.BCIN(BCIN), // 18-bit input: B cascade input
|
|
.CARRYCASCIN(CARRYCASCIN), // 1-bit input: Cascade carry input
|
|
.MULTSIGNIN(MULTSIGNIN), // 1-bit input: Multiplier sign input
|
|
.PCIN(PCIN), // 48-bit input: P cascade input
|
|
// Control: 4-bit (each) input: Control Inputs/Status Bits
|
|
.ALUMODE(ALUMODE), // 4-bit input: ALU control input
|
|
.CARRYINSEL(CARRYINSEL), // 3-bit input: Carry select input
|
|
.CLK(CLK), // 1-bit input: Clock input
|
|
.INMODE(INMODE), // 5-bit input: INMODE control input
|
|
.OPMODE(OPMODE), // 7-bit input: Operation mode input
|
|
// Data: 30-bit (each) input: Data Ports
|
|
.A(A), // 30-bit input: A data input
|
|
.B(B), // 18-bit input: B data input
|
|
.C(C), // 48-bit input: C data input
|
|
.CARRYIN(CARRYIN), // 1-bit input: Carry input signal
|
|
.D(D), // 25-bit input: D data input
|
|
// Reset/Clock Enable: 1-bit (each) input: Reset/Clock Enable Inputs
|
|
.CEA1(CEA1), // 1-bit input: Clock enable input for 1st stage AREG
|
|
.CEA2(CEA2), // 1-bit input: Clock enable input for 2nd stage AREG
|
|
.CEAD(CEAD), // 1-bit input: Clock enable input for ADREG
|
|
.CEALUMODE(CEALUMODE), // 1-bit input: Clock enable input for ALUMODE
|
|
.CEB1(CEB1), // 1-bit input: Clock enable input for 1st stage BREG
|
|
.CEB2(CEB2), // 1-bit input: Clock enable input for 2nd stage BREG
|
|
.CEC(CEC), // 1-bit input: Clock enable input for CREG
|
|
.CECARRYIN(CECARRYIN), // 1-bit input: Clock enable input for CARRYINREG
|
|
.CECTRL(CECTRL), // 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
|
|
.CED(CED), // 1-bit input: Clock enable input for DREG
|
|
.CEINMODE(CEINMODE), // 1-bit input: Clock enable input for INMODEREG
|
|
.CEM(CEM), // 1-bit input: Clock enable input for MREG
|
|
.CEP(CEP), // 1-bit input: Clock enable input for PREG
|
|
.RSTA(RSTA), // 1-bit input: Reset input for AREG
|
|
.RSTALLCARRYIN(RSTALLCARRYIN), // 1-bit input: Reset input for CARRYINREG
|
|
.RSTALUMODE(RSTALUMODE), // 1-bit input: Reset input for ALUMODEREG
|
|
.RSTB(RSTB), // 1-bit input: Reset input for BREG
|
|
.RSTC(RSTC), // 1-bit input: Reset input for CREG
|
|
.RSTCTRL(RSTCTRL), // 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
|
|
.RSTD(RSTD), // 1-bit input: Reset input for DREG and ADREG
|
|
.RSTINMODE(RSTINMODE), // 1-bit input: Reset input for INMODEREG
|
|
.RSTM(RSTM), // 1-bit input: Reset input for MREG
|
|
.RSTP(RSTP) // 1-bit input: Reset input for PREG
|
|
);
|
|
|
|
// End of DSP48E1_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="RAM/ROM" treetype="folder">
|
|
<SubFolder label="FIFO" treetype="folder">
|
|
<Template label="18Kb First-In-First-Out (FIFO) Buffer Memory (FIFO18E1)" treetype="template">
|
|
// FIFO18E1 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FIFO18E1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FIFO18E1: 18Kb FIFO (First-In-First-Out) Block RAM Memory
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FIFO18E1 #(
|
|
.ALMOST_EMPTY_OFFSET(13'h0080), // Sets the almost empty threshold
|
|
.ALMOST_FULL_OFFSET(13'h0080), // Sets almost full threshold
|
|
.DATA_WIDTH(4), // Sets data width to 4-36
|
|
.DO_REG(1), // Enable output register (1-0) Must be 1 if EN_SYN = FALSE
|
|
.EN_SYN("FALSE"), // Specifies FIFO as dual-clock (FALSE) or Synchronous (TRUE)
|
|
.FIFO_MODE("FIFO18"), // Sets mode to FIFO18 or FIFO18_36
|
|
.FIRST_WORD_FALL_THROUGH("FALSE"), // Sets the FIFO FWFT to FALSE, TRUE
|
|
.INIT(36'h000000000), // Initial values on output port
|
|
.SIM_DEVICE("7SERIES"), // Must be set to "7SERIES" for simulation behavior
|
|
.SRVAL(36'h000000000) // Set/Reset value for output port
|
|
)
|
|
FIFO18E1_inst (
|
|
// Read Data: 32-bit (each) output: Read output data
|
|
.DO(DO), // 32-bit output: Data output
|
|
.DOP(DOP), // 4-bit output: Parity data output
|
|
// Status: 1-bit (each) output: Flags and other FIFO status outputs
|
|
.ALMOSTEMPTY(ALMOSTEMPTY), // 1-bit output: Almost empty flag
|
|
.ALMOSTFULL(ALMOSTFULL), // 1-bit output: Almost full flag
|
|
.EMPTY(EMPTY), // 1-bit output: Empty flag
|
|
.FULL(FULL), // 1-bit output: Full flag
|
|
.RDCOUNT(RDCOUNT), // 12-bit output: Read count
|
|
.RDERR(RDERR), // 1-bit output: Read error
|
|
.WRCOUNT(WRCOUNT), // 12-bit output: Write count
|
|
.WRERR(WRERR), // 1-bit output: Write error
|
|
// Read Control Signals: 1-bit (each) input: Read clock, enable and reset input signals
|
|
.RDCLK(RDCLK), // 1-bit input: Read clock
|
|
.RDEN(RDEN), // 1-bit input: Read enable
|
|
.REGCE(REGCE), // 1-bit input: Clock enable
|
|
.RST(RST), // 1-bit input: Asynchronous Reset
|
|
.RSTREG(RSTREG), // 1-bit input: Output register set/reset
|
|
// Write Control Signals: 1-bit (each) input: Write clock and enable input signals
|
|
.WRCLK(WRCLK), // 1-bit input: Write clock
|
|
.WREN(WREN), // 1-bit input: Write enable
|
|
// Write Data: 32-bit (each) input: Write input data
|
|
.DI(DI), // 32-bit input: Data input
|
|
.DIP(DIP) // 4-bit input: Parity input
|
|
);
|
|
|
|
// End of FIFO18E1_inst instantiation
|
|
</Template>
|
|
<Template label="36Kb First-In-First-Out (FIFO) Buffer Memory (FIFO36E1)" treetype="template">
|
|
// FIFO36E1 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FIFO36E1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FIFO36E1: 36Kb FIFO (First-In-First-Out) Block RAM Memory
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FIFO36E1 #(
|
|
.ALMOST_EMPTY_OFFSET(13'h0080), // Sets the almost empty threshold
|
|
.ALMOST_FULL_OFFSET(13'h0080), // Sets almost full threshold
|
|
.DATA_WIDTH(4), // Sets data width to 4-72
|
|
.DO_REG(1), // Enable output register (1-0) Must be 1 if EN_SYN = FALSE
|
|
.EN_ECC_READ("FALSE"), // Enable ECC decoder, FALSE, TRUE
|
|
.EN_ECC_WRITE("FALSE"), // Enable ECC encoder, FALSE, TRUE
|
|
.EN_SYN("FALSE"), // Specifies FIFO as Asynchronous (FALSE) or Synchronous (TRUE)
|
|
.FIFO_MODE("FIFO36"), // Sets mode to "FIFO36" or "FIFO36_72"
|
|
.FIRST_WORD_FALL_THROUGH("FALSE"), // Sets the FIFO FWFT to FALSE, TRUE
|
|
.INIT(72'h000000000000000000), // Initial values on output port
|
|
.SIM_DEVICE("7SERIES"), // Must be set to "7SERIES" for simulation behavior
|
|
.SRVAL(72'h000000000000000000) // Set/Reset value for output port
|
|
)
|
|
FIFO36E1_inst (
|
|
// ECC Signals: 1-bit (each) output: Error Correction Circuitry ports
|
|
.DBITERR(DBITERR), // 1-bit output: Double bit error status
|
|
.ECCPARITY(ECCPARITY), // 8-bit output: Generated error correction parity
|
|
.SBITERR(SBITERR), // 1-bit output: Single bit error status
|
|
// Read Data: 64-bit (each) output: Read output data
|
|
.DO(DO), // 64-bit output: Data output
|
|
.DOP(DOP), // 8-bit output: Parity data output
|
|
// Status: 1-bit (each) output: Flags and other FIFO status outputs
|
|
.ALMOSTEMPTY(ALMOSTEMPTY), // 1-bit output: Almost empty flag
|
|
.ALMOSTFULL(ALMOSTFULL), // 1-bit output: Almost full flag
|
|
.EMPTY(EMPTY), // 1-bit output: Empty flag
|
|
.FULL(FULL), // 1-bit output: Full flag
|
|
.RDCOUNT(RDCOUNT), // 13-bit output: Read count
|
|
.RDERR(RDERR), // 1-bit output: Read error
|
|
.WRCOUNT(WRCOUNT), // 13-bit output: Write count
|
|
.WRERR(WRERR), // 1-bit output: Write error
|
|
// ECC Signals: 1-bit (each) input: Error Correction Circuitry ports
|
|
.INJECTDBITERR(INJECTDBITERR), // 1-bit input: Inject a double bit error input
|
|
.INJECTSBITERR(INJECTSBITERR),
|
|
// Read Control Signals: 1-bit (each) input: Read clock, enable and reset input signals
|
|
.RDCLK(RDCLK), // 1-bit input: Read clock
|
|
.RDEN(RDEN), // 1-bit input: Read enable
|
|
.REGCE(REGCE), // 1-bit input: Clock enable
|
|
.RST(RST), // 1-bit input: Reset
|
|
.RSTREG(RSTREG), // 1-bit input: Output register set/reset
|
|
// Write Control Signals: 1-bit (each) input: Write clock and enable input signals
|
|
.WRCLK(WRCLK), // 1-bit input: Rising edge write clock.
|
|
.WREN(WREN), // 1-bit input: Write enable
|
|
// Write Data: 64-bit (each) input: Write input data
|
|
.DI(DI), // 64-bit input: Data input
|
|
.DIP(DIP) // 8-bit input: Parity input
|
|
);
|
|
|
|
// End of FIFO36E1_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="BlockRAM" treetype="folder">
|
|
<Template label="18Kb Block RAM Memory (RAMB18E1)" treetype="template">
|
|
// RAMB18E1 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB18E1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB18E1: 18K-bit Configurable Synchronous Block RAM
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB18E1 #(
|
|
// Address Collision Mode: "PERFORMANCE" or "DELAYED_WRITE"
|
|
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
|
|
// Collision check: Values ("ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE")
|
|
.SIM_COLLISION_CHECK("ALL"),
|
|
// DOA_REG, DOB_REG: Optional output register (0 or 1)
|
|
.DOA_REG(0),
|
|
.DOB_REG(0),
|
|
// INITP_00 to INITP_07: Initial contents of parity memory array
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// INIT_00 to INIT_3F: Initial contents of data memory array
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// INIT_A, INIT_B: Initial values on output ports
|
|
.INIT_A(18'h00000),
|
|
.INIT_B(18'h00000),
|
|
// Initialization File: RAM initialization file
|
|
.INIT_FILE("NONE"),
|
|
// RAM Mode: "SDP" or "TDP"
|
|
.RAM_MODE("TDP"),
|
|
// READ_WIDTH_A/B, WRITE_WIDTH_A/B: Read/write width per port
|
|
.READ_WIDTH_A(0), // 0-72
|
|
.READ_WIDTH_B(0), // 0-18
|
|
.WRITE_WIDTH_A(0), // 0-18
|
|
.WRITE_WIDTH_B(0), // 0-72
|
|
// RSTREG_PRIORITY_A, RSTREG_PRIORITY_B: Reset or enable priority ("RSTREG" or "REGCE")
|
|
.RSTREG_PRIORITY_A("RSTREG"),
|
|
.RSTREG_PRIORITY_B("RSTREG"),
|
|
// SRVAL_A, SRVAL_B: Set/reset value for output
|
|
.SRVAL_A(18'h00000),
|
|
.SRVAL_B(18'h00000),
|
|
// Simulation Device: Must be set to "7SERIES" for simulation behavior
|
|
.SIM_DEVICE("7SERIES"),
|
|
// WriteMode: Value on output upon a write ("WRITE_FIRST", "READ_FIRST", or "NO_CHANGE")
|
|
.WRITE_MODE_A("WRITE_FIRST"),
|
|
.WRITE_MODE_B("WRITE_FIRST")
|
|
)
|
|
RAMB18E1_inst (
|
|
// Port A Data: 16-bit (each) output: Port A data
|
|
.DOADO(DOADO), // 16-bit output: A port data/LSB data
|
|
.DOPADOP(DOPADOP), // 2-bit output: A port parity/LSB parity
|
|
// Port B Data: 16-bit (each) output: Port B data
|
|
.DOBDO(DOBDO), // 16-bit output: B port data/MSB data
|
|
.DOPBDOP(DOPBDOP), // 2-bit output: B port parity/MSB parity
|
|
// Port A Address/Control Signals: 14-bit (each) input: Port A address and control signals (read port
|
|
// when RAM_MODE="SDP")
|
|
.ADDRARDADDR(ADDRARDADDR), // 14-bit input: A port address/Read address
|
|
.CLKARDCLK(CLKARDCLK), // 1-bit input: A port clock/Read clock
|
|
.ENARDEN(ENARDEN), // 1-bit input: A port enable/Read enable
|
|
.REGCEAREGCE(REGCEAREGCE), // 1-bit input: A port register enable/Register enable
|
|
.RSTRAMARSTRAM(RSTRAMARSTRAM), // 1-bit input: A port set/reset
|
|
.RSTREGARSTREG(RSTREGARSTREG), // 1-bit input: A port register set/reset
|
|
.WEA(WEA), // 2-bit input: A port write enable
|
|
// Port A Data: 16-bit (each) input: Port A data
|
|
.DIADI(DIADI), // 16-bit input: A port data/LSB data
|
|
.DIPADIP(DIPADIP), // 2-bit input: A port parity/LSB parity
|
|
// Port B Address/Control Signals: 14-bit (each) input: Port B address and control signals (write port
|
|
// when RAM_MODE="SDP")
|
|
.ADDRBWRADDR(ADDRBWRADDR), // 14-bit input: B port address/Write address
|
|
.CLKBWRCLK(CLKBWRCLK), // 1-bit input: B port clock/Write clock
|
|
.ENBWREN(ENBWREN), // 1-bit input: B port enable/Write enable
|
|
.REGCEB(REGCEB), // 1-bit input: B port register enable
|
|
.RSTRAMB(RSTRAMB), // 1-bit input: B port set/reset
|
|
.RSTREGB(RSTREGB), // 1-bit input: B port register set/reset
|
|
.WEBWE(WEBWE), // 4-bit input: B port write enable/Write enable
|
|
// Port B Data: 16-bit (each) input: Port B data
|
|
.DIBDI(DIBDI), // 16-bit input: B port data/MSB data
|
|
.DIPBDIP(DIPBDIP) // 2-bit input: B port parity/MSB parity
|
|
);
|
|
|
|
// End of RAMB18E1_inst instantiation
|
|
</Template>
|
|
<Template label="36Kb Block RAM Memory (RAMB36E1)" treetype="template">
|
|
// RAMB36E1 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB36E1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB36E1: 36K-bit Configurable Synchronous Block RAM
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB36E1 #(
|
|
// Address Collision Mode: "PERFORMANCE" or "DELAYED_WRITE"
|
|
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
|
|
// Collision check: Values ("ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE")
|
|
.SIM_COLLISION_CHECK("ALL"),
|
|
// DOA_REG, DOB_REG: Optional output register (0 or 1)
|
|
.DOA_REG(0),
|
|
.DOB_REG(0),
|
|
.EN_ECC_READ("FALSE"), // Enable ECC decoder,
|
|
// FALSE, TRUE
|
|
.EN_ECC_WRITE("FALSE"), // Enable ECC encoder,
|
|
// FALSE, TRUE
|
|
// INITP_00 to INITP_0F: Initial contents of the parity memory array
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// INIT_00 to INIT_7F: Initial contents of the data memory array
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// INIT_A, INIT_B: Initial values on output ports
|
|
.INIT_A(36'h000000000),
|
|
.INIT_B(36'h000000000),
|
|
// Initialization File: RAM initialization file
|
|
.INIT_FILE("NONE"),
|
|
// RAM Mode: "SDP" or "TDP"
|
|
.RAM_MODE("TDP"),
|
|
// RAM_EXTENSION_A, RAM_EXTENSION_B: Selects cascade mode ("UPPER", "LOWER", or "NONE")
|
|
.RAM_EXTENSION_A("NONE"),
|
|
.RAM_EXTENSION_B("NONE"),
|
|
// READ_WIDTH_A/B, WRITE_WIDTH_A/B: Read/write width per port
|
|
.READ_WIDTH_A(0), // 0-72
|
|
.READ_WIDTH_B(0), // 0-36
|
|
.WRITE_WIDTH_A(0), // 0-36
|
|
.WRITE_WIDTH_B(0), // 0-72
|
|
// RSTREG_PRIORITY_A, RSTREG_PRIORITY_B: Reset or enable priority ("RSTREG" or "REGCE")
|
|
.RSTREG_PRIORITY_A("RSTREG"),
|
|
.RSTREG_PRIORITY_B("RSTREG"),
|
|
// SRVAL_A, SRVAL_B: Set/reset value for output
|
|
.SRVAL_A(36'h000000000),
|
|
.SRVAL_B(36'h000000000),
|
|
// Simulation Device: Must be set to "7SERIES" for simulation behavior
|
|
.SIM_DEVICE("7SERIES"),
|
|
// WriteMode: Value on output upon a write ("WRITE_FIRST", "READ_FIRST", or "NO_CHANGE")
|
|
.WRITE_MODE_A("WRITE_FIRST"),
|
|
.WRITE_MODE_B("WRITE_FIRST")
|
|
)
|
|
RAMB36E1_inst (
|
|
// Cascade Signals: 1-bit (each) output: BRAM cascade ports (to create 64kx1)
|
|
.CASCADEOUTA(CASCADEOUTA), // 1-bit output: A port cascade
|
|
.CASCADEOUTB(CASCADEOUTB), // 1-bit output: B port cascade
|
|
// ECC Signals: 1-bit (each) output: Error Correction Circuitry ports
|
|
.DBITERR(DBITERR), // 1-bit output: Double bit error status
|
|
.ECCPARITY(ECCPARITY), // 8-bit output: Generated error correction parity
|
|
.RDADDRECC(RDADDRECC), // 9-bit output: ECC read address
|
|
.SBITERR(SBITERR), // 1-bit output: Single bit error status
|
|
// Port A Data: 32-bit (each) output: Port A data
|
|
.DOADO(DOADO), // 32-bit output: A port data/LSB data
|
|
.DOPADOP(DOPADOP), // 4-bit output: A port parity/LSB parity
|
|
// Port B Data: 32-bit (each) output: Port B data
|
|
.DOBDO(DOBDO), // 32-bit output: B port data/MSB data
|
|
.DOPBDOP(DOPBDOP), // 4-bit output: B port parity/MSB parity
|
|
// Cascade Signals: 1-bit (each) input: BRAM cascade ports (to create 64kx1)
|
|
.CASCADEINA(CASCADEINA), // 1-bit input: A port cascade
|
|
.CASCADEINB(CASCADEINB), // 1-bit input: B port cascade
|
|
// ECC Signals: 1-bit (each) input: Error Correction Circuitry ports
|
|
.INJECTDBITERR(INJECTDBITERR), // 1-bit input: Inject a double bit error
|
|
.INJECTSBITERR(INJECTSBITERR), // 1-bit input: Inject a single bit error
|
|
// Port A Address/Control Signals: 16-bit (each) input: Port A address and control signals (read port
|
|
// when RAM_MODE="SDP")
|
|
.ADDRARDADDR(ADDRARDADDR), // 16-bit input: A port address/Read address
|
|
.CLKARDCLK(CLKARDCLK), // 1-bit input: A port clock/Read clock
|
|
.ENARDEN(ENARDEN), // 1-bit input: A port enable/Read enable
|
|
.REGCEAREGCE(REGCEAREGCE), // 1-bit input: A port register enable/Register enable
|
|
.RSTRAMARSTRAM(RSTRAMARSTRAM), // 1-bit input: A port set/reset
|
|
.RSTREGARSTREG(RSTREGARSTREG), // 1-bit input: A port register set/reset
|
|
.WEA(WEA), // 4-bit input: A port write enable
|
|
// Port A Data: 32-bit (each) input: Port A data
|
|
.DIADI(DIADI), // 32-bit input: A port data/LSB data
|
|
.DIPADIP(DIPADIP), // 4-bit input: A port parity/LSB parity
|
|
// Port B Address/Control Signals: 16-bit (each) input: Port B address and control signals (write port
|
|
// when RAM_MODE="SDP")
|
|
.ADDRBWRADDR(ADDRBWRADDR), // 16-bit input: B port address/Write address
|
|
.CLKBWRCLK(CLKBWRCLK), // 1-bit input: B port clock/Write clock
|
|
.ENBWREN(ENBWREN), // 1-bit input: B port enable/Write enable
|
|
.REGCEB(REGCEB), // 1-bit input: B port register enable
|
|
.RSTRAMB(RSTRAMB), // 1-bit input: B port set/reset
|
|
.RSTREGB(RSTREGB), // 1-bit input: B port register set/reset
|
|
.WEBWE(WEBWE), // 8-bit input: B port write enable/Write enable
|
|
// Port B Data: 32-bit (each) input: Port B data
|
|
.DIBDI(DIBDI), // 32-bit input: B port data/MSB data
|
|
.DIPBDIP(DIPBDIP) // 4-bit input: B port parity/MSB parity
|
|
);
|
|
|
|
// End of RAMB36E1_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Distributed ROM" treetype="folder">
|
|
<Template label="32 X 1 (ROM32X1)" treetype="template">
|
|
// ROM32X1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ROM32X1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ROM32X1: 32 x 1 Asynchronous Distributed (LUT) ROM (Mapped to a SliceM LUT6)
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ROM32X1 #(
|
|
.INIT(32'h00000000) // Contents of ROM
|
|
) ROM32X1_inst (
|
|
.O(O), // ROM output
|
|
.A0(A0), // ROM address[0]
|
|
.A1(A1), // ROM address[1]
|
|
.A2(A2), // ROM address[2]
|
|
.A3(A3), // ROM address[3]
|
|
.A4(A4) // ROM address[4]
|
|
);
|
|
|
|
// End of ROM32X1_inst instantiation
|
|
</Template>
|
|
<Template label="64 X 1 (ROM64X1)" treetype="template">
|
|
// ROM64X1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ROM64X1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ROM64X1: 64 x 1 Asynchronous Distributed (LUT) ROM (Mapped to a SliceM LUT6)
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ROM64X1 #(
|
|
.INIT(64'h0000000000000000) // Contents of ROM
|
|
) ROM64X1_inst (
|
|
.O(O), // ROM output
|
|
.A0(A0), // ROM address[0]
|
|
.A1(A1), // ROM address[1]
|
|
.A2(A2), // ROM address[2]
|
|
.A3(A3), // ROM address[3]
|
|
.A4(A4), // ROM address[4]
|
|
.A5(A5) // ROM address[5]
|
|
);
|
|
|
|
// End of ROM64X1_inst instantiation
|
|
</Template>
|
|
<Template label="128 X 1 (ROM128X1)" treetype="template">
|
|
// ROM128X1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ROM128X1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ROM128X1: 128 x 1 Asynchronous Distributed (LUT) ROM (Mapped to two SliceM LUT6s)
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ROM128X1 #(
|
|
.INIT(128'h00000000000000000000000000000000) // Contents of ROM
|
|
) ROM128X1_inst (
|
|
.O(O), // ROM output
|
|
.A0(A0), // ROM address[0]
|
|
.A1(A1), // ROM address[1]
|
|
.A2(A2), // ROM address[2]
|
|
.A3(A3), // ROM address[3]
|
|
.A4(A4), // ROM address[4]
|
|
.A5(A5), // ROM address[5]
|
|
.A6(A6) // ROM address[6]
|
|
);
|
|
|
|
// End of ROM128X1_inst instantiation
|
|
</Template>
|
|
<Template label="256 X 1 (ROM256X1)" treetype="template">
|
|
// ROM256X1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ROM256X1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ROM256X1: 256 x 1 Asynchronous Distributed (LUT) ROM (Mapped to four SliceM LUT6s)
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ROM256X1 #(
|
|
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000) // Contents of ROM
|
|
) ROM256X1_inst (
|
|
.O(O), // ROM output
|
|
.A0(A0), // ROM address[0]
|
|
.A1(A1), // ROM address[1]
|
|
.A2(A2), // ROM address[2]
|
|
.A3(A3), // ROM address[3]
|
|
.A4(A4), // ROM address[4]
|
|
.A5(A5), // ROM address[5]
|
|
.A6(A6), // ROM address[6]
|
|
.A7(A7) // ROM address[7]
|
|
);
|
|
|
|
// End of ROM256X1_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Distributed RAM" treetype="folder">
|
|
<SubFolder label="Single-Port" treetype="folder">
|
|
<SubFolder label="32 Deep (5-bit address)" treetype="folder">
|
|
<Template label="32 x 1 posedge write (RAM32X1S)" treetype="template">
|
|
// RAM32X1S : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM32X1S_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM32X1S: 32 x 1 posedge write distributed (LUT) RAM (Mapped to a SliceM LUT6)
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM32X1S #(
|
|
.INIT(32'h00000000) // Initial contents of RAM
|
|
) RAM32X1S_inst (
|
|
.O(O), // RAM output
|
|
.A0(A0), // RAM address[0] input
|
|
.A1(A1), // RAM address[1] input
|
|
.A2(A2), // RAM address[2] input
|
|
.A3(A3), // RAM address[3] input
|
|
.A4(A4), // RAM address[4] input
|
|
.D(D), // RAM data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM32X1S_inst instantiation
|
|
</Template>
|
|
<Template label="32 x 1 negedge write (RAM32X1S_1)" treetype="template">
|
|
// RAM32X1S_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM32X1S_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM32X1S_1: 32 x 1 negedge write distributed (LUT) RAM (Mapped to a SliceM LUT6)
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM32X1S_1 #(
|
|
.INIT(32'h00000000) // Initial contents of RAM
|
|
)RAM32X1S_1_inst (
|
|
.O(O), // RAM output
|
|
.A0(A0), // RAM address[0] input
|
|
.A1(A1), // RAM address[1] input
|
|
.A2(A2), // RAM address[2] input
|
|
.A3(A3), // RAM address[3] input
|
|
.A4(A4), // RAM address[4] input
|
|
.D(D), // RAM data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM32X1S_1_inst instantiation
|
|
</Template>
|
|
<Template label="32 x 2 posedge write (RAM32X2S)" treetype="template">
|
|
// RAM32X2S : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM16X2S_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM32X2S: 32 x 2 posedge write distributed (LUT) RAM (Mapped to a SliceM LUT6)
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM32X2S #(
|
|
.INIT_00(32'h00000000), // INIT for bit 0 of RAM
|
|
.INIT_01(32'h00000000) // INIT for bit 1 of RAM
|
|
) RAM32X2S_inst (
|
|
.O0(O0), // RAM data[0] output
|
|
.O1(O1), // RAM data[1] output
|
|
.A0(A0), // RAM address[0] input
|
|
.A1(A1), // RAM address[1] input
|
|
.A2(A2), // RAM address[2] input
|
|
.A3(A3), // RAM address[3] input
|
|
.A4(A4), // RAM address[4] input
|
|
.D0(D0), // RAM data[0] input
|
|
.D1(D1), // RAM data[1] input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM32X2S_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="64 Deep (6-bit address)" treetype="folder">
|
|
<Template label="64 X 1 posedge write (RAM64X1S)" treetype="template">
|
|
// RAM64X1S : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM64X1S_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM64X1S: 64 x 1 positive edge write, asynchronous read single-port distributed RAM (Mapped to a SliceM LUT6)
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM64X1S #(
|
|
.INIT(64'h0000000000000000) // Initial contents of RAM
|
|
) RAM64X1S_inst (
|
|
.O(O), // 1-bit data output
|
|
.A0(A0), // Address[0] input bit
|
|
.A1(A1), // Address[1] input bit
|
|
.A2(A2), // Address[2] input bit
|
|
.A3(A3), // Address[3] input bit
|
|
.A4(A4), // Address[4] input bit
|
|
.A5(A5), // Address[5] input bit
|
|
.D(D), // 1-bit data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM64X1S_inst instantiation
|
|
</Template>
|
|
<Template label="64 X 1 negedge write (RAM64X1S_1)" treetype="template">
|
|
// RAM64X1S_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM64X1S_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM64X1S_1: 64 x 1 negative edge write, asynchronous read single-port distributed RAM (Mapped to a SliceM LUT6)
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM64X1S_1 #(
|
|
.INIT(64'h0000000000000000) // Initial contents of RAM
|
|
) RAM64X1S_1_inst (
|
|
.O(O), // 1-bit data output
|
|
.A0(A0), // Address[0] input bit
|
|
.A1(A1), // Address[1] input bit
|
|
.A2(A2), // Address[2] input bit
|
|
.A3(A3), // Address[3] input bit
|
|
.A4(A4), // Address[4] input bit
|
|
.A5(A5), // Address[5] input bit
|
|
.D(D), // 1-bit data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM64X1S_1_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="128 Deep (7-bit address)" treetype="folder">
|
|
<Template label="128 X 1 posedge write (RAM128X1S)" treetype="template">
|
|
// RAM128X1S : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM128X1S_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM128X1S: 128 x 1 positive edge write, asynchronous read single-port distributed RAM (Mapped to two SliceM LUT6s)
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM128X1S #(
|
|
.INIT(128'h00000000000000000000000000000000) // Initial contents of RAM
|
|
) RAM128X1S_inst (
|
|
.O(O), // 1-bit data output
|
|
.A0(A0), // Address[0] input bit
|
|
.A1(A1), // Address[1] input bit
|
|
.A2(A2), // Address[2] input bit
|
|
.A3(A3), // Address[3] input bit
|
|
.A4(A4), // Address[4] input bit
|
|
.A5(A5), // Address[5] input bit
|
|
.A6(A6), // Address[6] input bit
|
|
.D(D), // 1-bit data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM128X1S_inst instantiation
|
|
</Template>
|
|
<Template label="128 X 1 negedge write (RAM128X1S_1)" treetype="template">
|
|
// RAM128X1S_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM128X1S_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM128X1S_1: 128 x 1 negative edge write, asynchronous read single-port distributed RAM (Mapped to two SliceM LUT6s)
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM128X1S_1 #(
|
|
.INIT(128'h00000000000000000000000000000000) // Initial contents of RAM
|
|
) RAM128X1S_1_inst (
|
|
.O(O), // 1-bit data output
|
|
.A0(A0), // Address[0] input bit
|
|
.A1(A1), // Address[1] input bit
|
|
.A2(A2), // Address[2] input bit
|
|
.A3(A3), // Address[3] input bit
|
|
.A4(A4), // Address[4] input bit
|
|
.A5(A5), // Address[5] input bit
|
|
.A6(A6), // Address[6] input bit
|
|
.D(D), // 1-bit data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM128X1S_1_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="256 Deep (8-bit address)" treetype="folder">
|
|
<Template label="256 X 1 posedge write (RAM256X1S)" treetype="template">
|
|
// RAM256X1S : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM256X1S_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM256X1S: 256-deep by 1-wide positive edge write, asynchronous read (Mapped to four SliceM LUT6s)
|
|
// single-port distributed LUT RAM
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM256X1S #(
|
|
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAM256X1S_inst (
|
|
.O(O), // Read/write port 1-bit output
|
|
.A(A), // Read/write port 8-bit address input
|
|
.WE(WE), // Write enable input
|
|
.WCLK(WCLK), // Write clock input
|
|
.D(D) // RAM data input
|
|
);
|
|
|
|
// End of RAM256X1S_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Dual-Port" treetype="folder">
|
|
<Template label="32 X 1 posedge write (RAM32X1D)" treetype="template">
|
|
// RAM32X1D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM32X1D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM32X1D: 32 x 1 positive edge write, asynchronous read dual-port distributed RAM (Mapped to a SliceM LUT6)
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM32X1D #(
|
|
.INIT(32'h00000000) // Initial contents of RAM
|
|
) RAM32X1D_inst (
|
|
.DPO(DPO), // Read-only 1-bit data output
|
|
.SPO(SPO), // Rw/ 1-bit data output
|
|
.A0(A0), // Rw/ address[0] input bit
|
|
.A1(A1), // Rw/ address[1] input bit
|
|
.A2(A2), // Rw/ address[2] input bit
|
|
.A3(A3), // Rw/ address[3] input bit
|
|
.A4(A4), // Rw/ address[4] input bit
|
|
.D(D), // Write 1-bit data input
|
|
.DPRA0(DPRA0), // Read-only address[0] input bit
|
|
.DPRA1(DPRA1), // Read-only address[1] input bit
|
|
.DPRA2(DPRA2), // Read-only address[2] input bit
|
|
.DPRA3(DPRA3), // Read-only address[3] input bit
|
|
.DPRA4(DPRA4), // Read-only address[4] input bit
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM32X1D_inst instantiation
|
|
</Template>
|
|
<Template label="32 X 1 negedge write (RAM32X1D_1)" treetype="template">
|
|
// RAM32X1D_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM32X1D_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM32X1D_1: 32 x 1 negative edge write, asynchronous read dual-port distributed RAM (Mapped to a SliceM LUT6)
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM32X1D_1 #(
|
|
.INIT(32'h00000000) // Initial contents of RAM
|
|
) RAM32X1D_1_inst (
|
|
.DPO(DPO), // Read-only 1-bit data output
|
|
.SPO(SPO), // Rw/ 1-bit data output
|
|
.A0(A0), // Rw/ address[0] input bit
|
|
.A1(A1), // Rw/ address[1] input bit
|
|
.A2(A2), // Rw/ address[2] input bit
|
|
.A3(A3), // Rw/ address[3] input bit
|
|
.A4(A4), // Rw/ address[4] input bit
|
|
.D(D), // Write 1-bit data input
|
|
.DPRA0(DPRA0), // Read-only address[0] input bit
|
|
.DPRA1(DPRA1), // Read-only address[1] input bit
|
|
.DPRA2(DPRA2), // Read-only address[2] input bit
|
|
.DPRA3(DPRA3), // Read-only address[3] input bit
|
|
.DPRA4(DPRA4), // Read-only address[4] input bit
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM32X1D_1_inst instantiation
|
|
</Template>
|
|
<Template label="64 X 1 posedge write (RAM64X1D)" treetype="template">
|
|
// RAM64X1D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM64X1D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM64X1D: 64 x 1 positive edge write, asynchronous read dual-port distributed RAM (Mapped to a SliceM LUT6)
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM64X1D #(
|
|
.INIT(64'h0000000000000000) // Initial contents of RAM
|
|
) RAM64X1D_inst (
|
|
.DPO(DPO), // Read-only 1-bit data output
|
|
.SPO(SPO), // Rw/ 1-bit data output
|
|
.A0(A0), // Rw/ address[0] input bit
|
|
.A1(A1), // Rw/ address[1] input bit
|
|
.A2(A2), // Rw/ address[2] input bit
|
|
.A3(A3), // Rw/ address[3] input bit
|
|
.A4(A4), // Rw/ address[4] input bit
|
|
.A5(A5), // Rw/ address[5] input bit
|
|
.D(D), // Write 1-bit data input
|
|
.DPRA0(DPRA0), // Read-only address[0] input bit
|
|
.DPRA1(DPRA1), // Read-only address[1] input bit
|
|
.DPRA2(DPRA2), // Read-only address[2] input bit
|
|
.DPRA3(DPRA3), // Read-only address[3] input bit
|
|
.DPRA4(DPRA4), // Read-only address[4] input bit
|
|
.DPRA5(DPRA5), // Read-only address[5] input bit
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM64X1D_inst instantiation
|
|
</Template>
|
|
<Template label="128 X 1 posedge write (RAM128X1D)" treetype="template">
|
|
// RAM128X1D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM128X1D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM128X1D: 128-deep by 1-wide positive edge write, asynchronous read (Mapped to two SliceM LUT6s)
|
|
// dual-port distributed LUT RAM
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM128X1D #(
|
|
.INIT(128'h00000000000000000000000000000000)
|
|
) RAM128X1D_inst (
|
|
.DPO(DPO), // Read port 1-bit output
|
|
.SPO(SPO), // Read/write port 1-bit output
|
|
.A(A), // Read/write port 7-bit address input
|
|
.D(D), // RAM data input
|
|
.DPRA(DPRA), // Read port 7-bit address input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM128X1D_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Multi-Port" treetype="folder">
|
|
<Template label="32 X 8 (RAM32M)" treetype="template">
|
|
// RAM32M : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM32M_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM32M: 32-deep by 8-wide Multi Port LUT RAM (Mapped to four SliceM LUT6s)
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM32M #(
|
|
.INIT_A(64'h0000000000000000), // Initial contents of A Port
|
|
.INIT_B(64'h0000000000000000), // Initial contents of B Port
|
|
.INIT_C(64'h0000000000000000), // Initial contents of C Port
|
|
.INIT_D(64'h0000000000000000) // Initial contents of D Port
|
|
) RAM32M_inst (
|
|
.DOA(DOA), // Read port A 2-bit output
|
|
.DOB(DOB), // Read port B 2-bit output
|
|
.DOC(DOC), // Read port C 2-bit output
|
|
.DOD(DOD), // Read/write port D 2-bit output
|
|
.ADDRA(ADDRA), // Read port A 5-bit address input
|
|
.ADDRB(ADDRB), // Read port B 5-bit address input
|
|
.ADDRC(ADDRC), // Read port C 5-bit address input
|
|
.ADDRD(ADDRD), // Read/write port D 5-bit address input
|
|
.DIA(DIA), // RAM 2-bit data write input addressed by ADDRD,
|
|
// read addressed by ADDRA
|
|
.DIB(DIB), // RAM 2-bit data write input addressed by ADDRD,
|
|
// read addressed by ADDRB
|
|
.DIC(DIC), // RAM 2-bit data write input addressed by ADDRD,
|
|
// read addressed by ADDRC
|
|
.DID(DID), // RAM 2-bit data write input addressed by ADDRD,
|
|
// read addressed by ADDRD
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM32M_inst instantiation
|
|
</Template>
|
|
<Template label="64 X 4 (RAM64M)" treetype="template">
|
|
// RAM64M : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM64M_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM64M: 64-deep by 4-wide Multi Port LUT RAM (Mapped to four SliceM LUT6s)
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM64M #(
|
|
.INIT_A(64'h0000000000000000), // Initial contents of A Port
|
|
.INIT_B(64'h0000000000000000), // Initial contents of B Port
|
|
.INIT_C(64'h0000000000000000), // Initial contents of C Port
|
|
.INIT_D(64'h0000000000000000) // Initial contents of D Port
|
|
) RAM64M_inst (
|
|
.DOA(DOA), // Read port A 1-bit output
|
|
.DOB(DOB), // Read port B 1-bit output
|
|
.DOC(DOC), // Read port C 1-bit output
|
|
.DOD(DOD), // Read/write port D 1-bit output
|
|
.DIA(DIA), // RAM 1-bit data write input addressed by ADDRD,
|
|
// read addressed by ADDRA
|
|
.DIB(DIB), // RAM 1-bit data write input addressed by ADDRD,
|
|
// read addressed by ADDRB
|
|
.DIC(DIC), // RAM 1-bit data write input addressed by ADDRD,
|
|
// read addressed by ADDRC
|
|
.DID(DID), // RAM 1-bit data write input addressed by ADDRD,
|
|
// read addressed by ADDRD
|
|
.ADDRA(ADDRA), // Read port A 6-bit address input
|
|
.ADDRB(ADDRB), // Read port B 6-bit address input
|
|
.ADDRC(ADDRC), // Read port C 6-bit address input
|
|
.ADDRD(ADDRD), // Read/write port D 6-bit address input
|
|
.WE(WE), // Write enable input
|
|
.WCLK(WCLK) // Write clock input
|
|
);
|
|
|
|
// End of RAM64M_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Advanced" treetype="folder">
|
|
<Template label="Gigabit Transceiver Buffer (IBUFDS_GTE2)" treetype="template">
|
|
// IBUFDS_GTE2 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFDS_GTE2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFDS_GTE2: Gigabit Transceiver Buffer
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFDS_GTE2 #(
|
|
.CLKCM_CFG("TRUE"), // Refer to Transceiver User Guide
|
|
.CLKRCV_TRST("TRUE"), // Refer to Transceiver User Guide
|
|
.CLKSWING_CFG(2'b11) // Refer to Transceiver User Guide
|
|
)
|
|
IBUFDS_GTE2_inst (
|
|
.O(O), // 1-bit output: Refer to Transceiver User Guide
|
|
.ODIV2(ODIV2), // 1-bit output: Refer to Transceiver User Guide
|
|
.CEB(CEB), // 1-bit input: Refer to Transceiver User Guide
|
|
.I(I), // 1-bit input: Refer to Transceiver User Guide
|
|
.IB(IB) // 1-bit input: Refer to Transceiver User Guide
|
|
);
|
|
|
|
// End of IBUFDS_GTE2_inst instantiation
|
|
</Template>
|
|
<Template label="Xilinx Analog-to-Digital Converter (XADC)" treetype="template">
|
|
// XADC : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (XADC_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// XADC: Dual 12-Bit 1MSPS Analog-to-Digital Converter
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
XADC #(
|
|
// INIT_40 - INIT_42: XADC configuration registers
|
|
.INIT_40(16'h0000),
|
|
.INIT_41(16'h0000),
|
|
.INIT_42(16'h0800),
|
|
// INIT_48 - INIT_4F: Sequence Registers
|
|
.INIT_48(16'h0000),
|
|
.INIT_49(16'h0000),
|
|
.INIT_4A(16'h0000),
|
|
.INIT_4B(16'h0000),
|
|
.INIT_4C(16'h0000),
|
|
.INIT_4D(16'h0000),
|
|
.INIT_4F(16'h0000),
|
|
.INIT_4E(16'h0000), // Sequence register 6
|
|
// INIT_50 - INIT_58, INIT5C: Alarm Limit Registers
|
|
.INIT_50(16'h0000),
|
|
.INIT_51(16'h0000),
|
|
.INIT_52(16'h0000),
|
|
.INIT_53(16'h0000),
|
|
.INIT_54(16'h0000),
|
|
.INIT_55(16'h0000),
|
|
.INIT_56(16'h0000),
|
|
.INIT_57(16'h0000),
|
|
.INIT_58(16'h0000),
|
|
.INIT_5C(16'h0000),
|
|
// Simulation attributes: Set for proper simulation behavior
|
|
.SIM_DEVICE("7SERIES"), // Select target device (values)
|
|
.SIM_MONITOR_FILE(""design.txt"") // Analog simulation data file name
|
|
)
|
|
XADC_inst (
|
|
// ALARMS: 8-bit (each) output: ALM, OT
|
|
.ALM(ALM), // 8-bit output: Output alarm for temp, Vccint, Vccaux and Vccbram
|
|
.OT(OT), // 1-bit output: Over-Temperature alarm
|
|
// Dynamic Reconfiguration Port (DRP): 16-bit (each) output: Dynamic Reconfiguration Ports
|
|
.DO(DO), // 16-bit output: DRP output data bus
|
|
.DRDY(DRDY), // 1-bit output: DRP data ready
|
|
// STATUS: 1-bit (each) output: XADC status ports
|
|
.BUSY(BUSY), // 1-bit output: ADC busy output
|
|
.CHANNEL(CHANNEL), // 5-bit output: Channel selection outputs
|
|
.EOC(EOC), // 1-bit output: End of Conversion
|
|
.EOS(EOS), // 1-bit output: End of Sequence
|
|
.JTAGBUSY(JTAGBUSY), // 1-bit output: JTAG DRP transaction in progress output
|
|
.JTAGLOCKED(JTAGLOCKED), // 1-bit output: JTAG requested DRP port lock
|
|
.JTAGMODIFIED(JTAGMODIFIED), // 1-bit output: JTAG Write to the DRP has occurred
|
|
.MUXADDR(MUXADDR), // 5-bit output: External MUX channel decode
|
|
// Auxiliary Analog-Input Pairs: 16-bit (each) input: VAUXP[15:0], VAUXN[15:0]
|
|
.VAUXN(VAUXN), // 16-bit input: N-side auxiliary analog input
|
|
.VAUXP(VAUXP), // 16-bit input: P-side auxiliary analog input
|
|
// CONTROL and CLOCK: 1-bit (each) input: Reset, conversion start and clock inputs
|
|
.CONVST(CONVST), // 1-bit input: Convert start input
|
|
.CONVSTCLK(CONVSTCLK), // 1-bit input: Convert start input
|
|
.RESET(RESET), // 1-bit input: Active-high reset
|
|
// Dedicated Analog Input Pair: 1-bit (each) input: VP/VN
|
|
.VN(VN), // 1-bit input: N-side analog input
|
|
.VP(VP), // 1-bit input: P-side analog input
|
|
// Dynamic Reconfiguration Port (DRP): 7-bit (each) input: Dynamic Reconfiguration Ports
|
|
.DADDR(DADDR), // 7-bit input: DRP address bus
|
|
.DCLK(DCLK), // 1-bit input: DRP clock
|
|
.DEN(DEN), // 1-bit input: DRP enable signal
|
|
.DI(DI), // 16-bit input: DRP input data bus
|
|
.DWE(DWE) // 1-bit input: DRP write enable
|
|
);
|
|
|
|
// End of XADC_inst instantiation
|
|
</Template>
|
|
<Template label="XADC Simulation File" treetype="template">
|
|
// Must use valid headers on all columns
|
|
// Comments can be added to the stimulus file using '//'
|
|
|
|
TIME TEMP VCCAUX VCCINT VBRAM VP VN VAUXP[0] VAUXN[0]
|
|
00000 45 1.8 1.0 1.0 0.5 0.0 0.7 0.0
|
|
05000 85 1.77 1.01 1.01 0.3 0.0 0.2 0.0
|
|
|
|
// Time stamp data is in nano seconds (ns)
|
|
// Temperature is recorded in C (degrees centigrade)
|
|
// All other channels are recorded as V (Volts)
|
|
// Valid column headers are:
|
|
// TIME, TEMP, VCCAUX, VCCINT, VBRAM, VCCPINT, VCCPAUX, VCCDDRO, VP, VN,
|
|
// VAUXP[0], VAUXN[0],...............VAUXP[15], VAUXN[15]
|
|
// External analog inputs are differential so VP = 0.5 and VN = 0.1 the
|
|
// input on channel VP/VN in 0.5 - 0.1 = 0.4V
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Slice/CLB Primitives" treetype="folder">
|
|
<SubFolder label="MUXFx" treetype="folder">
|
|
<Template label="MUXF7" treetype="template">
|
|
// MUXF7 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF7_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF7: CLB MUX to tie two LUT6's together with general output
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF7 MUXF7_inst (
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie to LUT6 O6 pin)
|
|
.I1(I1), // Input (tie to LUT6 O6 pin)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF7_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF7_L" treetype="template">
|
|
// MUXF7_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF7_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF7_L: CLB MUX to tie two LUT6's together with local output
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF7_L MUXF7_L_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.I0(I0), // Input (tie to LUT6 O6 pin)
|
|
.I1(I1), // Input (tie to LUT6 O6 pin)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF7_L_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF7_D" treetype="template">
|
|
// MUXF7_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF7_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF7_D: CLB MUX to tie two LUT6's together with general and local outputs
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF7_D MUXF7_D_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie to LUT6 O6 pin)
|
|
.I1(I1), // Input (tie to LUT6 O6 pin)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF7_D_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF8" treetype="template">
|
|
// MUXF8 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF8_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF8: CLB MUX to tie two MUXF7's together with general output
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF8 MUXF8_inst (
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie to MUXF7 L/LO out)
|
|
.I1(I1), // Input (tie to MUXF7 L/LO out)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF8_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF8_L" treetype="template">
|
|
// MUXF8_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF8_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF8_L: CLB MUX to tie two MUXF7's together with local output
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF8_L MUXF8_L_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.I0(I0), // Input (tie to MUXF7 L/LO out)
|
|
.I1(I1), // Input (tie to MUXF7 L/LO out)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF8_L_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF8_D" treetype="template">
|
|
// MUXF8_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF8_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF8_D: CLB MUX to tie two MUXF7's together with general and local outputs
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF8_D MUXF8_D_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie to MUXF7 L/LO out)
|
|
.I1(I1), // Input (tie to MUXF7 L/LO out)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF8_D_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="LUTs" treetype="folder">
|
|
<SubFolder label="Info" treetype="folder">
|
|
<Template label="Info (LUT INIT)" treetype="template">
|
|
// The INIT parameter for the FPGA LUT primitive is what gives the LUT its
|
|
// logical value. By default this value is zero thus driving the output to a
|
|
// zero regardless of the input values (acting as a ground) however in most
|
|
// cases an new INIT value must be determined in order to specify the logic
|
|
// function for the LUT primitive. There are a few methods in which the LUT
|
|
// value can be determined and two of those methods will be discussed here.
|
|
//
|
|
// The Truth Table Method
|
|
// ----------------------
|
|
//
|
|
// A common method to determine the desired INIT value for a LUT is using a
|
|
// truth table. To do so, simply create a binary truth table of all possible
|
|
// inputs, specify the desired logic value of the output and then create the
|
|
// INIT string from those output values. An example is shown below:
|
|
//
|
|
// Example of determining an XOR INIT equation for a LUT4:
|
|
//
|
|
// _________________
|
|
// | I3 I2 I1 I0 | O |
|
|
// |-----------------|
|
|
// | 0 0 0 0 | 0 |\
|
|
// | 0 0 0 1 | 1 | \ = 4'b0110 = 4'h6 ---------------+
|
|
// | 0 0 1 0 | 1 | / |
|
|
// | 0 0 1 1 | 0 |/ |
|
|
// |-------------|---| |
|
|
// | 0 1 0 0 | 1 |\ |
|
|
// | 0 1 0 1 | 0 | \ = 4'b1001 = 4'h9 |
|
|
// | 0 1 1 0 | 0 | / |
|
|
// | 0 1 1 1 | 1 |/ |
|
|
// |-------------|---| INIT = 16'h6996
|
|
// | 1 0 0 0 | 1 |\ |
|
|
// | 1 0 0 1 | 0 | \ = 4'b0110 = 4'h9 |
|
|
// | 1 0 1 0 | 0 | / |
|
|
// | 1 0 1 1 | 1 |/ |
|
|
// |-------------|---| |
|
|
// | 1 1 0 0 | 0 |\ |
|
|
// | 1 1 0 1 | 1 | \ = 4'b1001 = 4'h6 ------------+
|
|
// | 1 1 1 0 | 1 | /
|
|
// | 1 1 1 1 | 0 |/
|
|
// -------------------
|
|
//
|
|
// Example of determining a 3-input AND gate:
|
|
//
|
|
// ______________
|
|
// | I2 I1 I0 | O |
|
|
// |--------------|
|
|
// | 0 0 0 | 0 |\
|
|
// | 0 0 1 | 0 | \ = 4'b0000 = 4'h0 --------------+
|
|
// | 0 1 0 | 0 | / |
|
|
// | 0 1 1 | 0 |/ |
|
|
// |----------|---| INIT = 8'h80
|
|
// | 1 0 0 | 0 |\ |
|
|
// | 1 0 1 | 0 | \ = 4'b1000 = 4'h8 -------------+
|
|
// | 1 1 0 | 0 | /
|
|
// | 1 1 1 | 1 |/
|
|
// ----------------
|
|
//
|
|
// The Equation Method
|
|
// -------------------
|
|
//
|
|
// Another method to determine the LUT value is to define parameters for each
|
|
// input to the LUT that correspond to their listed truth value and use those to
|
|
// build the logic equation you are after. This method is easier to understand
|
|
// once you have grasped the concept and more self-documenting that the above
|
|
// method however does require the code to first specify the appropriate
|
|
// parameters. See the example below.
|
|
//
|
|
// Example of specifying the equation (A and B) or (C and D) for a LUT4:
|
|
//
|
|
// The forllowing parameters are defined to allow for
|
|
// equation-based INIT specification.
|
|
parameter I0 = 16'haaaa;
|
|
parameter I1 = 16'hcccc;
|
|
parameter I2 = 16'hf0f0;
|
|
parameter I3 = 16'hff00;
|
|
|
|
// LUT4: 4-input Look-Up Table with general output (Mapped to a LUT6)
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT4 #(
|
|
.INIT((I0&I1)|(I2&I3)) // Specify LUT Contents
|
|
) LUT4_inst (
|
|
.O(O_LUT), // LUT general output
|
|
.I0(A), // LUT input
|
|
.I1(B), // LUT input
|
|
.I2(C), // LUT input
|
|
.I3(D) // LUT input
|
|
);
|
|
|
|
// End of LUT4_inst instantiation
|
|
|
|
// With the parameters specifying all possible cases for the truth table, a
|
|
// Verilog equation can be written to determine the end INIT value.
|
|
</Template>
|
|
<SubFolder label="INIT Parameters" treetype="folder">
|
|
<Template label="LUT1" treetype="template">
|
|
// The forllowing parameter is defined to allow for
|
|
// equation-based INIT specification for a LUT1.
|
|
parameter I0 = 2'b10;
|
|
</Template>
|
|
<Template label="LUT2" treetype="template">
|
|
// The forllowing parameters are defined to allow for
|
|
// equation-based INIT specification for a LUT2.
|
|
parameter I0 = 4'ha;
|
|
parameter I1 = 4'hc;
|
|
</Template>
|
|
<Template label="LUT3" treetype="template">
|
|
// The forllowing parameters are defined to allow for
|
|
// equation-based INIT specification for a LUT3.
|
|
parameter I0 = 8'haa;
|
|
parameter I1 = 8'hcc;
|
|
parameter I2 = 8'hf0;
|
|
</Template>
|
|
<Template label="LUT4" treetype="template">
|
|
// The forllowing parameters are defined to allow for
|
|
// equation-based INIT specification for a LUT4.
|
|
parameter I0 = 16'haaaa;
|
|
parameter I1 = 16'hcccc;
|
|
parameter I2 = 16'hf0f0;
|
|
parameter I3 = 16'hff00;
|
|
</Template>
|
|
<Template label="LUT5" treetype="template">
|
|
// The forllowing parameters are defined to allow for
|
|
// equation-based INIT specification for a LUT5.
|
|
parameter I0 = 32'haaaaaaaa;
|
|
parameter I1 = 32'hcccccccc;
|
|
parameter I2 = 32'hf0f0f0f0;
|
|
parameter I3 = 32'hff00ff00;
|
|
parameter I4 = 32'hffff0000;
|
|
</Template>
|
|
<Template label="LUT6" treetype="template">
|
|
// The forllowing parameters are defined to allow for
|
|
// equation-based INIT specification for a LUT6.
|
|
parameter I0 = 64'haaaaaaaaaaaaaaaa;
|
|
parameter I1 = 64'hcccccccccccccccc;
|
|
parameter I2 = 64'hf0f0f0f0f0f0f0f0;
|
|
parameter I3 = 64'hff00ff00ff00ff00;
|
|
parameter I4 = 64'hffff0000ffff0000;
|
|
parameter I5 = 64'hffffffff00000000;
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="INIT Truth Tables" treetype="folder">
|
|
<Template label="LUT1" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT1
|
|
// ________
|
|
// | I0 | O |
|
|
// |--------|
|
|
// | 0 | ? |\
|
|
// | 1 | ? |/ = 2'b??
|
|
// ----------
|
|
</Template>
|
|
<Template label="LUT2" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT2
|
|
// ______________
|
|
// | I2 I1 I0 | O |
|
|
// |--------------|
|
|
// | 0 0 0 | ? |\
|
|
// | 0 0 1 | ? | \ = INIT = 4'b???? = 4'h?
|
|
// | 0 1 0 | ? | /
|
|
// | 0 1 1 | ? |/
|
|
// ---------- ---
|
|
</Template>
|
|
<Template label="LUT3" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT3
|
|
// ______________
|
|
// | I2 I1 I0 | O |
|
|
// |--------------|
|
|
// | 0 0 0 | ? |\
|
|
// | 0 0 1 | ? | \ = 4'b???? = 4'h? --------------+
|
|
// | 0 1 0 | ? | / |
|
|
// | 0 1 1 | ? |/ |
|
|
// |----------|---| INIT = 8'h??
|
|
// | 1 0 0 | ? |\ |
|
|
// | 1 0 1 | ? | \ = 4'b???? = 4'h? -------------+
|
|
// | 1 1 0 | ? | /
|
|
// | 1 1 1 | ? |/
|
|
// ----------------
|
|
</Template>
|
|
<Template label="LUT4" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT4
|
|
// _________________
|
|
// | I3 I2 I1 I0 | O |
|
|
// |-----------------|
|
|
// | 0 0 0 0 | ? |\
|
|
// | 0 0 0 1 | ? | \ = 4'b???? = 4'h? ---------------+
|
|
// | 0 0 1 0 | ? | / |
|
|
// | 0 0 1 1 | ? |/ |
|
|
// |-------------|---| |
|
|
// | 0 1 0 0 | ? |\ |
|
|
// | 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 1 0 | ? | / |
|
|
// | 0 1 1 1 | ? |/ |
|
|
// |-------------|---| INIT = 16'h????
|
|
// | 1 0 0 0 | ? |\ |
|
|
// | 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 1 0 | ? | / |
|
|
// | 1 0 1 1 | ? |/ |
|
|
// |-------------|---| |
|
|
// | 1 1 0 0 | ? |\ |
|
|
// | 1 1 0 1 | ? | \ = 4'b???? = 4'h? ------------+
|
|
// | 1 1 1 0 | ? | /
|
|
// | 1 1 1 1 | ? |/
|
|
// -------------------
|
|
</Template>
|
|
<Template label="LUT5" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT5
|
|
// ____________________
|
|
// | I4 I3 I2 I1 I0 | O |
|
|
// |--------------------|
|
|
// | 0 0 0 0 0 | ? |\
|
|
// | 0 0 0 0 1 | ? | \ = 4'b???? = 4'h? -------------------+
|
|
// | 0 0 0 1 0 | ? | / |
|
|
// | 0 0 0 1 1 | ? |/ |
|
|
// |----------------|---| |
|
|
// | 0 0 1 0 0 | ? |\ |
|
|
// | 0 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 0 1 1 0 | ? | / |
|
|
// | 0 0 1 1 1 | ? |/ |
|
|
// |----------------|---| |
|
|
// | 0 1 0 0 0 | ? |\ |
|
|
// | 0 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 0 1 0 | ? | / |
|
|
// | 0 1 0 1 1 | ? |/ |
|
|
// |----------------|---| |
|
|
// | 0 1 1 0 0 | ? |\ |
|
|
// | 0 1 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 1 1 0 | ? | / |
|
|
// | 0 1 1 1 1 | ? |/ |
|
|
// ---------------------- INIT = 32'h????????
|
|
// | 1 0 0 0 0 | ? |\ |
|
|
// | 1 0 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 0 1 0 | ? | / |
|
|
// | 1 0 0 1 1 | ? |/ |
|
|
// |----------------|---| |
|
|
// | 1 0 1 0 0 | ? |\ |
|
|
// | 1 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 1 1 0 | ? | / |
|
|
// | 1 0 1 1 1 | ? |/ |
|
|
// |----------------|---| |
|
|
// | 1 1 0 0 0 | ? |\ |
|
|
// | 1 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 1 0 1 0 | ? | / |
|
|
// | 1 1 0 1 1 | ? |/ |
|
|
// |----------------|---| |
|
|
// | 1 1 1 0 0 | ? |\ |
|
|
// | 1 1 1 0 1 | ? | \ = 4'b???? = 4'h? ------------+
|
|
// | 1 1 1 1 0 | ? | /
|
|
// | 1 1 1 1 1 | ? |/
|
|
// ----------------------
|
|
</Template>
|
|
<Template label="LUT6" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT6
|
|
// _______________________
|
|
// | I5 I4 I3 I2 I1 I0 | O |
|
|
// |-----------------------|
|
|
// | 0 0 0 0 0 0 | ? |\
|
|
// | 0 0 0 0 0 1 | ? | \ = 4'b???? = 4'h? -------------------+
|
|
// | 0 0 0 0 1 0 | ? | / |
|
|
// | 0 0 0 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 0 0 0 1 0 0 | ? |\ |
|
|
// | 0 0 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 0 0 1 1 0 | ? | / |
|
|
// | 0 0 0 1 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 0 0 1 0 0 0 | ? |\ |
|
|
// | 0 0 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 0 1 0 1 0 | ? | / |
|
|
// | 0 0 1 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 0 0 1 1 0 0 | ? |\ |
|
|
// | 0 0 1 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 0 1 1 1 0 | ? | / |
|
|
// | 0 0 1 1 1 1 | ? |/ |
|
|
// ------------------------- |
|
|
// | 0 1 0 0 0 0 | ? |\ |
|
|
// | 0 1 0 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 0 0 1 0 | ? | / |
|
|
// | 0 1 0 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 0 1 0 1 0 0 | ? |\ |
|
|
// | 0 1 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 0 1 1 0 | ? | / |
|
|
// | 0 1 0 1 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 0 1 1 0 0 0 | ? |\ |
|
|
// | 0 1 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 1 0 1 0 | ? | / |
|
|
// | 0 1 1 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 0 1 1 1 0 0 | ? |\ |
|
|
// | 0 1 1 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 1 1 1 0 | ? | / |
|
|
// | 0 1 1 1 1 1 | ? |/ |
|
|
// ------------------------ INIT = 64'h????????????????
|
|
// | 1 0 0 0 0 0 | ? |\ |
|
|
// | 1 0 0 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 0 0 1 0 | ? | / |
|
|
// | 1 0 0 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 0 0 1 0 0 | ? |\ |
|
|
// | 1 0 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 0 1 1 0 | ? | / |
|
|
// | 1 0 0 1 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 0 1 0 0 0 | ? |\ |
|
|
// | 1 0 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 1 0 1 0 | ? | / |
|
|
// | 1 0 1 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 0 1 1 0 0 | ? |\ |
|
|
// | 1 0 1 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 1 1 1 0 | ? | / |
|
|
// | 1 0 1 1 1 1 | ? |/ |
|
|
// ------------------------- |
|
|
// | 1 1 0 0 0 0 | ? |\ |
|
|
// | 1 1 0 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 1 0 0 1 0 | ? | / |
|
|
// | 1 1 0 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 1 0 1 0 0 | ? |\ |
|
|
// | 1 1 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 1 0 1 1 0 | ? | / |
|
|
// | 1 1 0 1 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 1 1 0 0 0 | ? |\ |
|
|
// | 1 1 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 1 1 0 1 0 | ? | / |
|
|
// | 1 1 1 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 1 1 1 0 0 | ? |\ |
|
|
// | 1 1 1 1 0 1 | ? | \ = 4'b???? = 4'h? ----+
|
|
// | 1 1 1 1 1 0 | ? | /
|
|
// | 1 1 1 1 1 1 | ? |/
|
|
// ------------------------
|
|
</Template>
|
|
<Template label="LUT6_2" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT6_2
|
|
// _____________________________
|
|
// | I5 I4 I3 I2 I1 I0 | O6 | O5 |
|
|
// |-----------------------------|
|
|
// | 0 0 0 0 0 0 | ? |\
|
|
// | 0 0 0 0 0 1 | ? | \ = 4'b???? = 4'h? -------------+
|
|
// | 0 0 0 0 1 0 | ? | / |
|
|
// | 0 0 0 0 1 1 | ? |/ |
|
|
// |-------------------|---------| |
|
|
// | 0 0 0 1 0 0 | ? |\ |
|
|
// | 0 0 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 0 0 1 1 0 | ? | / |
|
|
// | 0 0 0 1 1 1 | ? |/ |
|
|
// |-------------------|---------| |
|
|
// | 0 0 1 0 0 0 | ? |\ |
|
|
// | 0 0 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 0 1 0 1 0 | ? | / |
|
|
// | 0 0 1 0 1 1 | ? |/ |
|
|
// |-------------------|---------| |
|
|
// | 0 0 1 1 0 0 | ? |\ |
|
|
// | 0 0 1 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 0 1 1 1 0 | ? | / |
|
|
// | 0 0 1 1 1 1 | ? |/ |
|
|
// ------------------------------- |
|
|
// | 0 1 0 0 0 0 | ? |\ |
|
|
// | 0 1 0 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 0 0 1 0 | ? | / |
|
|
// | 0 1 0 0 1 1 | ? |/ |
|
|
// |-------------------|---------| |
|
|
// | 0 1 0 1 0 0 | ? |\ |
|
|
// | 0 1 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 0 1 1 0 | ? | / |
|
|
// | 0 1 0 1 1 1 | ? |/ |
|
|
// |-------------------|---------| |
|
|
// | 0 1 1 0 0 0 | ? |\ |
|
|
// | 0 1 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 1 0 1 0 | ? | / |
|
|
// | 0 1 1 0 1 1 | ? |/ |
|
|
// |-------------------|---------| |
|
|
// | 0 1 1 1 0 0 | ? |\ |
|
|
// | 0 1 1 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 1 1 1 0 | ? | / |
|
|
// | 0 1 1 1 1 1 | ? |/ |
|
|
// ------------------------------ INIT = 64'h????????????????
|
|
// | 1 0 0 0 0 0 | ? |\ |
|
|
// | 1 0 0 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 0 0 1 0 | ? | / |
|
|
// | 1 0 0 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 0 0 1 0 0 | ? |\ |
|
|
// | 1 0 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 0 1 1 0 | ? | / |
|
|
// | 1 0 0 1 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 0 1 0 0 0 | ? |\ |
|
|
// | 1 0 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 1 0 1 0 | ? | / |
|
|
// | 1 0 1 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 0 1 1 0 0 | ? |\ |
|
|
// | 1 0 1 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 1 1 1 0 | ? | / |
|
|
// | 1 0 1 1 1 1 | ? |/ |
|
|
// ------------------------- |
|
|
// | 1 1 0 0 0 0 | ? |\ |
|
|
// | 1 1 0 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 1 0 0 1 0 | ? | / |
|
|
// | 1 1 0 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 1 0 1 0 0 | ? |\ |
|
|
// | 1 1 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 1 0 1 1 0 | ? | / |
|
|
// | 1 1 0 1 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 1 1 0 0 0 | ? |\ |
|
|
// | 1 1 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 1 1 0 1 0 | ? | / |
|
|
// | 1 1 1 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 1 1 1 0 0 | ? |\ |
|
|
// | 1 1 1 1 0 1 | ? | \ = 4'b???? = 4'h? ----+
|
|
// | 1 1 1 1 1 0 | ? | /
|
|
// | 1 1 1 1 1 1 | ? |/
|
|
// ------------------------
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<Template label="LUT4" treetype="template">
|
|
// LUT4 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT4_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT4: 4-input Look-Up Table with general output (Mapped to a LUT6)
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT4 #(
|
|
.INIT(16'h0000) // Specify LUT Contents
|
|
) LUT4_inst (
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3) // LUT input
|
|
);
|
|
|
|
// End of LUT4_inst instantiation
|
|
</Template>
|
|
<Template label="LUT4_L" treetype="template">
|
|
// LUT4_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT4_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT4_L: 4-input Look-Up Table with local output (Mapped to a LUT6)
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT4_L #(
|
|
.INIT(16'h0000) // Specify LUT Contents
|
|
) LUT4_L_inst (
|
|
.LO(LO), // LUT local output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3) // LUT input
|
|
);
|
|
|
|
// End of LUT4_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT4_D" treetype="template">
|
|
// LUT4_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT4_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT4_D: 4-input Look-Up Table with general and local outputs (Mapped to a LUT6)
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT4_D #(
|
|
.INIT(16'h0000) // Specify LUT Contents
|
|
) LUT4_D_inst (
|
|
.LO(LO), // LUT local output
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3) // LUT input
|
|
);
|
|
|
|
// End of LUT4_D_inst instantiation
|
|
</Template>
|
|
<Template label="LUT3" treetype="template">
|
|
// LUT3 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT3_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT3: 3-input Look-Up Table with general output (Mapped to a LUT6)
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT3 #(
|
|
.INIT(8'h00) // Specify LUT Contents
|
|
) LUT3_inst (
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2) // LUT input
|
|
);
|
|
|
|
// End of LUT3_inst instantiation
|
|
</Template>
|
|
<Template label="LUT3_L" treetype="template">
|
|
// LUT3_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT3_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT3_L: 3-input Look-Up Table with local output (Mapped to a LUT6)
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT3_L #(
|
|
.INIT(8'h00) // Specify LUT Contents
|
|
) LUT3_L_inst (
|
|
.LO(LO), // LUT local output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2) // LUT input
|
|
);
|
|
|
|
// End of LUT3_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT3_D" treetype="template">
|
|
// LUT3_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT3_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT3_D: 3-input Look-Up Table with general and local outputs (Mapped to a LUT6)
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT3_D #(
|
|
.INIT(8'h00) // Specify LUT Contents
|
|
) LUT3_D_inst (
|
|
.LO(LO), // LUT local output
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2) // LUT input
|
|
);
|
|
|
|
// End of LUT3_D_inst instantiation
|
|
</Template>
|
|
<Template label="LUT2" treetype="template">
|
|
// LUT2 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT2: 2-input Look-Up Table with general output (Mapped to a LUT6)
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT2 #(
|
|
.INIT(4'h0) // Specify LUT Contents
|
|
) LUT2_inst (
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1) // LUT input
|
|
);
|
|
|
|
// End of LUT2_inst instantiation
|
|
</Template>
|
|
<Template label="LUT2_L" treetype="template">
|
|
// LUT2_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT2_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT2_L: 2-input Look-Up Table with local output (Mapped to a LUT6)
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT2_L #(
|
|
.INIT(4'h0) // Specify LUT Contents
|
|
) LUT2_L_inst (
|
|
.LO(LO), // LUT local output
|
|
.I0(I0), // LUT input
|
|
.I1(I1) // LUT input
|
|
);
|
|
|
|
// End of LUT2_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT2_D" treetype="template">
|
|
// LUT2_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT2_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT2_D: 2-input Look-Up Table with general and local outputs (Mapped to a LUT6)
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT2_D #(
|
|
.INIT(4'h0) // Specify LUT Contents
|
|
) LUT2_D_inst (
|
|
.LO(LO), // LUT local output
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1) // LUT input
|
|
);
|
|
|
|
// End of LUT2_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT1" treetype="template">
|
|
// LUT1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT1: 1-input Look-Up Table with general output (Mapped to a LUT6)
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT1 #(
|
|
.INIT(2'b00) // Specify LUT Contents
|
|
) LUT1_inst (
|
|
.O(O), // LUT general output
|
|
.I0(I0) // LUT input
|
|
);
|
|
|
|
// End of LUT1_inst instantiation
|
|
</Template>
|
|
<Template label="LUT1_L" treetype="template">
|
|
// LUT1_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT1_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT1_L: 1-input Look-Up Table with local output (Mapped to a LUT6)
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT1_L #(
|
|
.INIT(2'b00) // Specify LUT Contents
|
|
) LUT1_L_inst (
|
|
.LO(LO), // LUT local output
|
|
.I0(I0) // LUT input
|
|
);
|
|
|
|
// End of LUT1_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT1_D" treetype="template">
|
|
// LUT1_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT1_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT1_D: 1-input Look-Up Table with general and local outputs (Mapped to a LUT6)
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT1_D #(
|
|
.INIT(2'b00) // Specify LUT Contents
|
|
) LUT1_D_inst (
|
|
.LO(LO), // LUT local output
|
|
.O(O), // LUT general output
|
|
.I0(I0) // LUT input
|
|
);
|
|
|
|
// End of LUT1_D_inst instantiation
|
|
</Template>
|
|
<Template label="Reconfigurable LUT (CFGLUT5)" treetype="template">
|
|
// CFGLUT5 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (CFGLUT5_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// CFGLUT5: Reconfigurable 5-input LUT (Mapped to a SliceM LUT6)
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
CFGLUT5 #(
|
|
.INIT(32'h00000000) // Specify initial LUT contents
|
|
) CFGLUT5_inst (
|
|
.CDO(CDO), // Reconfiguration cascade output
|
|
.O5(O5), // 4-LUT output
|
|
.O6(O6), // 5-LUT output
|
|
.CDI(CDI), // Reconfiguration data input
|
|
.CE(CE), // Reconfiguration enable input
|
|
.CLK(CLK), // Clock input
|
|
.I0(I0), // Logic data input
|
|
.I1(I1), // Logic data input
|
|
.I2(I2), // Logic data input
|
|
.I3(I3), // Logic data input
|
|
.I4(I4) // Logic data input
|
|
);
|
|
|
|
// End of CFGLUT5_inst instantiation
|
|
</Template>
|
|
<Template label="LUT5" treetype="template">
|
|
// LUT5 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT5_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT5: 5-input Look-Up Table with general output (Mapped to a LUT6)
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT5 #(
|
|
.INIT(32'h00000000) // Specify LUT Contents
|
|
) LUT5_inst (
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3), // LUT input
|
|
.I4(I4) // LUT input
|
|
);
|
|
|
|
// End of LUT5_inst instantiation
|
|
</Template>
|
|
<Template label="LUT5_L" treetype="template">
|
|
// LUT5_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT5_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT5_L: 5-input Look-Up Table with local output (Mapped to a LUT6)
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT5_L #(
|
|
.INIT(32'h0000000) // Specify LUT Contents
|
|
) LUT5_L_inst (
|
|
.LO(LO), // LUT local output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3), // LUT input
|
|
.I4(I4) // LUT input
|
|
);
|
|
|
|
// End of LUT5_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT5_D" treetype="template">
|
|
// LUT5_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT5_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT5_D: 5-input Look-Up Table with general and local outputs (Mapped to a LUT6)
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT5_D #(
|
|
.INIT(32'h0000000) // Specify LUT Contents
|
|
) LUT5_D_inst (
|
|
.LO(LO), // LUT local output
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3), // LUT input
|
|
.I4(I4) // LUT input
|
|
);
|
|
|
|
// End of LUT5_D_inst instantiation
|
|
</Template>
|
|
<Template label="LUT6" treetype="template">
|
|
// LUT6 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT6_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT6: 6-input Look-Up Table with general output
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT6 #(
|
|
.INIT(64'h0000000000000000) // Specify LUT Contents
|
|
) LUT6_inst (
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3), // LUT input
|
|
.I4(I4), // LUT input
|
|
.I5(I5) // LUT input
|
|
);
|
|
|
|
// End of LUT6_inst instantiation
|
|
</Template>
|
|
<Template label="LUT6_L" treetype="template">
|
|
// LUT6_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT6_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT6_L: 6-input Look-Up Table with local output
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT6_L #(
|
|
.INIT(64'h0000000000000000) // Specify LUT Contents
|
|
) LUT6_L_inst (
|
|
.LO(LO), // LUT local output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3), // LUT input
|
|
.I4(I4), // LUT input
|
|
.I5(I5) // LUT input
|
|
);
|
|
|
|
// End of LUT6_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT6_D" treetype="template">
|
|
// LUT6_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT6_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT6_D: 6-input Look-Up Table with general and local outputs
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT6_D #(
|
|
.INIT(64'h0000000000000000) // Specify LUT Contents
|
|
) LUT6_D_inst (
|
|
.LO(LO), // LUT local output
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3), // LUT input
|
|
.I4(I4), // LUT input
|
|
.I5(I5) // LUT input
|
|
);
|
|
|
|
// End of LUT6_D_inst instantiation
|
|
</Template>
|
|
<Template label="LUT6_2" treetype="template">
|
|
// LUT6_2 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT6_2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT6_2: 6-input, 2 output Look-Up Table
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT6_2 #(
|
|
.INIT(64'h0000000000000000) // Specify LUT Contents
|
|
) LUT6_2_inst (
|
|
.O6(O6), // 1-bit LUT6 output
|
|
.O5(O5), // 1-bit lower LUT5 output
|
|
.I0(I0), // 1-bit LUT input
|
|
.I1(I1), // 1-bit LUT input
|
|
.I2(I2), // 1-bit LUT input
|
|
.I3(I3), // 1-bit LUT input
|
|
.I4(I4), // 1-bit LUT input
|
|
.I5(I5) // 1-bit LUT input (fast MUX select only available to O6 output)
|
|
);
|
|
|
|
// End of LUT6_2_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Shift Register LUT" treetype="folder">
|
|
<Template label="16-bit w/ CE posedge SR (SRL16E)" treetype="template">
|
|
// SRL16E : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SRL16E_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SRL16E: 16-bit shift register LUT with clock enable operating on posedge of clock (Mapped to a SliceM LUT6)
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SRL16E #(
|
|
.INIT(16'h0000) // Initial Value of Shift Register
|
|
) SRL16E_inst (
|
|
.Q(Q), // SRL data output
|
|
.A0(A0), // Select[0] input
|
|
.A1(A1), // Select[1] input
|
|
.A2(A2), // Select[2] input
|
|
.A3(A3), // Select[3] input
|
|
.CE(CE), // Clock enable input
|
|
.CLK(CLK), // Clock input
|
|
.D(D) // SRL data input
|
|
);
|
|
|
|
// End of SRL16E_inst instantiation
|
|
</Template>
|
|
<Template label="32-bit w/ CE posedge SR (SRLC32E)" treetype="template">
|
|
// SRLC32E : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SRL32E_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SRLC32E: 32-bit variable length cascadable shift register LUT (Mapped to a SliceM LUT6)
|
|
// with clock enable
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SRLC32E #(
|
|
.INIT(32'h00000000) // Initial Value of Shift Register
|
|
) SRLC32E_inst (
|
|
.Q(Q), // SRL data output
|
|
.Q31(Q31), // SRL cascade output pin
|
|
.A(A), // 5-bit shift depth select input
|
|
.CE(CE), // Clock enable input
|
|
.CLK(CLK), // Clock input
|
|
.D(D) // SRL data input
|
|
);
|
|
|
|
// End of SRLC32E_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<Template label="Carry (CARRY4)" treetype="template">
|
|
// CARRY4 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (CARRY4_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs and
|
|
// : and outputs of this primitive should be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// CARRY4: Fast Carry Logic Component
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
CARRY4 CARRY4_inst (
|
|
.CO(CO), // 4-bit carry out
|
|
.O(O), // 4-bit carry chain XOR data out
|
|
.CI(CI), // 1-bit carry cascade input
|
|
.CYINIT(CYINIT), // 1-bit carry initialization
|
|
.DI(DI), // 4-bit carry-MUX data in
|
|
.S(S) // 4-bit carry-MUX select input
|
|
);
|
|
|
|
// End of CARRY4_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Registers & Latches" treetype="folder">
|
|
<SubFolder label="Single Data Rate" treetype="folder">
|
|
<Template label="Posedge D-FF w/ Async Clear and CE (FDCE)" treetype="template">
|
|
// FDCE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FDCE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FDCE: Single Data Rate D Flip-Flop with Asynchronous Clear and
|
|
// Clock Enable (posedge clk).
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FDCE #(
|
|
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
|
|
) FDCE_inst (
|
|
.Q(Q), // 1-bit Data output
|
|
.C(C), // 1-bit Clock input
|
|
.CE(CE), // 1-bit Clock enable input
|
|
.CLR(CLR), // 1-bit Asynchronous clear input
|
|
.D(D) // 1-bit Data input
|
|
);
|
|
|
|
// End of FDCE_inst instantiation
|
|
</Template>
|
|
<Template label="Posedge D-FF w/ Async Preset and CE (FDPE)" treetype="template">
|
|
// FDPE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FDPE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FDPE: Single Data Rate D Flip-Flop with Asynchronous Preset and
|
|
// Clock Enable (posedge clk).
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FDPE #(
|
|
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
|
|
) FDPE_inst (
|
|
.Q(Q), // 1-bit Data output
|
|
.C(C), // 1-bit Clock input
|
|
.CE(CE), // 1-bit Clock enable input
|
|
.PRE(PRE), // 1-bit Asynchronous preset input
|
|
.D(D) // 1-bit Data input
|
|
);
|
|
|
|
// End of FDPE_inst instantiation
|
|
</Template>
|
|
<Template label="Posedge D-FF w/ Sync Reset and CE (FDRE)" treetype="template">
|
|
// FDRE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FDRE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FDRE: Single Data Rate D Flip-Flop with Synchronous Reset and
|
|
// Clock Enable (posedge clk).
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FDRE #(
|
|
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
|
|
) FDRE_inst (
|
|
.Q(Q), // 1-bit Data output
|
|
.C(C), // 1-bit Clock input
|
|
.CE(CE), // 1-bit Clock enable input
|
|
.R(R), // 1-bit Synchronous reset input
|
|
.D(D) // 1-bit Data input
|
|
);
|
|
|
|
// End of FDRE_inst instantiation
|
|
</Template>
|
|
<Template label="Posedge D-FF w/ Sync Set and CE (FDSE)" treetype="template">
|
|
// FDSE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FDSE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FDSE: Single Data Rate D Flip-Flop with Synchronous Set and
|
|
// Clock Enable (posedge clk).
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FDSE #(
|
|
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
|
|
) FDSE_inst (
|
|
.Q(Q), // 1-bit Data output
|
|
.C(C), // 1-bit Clock input
|
|
.CE(CE), // 1-bit Clock enable input
|
|
.S(S), // 1-bit Synchronous set input
|
|
.D(D) // 1-bit Data input
|
|
);
|
|
|
|
// End of FDSE_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Transparent Latch" treetype="folder">
|
|
<Template label="Latch with Async Reset and Gate Enable (LDCE)" treetype="template">
|
|
// LDCE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LDCE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LDCE: Transparent latch with Asynchronous Reset and Gate Enable.
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LDCE #(
|
|
.INIT(1'b0) // Initial value of latch (1'b0 or 1'b1)
|
|
) LDCE_inst (
|
|
.Q(Q), // Data output
|
|
.CLR(CLR), // Asynchronous clear/reset input
|
|
.D(D), // Data input
|
|
.G(G), // Gate input
|
|
.GE(GE) // Gate enable input
|
|
);
|
|
|
|
// End of LDCE_inst instantiation
|
|
</Template>
|
|
<Template label="Latch with Async Set and Gate Enable (LDPE)" treetype="template">
|
|
// LDPE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LDPE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LDPE: Transparent latch with Asynchronous Preset and Gate Enable.
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LDPE #(
|
|
.INIT(1'b1) // Initial value of latch (1'b0 or 1'b1)
|
|
) LDPE_inst (
|
|
.Q(Q), // Data output
|
|
.PRE(PRE), // Asynchronous preset/set input
|
|
.D(D), // Data input
|
|
.G(G), // Gate input
|
|
.GE(GE) // Gate enable input
|
|
);
|
|
|
|
// End of LDPE_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Double Data Rate" treetype="folder">
|
|
<Template label="Dual-Clock, Input DDR Register (IDDR_2CLK)" treetype="template">
|
|
// IDDR_2CLK : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IDDR_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IDDR_2CLK: Dual-Clock, Input Double Data Rate Input Register with
|
|
// Set, Reset and Clock Enable.
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IDDR_2CLK #(
|
|
.DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE", "SAME_EDGE"
|
|
// or "SAME_EDGE_PIPELINED"
|
|
.INIT_Q1(1'b0), // Initial value of Q1: 1'b0 or 1'b1
|
|
.INIT_Q2(1'b0), // Initial value of Q2: 1'b0 or 1'b1
|
|
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
|
|
) IDDR_2CLK_inst (
|
|
.Q1(Q1), // 1-bit output for positive edge of clock
|
|
.Q2(Q2), // 1-bit output for negative edge of clock
|
|
.C(C), // 1-bit primary clock input
|
|
.CB(CB), // 1-bit secondary clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.D(D), // 1-bit DDR data input
|
|
.R(R), // 1-bit reset
|
|
.S(S) // 1-bit set
|
|
);
|
|
|
|
// End of IDDR_2CLK_inst instantiation
|
|
</Template>
|
|
<Template label="Input DDR Register (IDDR)" treetype="template">
|
|
// IDDR : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IDDR_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IDDR: Input Double Data Rate Input Register with Set, Reset
|
|
// and Clock Enable.
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IDDR #(
|
|
.DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE", "SAME_EDGE"
|
|
// or "SAME_EDGE_PIPELINED"
|
|
.INIT_Q1(1'b0), // Initial value of Q1: 1'b0 or 1'b1
|
|
.INIT_Q2(1'b0), // Initial value of Q2: 1'b0 or 1'b1
|
|
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
|
|
) IDDR_inst (
|
|
.Q1(Q1), // 1-bit output for positive edge of clock
|
|
.Q2(Q2), // 1-bit output for negative edge of clock
|
|
.C(C), // 1-bit clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.D(D), // 1-bit DDR data input
|
|
.R(R), // 1-bit reset
|
|
.S(S) // 1-bit set
|
|
);
|
|
|
|
// End of IDDR_inst instantiation
|
|
</Template>
|
|
<Template label="Output DDR Register (ODDR)" treetype="template">
|
|
// ODDR : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ODDR_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ODDR: Output Double Data Rate Output Register with Set, Reset
|
|
// and Clock Enable.
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ODDR #(
|
|
.DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE"
|
|
.INIT(1'b0), // Initial value of Q: 1'b0 or 1'b1
|
|
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
|
|
) ODDR_inst (
|
|
.Q(Q), // 1-bit DDR output
|
|
.C(C), // 1-bit clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.D1(D1), // 1-bit data input (positive edge)
|
|
.D2(D2), // 1-bit data input (negative edge)
|
|
.R(R), // 1-bit reset
|
|
.S(S) // 1-bit set
|
|
);
|
|
|
|
// End of ODDR_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Spartan-3A DSP" treetype="folder">
|
|
<SubFolder label="Slice/CLB Primitives" treetype="folder">
|
|
<SubFolder label="Carry-Chain" treetype="folder">
|
|
<Template label="MUXCY" treetype="template">
|
|
// MUXCY : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXCY_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs and
|
|
// : and outputs of this primitive should be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXCY: Carry-Chain MUX with general output
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXCY MUXCY_inst (
|
|
.O(O), // Carry output signal
|
|
.CI(CI), // Carry input signal
|
|
.DI(DI), // Data input signal
|
|
.S(S) // MUX select, tie to '1' or LUT4 out
|
|
);
|
|
|
|
// End of MUXCY_inst instantiation
|
|
</Template>
|
|
<Template label="MUXCY_L" treetype="template">
|
|
// MUXCY_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXCY_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXCY_L: Carry-Chain MUX with local output
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXCY_L MUXCY_L_inst (
|
|
.LO(LO), // Carry local output signal
|
|
.CI(CI), // Carry input signal
|
|
.DI(DI), // Data input signal
|
|
.S(S) // MUX select, tie to '1' or LUT4 out
|
|
);
|
|
|
|
// End of MUXCY_L_inst instantiation
|
|
</Template>
|
|
<Template label="MUXCY_D" treetype="template">
|
|
// MUXCY_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXCY_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXCY_D: Carry-Chain MUX with general and local outputs
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXCY_D MUXCY_D_inst (
|
|
.LO(LO), // Carry local output signal
|
|
.O(O), // Carry general output signal
|
|
.CI(CI), // Carry input signal
|
|
.DI(DI), // Data input signal
|
|
.S(S) // MUX select, tie to '1' or LUT4 out
|
|
);
|
|
|
|
// End of MUXCY_D_inst instantiation
|
|
</Template>
|
|
<Template label="XORCY" treetype="template">
|
|
// XORCY : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (XORCY_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// XORCY: Carry-Chain XOR-gate with general output
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
XORCY XORCY_inst (
|
|
.O(O), // XOR output signal
|
|
.CI(CI), // Carry input signal
|
|
.LI(LI) // LUT4 input signal
|
|
);
|
|
|
|
// End of XORCY_inst instantiation
|
|
</Template>
|
|
<Template label="XORCY_L" treetype="template">
|
|
// XORCY_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (XORCY_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// XORCY_L: Carry-Chain XOR-gate with local (direct-connect) output
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
XORCY_L XORCY_L_inst (
|
|
.LO(LO), // XOR local output signal
|
|
.CI(CI), // Carry input signal
|
|
.LI(LI) // LUT4 input signal
|
|
);
|
|
|
|
// End of XORCY_L_inst instantiation
|
|
</Template>
|
|
<Template label="XORCY_D" treetype="template">
|
|
// XORCY_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (XORCY_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// XORCY_D: Carry-Chain XOR-gate with local and general outputs
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
XORCY_D XORCY_D_inst (
|
|
.LO(LO), // XOR local output signal
|
|
.O(O), // XOR general output signal
|
|
.CI(CI), // Carry input signal
|
|
.LI(LI) // LUT4 input signal
|
|
);
|
|
|
|
// End of XORCY_D_inst instantiation
|
|
</Template>
|
|
<Template label="MULT_AND" treetype="template">
|
|
// MULT_AND : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MULT_AND_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MULT_AND: 2-input AND gate connected to Carry chain
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MULT_AND MULT_AND_inst (
|
|
.LO(LO), // MULT_AND output (connect to MUXCY DI)
|
|
.I0(I0), // MULT_AND data[0] input
|
|
.I1(I1) // MULT_AND data[1] input
|
|
);
|
|
|
|
// End of MULT_AND_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="MUXFx" treetype="folder">
|
|
<Template label="MUXF5" treetype="template">
|
|
// MUXF5 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF5_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF5: Slice MUX to tie two LUT4's together with general output
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF5 MUXF5_inst (
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie directly to the output of LUT4)
|
|
.I1(I1), // Input (tie directoy to the output of LUT4)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF5_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF5_L" treetype="template">
|
|
// MUXF5_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF5_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF5_L: Slice MUX to tie two LUT4's together with local output
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF5_L MUXF5_L_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.I0(I0), // Input (tie directly to the output of LUT4)
|
|
.I1(I1), // Input (tie directoy to the output of LUT4)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF5_L_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF5_D" treetype="template">
|
|
// MUXF5_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF5_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF5_D: Slice MUX to tie two LUT4's together with general and local outputs
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF5_D MUXF5_D_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie directly to the output of LUT4)
|
|
.I1(I1), // Input (tie directoy to the output of LUT4)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF5_D_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF6" treetype="template">
|
|
// MUXF6 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF6_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF6: CLB MUX to tie two MUXF5's together with general output
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF6 MUXF6_inst (
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie to MUXF5 LO out)
|
|
.I1(I1), // Input (tie to MUXF5 LO out)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF6_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF6_L" treetype="template">
|
|
// MUXF6_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF6_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF6_L: CLB MUX to tie two MUXF5's together with local output
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF6_L MUXF6_L_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.I0(I0), // Input (tie to MUXF5 LO out)
|
|
.I1(I1), // Input (tie to MUXF5 LO out)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF6_L_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF6_D" treetype="template">
|
|
// MUXF6_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF6_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF6_D: CLB MUX to tie two MUXF5's together with general and local outputs
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF6_D MUXF6_D_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie to MUXF5 LO out)
|
|
.I1(I1), // Input (tie to MUXF5 LO out)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF6_D_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF7" treetype="template">
|
|
// MUXF7 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF7_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF7: CLB MUX to tie two MUXF6's together with general output
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF7 MUXF7_inst (
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie to MUXF6 LO out or LUT6 O6 pin)
|
|
.I1(I1), // Input (tie to MUXF6 LO out or LUT6 O6 pin)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF7_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF7_L" treetype="template">
|
|
// MUXF7_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF7_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF7_L: CLB MUX to tie two MUXF6's together with local output
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF7_L MUXF7_L_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.I0(I0), // Input (tie to MUXF6 LO out or LUT6 O6 pin)
|
|
.I1(I1), // Input (tie to MUXF6 LO out or LUT6 O6 pin)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF7_L_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF7_D" treetype="template">
|
|
// MUXF7_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF7_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF7_D: CLB MUX to tie two MUXF6's together with general and local outputs
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF7_D MUXF7_D_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie to MUXF6 LO out or LUT6 O6 pin)
|
|
.I1(I1), // Input (tie to MUXF6 LO out or LUT6 O6 pin)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF7_D_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF8" treetype="template">
|
|
// MUXF8 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF8_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF8: CLB MUX to tie two MUXF7's together with general output
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF8 MUXF8_inst (
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie to MUXF7 LO out)
|
|
.I1(I1), // Input (tie to MUXF7 LO out)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF8_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF8_L" treetype="template">
|
|
// MUXF8_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF8_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF8_L: CLB MUX to tie two MUXF7's together with local output
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF8_L MUXF8_L_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.I0(I0), // Input (tie to MUXF7 LO out)
|
|
.I1(I1), // Input (tie to MUXF7 LO out)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF8_L_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF8_D" treetype="template">
|
|
// MUXF8_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF8_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF8_D: CLB MUX to tie two MUXF7's together with general and local outputs
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF8_D MUXF8_D_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie to MUXF7 LO out)
|
|
.I1(I1), // Input (tie to MUXF7 LO out)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF8_D_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="LUTs" treetype="folder">
|
|
<SubFolder label="Info" treetype="folder">
|
|
<Template label="Info (LUT INIT)" treetype="template">
|
|
// The INIT parameter for the FPGA LUT primitive is what gives the LUT its
|
|
// logical value. By default this value is zero thus driving the output to a
|
|
// zero regardless of the input values (acting as a ground) however in most
|
|
// cases an new INIT value must be determined in order to specify the logic
|
|
// function for the LUT primitive. There are a few methods in which the LUT
|
|
// value can be determined and two of those methods will be discussed here.
|
|
//
|
|
// The Truth Table Method
|
|
// ----------------------
|
|
//
|
|
// A common method to determine the desired INIT value for a LUT is using a
|
|
// truth table. To do so, simply create a binary truth table of all possible
|
|
// inputs, specify the desired logic value of the output and then create the
|
|
// INIT string from those output values. An example is shown below:
|
|
//
|
|
// Example of determining an XOR INIT equation for a LUT4:
|
|
//
|
|
// _________________
|
|
// | I3 I2 I1 I0 | O |
|
|
// |-----------------|
|
|
// | 0 0 0 0 | 0 |\
|
|
// | 0 0 0 1 | 1 | \ = 4'b0110 = 4'h6 ---------------+
|
|
// | 0 0 1 0 | 1 | / |
|
|
// | 0 0 1 1 | 0 |/ |
|
|
// |-------------|---| |
|
|
// | 0 1 0 0 | 1 |\ |
|
|
// | 0 1 0 1 | 0 | \ = 4'b1001 = 4'h9 |
|
|
// | 0 1 1 0 | 0 | / |
|
|
// | 0 1 1 1 | 1 |/ |
|
|
// |-------------|---| INIT = 16'h6996
|
|
// | 1 0 0 0 | 1 |\ |
|
|
// | 1 0 0 1 | 0 | \ = 4'b0110 = 4'h9 |
|
|
// | 1 0 1 0 | 0 | / |
|
|
// | 1 0 1 1 | 1 |/ |
|
|
// |-------------|---| |
|
|
// | 1 1 0 0 | 0 |\ |
|
|
// | 1 1 0 1 | 1 | \ = 4'b1001 = 4'h6 ------------+
|
|
// | 1 1 1 0 | 1 | /
|
|
// | 1 1 1 1 | 0 |/
|
|
// -------------------
|
|
//
|
|
// Example of determining a 3-input AND gate:
|
|
//
|
|
// ______________
|
|
// | I2 I1 I0 | O |
|
|
// |--------------|
|
|
// | 0 0 0 | 0 |\
|
|
// | 0 0 1 | 0 | \ = 4'b0000 = 4'h0 --------------+
|
|
// | 0 1 0 | 0 | / |
|
|
// | 0 1 1 | 0 |/ |
|
|
// |----------|---| INIT = 8'h80
|
|
// | 1 0 0 | 0 |\ |
|
|
// | 1 0 1 | 0 | \ = 4'b1000 = 4'h8 -------------+
|
|
// | 1 1 0 | 0 | /
|
|
// | 1 1 1 | 1 |/
|
|
// ----------------
|
|
//
|
|
// The Equation Method
|
|
// -------------------
|
|
//
|
|
// Another method to determine the LUT value is to define parameters for each
|
|
// input to the LUT that correspond to their listed truth value and use those to
|
|
// build the logic equation you are after. This method is easier to understand
|
|
// once you have grasped the concept and more self-documenting that the above
|
|
// method however does require the code to first specify the appropriate
|
|
// parameters. See the example below.
|
|
//
|
|
// Example of specifying the equation (A and B) or (C and D) for a LUT4:
|
|
//
|
|
// The forllowing parameters are defined to allow for
|
|
// equation-based INIT specification.
|
|
parameter I0 = 16'haaaa;
|
|
parameter I1 = 16'hcccc;
|
|
parameter I2 = 16'hf0f0;
|
|
parameter I3 = 16'hff00;
|
|
|
|
// LUT4: 4-input Look-Up Table with general output
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT4 #(
|
|
.INIT((I0&I1)|(I2&I3)) // Specify LUT Contents
|
|
) LUT4_inst (
|
|
.O(O_LUT), // LUT general output
|
|
.I0(A), // LUT input
|
|
.I1(B), // LUT input
|
|
.I2(C), // LUT input
|
|
.I3(D) // LUT input
|
|
);
|
|
|
|
// End of LUT4_inst instantiation
|
|
|
|
// With the parameters specifying all possible cases for the truth table, a
|
|
// Verilog equation can be written to determine the end INIT value.
|
|
</Template>
|
|
<SubFolder label="INIT Parameters" treetype="folder">
|
|
<Template label="LUT1" treetype="template">
|
|
// The forllowing parameter is defined to allow for
|
|
// equation-based INIT specification for a LUT1.
|
|
parameter I0 = 2'b10;
|
|
</Template>
|
|
<Template label="LUT2" treetype="template">
|
|
// The forllowing parameters are defined to allow for
|
|
// equation-based INIT specification for a LUT2.
|
|
parameter I0 = 4'ha;
|
|
parameter I1 = 4'hc;
|
|
</Template>
|
|
<Template label="LUT3" treetype="template">
|
|
// The forllowing parameters are defined to allow for
|
|
// equation-based INIT specification for a LUT3.
|
|
parameter I0 = 8'haa;
|
|
parameter I1 = 8'hcc;
|
|
parameter I2 = 8'hf0;
|
|
</Template>
|
|
<Template label="LUT4" treetype="template">
|
|
// The forllowing parameters are defined to allow for
|
|
// equation-based INIT specification for a LUT4.
|
|
parameter I0 = 16'haaaa;
|
|
parameter I1 = 16'hcccc;
|
|
parameter I2 = 16'hf0f0;
|
|
parameter I3 = 16'hff00;
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="INIT Truth Tables" treetype="folder">
|
|
<Template label="LUT1" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT1
|
|
// ________
|
|
// | I0 | O |
|
|
// |--------|
|
|
// | 0 | ? |\
|
|
// | 1 | ? |/ = 2'b??
|
|
// ----------
|
|
</Template>
|
|
<Template label="LUT2" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT2
|
|
// ______________
|
|
// | I2 I1 I0 | O |
|
|
// |--------------|
|
|
// | 0 0 0 | ? |\
|
|
// | 0 0 1 | ? | \ = INIT = 4'b???? = 4'h?
|
|
// | 0 1 0 | ? | /
|
|
// | 0 1 1 | ? |/
|
|
// ---------- ---
|
|
</Template>
|
|
<Template label="LUT3" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT3
|
|
// ______________
|
|
// | I2 I1 I0 | O |
|
|
// |--------------|
|
|
// | 0 0 0 | ? |\
|
|
// | 0 0 1 | ? | \ = 4'b???? = 4'h? --------------+
|
|
// | 0 1 0 | ? | / |
|
|
// | 0 1 1 | ? |/ |
|
|
// |----------|---| INIT = 8'h??
|
|
// | 1 0 0 | ? |\ |
|
|
// | 1 0 1 | ? | \ = 4'b???? = 4'h? -------------+
|
|
// | 1 1 0 | ? | /
|
|
// | 1 1 1 | ? |/
|
|
// ----------------
|
|
</Template>
|
|
<Template label="LUT4" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT4
|
|
// _________________
|
|
// | I3 I2 I1 I0 | O |
|
|
// |-----------------|
|
|
// | 0 0 0 0 | ? |\
|
|
// | 0 0 0 1 | ? | \ = 4'b???? = 4'h? ---------------+
|
|
// | 0 0 1 0 | ? | / |
|
|
// | 0 0 1 1 | ? |/ |
|
|
// |-------------|---| |
|
|
// | 0 1 0 0 | ? |\ |
|
|
// | 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 1 0 | ? | / |
|
|
// | 0 1 1 1 | ? |/ |
|
|
// |-------------|---| INIT = 16'h????
|
|
// | 1 0 0 0 | ? |\ |
|
|
// | 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 1 0 | ? | / |
|
|
// | 1 0 1 1 | ? |/ |
|
|
// |-------------|---| |
|
|
// | 1 1 0 0 | ? |\ |
|
|
// | 1 1 0 1 | ? | \ = 4'b???? = 4'h? ------------+
|
|
// | 1 1 1 0 | ? | /
|
|
// | 1 1 1 1 | ? |/
|
|
// -------------------
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<Template label="LUT4" treetype="template">
|
|
// LUT4 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT4_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT4: 4-input Look-Up Table with general output
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT4 #(
|
|
.INIT(16'h0000) // Specify LUT Contents
|
|
) LUT4_inst (
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3) // LUT input
|
|
);
|
|
|
|
// End of LUT4_inst instantiation
|
|
</Template>
|
|
<Template label="LUT4_L" treetype="template">
|
|
// LUT4_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT4_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT4_L: 4-input Look-Up Table with local output
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT4_L #(
|
|
.INIT(16'h0000) // Specify LUT Contents
|
|
) LUT4_L_inst (
|
|
.LO(LO), // LUT local output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3) // LUT input
|
|
);
|
|
|
|
// End of LUT4_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT4_D" treetype="template">
|
|
// LUT4_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT4_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT4_D: 4-input Look-Up Table with general and local outputs
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT4_D #(
|
|
.INIT(16'h0000) // Specify LUT Contents
|
|
) LUT4_D_inst (
|
|
.LO(LO), // LUT local output
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3) // LUT input
|
|
);
|
|
|
|
// End of LUT4_D_inst instantiation
|
|
</Template>
|
|
<Template label="LUT3" treetype="template">
|
|
// LUT3 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT3_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT3: 3-input Look-Up Table with general output
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT3 #(
|
|
.INIT(8'h00) // Specify LUT Contents
|
|
) LUT3_inst (
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2) // LUT input
|
|
);
|
|
|
|
// End of LUT3_inst instantiation
|
|
</Template>
|
|
<Template label="LUT3_L" treetype="template">
|
|
// LUT3_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT3_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT3_L: 3-input Look-Up Table with local output
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT3_L #(
|
|
.INIT(8'h00) // Specify LUT Contents
|
|
) LUT3_L_inst (
|
|
.LO(LO), // LUT local output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2) // LUT input
|
|
);
|
|
|
|
// End of LUT3_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT3_D" treetype="template">
|
|
// LUT3_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT3_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT3_D: 3-input Look-Up Table with general and local outputs
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT3_D #(
|
|
.INIT(8'h00) // Specify LUT Contents
|
|
) LUT3_D_inst (
|
|
.LO(LO), // LUT local output
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2) // LUT input
|
|
);
|
|
|
|
// End of LUT3_D_inst instantiation
|
|
</Template>
|
|
<Template label="LUT2" treetype="template">
|
|
// LUT2 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT2: 2-input Look-Up Table with general output
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT2 #(
|
|
.INIT(4'h0) // Specify LUT Contents
|
|
) LUT2_inst (
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1) // LUT input
|
|
);
|
|
|
|
// End of LUT2_inst instantiation
|
|
</Template>
|
|
<Template label="LUT2_L" treetype="template">
|
|
// LUT2_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT2_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT2_L: 2-input Look-Up Table with local output
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT2_L #(
|
|
.INIT(4'h0) // Specify LUT Contents
|
|
) LUT2_L_inst (
|
|
.LO(LO), // LUT local output
|
|
.I0(I0), // LUT input
|
|
.I1(I1) // LUT input
|
|
);
|
|
|
|
// End of LUT2_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT2_D" treetype="template">
|
|
// LUT2_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT2_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT2_D: 2-input Look-Up Table with general and local outputs
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT2_D #(
|
|
.INIT(4'h0) // Specify LUT Contents
|
|
) LUT2_D_inst (
|
|
.LO(LO), // LUT local output
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1) // LUT input
|
|
);
|
|
|
|
// End of LUT2_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT1" treetype="template">
|
|
// LUT1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT1: 1-input Look-Up Table with general output
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT1 #(
|
|
.INIT(2'b00) // Specify LUT Contents
|
|
) LUT1_inst (
|
|
.O(O), // LUT general output
|
|
.I0(I0) // LUT input
|
|
);
|
|
|
|
// End of LUT1_inst instantiation
|
|
</Template>
|
|
<Template label="LUT1_L" treetype="template">
|
|
// LUT1_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT1_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT1_L: 1-input Look-Up Table with local output
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT1_L #(
|
|
.INIT(2'b00) // Specify LUT Contents
|
|
) LUT1_L_inst (
|
|
.LO(LO), // LUT local output
|
|
.I0(I0) // LUT input
|
|
);
|
|
|
|
// End of LUT1_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT1_D" treetype="template">
|
|
// LUT1_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT1_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT1_D: 1-input Look-Up Table with general and local outputs
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT1_D #(
|
|
.INIT(2'b00) // Specify LUT Contents
|
|
) LUT1_D_inst (
|
|
.LO(LO), // LUT local output
|
|
.O(O), // LUT general output
|
|
.I0(I0) // LUT input
|
|
);
|
|
|
|
// End of LUT1_D_inst instantiation
|
|
</Template>
|
|
<Template label="LUT Local Connect Buffer (BUFCF)" treetype="template">
|
|
// BUFCF : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFCF_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFCF: Fast connect buffer used to connect the outputs of the LUTs
|
|
// and some dedicated logic directly to the input of another LUT.
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFCF BUFCF_inst (
|
|
.O(O), // Connect to the output of a LUT
|
|
.I(I) // Connect to the input of a LUT
|
|
);
|
|
|
|
// End of BUFCF_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Shift Register LUT" treetype="folder">
|
|
<SubFolder label="Non-cascadable" treetype="folder">
|
|
<Template label="16-bit posedge SR (SRL16)" treetype="template">
|
|
// SRL16 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SRL16_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SRL16: 16-bit shift register LUT operating on posedge of clock
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SRL16 #(
|
|
.INIT(16'h0000) // Initial Value of Shift Register
|
|
) SRL16_inst (
|
|
.Q(Q), // SRL data output
|
|
.A0(A0), // Select[0] input
|
|
.A1(A1), // Select[1] input
|
|
.A2(A2), // Select[2] input
|
|
.A3(A3), // Select[3] input
|
|
.CLK(CLK), // Clock input
|
|
.D(D) // SRL data input
|
|
);
|
|
|
|
// End of SRL16_inst instantiation
|
|
</Template>
|
|
<Template label="16-bit negedge SR (SRL16_1)" treetype="template">
|
|
// SRL16_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SRL16_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SRL16_1: 16-bit shift register LUT operating on negedge of clock
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SRL16_1 #(
|
|
.INIT(16'h0000) // Initial Value of Shift Register
|
|
) SRL16_1_inst (
|
|
.Q(Q), // SRL data output
|
|
.A0(A0), // Select[0] input
|
|
.A1(A1), // Select[1] input
|
|
.A2(A2), // Select[2] input
|
|
.A3(A3), // Select[3] input
|
|
.CLK(CLK), // Clock input
|
|
.D(D) // SRL data input
|
|
);
|
|
|
|
// End of SRL16_1_inst instantiation
|
|
</Template>
|
|
<Template label="16-bit w/ CE posedge SR (SRL16E)" treetype="template">
|
|
// SRL16E : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SRL16E_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SRL16E: 16-bit shift register LUT with clock enable operating on posedge of clock
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SRL16E #(
|
|
.INIT(16'h0000) // Initial Value of Shift Register
|
|
) SRL16E_inst (
|
|
.Q(Q), // SRL data output
|
|
.A0(A0), // Select[0] input
|
|
.A1(A1), // Select[1] input
|
|
.A2(A2), // Select[2] input
|
|
.A3(A3), // Select[3] input
|
|
.CE(CE), // Clock enable input
|
|
.CLK(CLK), // Clock input
|
|
.D(D) // SRL data input
|
|
);
|
|
|
|
// End of SRL16E_inst instantiation
|
|
</Template>
|
|
<Template label="16-bit w/ CE negedge SR (SRL16E_1)" treetype="template">
|
|
// SRL16E_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SRL16E_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SRL16E_1: 16-bit shift register LUT with clock enable operating on negedge of clock
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SRL16E_1 #(
|
|
.INIT(16'h0000) // Initial Value of Shift Register
|
|
) SRL16E_1_inst (
|
|
.Q(Q), // SRL data output
|
|
.A0(A0), // Select[0] input
|
|
.A1(A1), // Select[1] input
|
|
.A2(A2), // Select[2] input
|
|
.A3(A3), // Select[3] input
|
|
.CE(CE), // Clock enable input
|
|
.CLK(CLK), // Clock input
|
|
.D(D) // SRL data input
|
|
);
|
|
|
|
// End of SRL16E_1_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Cascable" treetype="folder">
|
|
<Template label="16-bit posedge SR (SRLC16)" treetype="template">
|
|
// SRLC16 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SRLC16_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SRLC16: 16-bit cascadable shift register LUT operating on posedge of clock
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SRLC16 #(
|
|
.INIT(16'h0000) // Initial Value of Shift Register
|
|
) SRLC16_inst (
|
|
.Q(Q), // SRL data output
|
|
.Q15(Q15), // Carry output (connect to next SRL)
|
|
.A0(A0), // Select[0] input
|
|
.A1(A1), // Select[1] input
|
|
.A2(A2), // Select[2] input
|
|
.A3(A3), // Select[3] input
|
|
.CLK(CLK), // Clock input
|
|
.D(D) // SRL data input
|
|
);
|
|
|
|
// End of SRLC16_inst instantiation
|
|
</Template>
|
|
<Template label="16-bit negedge SR (SRLC16_1)" treetype="template">
|
|
// SRLC16_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SRLC16_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SRLC16_1: 16-bit cascadable shift register LUT operating on negedge of clock
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SRLC16_1 #(
|
|
.INIT(16'h0000) // Initial Value of Shift Register
|
|
) SRLC16_1_inst (
|
|
.Q(Q), // SRL data output
|
|
.Q15(Q15), // Carry output (connect to next SRL)
|
|
.A0(A0), // Select[0] input
|
|
.A1(A1), // Select[1] input
|
|
.A2(A2), // Select[2] input
|
|
.A3(A3), // Select[3] input
|
|
.CLK(CLK), // Clock input
|
|
.D(D) // SRL data input
|
|
);
|
|
|
|
// End of SRLC16_1_inst instantiation
|
|
</Template>
|
|
<Template label="16-bit w/ CE posedge SR (SRLC16E)" treetype="template">
|
|
// SRLC16E : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SRL16E_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SRLC16E: 16-bit cascadable shift register LUT with clock enable operating on posedge of clock
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SRLC16E #(
|
|
.INIT(16'h0000) // Initial Value of Shift Register
|
|
) SRLC16E_inst (
|
|
.Q(Q), // SRL data output
|
|
.Q15(Q15), // Carry output (connect to next SRL)
|
|
.A0(A0), // Select[0] input
|
|
.A1(A1), // Select[1] input
|
|
.A2(A2), // Select[2] input
|
|
.A3(A3), // Select[3] input
|
|
.CE(CE), // Clock enable input
|
|
.CLK(CLK), // Clock input
|
|
.D(D) // SRL data input
|
|
);
|
|
|
|
// End of SRLC16E_inst instantiation
|
|
</Template>
|
|
<Template label="16-bit w/ CE negedge SR (SRLC16E_1)" treetype="template">
|
|
// SRLC16E_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SRLC16E_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SRLC16E_1: 16-bit shift register LUT with clock enable operating on negedge of clock
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SRLC16E_1 #(
|
|
.INIT(16'h0000) // Initial Value of Shift Register
|
|
) SRLC16E_1_inst (
|
|
.Q(Q), // SRL data output
|
|
.Q15(Q15), // Carry output (connect to next SRL)
|
|
.A0(A0), // Select[0] input
|
|
.A1(A1), // Select[1] input
|
|
.A2(A2), // Select[2] input
|
|
.A3(A3), // Select[3] input
|
|
.CE(CE), // Clock enable input
|
|
.CLK(CLK), // Clock input
|
|
.D(D) // SRL data input
|
|
);
|
|
|
|
// End of SRLC16E_1_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Clock Components" treetype="folder">
|
|
<Template label="Digital Clock Manager (DCM_SP)" treetype="template">
|
|
// DCM_SP : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (DCM_SP_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Unused inputs
|
|
// : and outputs may be removed or commented out.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// DCM_SP: Digital Clock Manager Circuit
|
|
// Spartan-3A DSP/3A, Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
DCM_SP #(
|
|
.CLKDV_DIVIDE(2.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
|
|
// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
|
|
.CLKFX_DIVIDE(1), // Can be any integer from 1 to 32
|
|
.CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32
|
|
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
|
|
.CLKIN_PERIOD(0.0), // Specify period of input clock
|
|
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
|
|
.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X
|
|
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
|
|
// an integer from 0 to 15
|
|
.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
|
|
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
|
|
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
|
|
.STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
|
|
) DCM_SP_inst (
|
|
.CLK0(CLK0), // 0 degree DCM CLK output
|
|
.CLK180(CLK180), // 180 degree DCM CLK output
|
|
.CLK270(CLK270), // 270 degree DCM CLK output
|
|
.CLK2X(CLK2X), // 2X DCM CLK output
|
|
.CLK2X180(CLK2X180), // 2X, 180 degree DCM CLK out
|
|
.CLK90(CLK90), // 90 degree DCM CLK output
|
|
.CLKDV(CLKDV), // Divided DCM CLK out (CLKDV_DIVIDE)
|
|
.CLKFX(CLKFX), // DCM CLK synthesis out (M/D)
|
|
.CLKFX180(CLKFX180), // 180 degree CLK synthesis out
|
|
.LOCKED(LOCKED), // DCM LOCK status output
|
|
.PSDONE(PSDONE), // Dynamic phase adjust done output
|
|
.STATUS(STATUS), // 8-bit DCM status bits output
|
|
.CLKFB(CLKFB), // DCM clock feedback
|
|
.CLKIN(CLKIN), // Clock input (from IBUFG, BUFG or DCM)
|
|
.PSCLK(PSCLK), // Dynamic phase adjust clock input
|
|
.PSEN(PSEN), // Dynamic phase adjust enable input
|
|
.PSINCDEC(PSINCDEC), // Dynamic phase adjust increment/decrement
|
|
.RST(RST) // DCM asynchronous reset input
|
|
);
|
|
|
|
// End of DCM_SP_inst instantiation
|
|
</Template>
|
|
<SubFolder label="Clock Buffers" treetype="folder">
|
|
<Template label="Global Clock Buffer (BUFG)" treetype="template">
|
|
// BUFG : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFG_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFG: Global Clock Buffer (source by an internal signal)
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFG BUFG_inst (
|
|
.O(O), // Clock buffer output
|
|
.I(I) // Clock buffer input
|
|
);
|
|
|
|
// End of BUFG_inst instantiation
|
|
</Template>
|
|
<Template label="Single-ended input Global Clock Buffer (IBUFG)" treetype="template">
|
|
// IBUFG : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFG_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFG: Global Clock Buffer (sourced by an external pin)
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFG #(
|
|
.IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for
|
|
// the buffer: "0"-"16" (Spartan-3A DSP)
|
|
.IOSTANDARD("DEFAULT")
|
|
) IBUFG_inst (
|
|
.O(O), // Clock buffer output
|
|
.I(I) // Clock buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUFG_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Input Global Clock Buffer (IBUFGDS)" treetype="template">
|
|
// IBUFGDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFGDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFGDS: Differential Global Clock Buffer (sourced by an external pin)
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFGDS #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination
|
|
.IOSTANDARD("DEFAULT"), // Specifies the I/O standard for this buffer
|
|
.IBUF_DELAY_VALUE("0") // Specify the amount of added input delay for
|
|
// the buffer: "0"-"16" (Spartan-3A DSP)
|
|
) IBUFGDS_inst (
|
|
.O(O), // Clock buffer output
|
|
.I(I), // Diff_p clock buffer input
|
|
.IB(IB) // Diff_n clock buffer input
|
|
);
|
|
|
|
// End of IBUFGDS_inst instantiation
|
|
</Template>
|
|
<Template label="Global Clock Buffer w/ Enable (BUFGCE)" treetype="template">
|
|
// BUFGCE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFGCE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFGCE: Global Clock Buffer with Clock Enable (active high)
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFGCE BUFGCE_inst (
|
|
.O(O), // Clock buffer output
|
|
.CE(CE), // Clock enable input
|
|
.I(I) // Clock buffer input
|
|
);
|
|
|
|
// End of BUFGCE_inst instantiation
|
|
</Template>
|
|
<Template label="Global Clock Buffer w/ Enable (BUFGCE_1)" treetype="template">
|
|
// BUFGCE_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFGCE_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFGCE_1: Global Clock Buffer with Clock Enable (active low)
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFGCE_1 BUFGCE_1_inst (
|
|
.O(O), // Clock buffer output
|
|
.CE(CE), // Clock enable input
|
|
.I(I) // Clock buffer input
|
|
);
|
|
|
|
// End of BUFGCE_1_inst instantiation
|
|
// End of BUFIO_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Clock MUX" treetype="folder">
|
|
<Template label="Global Clock Buffer MUX (BUFGMUX)" treetype="template">
|
|
// BUFGMUX : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFGMUX_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFGMUX: Global Clock Buffer 2-to-1 MUX
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFGMUX BUFGMUX_inst (
|
|
.O(O), // Clock MUX output
|
|
.I0(I0), // Clock0 input
|
|
.I1(I1), // Clock1 input
|
|
.S(S) // Clock select input
|
|
);
|
|
|
|
// End of BUFGMUX_inst instantiation
|
|
</Template>
|
|
<Template label="Global Clock Buffer MUX (BUFGMUX_1)" treetype="template">
|
|
// BUFGMUX_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFGMUX_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFGMUX_1: Global Clock Buffer 2-to-1 MUX (inverted select)
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFGMUX_1 BUFGMUX_1_inst (
|
|
.O(O), // Clock MUX output
|
|
.I0(I0), // Clock0 input
|
|
.I1(I1), // Clock1 input
|
|
.S(S) // Clock select input
|
|
);
|
|
|
|
// End of BUFGMUX_1_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="RAM/ROM" treetype="folder">
|
|
<SubFolder label="Distributed ROM" treetype="folder">
|
|
<Template label="16 X 1 (ROM16X1)" treetype="template">
|
|
// ROM16X1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ROM16X1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ROM16X1: 16 x 1 Asynchronous Distributed (LUT) ROM
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ROM16X1 #(
|
|
.INIT(16'h0000) // Contents of ROM
|
|
) ROM16X1_inst (
|
|
.O(O), // ROM output
|
|
.A0(A0), // ROM address[0]
|
|
.A1(A1), // ROM address[1]
|
|
.A2(A2), // ROM address[2]
|
|
.A3(A3) // ROM address[3]
|
|
);
|
|
|
|
// End of ROM16X1_inst instantiation
|
|
</Template>
|
|
<Template label="32 X 1 (ROM32X1)" treetype="template">
|
|
// ROM32X1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ROM32X1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ROM32X1: 32 x 1 Asynchronous Distributed (LUT) ROM
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ROM32X1 #(
|
|
.INIT(32'h00000000) // Contents of ROM
|
|
) ROM32X1_inst (
|
|
.O(O), // ROM output
|
|
.A0(A0), // ROM address[0]
|
|
.A1(A1), // ROM address[1]
|
|
.A2(A2), // ROM address[2]
|
|
.A3(A3), // ROM address[3]
|
|
.A4(A4) // ROM address[4]
|
|
);
|
|
|
|
// End of ROM32X1_inst instantiation
|
|
</Template>
|
|
<Template label="64 X 1 (ROM64X1)" treetype="template">
|
|
// ROM64X1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ROM64X1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ROM64X1: 64 x 1 Asynchronous Distributed (LUT) ROM
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ROM64X1 #(
|
|
.INIT(64'h0000000000000000) // Contents of ROM
|
|
) ROM64X1_inst (
|
|
.O(O), // ROM output
|
|
.A0(A0), // ROM address[0]
|
|
.A1(A1), // ROM address[1]
|
|
.A2(A2), // ROM address[2]
|
|
.A3(A3), // ROM address[3]
|
|
.A4(A4), // ROM address[4]
|
|
.A5(A5) // ROM address[5]
|
|
);
|
|
|
|
// End of ROM64X1_inst instantiation
|
|
</Template>
|
|
<Template label="128 X 1 (ROM128X1)" treetype="template">
|
|
// ROM128X1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ROM128X1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ROM128X1: 128 x 1 Asynchronous Distributed (LUT) ROM
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ROM128X1 #(
|
|
.INIT(128'h00000000000000000000000000000000) // Contents of ROM
|
|
) ROM128X1_inst (
|
|
.O(O), // ROM output
|
|
.A0(A0), // ROM address[0]
|
|
.A1(A1), // ROM address[1]
|
|
.A2(A2), // ROM address[2]
|
|
.A3(A3), // ROM address[3]
|
|
.A4(A4), // ROM address[4]
|
|
.A5(A5), // ROM address[5]
|
|
.A6(A6) // ROM address[6]
|
|
);
|
|
|
|
// End of ROM128X1_inst instantiation
|
|
</Template>
|
|
<Template label="256 X 1 (ROM256X1)" treetype="template">
|
|
// ROM256X1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ROM256X1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ROM256X1: 256 x 1 Asynchronous Distributed (LUT) ROM
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ROM256X1 #(
|
|
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000) // Contents of ROM
|
|
) ROM256X1_inst (
|
|
.O(O), // ROM output
|
|
.A0(A0), // ROM address[0]
|
|
.A1(A1), // ROM address[1]
|
|
.A2(A2), // ROM address[2]
|
|
.A3(A3), // ROM address[3]
|
|
.A4(A4), // ROM address[4]
|
|
.A5(A5), // ROM address[5]
|
|
.A6(A6), // ROM address[6]
|
|
.A7(A7) // ROM address[7]
|
|
);
|
|
|
|
// End of ROM256X1_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Distributed RAM" treetype="folder">
|
|
<SubFolder label="Single-Port" treetype="folder">
|
|
<SubFolder label="16 Deep (4-bit address)" treetype="folder">
|
|
<Template label="16 x 1 posedge write (RAM16X1S)" treetype="template">
|
|
// RAM16X1S : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM16X1S_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM16X1S: 16 x 1 posedge write distributed (LUT) RAM
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM16X1S #(
|
|
.INIT(16'h0000) // Initial contents of RAM
|
|
) RAM16X1S_inst (
|
|
.O(O), // RAM output
|
|
.A0(A0), // RAM address[0] input
|
|
.A1(A1), // RAM address[1] input
|
|
.A2(A2), // RAM address[2] input
|
|
.A3(A3), // RAM address[3] input
|
|
.D(D), // RAM data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM16X1S_inst instantiation
|
|
</Template>
|
|
<Template label="16 x 1 negedge write (RAM16X1S_1)" treetype="template">
|
|
// RAM16X1S_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM16X1S_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM16X1S_1: 16 x 1 negedge write distributed (LUT) RAM
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM16X1S_1 #(
|
|
.INIT(16'h0000) // Initial contents of RAM
|
|
) RAM16X1S_1_inst (
|
|
.O(O), // RAM output
|
|
.A0(A0), // RAM address[0] input
|
|
.A1(A1), // RAM address[1] input
|
|
.A2(A2), // RAM address[2] input
|
|
.A3(A3), // RAM address[3] input
|
|
.D(D), // RAM data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM16X1S_1_inst instantiation
|
|
</Template>
|
|
<Template label="16 x 2 posedge write (RAM16X2S)" treetype="template">
|
|
// RAM16X2S : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM16X2S_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM16X2S: 16 x 2 posedge write distributed (LUT) RAM
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM16X2S #(
|
|
.INIT_00(16'h0000), // Initial contents of bit 0 of RAM
|
|
.INIT_01(16'h0000) // Initial contents of bit 1 of RAM
|
|
) RAM16X2S_inst (
|
|
.O0(O0), // RAM data[0] output
|
|
.O1(O1), // RAM data[1] output
|
|
.A0(A0), // RAM address[0] input
|
|
.A1(A1), // RAM address[1] input
|
|
.A2(A2), // RAM address[2] input
|
|
.A3(A3), // RAM address[3] input
|
|
.D0(D0), // RAM data[0] input
|
|
.D1(D1), // RAM data[1] input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM16X2S_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="32 Deep (5-bit address)" treetype="folder">
|
|
<Template label="32 x 1 posedge write (RAM32X1S)" treetype="template">
|
|
// RAM32X1S : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM32X1S_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM32X1S: 32 x 1 posedge write distributed (LUT) RAM
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM32X1S #(
|
|
.INIT(32'h00000000) // Initial contents of RAM
|
|
) RAM32X1S_inst (
|
|
.O(O), // RAM output
|
|
.A0(A0), // RAM address[0] input
|
|
.A1(A1), // RAM address[1] input
|
|
.A2(A2), // RAM address[2] input
|
|
.A3(A3), // RAM address[3] input
|
|
.A4(A4), // RAM address[4] input
|
|
.D(D), // RAM data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM32X1S_inst instantiation
|
|
</Template>
|
|
<Template label="32 x 1 negedge write (RAM32X1S_1)" treetype="template">
|
|
// RAM32X1S_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM32X1S_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM32X1S_1: 32 x 1 negedge write distributed (LUT) RAM
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM32X1S_1 #(
|
|
.INIT(32'h00000000) // Initial contents of RAM
|
|
)RAM32X1S_1_inst (
|
|
.O(O), // RAM output
|
|
.A0(A0), // RAM address[0] input
|
|
.A1(A1), // RAM address[1] input
|
|
.A2(A2), // RAM address[2] input
|
|
.A3(A3), // RAM address[3] input
|
|
.A4(A4), // RAM address[4] input
|
|
.D(D), // RAM data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM32X1S_1_inst instantiation
|
|
</Template>
|
|
<Template label="32 x 2 posedge write (RAM32X2S)" treetype="template">
|
|
// RAM32X2S : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM16X2S_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM32X2S: 32 x 2 posedge write distributed (LUT) RAM
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM32X2S #(
|
|
.INIT_00(32'h00000000), // INIT for bit 0 of RAM
|
|
.INIT_01(32'h00000000) // INIT for bit 1 of RAM
|
|
) RAM32X2S_inst (
|
|
.O0(O0), // RAM data[0] output
|
|
.O1(O1), // RAM data[1] output
|
|
.A0(A0), // RAM address[0] input
|
|
.A1(A1), // RAM address[1] input
|
|
.A2(A2), // RAM address[2] input
|
|
.A3(A3), // RAM address[3] input
|
|
.A4(A4), // RAM address[4] input
|
|
.D0(D0), // RAM data[0] input
|
|
.D1(D1), // RAM data[1] input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM32X2S_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="64 Deep (6-bit address)" treetype="folder">
|
|
<Template label="64 X 1 posedge write (RAM64X1S)" treetype="template">
|
|
// RAM64X1S : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM64X1S_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM64X1S: 64 x 1 positive edge write, asynchronous read single-port distributed RAM
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM64X1S #(
|
|
.INIT(64'h0000000000000000) // Initial contents of RAM
|
|
) RAM64X1S_inst (
|
|
.O(O), // 1-bit data output
|
|
.A0(A0), // Address[0] input bit
|
|
.A1(A1), // Address[1] input bit
|
|
.A2(A2), // Address[2] input bit
|
|
.A3(A3), // Address[3] input bit
|
|
.A4(A4), // Address[4] input bit
|
|
.A5(A5), // Address[5] input bit
|
|
.D(D), // 1-bit data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM64X1S_inst instantiation
|
|
</Template>
|
|
<Template label="64 X 1 negedge write (RAM64X1S_1)" treetype="template">
|
|
// RAM64X1S_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM64X1S_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM64X1S_1: 64 x 1 negative edge write, asynchronous read single-port distributed RAM
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM64X1S_1 #(
|
|
.INIT(64'h0000000000000000) // Initial contents of RAM
|
|
) RAM64X1S_1_inst (
|
|
.O(O), // 1-bit data output
|
|
.A0(A0), // Address[0] input bit
|
|
.A1(A1), // Address[1] input bit
|
|
.A2(A2), // Address[2] input bit
|
|
.A3(A3), // Address[3] input bit
|
|
.A4(A4), // Address[4] input bit
|
|
.A5(A5), // Address[5] input bit
|
|
.D(D), // 1-bit data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM64X1S_1_inst instantiation
|
|
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Dual-Port" treetype="folder">
|
|
<Template label="16 X 1 posedge write (RAM16X1D)" treetype="template">
|
|
// RAM16X1D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM16X1D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM16X1D: 16 x 1 positive edge write, asynchronous read dual-port distributed RAM
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM16X1D #(
|
|
.INIT(16'h0000) // Initial contents of RAM
|
|
) RAM16X1D_inst (
|
|
.DPO(DPO), // Read-only 1-bit data output for DPRA
|
|
.SPO(SPO), // Rw/ 1-bit data output for A0-A3
|
|
.A0(A0), // Rw/ address[0] input bit
|
|
.A1(A1), // Rw/ address[1] input bit
|
|
.A2(A2), // Rw/ address[2] input bit
|
|
.A3(A3), // Rw/ address[3] input bit
|
|
.D(D), // Write 1-bit data input
|
|
.DPRA0(DPRA0), // Read address[0] input bit
|
|
.DPRA1(DPRA1), // Read address[1] input bit
|
|
.DPRA2(DPRA2), // Read address[2] input bit
|
|
.DPRA3(DPRA3), // Read address[3] input bit
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM16X1D_inst instantiation
|
|
</Template>
|
|
<Template label="16 X 1 negedge write (RAM16X1D_1)" treetype="template">
|
|
// RAM16X1D_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM16X1D_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM16X1D_1: 16 x 1 negative edge write, asynchronous read dual-port distributed RAM
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM16X1D_1 #(
|
|
.INIT(16'h0000) // Initial contents of RAM
|
|
) RAM16X1D_1_inst (
|
|
.DPO(DPO), // Read-only 1-bit data output
|
|
.SPO(SPO), // Rw/ 1-bit data output
|
|
.A0(A0), // Rw/ address[0] input bit
|
|
.A1(A1), // Rw/ address[1] input bit
|
|
.A2(A2), // Rw/ address[2] input bit
|
|
.A3(A3), // Rw/ address[3] input bit
|
|
.D(D), // Write 1-bit data input
|
|
.DPRA0(DPRA0), // Read-only address[0] input bit
|
|
.DPRA1(DPRA1), // Read-only address[1] input bit
|
|
.DPRA2(DPRA2), // Read-only address[2] input bit
|
|
.DPRA3(DPRA3), // Read-only address[3] input bit
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM16X1D_1_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Block RAM" treetype="folder">
|
|
<Template label="16k + 2k parity parameterizable BlockRAM (RAMB16BWER)" treetype="template">
|
|
// RAMB16BWER : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16BWER_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16BWER: 16k+2k Parity parameterizable, byte-wide enable BlockRAM, output registers
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16BWER #(
|
|
.DATA_WIDTH_A(0), // Valid values are 0, 1, 2, 4, 9, 18, or 36
|
|
.DATA_WIDTH_B(0), // Valid values are 0, 1, 2, 4, 9, 18, or 36
|
|
.DOA_REG(0), // Specifies to enable=1/disable=0 port A output registers
|
|
.DOB_REG(0), // Specifies to enable=1/disable=0 port B output registers
|
|
.INIT_A(36'h000000000), // Initial values on A output port
|
|
.INIT_B(36'h000000000), // Initial values on B output port
|
|
.RSTTYPE("SYNC"), // Specifes reset type to be "SYNC" or "ASYNC"
|
|
.SIM_COLLISION_CHECK("ALL"), // Collision check enable "ALL", "WARNING_ONLY",
|
|
// "GENERATE_X_ONLY" or "NONE"
|
|
.SRVAL_A(36'h000000000), // Set/Reset value for A port output
|
|
.SRVAL_B(36'h000000000), // Set/Reset value for B port output
|
|
.WRITE_MODE_A("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
|
|
.WRITE_MODE_B("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16BWER_inst (
|
|
.DOA(DOA), // 32-bit A port data output
|
|
.DOB(DOB), // 32-bit B port data output
|
|
.DOPA(DOPA), // 4-bit A port parity data output
|
|
.DOPB(DOPB), // 4-bit B port parity data output
|
|
.ADDRA(ADDRA), // 14-bit A port address input
|
|
.ADDRB(ADDRB), // 14-bit B port address input
|
|
.CLKA(CLKA), // 1-bit A port clock input
|
|
.CLKB(CLKB), // 1-bit B port clock input
|
|
.DIA(DIA), // 32-bit A port data input
|
|
.DIB(DIB), // 32-bit B port data input
|
|
.DIPA(DIPA), // 4-bit A port parity data input
|
|
.DIPB(DIPB), // 4-bit B port parity data input
|
|
.ENA(ENA), // 1-bit A port enable input
|
|
.ENB(ENB), // 1-bit B port enable input
|
|
.REGCEA(REGCEA), // 1-bit A port output register enable input
|
|
.REGCEB(REGCEB), // 1-bit B port output register enable input
|
|
.RSTA(RSTA), // 1-bit A port reset input
|
|
.RSTB(RSTB), // 1-bit B port reset input
|
|
.WEA(WEA), // 4-bit A port write enable input
|
|
.WEB(WEB) // 4-bit B port write enable input
|
|
);
|
|
|
|
// End of RAMB16BWER_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Arithmetic Functions" treetype="folder">
|
|
<Template label="DSP Block (DSP48A)" treetype="template">
|
|
// DSP48A : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (DSP48A_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// DSP48A: DSP Function Block
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
DSP48A #(
|
|
.A0REG(0), // Enable=1/disable=0 first stage A input pipeline register
|
|
.A1REG(1), // Enable=1/disable=0 second stage A input pipeline register
|
|
.B0REG(0), // Enable=1/disable=0 first stage B input pipeline register
|
|
.B1REG(1), // Enable=1/disable=0 second stage B input pipeline register
|
|
.CARRYINREG(1), // Enable=1/disable=0 CARRYIN input pipeline register
|
|
.CARRYINSEL("CARRYIN"), // Specify carry-in source, "CARRYIN" or "OPMODE5"
|
|
.CREG(1), // Enable=1/disable=0 C input pipeline register
|
|
.DREG(1), // Enable=1/disable=0 D pre-adder input pipeline register
|
|
.MREG(1), // Enable=1/disable=0 M pipeline register
|
|
.OPMODEREG(1), // Enable=1/disable=0 OPMODE input pipeline register
|
|
.PREG(1), // Enable=1/disable=0 P output pipeline register
|
|
.RSTTYPE("SYNC") // Specify reset type, "SYNC" or "ASYNC"
|
|
) DSP48A_inst (
|
|
.BCOUT(BCOUT), // 18-bit B port cascade output
|
|
.CARRYOUT(CARRYOUT), // 1-bit carry output
|
|
.P(P), // 48-bit output
|
|
.PCOUT(PCOUT), // 48-bit cascade output
|
|
.A(A), // 18-bit A data input
|
|
.B(B), // 18-bit B data input (can be connected to fabric or BCOUT of adjacent DSP48A)
|
|
.C(C), // 48-bit C data input
|
|
.CARRYIN(CARRYIN), // 1-bit carry input signal
|
|
.CEA(CEA), // 1-bit active high clock enable input for A input registers
|
|
.CEB(CEB), // 1-bit active high clock enable input for B input registers
|
|
.CEC(CEC), // 1-bit active high clock enable input for C input registers
|
|
.CECARRYIN(CECARRYIN), // 1-bit active high clock enable input for CARRYIN registers
|
|
.CED(CED), // 1-bit active high clock enable input for D input registers
|
|
.CEM(CEM), // 1-bit active high clock enable input for multiplier registers
|
|
.CEOPMODE(CEOPMODE), // 1-bit active high clock enable input for OPMODE registers
|
|
.CEP(CEP), // 1-bit active high clock enable input for P output registers
|
|
.CLK(CLK), // Clock input
|
|
.D(D), // 18-bit B pre-adder data input
|
|
.OPMODE(OPMODE), // 8-bit operation mode input
|
|
.PCIN(PCIN), // 48-bit P cascade input
|
|
.RSTA(RSTA), // 1-bit reset input for A input pipeline registers
|
|
.RSTB(RSTB), // 1-bit reset input for B input pipeline registers
|
|
.RSTC(RSTC), // 1-bit reset input for C input pipeline registers
|
|
.RSTCARRYIN(RSTCARRYIN), // 1-bit reset input for CARRYIN input pipeline registers
|
|
.RSTD(RSTD), // 1-bit reset input for D input pipeline registers
|
|
.RSTM(RSTM), // 1-bit reset input for M pipeline registers
|
|
.RSTOPMODE(RSTOPMODE), // 1-bit reset input for OPMODE input pipeline registers
|
|
.RSTP(RSTP) // 1-bit reset input for P output pipeline registers
|
|
);
|
|
|
|
// End of DSP48A_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Config/BSCAN Components" treetype="folder">
|
|
<Template label="Simulate Configuration (SIM_CONFIG_S3A)" treetype="template">
|
|
// SIM_CONFIG_S3A : In order to incorporate this function into the testbench (not the design),
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SIM_CONFIG_S3A_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SIM_CONFIG_S3A: Behavioral Simulation-only Model of FPGA SelectMap Configuration
|
|
// Spartan-3A DSP/3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SIM_CONFIG_S3A #(
|
|
.DEVICE_ID(32'h00000000)
|
|
) SIM_CONFIG_S3A_inst (
|
|
.CSOB(CSOB), // 1-bit output chip select pin
|
|
.DONE(DONE), // 1-bit bi-directional Done pin
|
|
.CCLK(CCLK), // 1-bit input configuration clock
|
|
.D(D), // 8-bit bi-directional configuration data
|
|
.DCMLOCK(DCMLOCK), // 1-bit input DCM Lock
|
|
.CSIB(CSIB), // 1-bit input chip select
|
|
.INITB(INITB), // 1-bit bi-directional INIT status pin
|
|
.M(M), // 3-bit input Mode pins
|
|
.PROGB(PROGB), // 1-bit input Program pin
|
|
.RDWRB(RDWRB) // 1-bit input Read/write pin
|
|
);
|
|
|
|
// End of SIM_CONFIG_S3A_inst instantiation
|
|
</Template>
|
|
<Template label="Boundary Scan (BSCAN_SPARTAN3A)" treetype="template">
|
|
// BSCAN_SPARTAN3A : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BSCAN_SPARTAN3A_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BSCAN_SPARTAN3A: Boundary Scan primitive for connecting internal logic to
|
|
// JTAG interface.
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BSCAN_SPARTAN3A BSCAN_SPARTAN3A_inst (
|
|
.CAPTURE(CAPTURE), // CAPTURE output from TAP controller
|
|
.DRCK1(DRCK1), // Data register output for USER1 functions
|
|
.DRCK2(DRCK2), // Data register output for USER2 functions
|
|
.RESET(RESET), // Reset output from TAP controller
|
|
.SEL1(SEL1), // USER1 active output
|
|
.SEL2(SEL2), // USER2 active output
|
|
.SHIFT(SHIFT), // SHIFT output from TAP controller
|
|
.TCK(TCK), // TCK output from TAP controller
|
|
.TDI(TDI), // TDI output from TAP controller
|
|
.TMS(TMS), // TMS output from TAP controller
|
|
.UPDATE(UPDATE), // UPDATE output from TAP controller
|
|
.TDO1(TDO1), // Data input for USER1 function
|
|
.TDO2(TDO2) // Data input for USER2 function
|
|
);
|
|
|
|
// End of BSCAN_SPARTAN3A_inst instantiation
|
|
</Template>
|
|
<Template label="Register Capture (CAPTURE_SPARTAN3A)" treetype="template">
|
|
// CAPTURE_SPARTAN3A : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (CAPTURE_SPARTAN3A_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// CAPTURE_SPARTAN3A: Register State Capture for Bitstream Readback
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
CAPTURE_SPARTAN3A #(
|
|
.ONESHOT("TRUE") // "TRUE" or "FALSE"
|
|
) CAPTURE_SPARTAN3A_inst (
|
|
.CAP(CAP), // Capture input
|
|
.CLK(CLK) // Clock input
|
|
);
|
|
|
|
// End of CAPTURE_SPARTAN3A_inst instantiation
|
|
</Template>
|
|
<Template label="Internal Config Port (ICAP_SPARTAN3A)" treetype="template">
|
|
// ICAP_SPARTAN3A : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ICAP_SPARTAN3A_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ICAP_SPARTAN3A: Internal Configuration Access Port
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ICAP_SPARTAN3A ICAP_SPARTAN3A_inst (
|
|
.BUSY(BUSY), // Busy output
|
|
.O(O), // 8-bit data output
|
|
.CE(CE), // Clock enable input
|
|
.CLK(CLK), // Clock input
|
|
.I(I), // 8-bit data input
|
|
.WRITE(WRITE) // Write input
|
|
);
|
|
|
|
// End of ICAP_SPARTAN3A_inst instantiation
|
|
</Template>
|
|
<Template label="Startup Block (STARTUP_SPARTAN3A)" treetype="template">
|
|
// STARTUP_SPARTAN3A : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (STARTUP_SPARTAN3A_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// STARTUP_SPARTAN3A: Startup primitive for GSR, GTS or startup sequence
|
|
// control.
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
STARTUP_SPARTAN3A STARTUP_SPARTAN3A_inst (
|
|
.CLK(CLK), // Clock input for start-up sequence
|
|
.GSR(GSR_PORT), // Global Set/Reset input (GSR cannot be used as a port name)
|
|
.GTS(GTS_PORT) // Global 3-state input (GTS cannot be used as a port name)
|
|
);
|
|
|
|
// End of STARTUP_SPARTAN3A_inst instantiation
|
|
</Template>
|
|
<Template label="DNA Access (DNA_PORT)" treetype="template">
|
|
// DNA_PORT : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (DNA_PORT_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// DNA_PORT: Access to the device-specific DNA value
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
DNA_PORT #(
|
|
.SIM_DNA_VALUE(57'h000000000000000) // Specifies the unique DNA value
|
|
// for simulation test
|
|
) DNA_PORT_inst (
|
|
|
|
.DOUT(DOUT), // 1-bit DNA output data
|
|
.CLK(CLK), // 1-bit clock input
|
|
.DIN(DIN), // 1-bit user data input pin
|
|
.READ(READ), // 1-bit input, active high load DNA, active low read
|
|
.SHIFT(SHIFT) // 1-bit input, active high shift enable
|
|
);
|
|
|
|
// End of DNA_PORT_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="I/O Components" treetype="folder">
|
|
<SubFolder label="Input" treetype="folder">
|
|
<Template label="Single-ended Buffer with Dynamic Delay Adjust (IBUF_DLY_ADJ)" treetype="template">
|
|
// IBUF_DLY_ADJ : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUF_DLY_ADJ_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUF_DLY_ADJ: Dynamically Adjustable Delay, Single-ended Input Buffer
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUF_DLY_ADJ #(
|
|
.DELAY_OFFSET("OFF"), // Enable Initial Delay Offset, "OFF" or "ON"
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
)IBUF_DLY_ADJ_inst (
|
|
.O(O), // Buffer output
|
|
.I(I), // Buffer input (connect directly to top-level port)
|
|
.S(S) // 3-bit buffer delay select input
|
|
);
|
|
|
|
// End of IBUF_DLY_ADJ_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer with Dynamic Delay Adjust (IBUFDS_DLY_ADJ)" treetype="template">
|
|
// IBUFDS_DLY_ADJ : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFDS_DLY_ADJ_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFDS_DLY_ADJ: Dynamically Adjustable Delay, Differential Input Buffer
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFDS_DLY_ADJ #(
|
|
.DELAY_OFFSET("OFF"), // Enable Initial Delay Offset, "OFF" or "ON"
|
|
.DIFF_TERM("FALSE"), // Differential Termination
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
) IBUFDS_DLY_ADJ_inst (
|
|
.O(O), // Buffer output
|
|
.I(I), // Diff_p buffer input (connect directly to top-level port)
|
|
.IB(IB), // Diff_n buffer input (connect directly to top-level port)
|
|
.S(S) // 3-bit buffer delay select input
|
|
);
|
|
|
|
// End of IBUFDS_DLY_ADJ_inst instantiation
|
|
</Template>
|
|
<Template label="Single-ended Buffer (IBUF)" treetype="template">
|
|
// IBUF : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUF_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUF: Single-ended Input Buffer
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUF #(
|
|
.IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for
|
|
// the buffer: "0"-"16" (Spartan-3A DSP)
|
|
.IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input
|
|
// register: "AUTO", "0"-"8" (Spartan-3A DSP)
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
)IBUF_inst (
|
|
.O(O), // Buffer output
|
|
.I(I) // Buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUF_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer (IBUFDS)" treetype="template">
|
|
// IBUFDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFDS: Differential Input Buffer
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFDS #(
|
|
.IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for
|
|
// the buffer: "0"-"16" (Spartan-3A DSP)
|
|
.IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input
|
|
// register: "AUTO", "0"-"8" (Spartan-3A DSP)
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
) IBUFDS_inst (
|
|
.O(O), // Buffer output
|
|
.I(I), // Diff_p buffer input (connect directly to top-level port)
|
|
.IB(IB) // Diff_n buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUFDS_inst instantiation
|
|
</Template>
|
|
<Template label="Single-ended Global Clock (IBUFG)" treetype="template">
|
|
// IBUFG : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFG_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFG: Single-ended global clock input buffer
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFG #(
|
|
.IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for
|
|
// the buffer: "0"-"16" (Spartan-3A DSP)
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
) IBUFG_inst (
|
|
.O(O), // Clock buffer output
|
|
.I(I) // Clock buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUFG_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Global Clock (IBUFGDS)" treetype="template">
|
|
// IBUFGDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFGDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFGDS: Differential Global Clock Input Buffer
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFGDS #(
|
|
.IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for
|
|
// the buffer, "0"-"16" (Spartan-3A DSP)
|
|
.DIFF_TERM("FALSE"), // Differential Termination
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
) IBUFGDS_inst (
|
|
.O(O), // Clock buffer output
|
|
.I(I), // Diff_p clock buffer input (connect directly to top-level port)
|
|
.IB(IB) // Diff_n clock buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUFGDS_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Output" treetype="folder">
|
|
<Template label="Single-ended Buffer (OBUF)" treetype="template">
|
|
// OBUF : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OBUF_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OBUF: Single-ended Output Buffer
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OBUF #(
|
|
.DRIVE(12), // Specify the output drive strength
|
|
.IOSTANDARD("DEFAULT"), // Specify the output I/O standard
|
|
.SLEW("SLOW") // Specify the output slew rate
|
|
) OBUF_inst (
|
|
.O(O), // Buffer output (connect directly to top-level port)
|
|
.I(I) // Buffer input
|
|
);
|
|
|
|
// End of OBUF_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer (OBUFDS)" treetype="template">
|
|
|
|
// OBUFDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OBUFDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OBUFDS: Differential Output Buffer
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OBUFDS #(
|
|
.IOSTANDARD("DEFAULT") // Specify the output I/O standard
|
|
) OBUFDS_inst (
|
|
.O(O), // Diff_p output (connect directly to top-level port)
|
|
.OB(OB), // Diff_n output (connect directly to top-level port)
|
|
.I(I) // Buffer input
|
|
);
|
|
|
|
// End of OBUFDS_inst instantiation
|
|
</Template>
|
|
<Template label="Single-ended 3-state Buffer (OBUFT)" treetype="template">
|
|
// OBUFT : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OBUFT_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OBUFT: Single-ended 3-state Output Buffer
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OBUFT #(
|
|
.DRIVE(12), // Specify the output drive strength
|
|
.IOSTANDARD("DEFAULT"), // Specify the output I/O standard
|
|
.SLEW("SLOW") // Specify the output slew rate
|
|
) OBUFT_inst (
|
|
.O(O), // Buffer output (connect directly to top-level port)
|
|
.I(I), // Buffer input
|
|
.T(T) // 3-state enable input
|
|
);
|
|
|
|
// End of OBUFT_inst instantiation
|
|
</Template>
|
|
<Template label="Differential 3-state Buffer (OBUFTDS)" treetype="template">
|
|
// OBUFTDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OBUFTDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OBUFTDS: Differential 3-state Output Buffer
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OBUFTDS #(
|
|
.IOSTANDARD("DEFAULT") // Specify the output I/O standard
|
|
) OBUFTDS_inst (
|
|
.O(O), // Diff_p output (connect directly to top-level port)
|
|
.OB(OB), // Diff_n output (connect directly to top-level port)
|
|
.I(I), // Buffer input
|
|
.T(T) // 3-state enable input
|
|
);
|
|
|
|
// End of OBUFTDS_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Bi-directional" treetype="folder">
|
|
<Template label="Single-ended Buffer (IOBUF)" treetype="template">
|
|
// IOBUF : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IOBUF_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IOBUF: Single-ended Bi-directional Buffer
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IOBUF #(
|
|
.DRIVE(12), // Specify the output drive strength
|
|
.IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for the buffer,
|
|
// "0"-"16" (Spartan-3A DSP only)
|
|
.IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input register,
|
|
// "AUTO", "0"-"8" (Spartan-3A DSP only)
|
|
.IOSTANDARD("DEFAULT"), // Specify the I/O standard
|
|
.SLEW("SLOW") // Specify the output slew rate
|
|
) IOBUF_inst (
|
|
.O(O), // Buffer output
|
|
.IO(IO), // Buffer inout port (connect directly to top-level port)
|
|
.I(I), // Buffer input
|
|
.T(T) // 3-state enable input, high=input, low=output
|
|
);
|
|
|
|
// End of IOBUF_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer (IOBUFDS)" treetype="template">
|
|
// IOBUFDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IOBUFDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IOBUFDS: Differential Bi-directional Buffer
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IOBUFDS #(
|
|
.IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for the buffer,
|
|
// "0"-"16" (Spartan-3A DSP only)
|
|
.IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input register,
|
|
// "AUTO", "0"-"8" (Spartan-3A DSP only)
|
|
.IOSTANDARD("DEFAULT") // Specify the I/O standard
|
|
) IOBUFDS_inst (
|
|
.O(O), // Buffer output
|
|
.IO(IO), // Diff_p inout (connect directly to top-level port)
|
|
.IOB(IOB), // Diff_n inout (connect directly to top-level port)
|
|
.I(I), // Buffer input
|
|
.T(T) // 3-state enable input, high=input, low=output
|
|
);
|
|
|
|
// End of IOBUFDS_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Weak drivers" treetype="folder">
|
|
<Template label="PULLUP" treetype="template">
|
|
// PULLUP : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (PULLUP_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design.
|
|
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// PULLUP: I/O Buffer Weak Pull-up
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
PULLUP PULLUP_inst (
|
|
.O(O) // Pullup output (connect directly to top-level port)
|
|
);
|
|
|
|
// End of PULLUP_inst instantiation
|
|
</Template>
|
|
<Template label="PULLDOWN" treetype="template">
|
|
// PULLDOWN : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (PULLDOWN_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// PULLDOWN: I/O Buffer Weak Pull-down
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
PULLDOWN PULLDOWN_inst (
|
|
.O(O) // Pulldown output (connect directly to top-level port)
|
|
);
|
|
|
|
// End of PULLDOWN_inst instantiation
|
|
</Template>
|
|
<Template label="KEEPER" treetype="template">
|
|
// KEEPER : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (KEEPER_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// KEEPER: I/O Buffer Weak Keeper
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
KEEPER KEEPER_inst (
|
|
.O(O) // Keeper output (connect directly to top-level port)
|
|
);
|
|
|
|
// End of KEEPER_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="DDR Registers" treetype="folder">
|
|
<Template label="Input DDR Register (IDDR2)" treetype="template">
|
|
// IDDR2 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IDDR2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IDDR2: Input Double Data Rate Input Register with Set, Reset
|
|
// and Clock Enable.
|
|
// Spartan-3A DSP/3A/6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IDDR2 #(
|
|
.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
|
|
.INIT_Q0(1'b0), // Sets initial state of the Q0 output to 1'b0 or 1'b1
|
|
.INIT_Q1(1'b0), // Sets initial state of the Q1 output to 1'b0 or 1'b1
|
|
.SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
|
|
) IDDR2_inst (
|
|
.Q0(Q0), // 1-bit output captured with C0 clock
|
|
.Q1(Q1), // 1-bit output captured with C1 clock
|
|
.C0(C0), // 1-bit clock input
|
|
.C1(C1), // 1-bit clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.D(D), // 1-bit DDR data input
|
|
.R(R), // 1-bit reset input
|
|
.S(S) // 1-bit set input
|
|
);
|
|
|
|
// End of IDDR2_inst instantiation
|
|
</Template>
|
|
<Template label="Output DDR Register (ODDR2)" treetype="template">
|
|
// ODDR2 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ODDR2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ODDR2: Output Double Data Rate Output Register with Set, Reset
|
|
// and Clock Enable.
|
|
// Spartan-3A DSP/3A/6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ODDR2 #(
|
|
.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
|
|
.INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1
|
|
.SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
|
|
) ODDR2_inst (
|
|
.Q(Q), // 1-bit DDR output data
|
|
.C0(C0), // 1-bit clock input
|
|
.C1(C1), // 1-bit clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.D0(D0), // 1-bit data input (associated with C0)
|
|
.D1(D1), // 1-bit data input (associated with C1)
|
|
.R(R), // 1-bit reset input
|
|
.S(S) // 1-bit set input
|
|
);
|
|
|
|
// End of ODDR2_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Registers & Latches" treetype="folder">
|
|
<SubFolder label="Double Data Rate (DDR)" treetype="folder">
|
|
<Template label="Input DDR Register (IDDR2)" treetype="template">
|
|
// IDDR2 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IDDR2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IDDR2: Input Double Data Rate Input Register with Set, Reset
|
|
// and Clock Enable.
|
|
// Spartan-3A DSP/3A/6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IDDR2 #(
|
|
.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
|
|
.INIT_Q0(1'b0), // Sets initial state of the Q0 output to 1'b0 or 1'b1
|
|
.INIT_Q1(1'b0), // Sets initial state of the Q1 output to 1'b0 or 1'b1
|
|
.SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
|
|
) IDDR2_inst (
|
|
.Q0(Q0), // 1-bit output captured with C0 clock
|
|
.Q1(Q1), // 1-bit output captured with C1 clock
|
|
.C0(C0), // 1-bit clock input
|
|
.C1(C1), // 1-bit clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.D(D), // 1-bit DDR data input
|
|
.R(R), // 1-bit reset input
|
|
.S(S) // 1-bit set input
|
|
);
|
|
|
|
// End of IDDR2_inst instantiation
|
|
</Template>
|
|
<Template label="Output DDR Register (ODDR2)" treetype="template">
|
|
// ODDR2 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ODDR2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ODDR2: Output Double Data Rate Output Register with Set, Reset
|
|
// and Clock Enable.
|
|
// Spartan-3A DSP/3A/6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ODDR2 #(
|
|
.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
|
|
.INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1
|
|
.SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
|
|
) ODDR2_inst (
|
|
.Q(Q), // 1-bit DDR output data
|
|
.C0(C0), // 1-bit clock input
|
|
.C1(C1), // 1-bit clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.D0(D0), // 1-bit data input (associated with C0)
|
|
.D1(D1), // 1-bit data input (associated with C1)
|
|
.R(R), // 1-bit reset input
|
|
.S(S) // 1-bit set input
|
|
);
|
|
|
|
// End of ODDR2_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Single Data Rate" treetype="folder">
|
|
<Template label="Posedge D-FF w/ Async Clear, and CE (FDCE)" treetype="template">
|
|
// FDCE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FDCE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FDCE: Single Data Rate D Flip-Flop with Asynchronous Clear and
|
|
// Clock Enable (posedge clk).
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FDCE #(
|
|
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
|
|
) FDCE_inst (
|
|
.Q(Q), // Data output
|
|
.C(C), // Clock input
|
|
.CE(CE), // Clock enable input
|
|
.CLR(CLR), // Asynchronous clear input
|
|
.D(D) // Data input
|
|
);
|
|
|
|
// End of FDCE_inst instantiation
|
|
</Template>
|
|
<Template label="Negedge D-FF w/ Async Clear, and CE (FDCE_1)" treetype="template">
|
|
// FDCE_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FDCE_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FDCE_1: Single Data Rate D Flip-Flop with Asynchronous Clear and
|
|
// Clock Enable (negedge clock).
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FDCE_1 #(
|
|
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
|
|
) FDCE_1_inst (
|
|
.Q(Q), // Data output
|
|
.C(C), // Clock input
|
|
.CE(CE), // Clock enable input
|
|
.CLR(CLR), // Asynchronous clear input
|
|
.D(D) // Data input
|
|
);
|
|
|
|
// End of FDCE_1_inst instantiation
|
|
</Template>
|
|
<Template label="Posedge D-FF w/ Async Clear, Set and CE (FDCPE)" treetype="template">
|
|
// FDCPE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FDCPE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FDCPE: Single Data Rate D Flip-Flop with Asynchronous Clear, Set and
|
|
// Clock Enable (posedge clk).
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FDCPE #(
|
|
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
|
|
) FDCPE_inst (
|
|
.Q(Q), // Data output
|
|
.C(C), // Clock input
|
|
.CE(CE), // Clock enable input
|
|
.CLR(CLR), // Asynchronous clear input
|
|
.D(D), // Data input
|
|
.PRE(PRE) // Asynchronous set input
|
|
);
|
|
|
|
// End of FDCPE_inst instantiation
|
|
</Template>
|
|
<Template label="Negedge D-FF w/ Async Clear, Set and CE (FDCPE_1)" treetype="template">
|
|
// FDCPE_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FDCPE_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FDCPE_1: Single Data Rate D Flip-Flop with Asynchronous Clear, Set and
|
|
// Clock Enable (negedge clock).
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FDCPE_1 #(
|
|
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
|
|
) FDCPE_1_inst (
|
|
.Q(Q), // Data output
|
|
.C(C), // Clock input
|
|
.CE(CE), // Clock enable input
|
|
.CLR(CLR), // Asynchronous clear input
|
|
.D(D), // Data input
|
|
.PRE(PRE) // Asynchronous set input
|
|
);
|
|
|
|
// End of FDCPE_1_inst instantiation
|
|
</Template>
|
|
<Template label="Posedge D-FF w/ Sync Clear, Set and CE (FDRSE)" treetype="template">
|
|
// FDRSE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FDCRS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FDRSE: Single Data Rate D Flip-Flop with Synchronous Clear, Set and
|
|
// Clock Enable (posedge clk).
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FDRSE #(
|
|
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
|
|
) FDRSE_inst (
|
|
.Q(Q), // Data output
|
|
.C(C), // Clock input
|
|
.CE(CE), // Clock enable input
|
|
.D(D), // Data input
|
|
.R(R), // Synchronous reset input
|
|
.S(S) // Synchronous set input
|
|
);
|
|
|
|
// End of FDRSE_inst instantiation
|
|
</Template>
|
|
<Template label="Negedge D-FF w/ Sync Clear, Set and CE (FDRSE_1)" treetype="template">
|
|
// FDRSE_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FDRSE_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FDRSE_1: Single Data Rate D Flip-Flop with Synchronous Clear, Set and
|
|
// Clock Enable (negedge clock).
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FDRSE_1 #(
|
|
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
|
|
) FDRSE_1_inst (
|
|
.Q(Q), // Data output
|
|
.C(C), // Clock input
|
|
.CE(CE), // Clock enable input
|
|
.D(D), // Data input
|
|
.R(R), // Synchronous reset input
|
|
.S(S) // Synchronous set input
|
|
);
|
|
// End of FDRSE_1_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Transparent Latch" treetype="folder">
|
|
<Template label="Latch with Async Reset, Set and Gate Enable (LDCPE)" treetype="template">
|
|
// LDCPE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LDCPE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LDCPE: Transparent latch with Asynchronous Reset, Preset and
|
|
// Gate Enable.
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LDCPE #(
|
|
.INIT(1'b0) // Initial value of latch (1'b0 or 1'b1)
|
|
) LDCPE_inst (
|
|
.Q(Q), // Data output
|
|
.CLR(CLR), // Asynchronous clear/reset input
|
|
.D(D), // Data input
|
|
.G(G), // Gate input
|
|
.GE(GE), // Gate enable input
|
|
.PRE(PRE) // Asynchronous preset/set input
|
|
);
|
|
|
|
// End of LDCPE_inst instantiation
|
|
</Template>
|
|
<Template label="Latch with Async Reset and Gate Enable (LDCE)" treetype="template">
|
|
// LDCE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LDCE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LDCE: Transparent latch with Asynchronous Reset and Gate Enable.
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LDCE #(
|
|
.INIT(1'b0) // Initial value of latch (1'b0 or 1'b1)
|
|
) LDCE_inst (
|
|
.Q(Q), // Data output
|
|
.CLR(CLR), // Asynchronous clear/reset input
|
|
.D(D), // Data input
|
|
.G(G), // Gate input
|
|
.GE(GE) // Gate enable input
|
|
);
|
|
|
|
// End of LDCE_inst instantiation
|
|
</Template>
|
|
<Template label="Latch with Async Set and Gate Enable (LDPE)" treetype="template">
|
|
// LDPE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LDPE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LDPE: Transparent latch with Asynchronous Preset and Gate Enable.
|
|
// Spartan-3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LDPE #(
|
|
.INIT(1'b0) // Initial value of latch (1'b0 or 1'b1)
|
|
) LDPE_inst (
|
|
.Q(Q), // Data output
|
|
.PRE(PRE), // Asynchronous preset/set input
|
|
.D(D), // Data input
|
|
.G(G), // Gate input
|
|
.GE(GE) // Gate enable input
|
|
);
|
|
|
|
// End of LDPE_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Spartan-3A" treetype="folder">
|
|
<SubFolder label="Slice/CLB Primitives" treetype="folder">
|
|
<SubFolder label="Carry-Chain" treetype="folder">
|
|
<Template label="MUXCY" treetype="template">
|
|
// MUXCY : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXCY_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs and
|
|
// : and outputs of this primitive should be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXCY: Carry-Chain MUX with general output
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXCY MUXCY_inst (
|
|
.O(O), // Carry output signal
|
|
.CI(CI), // Carry input signal
|
|
.DI(DI), // Data input signal
|
|
.S(S) // MUX select, tie to '1' or LUT4 out
|
|
);
|
|
|
|
// End of MUXCY_inst instantiation
|
|
</Template>
|
|
<Template label="MUXCY_L" treetype="template">
|
|
// MUXCY_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXCY_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXCY_L: Carry-Chain MUX with local output
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXCY_L MUXCY_L_inst (
|
|
.LO(LO), // Carry local output signal
|
|
.CI(CI), // Carry input signal
|
|
.DI(DI), // Data input signal
|
|
.S(S) // MUX select, tie to '1' or LUT4 out
|
|
);
|
|
|
|
// End of MUXCY_L_inst instantiation
|
|
</Template>
|
|
<Template label="MUXCY_D" treetype="template">
|
|
// MUXCY_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXCY_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXCY_D: Carry-Chain MUX with general and local outputs
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXCY_D MUXCY_D_inst (
|
|
.LO(LO), // Carry local output signal
|
|
.O(O), // Carry general output signal
|
|
.CI(CI), // Carry input signal
|
|
.DI(DI), // Data input signal
|
|
.S(S) // MUX select, tie to '1' or LUT4 out
|
|
);
|
|
|
|
// End of MUXCY_D_inst instantiation
|
|
</Template>
|
|
<Template label="XORCY" treetype="template">
|
|
// XORCY : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (XORCY_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// XORCY: Carry-Chain XOR-gate with general output
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
XORCY XORCY_inst (
|
|
.O(O), // XOR output signal
|
|
.CI(CI), // Carry input signal
|
|
.LI(LI) // LUT4 input signal
|
|
);
|
|
|
|
// End of XORCY_inst instantiation
|
|
</Template>
|
|
<Template label="XORCY_L" treetype="template">
|
|
// XORCY_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (XORCY_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// XORCY_L: Carry-Chain XOR-gate with local (direct-connect) output
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
XORCY_L XORCY_L_inst (
|
|
.LO(LO), // XOR local output signal
|
|
.CI(CI), // Carry input signal
|
|
.LI(LI) // LUT4 input signal
|
|
);
|
|
|
|
// End of XORCY_L_inst instantiation
|
|
</Template>
|
|
<Template label="XORCY_D" treetype="template">
|
|
// XORCY_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (XORCY_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// XORCY_D: Carry-Chain XOR-gate with local and general outputs
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
XORCY_D XORCY_D_inst (
|
|
.LO(LO), // XOR local output signal
|
|
.O(O), // XOR general output signal
|
|
.CI(CI), // Carry input signal
|
|
.LI(LI) // LUT4 input signal
|
|
);
|
|
|
|
// End of XORCY_D_inst instantiation
|
|
</Template>
|
|
<Template label="MULT_AND" treetype="template">
|
|
// MULT_AND : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MULT_AND_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MULT_AND: 2-input AND gate connected to Carry chain
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MULT_AND MULT_AND_inst (
|
|
.LO(LO), // MULT_AND output (connect to MUXCY DI)
|
|
.I0(I0), // MULT_AND data[0] input
|
|
.I1(I1) // MULT_AND data[1] input
|
|
);
|
|
|
|
// End of MULT_AND_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="MUXFx" treetype="folder">
|
|
<Template label="MUXF5" treetype="template">
|
|
// MUXF5 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF5_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF5: Slice MUX to tie two LUT4's together with general output
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF5 MUXF5_inst (
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie directly to the output of LUT4)
|
|
.I1(I1), // Input (tie directoy to the output of LUT4)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF5_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF5_L" treetype="template">
|
|
// MUXF5_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF5_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF5_L: Slice MUX to tie two LUT4's together with local output
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF5_L MUXF5_L_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.I0(I0), // Input (tie directly to the output of LUT4)
|
|
.I1(I1), // Input (tie directoy to the output of LUT4)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF5_L_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF5_D" treetype="template">
|
|
// MUXF5_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF5_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF5_D: Slice MUX to tie two LUT4's together with general and local outputs
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF5_D MUXF5_D_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie directly to the output of LUT4)
|
|
.I1(I1), // Input (tie directoy to the output of LUT4)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF5_D_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF6" treetype="template">
|
|
// MUXF6 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF6_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF6: CLB MUX to tie two MUXF5's together with general output
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF6 MUXF6_inst (
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie to MUXF5 LO out)
|
|
.I1(I1), // Input (tie to MUXF5 LO out)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF6_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF6_L" treetype="template">
|
|
// MUXF6_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF6_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF6_L: CLB MUX to tie two MUXF5's together with local output
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF6_L MUXF6_L_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.I0(I0), // Input (tie to MUXF5 LO out)
|
|
.I1(I1), // Input (tie to MUXF5 LO out)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF6_L_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF6_D" treetype="template">
|
|
// MUXF6_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF6_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF6_D: CLB MUX to tie two MUXF5's together with general and local outputs
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF6_D MUXF6_D_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie to MUXF5 LO out)
|
|
.I1(I1), // Input (tie to MUXF5 LO out)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF6_D_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF7" treetype="template">
|
|
// MUXF7 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF7_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF7: CLB MUX to tie two MUXF6's together with general output
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF7 MUXF7_inst (
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie to MUXF6 LO out or LUT6 O6 pin)
|
|
.I1(I1), // Input (tie to MUXF6 LO out or LUT6 O6 pin)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF7_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF7_L" treetype="template">
|
|
// MUXF7_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF7_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF7_L: CLB MUX to tie two MUXF6's together with local output
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF7_L MUXF7_L_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.I0(I0), // Input (tie to MUXF6 LO out or LUT6 O6 pin)
|
|
.I1(I1), // Input (tie to MUXF6 LO out or LUT6 O6 pin)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF7_L_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF7_D" treetype="template">
|
|
// MUXF7_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF7_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF7_D: CLB MUX to tie two MUXF6's together with general and local outputs
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF7_D MUXF7_D_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie to MUXF6 LO out or LUT6 O6 pin)
|
|
.I1(I1), // Input (tie to MUXF6 LO out or LUT6 O6 pin)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF7_D_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF8" treetype="template">
|
|
// MUXF8 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF8_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF8: CLB MUX to tie two MUXF7's together with general output
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF8 MUXF8_inst (
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie to MUXF7 LO out)
|
|
.I1(I1), // Input (tie to MUXF7 LO out)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF8_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF8_L" treetype="template">
|
|
// MUXF8_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF8_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF8_L: CLB MUX to tie two MUXF7's together with local output
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF8_L MUXF8_L_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.I0(I0), // Input (tie to MUXF7 LO out)
|
|
.I1(I1), // Input (tie to MUXF7 LO out)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF8_L_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF8_D" treetype="template">
|
|
// MUXF8_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF8_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF8_D: CLB MUX to tie two MUXF7's together with general and local outputs
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF8_D MUXF8_D_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie to MUXF7 LO out)
|
|
.I1(I1), // Input (tie to MUXF7 LO out)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF8_D_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="LUTs" treetype="folder">
|
|
<SubFolder label="Info" treetype="folder">
|
|
<Template label="Info (LUT INIT)" treetype="template">
|
|
// The INIT parameter for the FPGA LUT primitive is what gives the LUT its
|
|
// logical value. By default this value is zero thus driving the output to a
|
|
// zero regardless of the input values (acting as a ground) however in most
|
|
// cases an new INIT value must be determined in order to specify the logic
|
|
// function for the LUT primitive. There are a few methods in which the LUT
|
|
// value can be determined and two of those methods will be discussed here.
|
|
//
|
|
// The Truth Table Method
|
|
// ----------------------
|
|
//
|
|
// A common method to determine the desired INIT value for a LUT is using a
|
|
// truth table. To do so, simply create a binary truth table of all possible
|
|
// inputs, specify the desired logic value of the output and then create the
|
|
// INIT string from those output values. An example is shown below:
|
|
//
|
|
// Example of determining an XOR INIT equation for a LUT4:
|
|
//
|
|
// _________________
|
|
// | I3 I2 I1 I0 | O |
|
|
// |-----------------|
|
|
// | 0 0 0 0 | 0 |\
|
|
// | 0 0 0 1 | 1 | \ = 4'b0110 = 4'h6 ---------------+
|
|
// | 0 0 1 0 | 1 | / |
|
|
// | 0 0 1 1 | 0 |/ |
|
|
// |-------------|---| |
|
|
// | 0 1 0 0 | 1 |\ |
|
|
// | 0 1 0 1 | 0 | \ = 4'b1001 = 4'h9 |
|
|
// | 0 1 1 0 | 0 | / |
|
|
// | 0 1 1 1 | 1 |/ |
|
|
// |-------------|---| INIT = 16'h6996
|
|
// | 1 0 0 0 | 1 |\ |
|
|
// | 1 0 0 1 | 0 | \ = 4'b0110 = 4'h9 |
|
|
// | 1 0 1 0 | 0 | / |
|
|
// | 1 0 1 1 | 1 |/ |
|
|
// |-------------|---| |
|
|
// | 1 1 0 0 | 0 |\ |
|
|
// | 1 1 0 1 | 1 | \ = 4'b1001 = 4'h6 ------------+
|
|
// | 1 1 1 0 | 1 | /
|
|
// | 1 1 1 1 | 0 |/
|
|
// -------------------
|
|
//
|
|
// Example of determining a 3-input AND gate:
|
|
//
|
|
// ______________
|
|
// | I2 I1 I0 | O |
|
|
// |--------------|
|
|
// | 0 0 0 | 0 |\
|
|
// | 0 0 1 | 0 | \ = 4'b0000 = 4'h0 --------------+
|
|
// | 0 1 0 | 0 | / |
|
|
// | 0 1 1 | 0 |/ |
|
|
// |----------|---| INIT = 8'h80
|
|
// | 1 0 0 | 0 |\ |
|
|
// | 1 0 1 | 0 | \ = 4'b1000 = 4'h8 -------------+
|
|
// | 1 1 0 | 0 | /
|
|
// | 1 1 1 | 1 |/
|
|
// ----------------
|
|
//
|
|
// The Equation Method
|
|
// -------------------
|
|
//
|
|
// Another method to determine the LUT value is to define parameters for each
|
|
// input to the LUT that correspond to their listed truth value and use those to
|
|
// build the logic equation you are after. This method is easier to understand
|
|
// once you have grasped the concept and more self-documenting that the above
|
|
// method however does require the code to first specify the appropriate
|
|
// parameters. See the example below.
|
|
//
|
|
// Example of specifying the equation (A and B) or (C and D) for a LUT4:
|
|
//
|
|
// The forllowing parameters are defined to allow for
|
|
// equation-based INIT specification.
|
|
parameter I0 = 16'haaaa;
|
|
parameter I1 = 16'hcccc;
|
|
parameter I2 = 16'hf0f0;
|
|
parameter I3 = 16'hff00;
|
|
|
|
// LUT4: 4-input Look-Up Table with general output
|
|
// for use with all FPGAs.
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT4 #(
|
|
.INIT((I0&I1)|(I2&I3)) // Specify LUT Contents
|
|
) LUT4_inst (
|
|
.O(O_LUT), // LUT general output
|
|
.I0(A), // LUT input
|
|
.I1(B), // LUT input
|
|
.I2(C), // LUT input
|
|
.I3(D) // LUT input
|
|
);
|
|
|
|
// End of LUT4_inst instantiation
|
|
|
|
// With the parameters specifying all possible cases for the truth table, a
|
|
// Verilog equation can be written to determine the end INIT value.
|
|
</Template>
|
|
<SubFolder label="INIT Parameters" treetype="folder">
|
|
<Template label="LUT1" treetype="template">
|
|
// The forllowing parameter is defined to allow for
|
|
// equation-based INIT specification for a LUT1.
|
|
parameter I0 = 2'b10;
|
|
</Template>
|
|
<Template label="LUT2" treetype="template">
|
|
// The forllowing parameters are defined to allow for
|
|
// equation-based INIT specification for a LUT2.
|
|
parameter I0 = 4'ha;
|
|
parameter I1 = 4'hc;
|
|
</Template>
|
|
<Template label="LUT3" treetype="template">
|
|
// The forllowing parameters are defined to allow for
|
|
// equation-based INIT specification for a LUT3.
|
|
parameter I0 = 8'haa;
|
|
parameter I1 = 8'hcc;
|
|
parameter I2 = 8'hf0;
|
|
</Template>
|
|
<Template label="LUT4" treetype="template">
|
|
// The forllowing parameters are defined to allow for
|
|
// equation-based INIT specification for a LUT4.
|
|
parameter I0 = 16'haaaa;
|
|
parameter I1 = 16'hcccc;
|
|
parameter I2 = 16'hf0f0;
|
|
parameter I3 = 16'hff00;
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="INIT Truth Tables" treetype="folder">
|
|
<Template label="LUT1" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT1
|
|
// ________
|
|
// | I0 | O |
|
|
// |--------|
|
|
// | 0 | ? |\
|
|
// | 1 | ? |/ = 2'b??
|
|
// ----------
|
|
</Template>
|
|
<Template label="LUT2" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT2
|
|
// ______________
|
|
// | I2 I1 I0 | O |
|
|
// |--------------|
|
|
// | 0 0 0 | ? |\
|
|
// | 0 0 1 | ? | \ = INIT = 4'b???? = 4'h?
|
|
// | 0 1 0 | ? | /
|
|
// | 0 1 1 | ? |/
|
|
// ---------- ---
|
|
</Template>
|
|
<Template label="LUT3" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT3
|
|
// ______________
|
|
// | I2 I1 I0 | O |
|
|
// |--------------|
|
|
// | 0 0 0 | ? |\
|
|
// | 0 0 1 | ? | \ = 4'b???? = 4'h? --------------+
|
|
// | 0 1 0 | ? | / |
|
|
// | 0 1 1 | ? |/ |
|
|
// |----------|---| INIT = 8'h??
|
|
// | 1 0 0 | ? |\ |
|
|
// | 1 0 1 | ? | \ = 4'b???? = 4'h? -------------+
|
|
// | 1 1 0 | ? | /
|
|
// | 1 1 1 | ? |/
|
|
// ----------------
|
|
</Template>
|
|
<Template label="LUT4" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT4
|
|
// _________________
|
|
// | I3 I2 I1 I0 | O |
|
|
// |-----------------|
|
|
// | 0 0 0 0 | ? |\
|
|
// | 0 0 0 1 | ? | \ = 4'b???? = 4'h? ---------------+
|
|
// | 0 0 1 0 | ? | / |
|
|
// | 0 0 1 1 | ? |/ |
|
|
// |-------------|---| |
|
|
// | 0 1 0 0 | ? |\ |
|
|
// | 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 1 0 | ? | / |
|
|
// | 0 1 1 1 | ? |/ |
|
|
// |-------------|---| INIT = 16'h????
|
|
// | 1 0 0 0 | ? |\ |
|
|
// | 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 1 0 | ? | / |
|
|
// | 1 0 1 1 | ? |/ |
|
|
// |-------------|---| |
|
|
// | 1 1 0 0 | ? |\ |
|
|
// | 1 1 0 1 | ? | \ = 4'b???? = 4'h? ------------+
|
|
// | 1 1 1 0 | ? | /
|
|
// | 1 1 1 1 | ? |/
|
|
// -------------------
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<Template label="LUT4" treetype="template">
|
|
// LUT4 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT4_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT4: 4-input Look-Up Table with general output
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT4 #(
|
|
.INIT(16'h0000) // Specify LUT Contents
|
|
) LUT4_inst (
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3) // LUT input
|
|
);
|
|
|
|
// End of LUT4_inst instantiation
|
|
</Template>
|
|
<Template label="LUT4_L" treetype="template">
|
|
// LUT4_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT4_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT4_L: 4-input Look-Up Table with local output
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT4_L #(
|
|
.INIT(16'h0000) // Specify LUT Contents
|
|
) LUT4_L_inst (
|
|
.LO(LO), // LUT local output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3) // LUT input
|
|
);
|
|
|
|
// End of LUT4_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT4_D" treetype="template">
|
|
// LUT4_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT4_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT4_D: 4-input Look-Up Table with general and local outputs
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT4_D #(
|
|
.INIT(16'h0000) // Specify LUT Contents
|
|
) LUT4_D_inst (
|
|
.LO(LO), // LUT local output
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3) // LUT input
|
|
);
|
|
|
|
// End of LUT4_D_inst instantiation
|
|
</Template>
|
|
<Template label="LUT3" treetype="template">
|
|
// LUT3 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT3_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT3: 3-input Look-Up Table with general output
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT3 #(
|
|
.INIT(8'h00) // Specify LUT Contents
|
|
) LUT3_inst (
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2) // LUT input
|
|
);
|
|
|
|
// End of LUT3_inst instantiation
|
|
</Template>
|
|
<Template label="LUT3_L" treetype="template">
|
|
// LUT3_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT3_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT3_L: 3-input Look-Up Table with local output
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT3_L #(
|
|
.INIT(8'h00) // Specify LUT Contents
|
|
) LUT3_L_inst (
|
|
.LO(LO), // LUT local output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2) // LUT input
|
|
);
|
|
|
|
// End of LUT3_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT3_D" treetype="template">
|
|
// LUT3_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT3_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT3_D: 3-input Look-Up Table with general and local outputs
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT3_D #(
|
|
.INIT(8'h00) // Specify LUT Contents
|
|
) LUT3_D_inst (
|
|
.LO(LO), // LUT local output
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2) // LUT input
|
|
);
|
|
|
|
// End of LUT3_D_inst instantiation
|
|
</Template>
|
|
<Template label="LUT2" treetype="template">
|
|
// LUT2 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT2: 2-input Look-Up Table with general output
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT2 #(
|
|
.INIT(4'h0) // Specify LUT Contents
|
|
) LUT2_inst (
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1) // LUT input
|
|
);
|
|
|
|
// End of LUT2_inst instantiation
|
|
</Template>
|
|
<Template label="LUT2_L" treetype="template">
|
|
// LUT2_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT2_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT2_L: 2-input Look-Up Table with local output
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT2_L #(
|
|
.INIT(4'h0) // Specify LUT Contents
|
|
) LUT2_L_inst (
|
|
.LO(LO), // LUT local output
|
|
.I0(I0), // LUT input
|
|
.I1(I1) // LUT input
|
|
);
|
|
|
|
// End of LUT2_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT2_D" treetype="template">
|
|
// LUT2_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT2_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT2_D: 2-input Look-Up Table with general and local outputs
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT2_D #(
|
|
.INIT(4'h0) // Specify LUT Contents
|
|
) LUT2_D_inst (
|
|
.LO(LO), // LUT local output
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1) // LUT input
|
|
);
|
|
|
|
// End of LUT2_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT1" treetype="template">
|
|
// LUT1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT1: 1-input Look-Up Table with general output
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT1 #(
|
|
.INIT(2'b00) // Specify LUT Contents
|
|
) LUT1_inst (
|
|
.O(O), // LUT general output
|
|
.I0(I0) // LUT input
|
|
);
|
|
|
|
// End of LUT1_inst instantiation
|
|
</Template>
|
|
<Template label="LUT1_L" treetype="template">
|
|
// LUT1_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT1_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT1_L: 1-input Look-Up Table with local output
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT1_L #(
|
|
.INIT(2'b00) // Specify LUT Contents
|
|
) LUT1_L_inst (
|
|
.LO(LO), // LUT local output
|
|
.I0(I0) // LUT input
|
|
);
|
|
|
|
// End of LUT1_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT1_D" treetype="template">
|
|
// LUT1_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT1_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT1_D: 1-input Look-Up Table with general and local outputs
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT1_D #(
|
|
.INIT(2'b00) // Specify LUT Contents
|
|
) LUT1_D_inst (
|
|
.LO(LO), // LUT local output
|
|
.O(O), // LUT general output
|
|
.I0(I0) // LUT input
|
|
);
|
|
|
|
// End of LUT1_D_inst instantiation
|
|
</Template>
|
|
<Template label="LUT Local Connect Buffer (BUFCF)" treetype="template">
|
|
// BUFCF : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFCF_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFCF: Fast connect buffer used to connect the outputs of the LUTs
|
|
// and some dedicated logic directly to the input of another LUT.
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFCF BUFCF_inst (
|
|
.O(O), // Connect to the output of a LUT
|
|
.I(I) // Connect to the input of a LUT
|
|
);
|
|
|
|
// End of BUFCF_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Shift Register LUT" treetype="folder">
|
|
<SubFolder label="Non-cascadable" treetype="folder">
|
|
<Template label="16-bit posedge SR (SRL16)" treetype="template">
|
|
// SRL16 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SRL16_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SRL16: 16-bit shift register LUT operating on posedge of clock
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SRL16 #(
|
|
.INIT(16'h0000) // Initial Value of Shift Register
|
|
) SRL16_inst (
|
|
.Q(Q), // SRL data output
|
|
.A0(A0), // Select[0] input
|
|
.A1(A1), // Select[1] input
|
|
.A2(A2), // Select[2] input
|
|
.A3(A3), // Select[3] input
|
|
.CLK(CLK), // Clock input
|
|
.D(D) // SRL data input
|
|
);
|
|
|
|
// End of SRL16_inst instantiation
|
|
</Template>
|
|
<Template label="16-bit negedge SR (SRL16_1)" treetype="template">
|
|
// SRL16_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SRL16_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SRL16_1: 16-bit shift register LUT operating on negedge of clock
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SRL16_1 #(
|
|
.INIT(16'h0000) // Initial Value of Shift Register
|
|
) SRL16_1_inst (
|
|
.Q(Q), // SRL data output
|
|
.A0(A0), // Select[0] input
|
|
.A1(A1), // Select[1] input
|
|
.A2(A2), // Select[2] input
|
|
.A3(A3), // Select[3] input
|
|
.CLK(CLK), // Clock input
|
|
.D(D) // SRL data input
|
|
);
|
|
|
|
// End of SRL16_1_inst instantiation
|
|
</Template>
|
|
<Template label="16-bit w/ CE posedge SR (SRL16E)" treetype="template">
|
|
// SRL16E : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SRL16E_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SRL16E: 16-bit shift register LUT with clock enable operating on posedge of clock
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SRL16E #(
|
|
.INIT(16'h0000) // Initial Value of Shift Register
|
|
) SRL16E_inst (
|
|
.Q(Q), // SRL data output
|
|
.A0(A0), // Select[0] input
|
|
.A1(A1), // Select[1] input
|
|
.A2(A2), // Select[2] input
|
|
.A3(A3), // Select[3] input
|
|
.CE(CE), // Clock enable input
|
|
.CLK(CLK), // Clock input
|
|
.D(D) // SRL data input
|
|
);
|
|
|
|
// End of SRL16E_inst instantiation
|
|
</Template>
|
|
<Template label="16-bit w/ CE negedge SR (SRL16E_1)" treetype="template">
|
|
// SRL16E_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SRL16E_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SRL16E_1: 16-bit shift register LUT with clock enable operating on negedge of clock
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SRL16E_1 #(
|
|
.INIT(16'h0000) // Initial Value of Shift Register
|
|
) SRL16E_1_inst (
|
|
.Q(Q), // SRL data output
|
|
.A0(A0), // Select[0] input
|
|
.A1(A1), // Select[1] input
|
|
.A2(A2), // Select[2] input
|
|
.A3(A3), // Select[3] input
|
|
.CE(CE), // Clock enable input
|
|
.CLK(CLK), // Clock input
|
|
.D(D) // SRL data input
|
|
);
|
|
|
|
// End of SRL16E_1_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Cascable" treetype="folder">
|
|
<Template label="16-bit posedge SR (SRLC16)" treetype="template">
|
|
// SRLC16 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SRLC16_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SRLC16: 16-bit cascadable shift register LUT operating on posedge of clock
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SRLC16 #(
|
|
.INIT(16'h0000) // Initial Value of Shift Register
|
|
) SRLC16_inst (
|
|
.Q(Q), // SRL data output
|
|
.Q15(Q15), // Carry output (connect to next SRL)
|
|
.A0(A0), // Select[0] input
|
|
.A1(A1), // Select[1] input
|
|
.A2(A2), // Select[2] input
|
|
.A3(A3), // Select[3] input
|
|
.CLK(CLK), // Clock input
|
|
.D(D) // SRL data input
|
|
);
|
|
|
|
// End of SRLC16_inst instantiation
|
|
</Template>
|
|
<Template label="16-bit negedge SR (SRLC16_1)" treetype="template">
|
|
// SRLC16_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SRLC16_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SRLC16_1: 16-bit cascadable shift register LUT operating on negedge of clock
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SRLC16_1 #(
|
|
.INIT(16'h0000) // Initial Value of Shift Register
|
|
) SRLC16_1_inst (
|
|
.Q(Q), // SRL data output
|
|
.Q15(Q15), // Carry output (connect to next SRL)
|
|
.A0(A0), // Select[0] input
|
|
.A1(A1), // Select[1] input
|
|
.A2(A2), // Select[2] input
|
|
.A3(A3), // Select[3] input
|
|
.CLK(CLK), // Clock input
|
|
.D(D) // SRL data input
|
|
);
|
|
|
|
// End of SRLC16_1_inst instantiation
|
|
</Template>
|
|
<Template label="16-bit w/ CE posedge SR (SRLC16E)" treetype="template">
|
|
// SRLC16E : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SRL16E_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SRLC16E: 16-bit cascadable shift register LUT with clock enable operating on posedge of clock
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SRLC16E #(
|
|
.INIT(16'h0000) // Initial Value of Shift Register
|
|
) SRLC16E_inst (
|
|
.Q(Q), // SRL data output
|
|
.Q15(Q15), // Carry output (connect to next SRL)
|
|
.A0(A0), // Select[0] input
|
|
.A1(A1), // Select[1] input
|
|
.A2(A2), // Select[2] input
|
|
.A3(A3), // Select[3] input
|
|
.CE(CE), // Clock enable input
|
|
.CLK(CLK), // Clock input
|
|
.D(D) // SRL data input
|
|
);
|
|
|
|
// End of SRLC16E_inst instantiation
|
|
</Template>
|
|
<Template label="16-bit w/ CE negedge SR (SRLC16E_1)" treetype="template">
|
|
// SRLC16E_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SRLC16E_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SRLC16E_1: 16-bit shift register LUT with clock enable operating on negedge of clock
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SRLC16E_1 #(
|
|
.INIT(16'h0000) // Initial Value of Shift Register
|
|
) SRLC16E_1_inst (
|
|
.Q(Q), // SRL data output
|
|
.Q15(Q15), // Carry output (connect to next SRL)
|
|
.A0(A0), // Select[0] input
|
|
.A1(A1), // Select[1] input
|
|
.A2(A2), // Select[2] input
|
|
.A3(A3), // Select[3] input
|
|
.CE(CE), // Clock enable input
|
|
.CLK(CLK), // Clock input
|
|
.D(D) // SRL data input
|
|
);
|
|
|
|
// End of SRLC16E_1_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Clock Components" treetype="folder">
|
|
<Template label="Digital Clock Manager (DCM_SP)" treetype="template">
|
|
// DCM_SP : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (DCM_SP_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Unused inputs
|
|
// : and outputs may be removed or commented out.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// DCM_SP: Digital Clock Manager Circuit
|
|
// Spartan-3A
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
DCM_SP #(
|
|
.CLKDV_DIVIDE(2.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
|
|
// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
|
|
.CLKFX_DIVIDE(1), // Can be any integer from 1 to 32
|
|
.CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32
|
|
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
|
|
.CLKIN_PERIOD(0.0), // Specify period of input clock
|
|
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
|
|
.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X
|
|
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
|
|
// an integer from 0 to 15
|
|
.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
|
|
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
|
|
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
|
|
.STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
|
|
) DCM_SP_inst (
|
|
.CLK0(CLK0), // 0 degree DCM CLK output
|
|
.CLK180(CLK180), // 180 degree DCM CLK output
|
|
.CLK270(CLK270), // 270 degree DCM CLK output
|
|
.CLK2X(CLK2X), // 2X DCM CLK output
|
|
.CLK2X180(CLK2X180), // 2X, 180 degree DCM CLK out
|
|
.CLK90(CLK90), // 90 degree DCM CLK output
|
|
.CLKDV(CLKDV), // Divided DCM CLK out (CLKDV_DIVIDE)
|
|
.CLKFX(CLKFX), // DCM CLK synthesis out (M/D)
|
|
.CLKFX180(CLKFX180), // 180 degree CLK synthesis out
|
|
.LOCKED(LOCKED), // DCM LOCK status output
|
|
.PSDONE(PSDONE), // Dynamic phase adjust done output
|
|
.STATUS(STATUS), // 8-bit DCM status bits output
|
|
.CLKFB(CLKFB), // DCM clock feedback
|
|
.CLKIN(CLKIN), // Clock input (from IBUFG, BUFG or DCM)
|
|
.PSCLK(PSCLK), // Dynamic phase adjust clock input
|
|
.PSEN(PSEN), // Dynamic phase adjust enable input
|
|
.PSINCDEC(PSINCDEC), // Dynamic phase adjust increment/decrement
|
|
.RST(RST) // DCM asynchronous reset input
|
|
);
|
|
|
|
// End of DCM_SP_inst instantiation
|
|
</Template>
|
|
<SubFolder label="Clock Buffers" treetype="folder">
|
|
<Template label="Global Clock Buffer (BUFG)" treetype="template">
|
|
// BUFG : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFG_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFG: Global Clock Buffer (source by an internal signal)
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFG BUFG_inst (
|
|
.O(O), // Clock buffer output
|
|
.I(I) // Clock buffer input
|
|
);
|
|
|
|
// End of BUFG_inst instantiation
|
|
</Template>
|
|
<Template label="Single-ended input Global Clock Buffer (IBUFG)" treetype="template">
|
|
// IBUFG : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFG_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFG: Global Clock Buffer (sourced by an external pin)
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFG #(
|
|
.IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for
|
|
// the buffer: "0"-"16" (Spartan-3A)
|
|
.IOSTANDARD("DEFAULT")
|
|
) IBUFG_inst (
|
|
.O(O), // Clock buffer output
|
|
.I(I) // Clock buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUFG_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Input Global Clock Buffer (IBUFGDS)" treetype="template">
|
|
// IBUFGDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFGDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFGDS: Differential Global Clock Buffer (sourced by an external pin)
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFGDS #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination
|
|
.IOSTANDARD("DEFAULT"), // Specifies the I/O standard for this buffer
|
|
.IBUF_DELAY_VALUE("0") // Specify the amount of added input delay for
|
|
// the buffer: "0"-"16" (Spartan-3A)
|
|
) IBUFGDS_inst (
|
|
.O(O), // Clock buffer output
|
|
.I(I), // Diff_p clock buffer input
|
|
.IB(IB) // Diff_n clock buffer input
|
|
);
|
|
|
|
// End of IBUFGDS_inst instantiation
|
|
</Template>
|
|
<Template label="Global Clock Buffer w/ Enable (BUFGCE)" treetype="template">
|
|
// BUFGCE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFGCE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFGCE: Global Clock Buffer with Clock Enable (active high)
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFGCE BUFGCE_inst (
|
|
.O(O), // Clock buffer output
|
|
.CE(CE), // Clock enable input
|
|
.I(I) // Clock buffer input
|
|
);
|
|
|
|
// End of BUFGCE_inst instantiation
|
|
</Template>
|
|
<Template label="Global Clock Buffer w/ Enable (BUFGCE_1)" treetype="template">
|
|
// BUFGCE_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFGCE_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFGCE_1: Global Clock Buffer with Clock Enable (active low)
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFGCE_1 BUFGCE_1_inst (
|
|
.O(O), // Clock buffer output
|
|
.CE(CE), // Clock enable input
|
|
.I(I) // Clock buffer input
|
|
);
|
|
|
|
// End of BUFGCE_1_inst instantiation
|
|
// End of BUFIO_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Clock MUX" treetype="folder">
|
|
<Template label="Global Clock Buffer MUX (BUFGMUX)" treetype="template">
|
|
// BUFGMUX : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFGMUX_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFGMUX: Global Clock Buffer 2-to-1 MUX
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFGMUX BUFGMUX_inst (
|
|
.O(O), // Clock MUX output
|
|
.I0(I0), // Clock0 input
|
|
.I1(I1), // Clock1 input
|
|
.S(S) // Clock select input
|
|
);
|
|
|
|
// End of BUFGMUX_inst instantiation
|
|
</Template>
|
|
<Template label="Global Clock Buffer MUX (BUFGMUX_1)" treetype="template">
|
|
// BUFGMUX_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFGMUX_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFGMUX_1: Global Clock Buffer 2-to-1 MUX (inverted select)
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFGMUX_1 BUFGMUX_1_inst (
|
|
.O(O), // Clock MUX output
|
|
.I0(I0), // Clock0 input
|
|
.I1(I1), // Clock1 input
|
|
.S(S) // Clock select input
|
|
);
|
|
|
|
// End of BUFGMUX_1_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="RAM/ROM" treetype="folder">
|
|
<SubFolder label="Distributed ROM" treetype="folder">
|
|
<Template label="16 X 1 (ROM16X1)" treetype="template">
|
|
// ROM16X1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ROM16X1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ROM16X1: 16 x 1 Asynchronous Distributed (LUT) ROM
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ROM16X1 #(
|
|
.INIT(16'h0000) // Contents of ROM
|
|
) ROM16X1_inst (
|
|
.O(O), // ROM output
|
|
.A0(A0), // ROM address[0]
|
|
.A1(A1), // ROM address[1]
|
|
.A2(A2), // ROM address[2]
|
|
.A3(A3) // ROM address[3]
|
|
);
|
|
|
|
// End of ROM16X1_inst instantiation
|
|
</Template>
|
|
<Template label="32 X 1 (ROM32X1)" treetype="template">
|
|
// ROM32X1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ROM32X1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ROM32X1: 32 x 1 Asynchronous Distributed (LUT) ROM
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ROM32X1 #(
|
|
.INIT(32'h00000000) // Contents of ROM
|
|
) ROM32X1_inst (
|
|
.O(O), // ROM output
|
|
.A0(A0), // ROM address[0]
|
|
.A1(A1), // ROM address[1]
|
|
.A2(A2), // ROM address[2]
|
|
.A3(A3), // ROM address[3]
|
|
.A4(A4) // ROM address[4]
|
|
);
|
|
|
|
// End of ROM32X1_inst instantiation
|
|
</Template>
|
|
<Template label="64 X 1 (ROM64X1)" treetype="template">
|
|
// ROM64X1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ROM64X1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ROM64X1: 64 x 1 Asynchronous Distributed (LUT) ROM
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ROM64X1 #(
|
|
.INIT(64'h0000000000000000) // Contents of ROM
|
|
) ROM64X1_inst (
|
|
.O(O), // ROM output
|
|
.A0(A0), // ROM address[0]
|
|
.A1(A1), // ROM address[1]
|
|
.A2(A2), // ROM address[2]
|
|
.A3(A3), // ROM address[3]
|
|
.A4(A4), // ROM address[4]
|
|
.A5(A5) // ROM address[5]
|
|
);
|
|
|
|
// End of ROM64X1_inst instantiation
|
|
</Template>
|
|
<Template label="128 X 1 (ROM128X1)" treetype="template">
|
|
// ROM128X1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ROM128X1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ROM128X1: 128 x 1 Asynchronous Distributed (LUT) ROM
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ROM128X1 #(
|
|
.INIT(128'h00000000000000000000000000000000) // Contents of ROM
|
|
) ROM128X1_inst (
|
|
.O(O), // ROM output
|
|
.A0(A0), // ROM address[0]
|
|
.A1(A1), // ROM address[1]
|
|
.A2(A2), // ROM address[2]
|
|
.A3(A3), // ROM address[3]
|
|
.A4(A4), // ROM address[4]
|
|
.A5(A5), // ROM address[5]
|
|
.A6(A6) // ROM address[6]
|
|
);
|
|
|
|
// End of ROM128X1_inst instantiation
|
|
</Template>
|
|
<Template label="256 X 1 (ROM256X1)" treetype="template">
|
|
// ROM256X1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ROM256X1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ROM256X1: 256 x 1 Asynchronous Distributed (LUT) ROM
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ROM256X1 #(
|
|
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000) // Contents of ROM
|
|
) ROM256X1_inst (
|
|
.O(O), // ROM output
|
|
.A0(A0), // ROM address[0]
|
|
.A1(A1), // ROM address[1]
|
|
.A2(A2), // ROM address[2]
|
|
.A3(A3), // ROM address[3]
|
|
.A4(A4), // ROM address[4]
|
|
.A5(A5), // ROM address[5]
|
|
.A6(A6), // ROM address[6]
|
|
.A7(A7) // ROM address[7]
|
|
);
|
|
|
|
// End of ROM256X1_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Distributed RAM" treetype="folder">
|
|
<SubFolder label="Single-Port" treetype="folder">
|
|
<SubFolder label="16 Deep (4-bit address)" treetype="folder">
|
|
<Template label="16 x 1 posedge write (RAM16X1S)" treetype="template">
|
|
// RAM16X1S : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM16X1S_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM16X1S: 16 x 1 posedge write distributed (LUT) RAM
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM16X1S #(
|
|
.INIT(16'h0000) // Initial contents of RAM
|
|
) RAM16X1S_inst (
|
|
.O(O), // RAM output
|
|
.A0(A0), // RAM address[0] input
|
|
.A1(A1), // RAM address[1] input
|
|
.A2(A2), // RAM address[2] input
|
|
.A3(A3), // RAM address[3] input
|
|
.D(D), // RAM data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM16X1S_inst instantiation
|
|
</Template>
|
|
<Template label="16 x 1 negedge write (RAM16X1S_1)" treetype="template">
|
|
// RAM16X1S_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM16X1S_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM16X1S_1: 16 x 1 negedge write distributed (LUT) RAM
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM16X1S_1 #(
|
|
.INIT(16'h0000) // Initial contents of RAM
|
|
) RAM16X1S_1_inst (
|
|
.O(O), // RAM output
|
|
.A0(A0), // RAM address[0] input
|
|
.A1(A1), // RAM address[1] input
|
|
.A2(A2), // RAM address[2] input
|
|
.A3(A3), // RAM address[3] input
|
|
.D(D), // RAM data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM16X1S_1_inst instantiation
|
|
</Template>
|
|
<Template label="16 x 2 posedge write (RAM16X2S)" treetype="template">
|
|
// RAM16X2S : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM16X2S_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM16X2S: 16 x 2 posedge write distributed (LUT) RAM
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM16X2S #(
|
|
.INIT_00(16'h0000), // Initial contents of bit 0 of RAM
|
|
.INIT_01(16'h0000) // Initial contents of bit 1 of RAM
|
|
) RAM16X2S_inst (
|
|
.O0(O0), // RAM data[0] output
|
|
.O1(O1), // RAM data[1] output
|
|
.A0(A0), // RAM address[0] input
|
|
.A1(A1), // RAM address[1] input
|
|
.A2(A2), // RAM address[2] input
|
|
.A3(A3), // RAM address[3] input
|
|
.D0(D0), // RAM data[0] input
|
|
.D1(D1), // RAM data[1] input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM16X2S_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="32 Deep (5-bit address)" treetype="folder">
|
|
<Template label="32 x 1 posedge write (RAM32X1S)" treetype="template">
|
|
// RAM32X1S : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM32X1S_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM32X1S: 32 x 1 posedge write distributed (LUT) RAM
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM32X1S #(
|
|
.INIT(32'h00000000) // Initial contents of RAM
|
|
) RAM32X1S_inst (
|
|
.O(O), // RAM output
|
|
.A0(A0), // RAM address[0] input
|
|
.A1(A1), // RAM address[1] input
|
|
.A2(A2), // RAM address[2] input
|
|
.A3(A3), // RAM address[3] input
|
|
.A4(A4), // RAM address[4] input
|
|
.D(D), // RAM data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM32X1S_inst instantiation
|
|
</Template>
|
|
<Template label="32 x 1 negedge write (RAM32X1S_1)" treetype="template">
|
|
// RAM32X1S_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM32X1S_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM32X1S_1: 32 x 1 negedge write distributed (LUT) RAM
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM32X1S_1 #(
|
|
.INIT(32'h00000000) // Initial contents of RAM
|
|
)RAM32X1S_1_inst (
|
|
.O(O), // RAM output
|
|
.A0(A0), // RAM address[0] input
|
|
.A1(A1), // RAM address[1] input
|
|
.A2(A2), // RAM address[2] input
|
|
.A3(A3), // RAM address[3] input
|
|
.A4(A4), // RAM address[4] input
|
|
.D(D), // RAM data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM32X1S_1_inst instantiation
|
|
</Template>
|
|
<Template label="32 x 2 posedge write (RAM32X2S)" treetype="template">
|
|
// RAM32X2S : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM16X2S_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM32X2S: 32 x 2 posedge write distributed (LUT) RAM
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM32X2S #(
|
|
.INIT_00(32'h00000000), // INIT for bit 0 of RAM
|
|
.INIT_01(32'h00000000) // INIT for bit 1 of RAM
|
|
) RAM32X2S_inst (
|
|
.O0(O0), // RAM data[0] output
|
|
.O1(O1), // RAM data[1] output
|
|
.A0(A0), // RAM address[0] input
|
|
.A1(A1), // RAM address[1] input
|
|
.A2(A2), // RAM address[2] input
|
|
.A3(A3), // RAM address[3] input
|
|
.A4(A4), // RAM address[4] input
|
|
.D0(D0), // RAM data[0] input
|
|
.D1(D1), // RAM data[1] input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM32X2S_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="64 Deep (6-bit address)" treetype="folder">
|
|
<Template label="64 X 1 posedge write (RAM64X1S)" treetype="template">
|
|
// RAM64X1S : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM64X1S_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM64X1S: 64 x 1 positive edge write, asynchronous read single-port distributed RAM
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM64X1S #(
|
|
.INIT(64'h0000000000000000) // Initial contents of RAM
|
|
) RAM64X1S_inst (
|
|
.O(O), // 1-bit data output
|
|
.A0(A0), // Address[0] input bit
|
|
.A1(A1), // Address[1] input bit
|
|
.A2(A2), // Address[2] input bit
|
|
.A3(A3), // Address[3] input bit
|
|
.A4(A4), // Address[4] input bit
|
|
.A5(A5), // Address[5] input bit
|
|
.D(D), // 1-bit data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM64X1S_inst instantiation
|
|
</Template>
|
|
<Template label="64 X 1 negedge write (RAM64X1S_1)" treetype="template">
|
|
// RAM64X1S_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM64X1S_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM64X1S_1: 64 x 1 negative edge write, asynchronous read single-port distributed RAM
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM64X1S_1 #(
|
|
.INIT(64'h0000000000000000) // Initial contents of RAM
|
|
) RAM64X1S_1_inst (
|
|
.O(O), // 1-bit data output
|
|
.A0(A0), // Address[0] input bit
|
|
.A1(A1), // Address[1] input bit
|
|
.A2(A2), // Address[2] input bit
|
|
.A3(A3), // Address[3] input bit
|
|
.A4(A4), // Address[4] input bit
|
|
.A5(A5), // Address[5] input bit
|
|
.D(D), // 1-bit data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM64X1S_1_inst instantiation
|
|
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Dual-Port" treetype="folder">
|
|
<Template label="16 X 1 posedge write (RAM16X1D)" treetype="template">
|
|
// RAM16X1D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM16X1D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM16X1D: 16 x 1 positive edge write, asynchronous read dual-port distributed RAM
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM16X1D #(
|
|
.INIT(16'h0000) // Initial contents of RAM
|
|
) RAM16X1D_inst (
|
|
.DPO(DPO), // Read-only 1-bit data output for DPRA
|
|
.SPO(SPO), // Rw/ 1-bit data output for A0-A3
|
|
.A0(A0), // Rw/ address[0] input bit
|
|
.A1(A1), // Rw/ address[1] input bit
|
|
.A2(A2), // Rw/ address[2] input bit
|
|
.A3(A3), // Rw/ address[3] input bit
|
|
.D(D), // Write 1-bit data input
|
|
.DPRA0(DPRA0), // Read address[0] input bit
|
|
.DPRA1(DPRA1), // Read address[1] input bit
|
|
.DPRA2(DPRA2), // Read address[2] input bit
|
|
.DPRA3(DPRA3), // Read address[3] input bit
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM16X1D_inst instantiation
|
|
</Template>
|
|
<Template label="16 X 1 negedge write (RAM16X1D_1)" treetype="template">
|
|
// RAM16X1D_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM16X1D_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM16X1D_1: 16 x 1 negative edge write, asynchronous read dual-port distributed RAM
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM16X1D_1 #(
|
|
.INIT(16'h0000) // Initial contents of RAM
|
|
) RAM16X1D_1_inst (
|
|
.DPO(DPO), // Read-only 1-bit data output
|
|
.SPO(SPO), // Rw/ 1-bit data output
|
|
.A0(A0), // Rw/ address[0] input bit
|
|
.A1(A1), // Rw/ address[1] input bit
|
|
.A2(A2), // Rw/ address[2] input bit
|
|
.A3(A3), // Rw/ address[3] input bit
|
|
.D(D), // Write 1-bit data input
|
|
.DPRA0(DPRA0), // Read-only address[0] input bit
|
|
.DPRA1(DPRA1), // Read-only address[1] input bit
|
|
.DPRA2(DPRA2), // Read-only address[2] input bit
|
|
.DPRA3(DPRA3), // Read-only address[3] input bit
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM16X1D_1_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Block RAM" treetype="folder">
|
|
<Template label="16k + 2k parity parameterizable BlockRAM (RAMB16BWE)" treetype="template">
|
|
// RAMB16BWE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16BWE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16BWE: 16k+2k Parity parameterizable, byte-wide enable BlockRAM
|
|
// Spartan-3A
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16BWE #(
|
|
.DATA_WIDTH_A(0), // Valid values are 1, 2, 4, 9, 18, or 36
|
|
.DATA_WIDTH_B(0), // Valid values are 1, 2, 4, 9, 18, or 36
|
|
.INIT_A(36'h000000000), // Initial values on A output port
|
|
.INIT_B(36'h000000000), // Initial values on B output port
|
|
.SIM_COLLISION_CHECK("ALL"), // Collision check enable "ALL", "WARNING_ONLY",
|
|
// "GENERATE_X_ONLY" or "NONE"
|
|
.SRVAL_A(36'h000000000), // Set/Reset value for A port output
|
|
.SRVAL_B(36'h000000000), // Set/Reset value for B port output
|
|
.WRITE_MODE_A("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
|
|
.WRITE_MODE_B("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16BWE_inst (
|
|
.DOA(DOA), // 32-bit A port data output
|
|
.DOB(DOB), // 32-bit B port data output
|
|
.DOPA(DOPA), // 4-bit A port parity data output
|
|
.DOPB(DOPB), // 4-bit B port parity data output
|
|
.ADDRA(ADDRA), // 14-bit A port address input
|
|
.ADDRB(ADDRB), // 14-bit B port address input
|
|
.CLKA(CLKA), // 1-bit A port clock input
|
|
.CLKB(CLKB), // 1-bit B port clock input
|
|
.DIA(DIA), // 32-bit A port data input
|
|
.DIB(DIB), // 32-bit B port data input
|
|
.DIPA(DIPA), // 4-bit A port parity data input
|
|
.DIPB(DIPB), // 4-bit B port parity data input
|
|
.ENA(ENA), // 1-bit A port enable input
|
|
.ENB(ENB), // 1-bit B port enable input
|
|
.SSRA(SSRA), // 1-bit A port set/reset input
|
|
.SSRB(SSRB), // 1-bit B port set/reset input
|
|
.WEA(WEA), // 4-bit A port write enable input
|
|
.WEB(WEB) // 4-bit B port write enable input
|
|
);
|
|
|
|
// End of RAMB16BWE_inst instantiation
|
|
</Template>
|
|
<SubFolder label="Single-Port" treetype="folder">
|
|
<Template label="1k x 16 + 2 parity bits (RAMB16BWE_S18)" treetype="template">
|
|
// RAMB16BWE_S18 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16BWE_S18_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16BWE_S18: 1k x 16 + 2 Parity bits Single-Port byte-wide write RAM
|
|
// Spartan-3A
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16BWE_S18 #(
|
|
.INIT(18'h00000), // Value of output RAM registers at startup
|
|
.SRVAL(18'h00000), // Output value upon SSR assertion
|
|
.WRITE_MODE("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Address 0 to 255
|
|
.INIT_00(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_01(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_02(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_03(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_04(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_05(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_06(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_07(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_08(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_09(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_0A(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_0B(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_0C(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_0D(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_0E(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_0F(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
// Address 256 to 511
|
|
.INIT_10(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_11(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_12(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_13(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_14(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_15(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_16(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_17(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_18(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_19(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_1A(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_1B(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_1C(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_1D(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_1E(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_1F(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
// Address 512 to 767
|
|
.INIT_20(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_21(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_22(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_23(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_24(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_25(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_26(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_27(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_28(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_29(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_2A(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_2B(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_2C(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_2D(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_2E(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_2F(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
// Address 768 to 1023
|
|
.INIT_30(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_31(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_32(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_33(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_34(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_35(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_36(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_37(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_38(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_39(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_3A(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_3B(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_3C(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_3D(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_3E(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_3F(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
// Address 0 to 255
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 256 to 511
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 512 to 767
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 768 to 1023
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16BWE_S18_inst (
|
|
.DO(DO), // 16-bit Data Output
|
|
.DOP(DOP), // 2-bit Data Parity Output
|
|
.ADDR(ADDR), // 10-bit Address Input
|
|
.CLK(CLK), // 1-bit Clock
|
|
.DI(DI), // 16-bit Data Input
|
|
.DIP(DIP), // 2-bit parity Input
|
|
.EN(EN), // 1-bit RAM Enable Input
|
|
.SSR(SSR), // 1-bit Synchronous Set/Reset Input
|
|
.WE(WE) // 2-bit Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16BWE_S18_inst instantiation
|
|
</Template>
|
|
<Template label="512 x 32 + 4 Parity bits (RAMB16BWE_S36)" treetype="template">
|
|
// RAMB16BWE_S36 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16BWE_S36_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16BWE_S36: 512 x 32 + 4 Parity bits Single-Port byte-wide write RAM
|
|
// Spartan-3A
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16BWE_S36 #(
|
|
.INIT(36'h000000000), // Value of output RAM registers at startup
|
|
.SRVAL(36'h000000000), // Output value upon SSR assertion
|
|
.WRITE_MODE("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Address 0 to 127
|
|
.INIT_00(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_01(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_02(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_03(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_04(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_05(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_06(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_07(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_08(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_09(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_0A(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_0B(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_0C(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_0D(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_0E(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_0F(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
// Address 128 to 255
|
|
.INIT_10(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_11(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_12(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_13(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_14(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_15(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_16(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_17(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_18(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_19(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_1A(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_1B(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_1C(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_1D(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_1E(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_1F(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
// Address 256 to 383
|
|
.INIT_20(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_21(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_22(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_23(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_24(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_25(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_26(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_27(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_28(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_29(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_2A(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_2B(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_2C(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_2D(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_2E(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_2F(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
// Address 384 to 511
|
|
.INIT_30(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_31(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_32(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_33(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_34(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_35(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_36(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_37(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_38(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_39(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_3A(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_3B(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_3C(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_3D(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_3E(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_3F(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
// Address 0 to 127
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 128 to 255
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 256 to 383
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 384 to 511
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16BWE_S36_inst (
|
|
.DO(DO), // 32-bit Data Output
|
|
.DOP(DOP), // 4-bit parity Output
|
|
.ADDR(ADDR), // 9-bit Address Input
|
|
.CLK(CLK), // 1-bit Clock
|
|
.DI(DI), // 32-bit Data Input
|
|
.DIP(DIP), // 4-bit parity Input
|
|
.EN(EN), // 1-bit RAM Enable Input
|
|
.SSR(SSR), // 1-bit Synchronous Set/Reset Input
|
|
.WE(WE) // 4-bit Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16BWE_S36_inst instantiation
|
|
</Template>
|
|
<Template label="16k x 1 (RAMB16_S1)" treetype="template">
|
|
// RAMB16_S1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S1: Spartan-3/3E/3A/3AN/3AD 16kx1 Single-Port RAM
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S1 #(
|
|
.INIT(1'b0), // Value of output RAM registers at startup
|
|
.SRVAL(1'b0), // Output value upon SSR assertion
|
|
.WRITE_MODE("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Address 0 to 4095
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 4096 to 8191
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 8192 to 12287
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 12288 to 16383
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S1_inst (
|
|
.DO(DO), // 1-bit Data Output
|
|
.ADDR(ADDR), // 14-bit Address Input
|
|
.CLK(CLK), // Clock
|
|
.DI(DI), // 1-bit Data Input
|
|
.EN(EN), // RAM Enable Input
|
|
.SSR(SSR), // Synchronous Set/Reset Input
|
|
.WE(WE) // Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S1_inst instantiation
|
|
</Template>
|
|
<Template label="8k x 2 (RAMB16_S2)" treetype="template">
|
|
// RAMB16_S2 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S2: Spartan-3/3E/3A/3AN/3AD 8k x 2 Single-Port RAM
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S2 #(
|
|
.INIT(2'b00), // Value of output RAM registers at startup
|
|
.SRVAL(2'b00), // Output value upon SSR assertion
|
|
.WRITE_MODE("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Address 0 to 2047
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 2048 to 4095
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 4096 to 6143
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 6143 to 8191
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S2_inst (
|
|
.DO(DO), // 2-bit Data Output
|
|
.ADDR(ADDR), // 13-bit Address Input
|
|
.CLK(CLK), // Clock
|
|
.DI(DI), // 2-bit Data Input
|
|
.EN(EN), // RAM Enable Input
|
|
.SSR(SSR), // Synchronous Set/Reset Input
|
|
.WE(WE) // Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S2_inst instantiation
|
|
</Template>
|
|
<Template label="4k x 4 (RAMB16_S4)" treetype="template">
|
|
// RAMB16_S4 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S4_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S4: Spartan-3/3E/3A/3AN/3AD 4k x 4 Single-Port RAM
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S4 #(
|
|
.INIT(4'h0), // Value of output RAM registers at startup
|
|
.SRVAL(4'h0), // Output value upon SSR assertion
|
|
.WRITE_MODE("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Address 0 to 1023
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 1024 to 2047
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 2048 to 3071
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 3072 to 4095
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S4_inst (
|
|
.DO(DO), // 4-bit Data Output
|
|
.ADDR(ADDR), // 12-bit Address Input
|
|
.CLK(CLK), // Clock
|
|
.DI(DI), // 4-bit Data Input
|
|
.EN(EN), // RAM Enable Input
|
|
.SSR(SSR), // Synchronous Set/Reset Input
|
|
.WE(WE) // Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S4_inst instantiation
|
|
</Template>
|
|
<Template label="2k x 8 + 1 Parity bit (RAMB16_S9)" treetype="template">
|
|
// RAMB16_S9 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S9_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S9: Spartan-3/3E/3A/3AN/3AD 2k x 8 + 1 Parity bit Single-Port RAM
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S9 #(
|
|
.INIT(9'h000), // Value of output RAM registers at startup
|
|
.SRVAL(9'h000), // Output value upon SSR assertion
|
|
.WRITE_MODE("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Address 0 to 511
|
|
.INIT_00(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_01(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_02(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_03(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_04(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_05(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_06(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_07(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_08(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_09(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_0A(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_0B(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_0C(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_0D(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_0E(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_0F(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
// Address 512 to 1023
|
|
.INIT_10(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_11(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_12(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_13(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_14(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_15(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_16(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_17(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_18(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_19(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_1A(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_1B(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_1C(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_1D(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_1E(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_1F(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
// Address 1024 to 1535
|
|
.INIT_20(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_21(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_22(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_23(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_24(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_25(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_26(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_27(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_28(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_29(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_2A(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_2B(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_2C(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_2D(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_2E(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_2F(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
// Address 1536 to 2047
|
|
.INIT_30(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_31(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_32(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_33(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_34(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_35(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_36(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_37(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_38(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_39(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_3A(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_3B(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_3C(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_3D(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_3E(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_3F(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
// Address 0 to 511
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 512 to 1023
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 1024 to 1535
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 1536 to 2047
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S9_inst (
|
|
.DO(DO), // 8-bit Data Output
|
|
.DOP(DOP), // 1-bit parity Output
|
|
.ADDR(ADDR), // 11-bit Address Input
|
|
.CLK(CLK), // Clock
|
|
.DI(DI), // 8-bit Data Input
|
|
.DIP(DIP), // 1-bit parity Input
|
|
.EN(EN), // RAM Enable Input
|
|
.SSR(SSR), // Synchronous Set/Reset Input
|
|
.WE(WE) // Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S9_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Dual-Port (Matched Port Widths)" treetype="folder">
|
|
<Template label="1k x 16 + 2 Parity bits (RAMB16BWE_S18_S18)" treetype="template">
|
|
// RAMB16BWE_S18_S18 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16BWE_S18_S18_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16BWE_S18_S18: 1k x 16 + 2 Parity bits Dual-Port byte-wide write RAM
|
|
// Spartan-3A
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16BWE_S18_S18 #(
|
|
.INIT_A(18'h00000), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(18'h00000), // Value of output RAM registers on Port B at startup
|
|
.SIM_COLLISION_CHECK("ALL"), // Collision check enable "ALL", "WARNING_ONLY",
|
|
// "GENERATE_X_ONLY" or "NONE"
|
|
.SRVAL_A(18'h00000), // Port A output value upon SSR assertion
|
|
.SRVAL_B(18'h00000), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Address 0 to 255
|
|
.INIT_00(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_01(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_02(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_03(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_04(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_05(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_06(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_07(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_08(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_09(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_0A(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_0B(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_0C(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_0D(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_0E(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_0F(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
// Address 256 to 511
|
|
.INIT_10(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_11(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_12(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_13(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_14(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_15(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_16(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_17(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_18(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_19(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_1A(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_1B(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_1C(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_1D(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_1E(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_1F(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
// Address 512 to 767
|
|
.INIT_20(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_21(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_22(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_23(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_24(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_25(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_26(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_27(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_28(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_29(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_2A(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_2B(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_2C(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_2D(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_2E(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_2F(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
// Address 768 to 1023
|
|
.INIT_30(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_31(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_32(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_33(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_34(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_35(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_36(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_37(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_38(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_39(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_3A(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_3B(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_3C(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_3D(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_3E(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_3F(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
// Address 0 to 255
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 256 to 511
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 512 to 767
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 768 to 1023
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16BWE_S18_S18_inst (
|
|
.DOA(DOA), // Port A 16-bit Data Output
|
|
.DOB(DOB), // Port B 16-bit Data Output
|
|
.DOPA(DOPA), // Port A 2-bit Data Parity Output
|
|
.DOPB(DOPB), // Port B 2-bit Data Parity Output
|
|
.ADDRA(ADDRA), // Port A 10-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 10-bit Address Input
|
|
.CLKA(CLKA), // Port A 1-bit Clock
|
|
.CLKB(CLKB), // Port B 1-bit Clock
|
|
.DIA(DIA), // Port A 16-bit Data Input
|
|
.DIB(DIB), // Port B 16-bit Data Input
|
|
.DIPA(DIPA), // Port A 2-bit parity Input
|
|
.DIPB(DIPB), // Port-B 2-bit parity Input
|
|
.ENA(ENA), // Port A 1-bit RAM Enable Input
|
|
.ENB(ENB), // Port B 1-bit RAM Enable Input
|
|
.SSRA(SSRA), // Port A 1-bit Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B 1-bit Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A 2-bit Write Enable Input
|
|
.WEB(WEB) // Port B 2-bit Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16BWE_S18_S18_inst instantiation
|
|
</Template>
|
|
<Template label="512 x 32 + 4 Parity bits (RAMB16BWE_S36_S36)" treetype="template">
|
|
// RAMB16BWE_S36_S36 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16BWE_S36_S36_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16BWE_S36_S36: 512 x 32 + 4 Parity bits byte-wide write Dual-Port RAM
|
|
// Spartan-3A
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16BWE_S36_S36 #(
|
|
.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
.SRVAL_A(36'h000000000), // Port A output value upon SSR assertion
|
|
.SRVAL_B(36'h000000000), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Address 0 to 127
|
|
.INIT_00(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_01(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_02(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_03(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_04(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_05(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_06(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_07(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_08(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_09(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_0A(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_0B(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_0C(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_0D(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_0E(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_0F(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
// Address 128 to 255
|
|
.INIT_10(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_11(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_12(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_13(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_14(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_15(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_16(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_17(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_18(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_19(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_1A(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_1B(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_1C(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_1D(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_1E(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_1F(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
// Address 256 to 383
|
|
.INIT_20(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_21(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_22(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_23(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_24(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_25(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_26(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_27(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_28(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_29(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_2A(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_2B(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_2C(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_2D(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_2E(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_2F(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
// Address 384 to 511
|
|
.INIT_30(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_31(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_32(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_33(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_34(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_35(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_36(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_37(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_38(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_39(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_3A(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_3B(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_3C(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_3D(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_3E(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_3F(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
// Address 0 to 127
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 128 to 255
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 256 to 383
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 384 to 511
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16BWE_S36_S36_inst (
|
|
.DOA(DOA), // Port A 32-bit Data Output
|
|
.DOB(DOB), // Port B 32-bit Data Output
|
|
.DOPA(DOPA), // Port A 4-bit Parity Output
|
|
.DOPB(DOPB), // Port B 4-bit Parity Output
|
|
.ADDRA(ADDRA), // Port A 9-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 9-bit Address Input
|
|
.CLKA(CLKA), // Port A 1-bit Clock
|
|
.CLKB(CLKB), // Port B 1-bit Clock
|
|
.DIA(DIA), // Port A 32-bit Data Input
|
|
.DIB(DIB), // Port B 32-bit Data Input
|
|
.DIPA(DIPA), // Port A 4-bit parity Input
|
|
.DIPB(DIPB), // Port-B 4-bit parity Input
|
|
.ENA(ENA), // Port A 1-bit RAM Enable Input
|
|
.ENB(ENB), // Port B 1-bit RAM Enable Input
|
|
.SSRA(SSRA), // Port A 1-bit Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B 1-bit Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A 4-bit Write Enable Input
|
|
.WEB(WEB) // Port B 4-bit Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16BWE_S36_S36_inst instantiation
|
|
</Template>
|
|
<Template label="16k x 1 (RAMB16_S1_S1)" treetype="template">
|
|
// RAMB16_S1_S1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S1_S1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S1_S1: Spartan-3/3E/3A/3AN/3AD 16k x 1 Dual-Port RAM
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S1_S1 #(
|
|
.INIT_A(1'b0), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(1'b0), // Value of output RAM registers on Port B at startup
|
|
.SRVAL_A(1'b0), // Port A output value upon SSR assertion
|
|
.SRVAL_B(1'b0), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Address 0 to 4095
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 4096 to 8191
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 8192 to 12287
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 12288 to 16383
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S1_S1_inst (
|
|
.DOA(DOA), // Port A 1-bit Data Output
|
|
.DOB(DOB), // Port B 1-bit Data Output
|
|
.ADDRA(ADDRA), // Port A 14-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 14-bit Address Input
|
|
.CLKA(CLKA), // Port A Clock
|
|
.CLKB(CLKB), // Port B Clock
|
|
.DIA(DIA), // Port A 1-bit Data Input
|
|
.DIB(DIB), // Port B 1-bit Data Input
|
|
.ENA(ENA), // Port A RAM Enable Input
|
|
.ENB(ENB), // Port B RAM Enable Input
|
|
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A Write Enable Input
|
|
.WEB(WEB) // Port B Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S1_S1_inst instantiation
|
|
</Template>
|
|
<Template label="8k x 2 (RAMB16_S2_S2)" treetype="template">
|
|
// RAMB16_S2_S2 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S2_S2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S2_S2: Spartan-3/3E/3A/3AN/3AD 8k x 2 Dual-Port RAM
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S2_S2 #(
|
|
.INIT_A(2'b00), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(2'b00), // Value of output RAM registers on Port B at startup
|
|
.SRVAL_A(2'b00), // Port A output value upon SSR assertion
|
|
.SRVAL_B(2'b00), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
|
|
// Address 0 to 2047
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 2048 to 4095
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 4096 to 6143
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 6143 to 8191
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S2_S2_inst (
|
|
.DOA(DOA), // Port A 2-bit Data Output
|
|
.DOB(DOB), // Port B 2-bit Data Output
|
|
.ADDRA(ADDRA), // Port A 13-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 13-bit Address Input
|
|
.CLKA(CLKA), // Port A Clock
|
|
.CLKB(CLKB), // Port B Clock
|
|
.DIA(DIA), // Port A 2-bit Data Input
|
|
.DIB(DIB), // Port B 2-bit Data Input
|
|
.ENA(ENA), // Port A RAM Enable Input
|
|
.ENB(ENB), // Port B RAM Enable Input
|
|
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A Write Enable Input
|
|
.WEB(WEB) // Port B Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S2_S2_inst instantiation
|
|
</Template>
|
|
<Template label="4k x 4 (RAMB16_S4_S4)" treetype="template">
|
|
// RAMB16_S4_S4 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S4_S4_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S4_S4: Spartan-3/3E/3A/3AN/3AD 4k x 4 Dual-Port RAM
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S4_S4 #(
|
|
.INIT_A(4'h0), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(4'h0), // Value of output RAM registers on Port B at startup
|
|
.SRVAL_A(4'h0), // Port A output value upon SSR assertion
|
|
.SRVAL_B(4'h0), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Address 0 to 1023
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 1024 to 2047
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 2048 to 3071
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 3072 to 4095
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S4_S4_inst (
|
|
.DOA(DOA), // Port A 4-bit Data Output
|
|
.DOB(DOB), // Port B 4-bit Data Output
|
|
.ADDRA(ADDRA), // Port A 12-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 12-bit Address Input
|
|
.CLKA(CLKA), // Port A Clock
|
|
.CLKB(CLKB), // Port B Clock
|
|
.DIA(DIA), // Port A 4-bit Data Input
|
|
.DIB(DIB), // Port B 4-bit Data Input
|
|
.ENA(ENA), // Port A RAM Enable Input
|
|
.ENB(ENB), // Port B RAM Enable Input
|
|
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A Write Enable Input
|
|
.WEB(WEB) // Port B Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S4_S4_inst instantiation
|
|
</Template>
|
|
<Template label="2k x 8 + 1 Parity bit (RAMB16_S9_S9)" treetype="template">
|
|
// RAMB16_S9_S9 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S9_S9_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S9_S9: Spartan-3/3E/3A/3AN/3AD 2k x 8 + 1 Parity bit Dual-Port RAM
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S9_S9 #(
|
|
.INIT_A(9'h000), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(9'h000), // Value of output RAM registers on Port B at startup
|
|
.SRVAL_A(9'h000), // Port A output value upon SSR assertion
|
|
.SRVAL_B(9'h000), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Address 0 to 511
|
|
.INIT_00(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_01(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_02(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_03(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_04(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_05(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_06(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_07(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_08(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_09(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_0A(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_0B(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_0C(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_0D(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_0E(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_0F(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
// Address 512 to 1023
|
|
.INIT_10(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_11(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_12(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_13(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_14(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_15(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_16(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_17(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_18(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_19(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_1A(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_1B(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_1C(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_1D(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_1E(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_1F(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
// Address 1024 to 1535
|
|
.INIT_20(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_21(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_22(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_23(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_24(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_25(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_26(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_27(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_28(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_29(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_2A(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_2B(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_2C(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_2D(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_2E(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_2F(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
// Address 1536 to 2047
|
|
.INIT_30(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_31(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_32(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_33(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_34(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_35(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_36(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_37(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_38(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_39(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_3A(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_3B(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_3C(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_3D(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_3E(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_3F(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
// Address 0 to 511
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 512 to 1023
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 1024 to 1535
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 1536 to 2047
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S9_S9_inst (
|
|
.DOA(DOA), // Port A 8-bit Data Output
|
|
.DOB(DOB), // Port B 8-bit Data Output
|
|
.DOPA(DOPA), // Port A 1-bit Parity Output
|
|
.DOPB(DOPB), // Port B 1-bit Parity Output
|
|
.ADDRA(ADDRA), // Port A 11-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 11-bit Address Input
|
|
.CLKA(CLKA), // Port A Clock
|
|
.CLKB(CLKB), // Port B Clock
|
|
.DIA(DIA), // Port A 8-bit Data Input
|
|
.DIB(DIB), // Port B 8-bit Data Input
|
|
.DIPA(DIPA), // Port A 1-bit parity Input
|
|
.DIPB(DIPB), // Port-B 1-bit parity Input
|
|
.ENA(ENA), // Port A RAM Enable Input
|
|
.ENB(ENB), // Port B RAM Enable Input
|
|
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A Write Enable Input
|
|
.WEB(WEB) // Port B Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S9_S9_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Dual-Port (Mis-matched Port Widths)" treetype="folder">
|
|
<Template label="1k/2k x 16/9 + 2/1 Parity bits (RAMB16BWE_S18_S9)" treetype="template">
|
|
// RAMB16BWE_S18_S9 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16BWE_S18_S9_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16BWE_S18_S9: 1k/2k x 16/8 + 2/1 Parity bits Dual-Port byte-wide write RAM
|
|
// Spartan-3A
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16BWE_S18_S9 #(
|
|
.INIT_A(18'h00000), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(9'h000), // Value of output RAM registers on Port B at startup
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
.SRVAL_A(18'h00000), // Port A output value upon SSR assertion
|
|
.SRVAL_B(9'h000), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Port A Address 0 to 255, Port B Address 0 to 127
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 256 to 511, Port B Address 128 to 255
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 512 to 767, Port B Address 256 to 383
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 768 to 1023, Port B Address 384 to 511
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
// Port A Address 0 to 255, Port B Address 0 to 127
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 256 to 511, Port B Address 128 to 255
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 512 to 767, Port B Address 256 to 383
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 768 to 1023, Port B Address 384 to 511
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16BWE_S18_S9_inst (
|
|
.DOA(DOA), // Port A 16-bit Data Output
|
|
.DOB(DOB), // Port B 8-bit Data Output
|
|
.DOPA(DOPA), // Port A 2-bit Parity Output
|
|
.DOPB(DOPB), // Port B 1-bit Parity Output
|
|
.ADDRA(ADDRA), // Port A 10-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 11-bit Address Input
|
|
.CLKA(CLKA), // Port A 1-bit Clock
|
|
.CLKB(CLKB), // Port B 1-bit Clock
|
|
.DIA(DIA), // Port A 16-bit Data Input
|
|
.DIB(DIB), // Port B 8-bit Data Input
|
|
.DIPA(DIPA), // Port A 2-bit parity Input
|
|
.DIPB(DIPB), // Port-B 1-bit parity Input
|
|
.ENA(ENA), // Port A 1-bit RAM Enable Input
|
|
.ENB(ENB), // Port B 1-bit RAM Enable Input
|
|
.SSRA(SSRA), // Port A 1-bit Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B 1-bit Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A 2-bit Write Enable Input
|
|
.WEB(WEB) // Port B 1-bit Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16BWE_S18_S9_inst instantiation
|
|
</Template>
|
|
<Template label="1k/512 x 16/32 + 2/4 Parity bits (RAMB16BWE_S36_S18)" treetype="template">
|
|
// RAMB16BWE_S36_S18 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16BWE_S36_S18_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16BWE_S36_S18: 1k/512 x 16/32 + 2/4 Parity bits Dual-Port byte-wide write RAM
|
|
// Spartan-3A
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16BWE_S36_S18 #(
|
|
.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(18'h00000), // Value of output RAM registers on Port B at startup
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
.SRVAL_A(36'h000000000), // Port A output value upon SSR assertion
|
|
.SRVAL_B(18'h00000), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Port A Address 0 to 255, Port B Address 0 to 127
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 256 to 511, Port B Address 128 to 255
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 512 to 767, Port B Address 256 to 383
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 768 to 1023, Port B Address 384 to 511
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
// Port A Address 0 to 255, Port B Address 0 to 127
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 256 to 511, Port B Address 128 to 255
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 512 to 767, Port B Address 256 to 383
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 768 to 1023, Port B Address 384 to 511
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16BWE_S36_S18_inst (
|
|
.DOA(DOA), // Port A 32-bit Data Output
|
|
.DOB(DOB), // Port B 16-bit Data Output
|
|
.DOPA(DOPA), // Port A 4-bit Parity Output
|
|
.DOPB(DOPB), // Port B 2-bit Parity Output
|
|
.ADDRA(ADDRA), // Port A 9-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 10-bit Address Input
|
|
.CLKA(CLKA), // Port A 1-bit Clock
|
|
.CLKB(CLKB), // Port B 1-bit Clock
|
|
.DIA(DIA), // Port A 32-bit Data Input
|
|
.DIB(DIB), // Port B 16-bit Data Input
|
|
.DIPA(DIPA), // Port A 4-bit parity Input
|
|
.DIPB(DIPB), // Port-B 2-bit parity Input
|
|
.ENA(ENA), // Port A 1-bit RAM Enable Input
|
|
.ENB(ENB), // Port B 1-bit RAM Enable Input
|
|
.SSRA(SSRA), // Port A 1-bit Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B 1-bit Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A 4-bit Write Enable Input
|
|
.WEB(WEB) // Port B 2-bit Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16BWE_S36_S18_inst instantiation
|
|
</Template>
|
|
<Template label="2k/512 x 8/32 + 1/4 Parity bits (RAMB16BWE_S36_S9)" treetype="template">
|
|
// RAMB16BWE_S36_S9 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16BWE_S36_S9_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16BWE_S36_S9: 2k/512 x 8/32 + 1/4 Parity bits Dual-Port byte-wide write RAM
|
|
// Spartan-3A
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16BWE_S36_S9 #(
|
|
.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(9'h000), // Value of output RAM registers on Port B at startup
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
.SRVAL_A(36'h000000000), // Port A output value upon SSR assertion
|
|
.SRVAL_B(9'h000), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Port A Address 0 to 255, Port B Address 0 to 127
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 256 to 511, Port B Address 128 to 255
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 512 to 767, Port B Address 256 to 383
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 768 to 1023, Port B Address 384 to 511
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
// Port A Address 0 to 255, Port B Address 0 to 127
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 256 to 511, Port B Address 128 to 255
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 512 to 767, Port B Address 256 to 383
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 768 to 1023, Port B Address 384 to 511
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16BWE_S36_S9_inst (
|
|
.DOA(DOA), // Port A 32-bit Data Output
|
|
.DOB(DOB), // Port B 8-bit Data Output
|
|
.DOPA(DOPA), // Port A 4-bit Parity Output
|
|
.DOPB(DOPB), // Port B 1-bit Parity Output
|
|
.ADDRA(ADDRA), // Port A 9-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 11-bit Address Input
|
|
.CLKA(CLKA), // Port A 1-bit Clock
|
|
.CLKB(CLKB), // Port B 1-bit Clock
|
|
.DIA(DIA), // Port A 32-bit Data Input
|
|
.DIB(DIB), // Port B 8-bit Data Input
|
|
.DIPA(DIPA), // Port A 4-bit parity Input
|
|
.DIPB(DIPB), // Port-B 1-bit parity Input
|
|
.ENA(ENA), // Port A 1-bit RAM Enable Input
|
|
.ENB(ENB), // Port B 1-bit RAM Enable Input
|
|
.SSRA(SSRA), // Port A 1-bit Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B 1-bit Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A 4-bit Write Enable Input
|
|
.WEB(WEB) // Port B 1-bit Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16BWE_S36_S9_inst instantiation
|
|
</Template>
|
|
<Template label="16k/1k x 1/16 + 0/2 Parity bits (RAMB16_S1_S18)" treetype="template">
|
|
// RAMB16_S1_S18 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S1_S18_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S1_S18: Spartan-3/3E/3A/3AN/3AD 16k/1k x 1/16 + 0/2 Parity bits Dual-Port RAM
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S1_S18 #(
|
|
.INIT_A(1'b0), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(18'h00000), // Value of output RAM registers on Port B at startup
|
|
.SRVAL_A(1'b0), // Port A output value upon SSR assertion
|
|
.SRVAL_B(18'h00000), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Port A Address 0 to 4095, Port B Address 0 to 255
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 4096 to 8191, Port B Address 256 to 511
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 8192 to 12287, Port B Address 512 to 767
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 12288 to 16383, Port B Address 768 to 1023
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
// Port B Address 0 to 255
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 256 to 511
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 512 to 767
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 768 to 1023
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S1_S18_inst (
|
|
.DOA(DOA), // Port A 1-bit Data Output
|
|
.DOB(DOB), // Port B 16-bit Data Output
|
|
.DOPB(DOPB), // Port B 2-bit Parity Output
|
|
.ADDRA(ADDRA), // Port A 14-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 10-bit Address Input
|
|
.CLKA(CLKA), // Port A Clock
|
|
.CLKB(CLKB), // Port B Clock
|
|
.DIA(DIA), // Port A 1-bit Data Input
|
|
.DIB(DIB), // Port B 16-bit Data Input
|
|
.DIPB(DIPB), // Port-B 2-bit parity Input
|
|
.ENA(ENA), // Port A RAM Enable Input
|
|
.ENB(ENB), // Port B RAM Enable Input
|
|
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A Write Enable Input
|
|
.WEB(WEB) // Port B Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S1_S18_inst instantiation
|
|
</Template>
|
|
<Template label="16k/8k x 1/2 (RAMB16_S1_S2)" treetype="template">
|
|
// RAMB16_S1_S2 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S1_S2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S1_S2: Spartan-3/3E/3A/3AN/3AD 16k/8k x 1/2 Dual-Port RAM
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S1_S2 #(
|
|
.INIT_A(1'b0), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(2'b00), // Value of output RAM registers on Port B at startup
|
|
.SRVAL_A(1'b0), // Port A output value upon SSR assertion
|
|
.SRVAL_B(2'b00), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Port A Address 0 to 4095, Port B Address 0 to 2047
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 4096 to 8191, Port B Address 2048 to 4095
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 8192 to 12287, Port B Address 4095 to 6143
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 12288 to 16383, Port B Address 6144 to 8091
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S1_S2_inst (
|
|
.DOA(DOA), // Port A 1-bit Data Output
|
|
.DOB(DOB), // Port B 2-bit Data Output
|
|
.ADDRA(ADDRA), // Port A 14-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 13-bit Address Input
|
|
.CLKA(CLKA), // Port A Clock
|
|
.CLKB(CLKB), // Port B Clock
|
|
.DIA(DIA), // Port A 1-bit Data Input
|
|
.DIB(DIB), // Port B 2-bit Data Input
|
|
.ENA(ENA), // Port A RAM Enable Input
|
|
.ENB(ENB), // Port B RAM Enable Input
|
|
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A Write Enable Input
|
|
.WEB(WEB) // Port B Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S1_S2_inst instantiation
|
|
</Template>
|
|
<Template label="16k/512 x 1/32 + 0/4 Parity bits (RAMB16_S1_S36)" treetype="template">
|
|
// RAMB16_S1_S36 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S1_S36_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S1_S36: Spartan-3/3E/3A/3AN/3AD 16k/512 x 1/32 + 0/4 Parity bits Dual-Port RAM
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S1_S36 #(
|
|
.INIT_A(1'b0), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup
|
|
.SRVAL_A(1'b0), // Port A output value upon SSR assertion
|
|
.SRVAL_B(36'h000000000), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Port A Address 0 to 4095, Port B Address 0 to 127
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 4096 to 8191, Port B Address 128 to 255
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 8192 to 12287, Port B Address 256 to 383
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 12288 to 16383, Port B Address 384 to 512
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
// Port B Address 0 to 127
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 128 to 255
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 256 to 383
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 384 to 512
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S1_S36_inst (
|
|
.DOA(DOA), // Port A 1-bit Data Output
|
|
.DOB(DOB), // Port B 32-bit Data Output
|
|
.DOPB(DOPB), // Port B 4-bit Parity Output
|
|
.ADDRA(ADDRA), // Port A 14-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 9-bit Address Input
|
|
.CLKA(CLKA), // Port A Clock
|
|
.CLKB(CLKB), // Port B Clock
|
|
.DIA(DIA), // Port A 1-bit Data Input
|
|
.DIB(DIB), // Port B 32-bit Data Input
|
|
.DIPB(DIPB), // Port-B 4-bit parity Input
|
|
.ENA(ENA), // Port A RAM Enable Input
|
|
.ENB(ENB), // Port B RAM Enable Input
|
|
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A Write Enable Input
|
|
.WEB(WEB) // Port B Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S1_S36_inst instantiation
|
|
</Template>
|
|
<Template label="16k/4k x 1/4 (RAMB16_S1_S4)" treetype="template">
|
|
// RAMB16_S1_S4 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S1_S4_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S1_S4: Spartan-3/3E/3A/3AN/3AD 16k/4k x 1/4 Dual-Port RAM
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S1_S4 #(
|
|
.INIT_A(1'b0), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(4'h0), // Value of output RAM registers on Port B at startup
|
|
.SRVAL_A(1'b0), // Port A output value upon SSR assertion
|
|
.SRVAL_B(4'h0), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Port A Address 0 to 4095, Port B Address 0 to 1023
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 4096 to 8191, Port B Address 1024 to 2047
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 8192 to 12287, Port B Address 2048 to 3071
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 12288 to 16383, Port B Address 3072 to 4095
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S1_S4_inst (
|
|
.DOA(DOA), // Port A 1-bit Data Output
|
|
.DOB(DOB), // Port B 4-bit Data Output
|
|
.ADDRA(ADDRA), // Port A 14-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 12-bit Address Input
|
|
.CLKA(CLKA), // Port A Clock
|
|
.CLKB(CLKB), // Port B Clock
|
|
.DIA(DIA), // Port A 1-bit Data Input
|
|
.DIB(DIB), // Port B 4-bit Data Input
|
|
.ENA(ENA), // Port A RAM Enable Input
|
|
.ENB(ENB), // Port B RAM Enable Input
|
|
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A Write Enable Input
|
|
.WEB(WEB) // Port B Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S1_S4_inst instantiation
|
|
</Template>
|
|
<Template label="16k/2k x 1/8 + 0/1 Parity bit (RAMB16_S1_S9)" treetype="template">
|
|
|
|
// RAMB16_S1_S9 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S1_S9_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S1_S9: Spartan-3/3E/3A/3AN/3AD 16k/2k x 1/8 + 0/1 Parity bit Dual-Port RAM
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S1_S9 #(
|
|
.INIT_A(1'b0), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(9'h000), // Value of output RAM registers on Port B at startup
|
|
.SRVAL_A(1'b0), // Port A output value upon SSR assertion
|
|
.SRVAL_B(9'h000), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Port A Address 0 to 4095, Port B Address 0 to 511
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 4096 to 8191, Port B Address 512 to 1023
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 8192 to 12287, Port B Address 1024 to 1535
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 12288 to 16383, Port B Address 1535 to 2047
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
// Port B Address 0 to 511
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 512 to 1023
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 1024 to 1535
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 1535 to 2047
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S1_S9_inst (
|
|
.DOA(DOA), // Port A 1-bit Data Output
|
|
.DOB(DOB), // Port B 8-bit Data Output
|
|
.DOPB(DOPB), // Port B 1-bit Parity Output
|
|
.ADDRA(ADDRA), // Port A 14-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 11-bit Address Input
|
|
.CLKA(CLKA), // Port A Clock
|
|
.CLKB(CLKB), // Port B Clock
|
|
.DIA(DIA), // Port A 1-bit Data Input
|
|
.DIB(DIB), // Port B 8-bit Data Input
|
|
.DIPB(DIPB), // Port-B 1-bit parity Input
|
|
.ENA(ENA), // Port A RAM Enable Input
|
|
.ENB(ENB), // Port B RAM Enable Input
|
|
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A Write Enable Input
|
|
.WEB(WEB) // Port B Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S1_S9_inst instantiation
|
|
</Template>
|
|
<Template label="8k/1k x 2/16 + 0/2 Parity bit (RAMB16_S2_S18)" treetype="template">
|
|
// RAMB16_S2_S18 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S2_S18_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S2_S18: Spartan-3/3E/3A/3AN/3AD 8k/1k x 2/16 + 0/2 Parity bits Dual-Port RAM
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S2_S18 #(
|
|
.INIT_A(2'b00), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(9'h000), // Value of output RAM registers on Port B at startup
|
|
.SRVAL_A(2'b00), // Port A output value upon SSR assertion
|
|
.SRVAL_B(9'h000), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Port A Address 0 to 2047, Port B Address 0 to 255
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 2048 to 4095, Port B Address 256 to 511
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 4096 to 6143, Port B Address 512 to 767
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 6144 to 8191, Port B Address 768 to 1023
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
// Port B Address 0 to 255
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 256 to 511
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 512 to 767
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 768 to 1023
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S2_S18_inst (
|
|
.DOA(DOA), // Port A 2-bit Data Output
|
|
.DOB(DOB), // Port B 16-bit Data Output
|
|
.DOPB(DOPB), // Port B 2-bit Parity Output
|
|
.ADDRA(ADDRA), // Port A 13-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 10-bit Address Input
|
|
.CLKA(CLKA), // Port A Clock
|
|
.CLKB(CLKB), // Port B Clock
|
|
.DIA(DIA), // Port A 2-bit Data Input
|
|
.DIB(DIB), // Port B 16-bit Data Input
|
|
.DIPB(DIPB), // Port-B 2-bit parity Input
|
|
.ENA(ENA), // Port A RAM Enable Input
|
|
.ENB(ENB), // Port B RAM Enable Input
|
|
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A Write Enable Input
|
|
.WEB(WEB) // Port B Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S2_S18_inst instantiation
|
|
</Template>
|
|
<Template label="8k/512 x 2/32 + 0/4 Parity bits (RAMB16_S2_S36)" treetype="template">
|
|
// RAMB16_S2_S36 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S2_S36_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S2_S36: Spartan-3/3E/3A/3AN/3AD 8k/512 x 2/32 + 0/4 Parity bits Dual-Port RAM
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S2_S36 #(
|
|
.INIT_A(2'b00), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup
|
|
.SRVAL_A(2'b00), // Port A output value upon SSR assertion
|
|
.SRVAL_B(36'h000000000), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Port A Address 0 to 2047, Port B Address 0 to 127
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 2048 to 4095, Port B Address 128 to 255
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 4096 to 6143, Port B Address 256 to 383
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 6144 to 8191, Port B Address 384 to 511
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
// Port B Address 0 to 127
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 128 to 255
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 256 to 383
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 384 to 511
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S2_S36_inst (
|
|
.DOA(DOA), // Port A 2-bit Data Output
|
|
.DOB(DOB), // Port B 32-bit Data Output
|
|
.DOPB(DOPB), // Port B 4-bit Parity Output
|
|
.ADDRA(ADDRA), // Port A 13-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 9-bit Address Input
|
|
.CLKA(CLKA), // Port A Clock
|
|
.CLKB(CLKB), // Port B Clock
|
|
.DIA(DIA), // Port A 2-bit Data Input
|
|
.DIB(DIB), // Port B 32-bit Data Input
|
|
.DIPB(DIPB), // Port-B 4-bit parity Input
|
|
.ENA(ENA), // Port A RAM Enable Input
|
|
.ENB(ENB), // Port B RAM Enable Input
|
|
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A Write Enable Input
|
|
.WEB(WEB) // Port B Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S2_S36_inst instantiation
|
|
</Template>
|
|
<Template label="8k/4k x 2/4 (RAMB16_S2_S4)" treetype="template">
|
|
// RAMB16_S2_S4 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S2_S4_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S2_S4: Spartan-3/3E/3A/3AN/3AD 8k/4k x 2/4 Dual-Port RAM
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S2_S4 #(
|
|
.INIT_A(2'b00), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(4'h0), // Value of output RAM registers on Port B at startup
|
|
.SRVAL_A(2'b00), // Port A output value upon SSR assertion
|
|
.SRVAL_B(4'h0), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Port A Address 0 to 2047, Port B Address 0 to 1023
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 2048 to 4095, Port B Address 1024 to 2047
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 4096 to 6143, Port B Address 2048 to 3071
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 6144 to 8191, Port B Address 3072 to 4095
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S2_S4_inst (
|
|
.DOA(DOA), // Port A 2-bit Data Output
|
|
.DOB(DOB), // Port B 4-bit Data Output
|
|
.ADDRA(ADDRA), // Port A 13-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 12-bit Address Input
|
|
.CLKA(CLKA), // Port A Clock
|
|
.CLKB(CLKB), // Port B Clock
|
|
.DIA(DIA), // Port A 2-bit Data Input
|
|
.DIB(DIB), // Port B 4-bit Data Input
|
|
.ENA(ENA), // Port A RAM Enable Input
|
|
.ENB(ENB), // Port B RAM Enable Input
|
|
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A Write Enable Input
|
|
.WEB(WEB) // Port B Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S2_S4_inst instantiation
|
|
</Template>
|
|
<Template label="8k/2k x 2/8 + 0/1 Parity bit (RAMB16_S2_S9)" treetype="template">
|
|
// RAMB16_S2_S9 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S2_S9_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S2_S9: Spartan-3/3E/3A/3AN/3AD 8k/2k x 2/8 + 0/1 Parity bit Dual-Port RAM
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S2_S9 #(
|
|
.INIT_A(2'b00), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(9'h000), // Value of output RAM registers on Port B at startup
|
|
.SRVAL_A(2'b00), // Port A output value upon SSR assertion
|
|
.SRVAL_B(9'h000), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Port A Address 0 to 2047, Port B Address 0 to 511
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 2048 to 4095, Port B Address 512 to 1023
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 4096 to 6143, Port B Address 1024 to 1535
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 6144 to 8191, Port B Address 1536 to 2047
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
// Port B Address 0 to 511
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 512 to 1023
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 1024 to 1535
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 6144 to 8191, Port B Address 1536 to 2047
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S2_S9_inst (
|
|
.DOA(DOA), // Port A 2-bit Data Output
|
|
.DOB(DOB), // Port B 8-bit Data Output
|
|
.DOPB(DOPB), // Port B 1-bit Parity Output
|
|
.ADDRA(ADDRA), // Port A 13-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 11-bit Address Input
|
|
.CLKA(CLKA), // Port A Clock
|
|
.CLKB(CLKB), // Port B Clock
|
|
.DIA(DIA), // Port A 2-bit Data Input
|
|
.DIB(DIB), // Port B 8-bit Data Input
|
|
.DIPB(DIPB), // Port-B 1-bit parity Input
|
|
.ENA(ENA), // Port A RAM Enable Input
|
|
.ENB(ENB), // Port B RAM Enable Input
|
|
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A Write Enable Input
|
|
.WEB(WEB) // Port B Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S2_S9_inst instantiation
|
|
</Template>
|
|
<Template label="4k/1k x 4/16 + 0/2 Parity bits (RAMB16_S4_S18)" treetype="template">
|
|
// RAMB16_S4_S18 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S4_S18_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S4_S18: Spartan-3/3E/3A/3AN/3AD 4k/1k x 4/16 + 0/2 Parity bits Dual-Port RAM
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S4_S18 #(
|
|
.INIT_A(4'h0), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(18'h00000), // Value of output RAM registers on Port B at startup
|
|
.SRVAL_A(4'h0), // Port A output value upon SSR assertion
|
|
.SRVAL_B(18'h00000), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Port A Address 0 to 1023, Port B Address 0 to 255
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 1024 to 2047, Port B Address 256 to 511
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 2048 to 3071, Port B Address 512 to 767
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 3072 to 4095, Port B Address 768 to 1023
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
// Port A Address 0 to 1023, Port B Address 0 to 255
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 1024 to 2047, Port B Address 256 to 511
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 2048 to 3071, Port B Address 512 to 767
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 3072 to 4095, Port B Address 768 to 1023
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S4_S18_inst (
|
|
.DOA(DOA), // Port A 4-bit Data Output
|
|
.DOB(DOB), // Port B 16-bit Data Output
|
|
.DOPB(DOPB), // Port B 2-bit Parity Output
|
|
.ADDRA(ADDRA), // Port A 12-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 10-bit Address Input
|
|
.CLKA(CLKA), // Port A Clock
|
|
.CLKB(CLKB), // Port B Clock
|
|
.DIA(DIA), // Port A 4-bit Data Input
|
|
.DIB(DIB), // Port B 16-bit Data Input
|
|
.DIPB(DIPB), // Port-B 2-bit parity Input
|
|
.ENA(ENA), // Port A RAM Enable Input
|
|
.ENB(ENB), // Port B RAM Enable Input
|
|
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A Write Enable Input
|
|
.WEB(WEB) // Port B Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S4_S18_inst instantiation
|
|
</Template>
|
|
<Template label="4k/512 x 4/32 + 0/4 Parity bits (RAMB16_S4_S36)" treetype="template">
|
|
// RAMB16_S4_S36 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S4_S36_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S4_S36: Spartan-3/3E/3A/3AN/3AD 4k/512 x 4/32 + 0/4 Parity bits Dual-Port RAM
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S4_S36 #(
|
|
.INIT_A(4'h0), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup
|
|
.SRVAL_A(4'h0), // Port A output value upon SSR assertion
|
|
.SRVAL_B(36'h000000000), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Port A Address 0 to 1023, Port B Address 0 to 127
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 1024 to 2047, Port B Address 128 to 255
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 2048 to 3071, Port B Address 256 to 383
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 3072 to 4095, Port B Address 384 to 511
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
// Port A Address 0 to 1023, Port B Address 0 to 127
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 1024 to 2047, Port B Address 128 to 255
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 2048 to 3071, Port B Address 256 to 383
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 3072 to 4095, Port B Address 384 to 511
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S4_S36_inst (
|
|
.DOA(DOA), // Port A 4-bit Data Output
|
|
.DOB(DOB), // Port B 32-bit Data Output
|
|
.DOPB(DOPB), // Port B 4-bit Parity Output
|
|
.ADDRA(ADDRA), // Port A 12-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 9-bit Address Input
|
|
.CLKA(CLKA), // Port A Clock
|
|
.CLKB(CLKB), // Port B Clock
|
|
.DIA(DIA), // Port A 4-bit Data Input
|
|
.DIB(DIB), // Port B 32-bit Data Input
|
|
.DIPB(DIPB), // Port-B 4-bit parity Input
|
|
.ENA(ENA), // Port A RAM Enable Input
|
|
.ENB(ENB), // Port B RAM Enable Input
|
|
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A Write Enable Input
|
|
.WEB(WEB) // Port B Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S4_S36_inst instantiation
|
|
</Template>
|
|
<Template label="4k/2k x 4/8 + 0/1 Parity bit (RAMB16_S4_S9)" treetype="template">
|
|
// RAMB16_S4_S9 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S4_S9_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S4_S9: Spartan-3/3E/3A/3AN/3AD 4k/2k x 4/8 + 0/1 Parity bit Dual-Port RAM
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S4_S9 #(
|
|
.INIT_A(4'h0), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(9'h000), // Value of output RAM registers on Port B at startup
|
|
.SRVAL_A(4'h0), // Port A output value upon SSR assertion
|
|
.SRVAL_B(9'h000), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Port A Address 0 to 1023, Port B Address 0 to 511
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 1024 to 2047, Port B Address 512 to 1023
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 2048 to 3071, Port B Address 1024 to 1535
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 3072 to 4095, Port B Address 1536 to 2047
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
// Port B Address 0 to 511
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 512 to 1023
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 1024 to 1535
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 1536 to 2047
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S4_S9_inst (
|
|
.DOA(DOA), // Port A 4-bit Data Output
|
|
.DOB(DOB), // Port B 8-bit Data Output
|
|
.DOPB(DOPB), // Port B 1-bit Parity Output
|
|
.ADDRA(ADDRA), // Port A 12-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 11-bit Address Input
|
|
.CLKA(CLKA), // Port A Clock
|
|
.CLKB(CLKB), // Port B Clock
|
|
.DIA(DIA), // Port A 4-bit Data Input
|
|
.DIB(DIB), // Port B 8-bit Data Input
|
|
.DIPB(DIPB), // Port-B 1-bit parity Input
|
|
.ENA(ENA), // Port A RAM Enable Input
|
|
.ENB(ENB), // Port B RAM Enable Input
|
|
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A Write Enable Input
|
|
.WEB(WEB) // Port B Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S4_S9_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Arithmetic Functions" treetype="folder">
|
|
<Template label="18X18 Asynchronous Multiplier (MULT18X18)" treetype="template">
|
|
// MULT18X18 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MULT18X18_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MULT18X18: 18 x 18 signed asynchronous multiplier
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MULT18X18 MULT18X18_inst (
|
|
.P(P), // 36-bit multiplier output
|
|
.A(A), // 18-bit multiplier input
|
|
.B(B) // 18-bit multiplier input
|
|
);
|
|
|
|
// End of MULT18X18_inst instantiation
|
|
</Template>
|
|
<Template label="18X18 Synchronous Multiplier (MULT18X18S)" treetype="template">
|
|
// MULT18X18S : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MULT18X18S_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MULT18X18S: 18 x 18 signed synchronous multiplier
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MULT18X18S MULT18X18S_inst (
|
|
.P(P), // 36-bit multiplier output
|
|
.A(A), // 18-bit multiplier input
|
|
.B(B), // 18-bit multiplier input
|
|
.C(C), // Clock input
|
|
.CE(CE), // Clock enable input
|
|
.R(R) // Synchronous reset input
|
|
);
|
|
|
|
// End of MULT18X18S_inst instantiation
|
|
</Template>
|
|
<Template label="18X18 Cascadable Multiplier (MULT18X18SIO)" treetype="template">
|
|
// MULT18X18SIO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MULT18X18SIO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MULT18X18SIO: 18 x 18 cascadable, signed synchronous/asynchronous multiplier
|
|
// Spartan-3E/3A
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MULT18X18SIO #(
|
|
.AREG(1), // Enable the input registers on the A port (1=on, 0=off)
|
|
.BREG(1), // Enable the input registers on the B port (1=on, 0=off)
|
|
.B_INPUT("DIRECT"), // B cascade input "DIRECT" or "CASCADE"
|
|
.PREG(1) // Enable the input registers on the P port (1=on, 0=off)
|
|
) MULT18X18SIO_inst (
|
|
.BCOUT(BCOUT), // 18-bit cascade output
|
|
.P(P), // 36-bit multiplier output
|
|
.A(A), // 18-bit multiplier input
|
|
.B(B), // 18-bit multiplier input
|
|
.BCIN(BCIN), // 18-bit cascade input
|
|
.CEA(CEA), // Clock enable input for the A port
|
|
.CEB(CEB), // Clock enable input for the B port
|
|
.CEP(CEP), // Clock enable input for the P port
|
|
.CLK(CLK), // Clock input
|
|
.RSTA(RSTA), // Synchronous reset input for the A port
|
|
.RSTB(RSTB), // Synchronous reset input for the B port
|
|
.RSTP(RSTP) // Synchronous reset input for the P port
|
|
);
|
|
|
|
// End of MULT18X18SIO_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Config/BSCAN Components" treetype="folder">
|
|
<Template label="Simulate Configuration (SIM_CONFIG_S3A)" treetype="template">
|
|
// SIM_CONFIG_S3A : In order to incorporate this function into the testbench (not the design),
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SIM_CONFIG_S3A_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SIM_CONFIG_S3A: Behavioral Simulation-only Model of FPGA SelectMap Configuration
|
|
// Spartan-3A
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SIM_CONFIG_S3A #(
|
|
.DEVICE_ID(32'h00000000)
|
|
) SIM_CONFIG_S3A_inst (
|
|
.CSOB(CSOB), // 1-bit output chip select pin
|
|
.DONE(DONE), // 1-bit bi-directional Done pin
|
|
.CCLK(CCLK), // 1-bit input configuration clock
|
|
.D(D), // 8-bit bi-directional configuration data
|
|
.DCMLOCK(DCMLOCK), // 1-bit input DCM Lock
|
|
.CSIB(CSIB), // 1-bit input chip select
|
|
.INITB(INITB), // 1-bit bi-directional INIT status pin
|
|
.M(M), // 3-bit input Mode pins
|
|
.PROGB(PROGB), // 1-bit input Program pin
|
|
.RDWRB(RDWRB) // 1-bit input Read/write pin
|
|
);
|
|
|
|
// End of SIM_CONFIG_S3A_inst instantiation
|
|
</Template>
|
|
<Template label="Boundary Scan (BSCAN_SPARTAN3A)" treetype="template">
|
|
// BSCAN_SPARTAN3A : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BSCAN_SPARTAN3A_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BSCAN_SPARTAN3A: Boundary Scan primitive for connecting internal logic to
|
|
// JTAG interface.
|
|
// Spartan-3A
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BSCAN_SPARTAN3A BSCAN_SPARTAN3A_inst (
|
|
.CAPTURE(CAPTURE), // CAPTURE output from TAP controller
|
|
.DRCK1(DRCK1), // Data register output for USER1 functions
|
|
.DRCK2(DRCK2), // Data register output for USER2 functions
|
|
.RESET(RESET), // Reset output from TAP controller
|
|
.SEL1(SEL1), // USER1 active output
|
|
.SEL2(SEL2), // USER2 active output
|
|
.SHIFT(SHIFT), // SHIFT output from TAP controller
|
|
.TCK(TCK), // TCK output from TAP controller
|
|
.TDI(TDI), // TDI output from TAP controller
|
|
.TMS(TMS), // TMS output from TAP controller
|
|
.UPDATE(UPDATE), // UPDATE output from TAP controller
|
|
.TDO1(TDO1), // Data input for USER1 function
|
|
.TDO2(TDO2) // Data input for USER2 function
|
|
);
|
|
|
|
// End of BSCAN_SPARTAN3A_inst instantiation
|
|
</Template>
|
|
<Template label="Register Capture (CAPTURE_SPARTAN3A)" treetype="template">
|
|
// CAPTURE_SPARTAN3A : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (CAPTURE_SPARTAN3A_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// CAPTURE_SPARTAN3A: Register State Capture for Bitstream Readback
|
|
// Spartan-3A
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
CAPTURE_SPARTAN3A #(
|
|
.ONESHOT("TRUE") // "TRUE" or "FALSE"
|
|
) CAPTURE_SPARTAN3A_inst (
|
|
.CAP(CAP), // Capture input
|
|
.CLK(CLK) // Clock input
|
|
);
|
|
|
|
// End of CAPTURE_SPARTAN3A_inst instantiation
|
|
</Template>
|
|
<Template label="Internal Config Port (ICAP_SPARTAN3A)" treetype="template">
|
|
// ICAP_SPARTAN3A : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ICAP_SPARTAN3A_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ICAP_SPARTAN3A: Internal Configuration Access Port
|
|
// Spartan-3A
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ICAP_SPARTAN3A ICAP_SPARTAN3A_inst (
|
|
.BUSY(BUSY), // Busy output
|
|
.O(O), // 8-bit data output
|
|
.CE(CE), // Clock enable input
|
|
.CLK(CLK), // Clock input
|
|
.I(I), // 8-bit data input
|
|
.WRITE(WRITE) // Write input
|
|
);
|
|
|
|
// End of ICAP_SPARTAN3A_inst instantiation
|
|
</Template>
|
|
<Template label="Startup block (STARTUP_SPARTAN3A)" treetype="template">
|
|
// STARTUP_SPARTAN3A : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (STARTUP_SPARTAN3A_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// STARTUP_SPARTAN3A: Startup primitive for GSR, GTS or startup sequence
|
|
// control.
|
|
// Spartan-3A
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
STARTUP_SPARTAN3A STARTUP_SPARTAN3A_inst (
|
|
.CLK(CLK), // Clock input for start-up sequence
|
|
.GSR(GSR_PORT), // Global Set/Reset input (GSR cannot be used as a port name)
|
|
.GTS(GTS_PORT) // Global 3-state input (GTS cannot be used as a port name)
|
|
);
|
|
|
|
// End of STARTUP_SPARTAN3A_inst instantiation
|
|
</Template>
|
|
<Template label="Spartan-3AN SPI PROM Access (SPI_ACCESS)" treetype="template">
|
|
// SPI_ACCESS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SPI_ACCESS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SPI_ACCESS: Internal Logic Access to the Serial Peripheral
|
|
// Interface (SPI) PROM Data
|
|
// Spartan-3AN
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SPI_ACCESS #(
|
|
.SIM_DELAY_TYPE("SCALED"), // "ACCURATE" spec timing delays, "SCALED" shorten delays (faster sim)
|
|
.SIM_DEVICE("3S1400AN"), // "3S50AN", "3S200AN", "3S400AN", "3S700AN", "3S1400AN"
|
|
.SIM_FACTORY_ID(64'h0), // Specifies the Pre-programmed factory ID value
|
|
.SIM_MEM_FILE("NONE"), // Name/location of file containing memory contents
|
|
.SIM_USER_ID(64'h0) // Specifies the programmed User ID value
|
|
) SPI_ACCESS_inst (
|
|
.MISO(MISO), // Serial output data from SPI PROM
|
|
.CLK(CLK), // SPI PROM clock input
|
|
.CSB(CSB), // SPI PROM enable input
|
|
.MOSI(MOSI) // Serial input data to SPI PROM
|
|
);
|
|
|
|
// End of SPI_ACCESS_inst instantiation
|
|
</Template>
|
|
<Template label="DNA Access (DNA_PORT)" treetype="template">
|
|
// DNA_PORT : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (DNA_PORT_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// DNA_PORT: Access to the device-specific DNA value
|
|
// Spartan-3A, Virtex-6, Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
DNA_PORT #(
|
|
.SIM_DNA_VALUE(57'h000000000000000) // Specifies the unique DNA value
|
|
// for simulation test
|
|
) DNA_PORT_inst (
|
|
|
|
.DOUT(DOUT), // 1-bit DNA output data
|
|
.CLK(CLK), // 1-bit clock input
|
|
.DIN(DIN), // 1-bit user data input pin
|
|
.READ(READ), // 1-bit input, active high load DNA, active low read
|
|
.SHIFT(SHIFT) // 1-bit input, active high shift enable
|
|
);
|
|
|
|
// End of DNA_PORT_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="I/O Components" treetype="folder">
|
|
<SubFolder label="Input" treetype="folder">
|
|
<Template label="Single-ended Buffer with Dynamic Delay Adjust (IBUF_DLY_ADJ)" treetype="template">
|
|
// IBUF_DLY_ADJ : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUF_DLY_ADJ_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUF_DLY_ADJ: Dynamically Adjustable Delay, Single-ended Input Buffer
|
|
// Spartan-3A
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUF_DLY_ADJ #(
|
|
.DELAY_OFFSET("OFF"), // Enable Initial Delay Offset, "OFF" or "ON"
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
)IBUF_DLY_ADJ_inst (
|
|
.O(O), // Buffer output
|
|
.I(I), // Buffer input (connect directly to top-level port)
|
|
.S(S) // 3-bit buffer delay select input
|
|
);
|
|
|
|
// End of IBUF_DLY_ADJ_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer with Dynamic Delay Adjust (IBUFDS_DLY_ADJ)" treetype="template">
|
|
// IBUFDS_DLY_ADJ : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFDS_DLY_ADJ_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFDS_DLY_ADJ: Dynamically Adjustable Delay, Differential Input Buffer
|
|
// Spartan-3A
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFDS_DLY_ADJ #(
|
|
.DELAY_OFFSET("OFF"), // Enable Initial Delay Offset, "OFF" or "ON"
|
|
.DIFF_TERM("FALSE"), // Differential Termination
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
) IBUFDS_DLY_ADJ_inst (
|
|
.O(O), // Buffer output
|
|
.I(I), // Diff_p buffer input (connect directly to top-level port)
|
|
.IB(IB), // Diff_n buffer input (connect directly to top-level port)
|
|
.S(S) // 3-bit buffer delay select input
|
|
);
|
|
|
|
// End of IBUFDS_DLY_ADJ_inst instantiation
|
|
</Template>
|
|
<Template label="Single-ended Buffer (IBUF)" treetype="template">
|
|
// IBUF : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUF_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUF: Single-ended Input Buffer
|
|
// Spartan-3A
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUF #(
|
|
.IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for
|
|
// the buffer: "0"-"16" (Spartan-3A)
|
|
.IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input
|
|
// register: "AUTO", "0"-"8" (Spartan-3A)
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
)IBUF_inst (
|
|
.O(O), // Buffer output
|
|
.I(I) // Buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUF_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer (IBUFDS)" treetype="template">
|
|
// IBUFDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFDS: Differential Input Buffer
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFDS #(
|
|
.IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for
|
|
// the buffer: "0"-"16" (Spartan-3A)
|
|
.IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input
|
|
// register: "AUTO", "0"-"8" (Spartan-3A)
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
) IBUFDS_inst (
|
|
.O(O), // Buffer output
|
|
.I(I), // Diff_p buffer input (connect directly to top-level port)
|
|
.IB(IB) // Diff_n buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUFDS_inst instantiation
|
|
</Template>
|
|
<Template label="Single-ended Global Clock (IBUFG)" treetype="template">
|
|
// IBUFG : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFG_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFG: Single-ended global clock input buffer
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFG #(
|
|
.IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for
|
|
// the buffer: "0"-"16" (Spartan-3A)
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
) IBUFG_inst (
|
|
.O(O), // Clock buffer output
|
|
.I(I) // Clock buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUFG_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Global Clock (IBUFGDS)" treetype="template">
|
|
// IBUFGDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFGDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFGDS: Differential Global Clock Input Buffer
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFGDS #(
|
|
.IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for
|
|
// the buffer, "0"-"16" (Spartan-3A)
|
|
.DIFF_TERM("FALSE"), // Differential Termination
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
) IBUFGDS_inst (
|
|
.O(O), // Clock buffer output
|
|
.I(I), // Diff_p clock buffer input (connect directly to top-level port)
|
|
.IB(IB) // Diff_n clock buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUFGDS_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Output" treetype="folder">
|
|
<Template label="Single-ended Buffer (OBUF)" treetype="template">
|
|
// OBUF : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OBUF_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OBUF: Single-ended Output Buffer
|
|
// Spartan-3A
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OBUF #(
|
|
.DRIVE(12), // Specify the output drive strength
|
|
.IOSTANDARD("DEFAULT"), // Specify the output I/O standard
|
|
.SLEW("SLOW") // Specify the output slew rate
|
|
) OBUF_inst (
|
|
.O(O), // Buffer output (connect directly to top-level port)
|
|
.I(I) // Buffer input
|
|
);
|
|
|
|
// End of OBUF_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer (OBUFDS)" treetype="template">
|
|
|
|
// OBUFDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OBUFDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OBUFDS: Differential Output Buffer
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OBUFDS #(
|
|
.IOSTANDARD("DEFAULT") // Specify the output I/O standard
|
|
) OBUFDS_inst (
|
|
.O(O), // Diff_p output (connect directly to top-level port)
|
|
.OB(OB), // Diff_n output (connect directly to top-level port)
|
|
.I(I) // Buffer input
|
|
);
|
|
|
|
// End of OBUFDS_inst instantiation
|
|
</Template>
|
|
<Template label="Single-ended 3-state Buffer (OBUFT)" treetype="template">
|
|
// OBUFT : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OBUFT_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OBUFT: Single-ended 3-state Output Buffer
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OBUFT #(
|
|
.DRIVE(12), // Specify the output drive strength
|
|
.IOSTANDARD("DEFAULT"), // Specify the output I/O standard
|
|
.SLEW("SLOW") // Specify the output slew rate
|
|
) OBUFT_inst (
|
|
.O(O), // Buffer output (connect directly to top-level port)
|
|
.I(I), // Buffer input
|
|
.T(T) // 3-state enable input
|
|
);
|
|
|
|
// End of OBUFT_inst instantiation
|
|
</Template>
|
|
<Template label="Differential 3-state Buffer (OBUFTDS)" treetype="template">
|
|
// OBUFTDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OBUFTDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OBUFTDS: Differential 3-state Output Buffer
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OBUFTDS #(
|
|
.IOSTANDARD("DEFAULT") // Specify the output I/O standard
|
|
) OBUFTDS_inst (
|
|
.O(O), // Diff_p output (connect directly to top-level port)
|
|
.OB(OB), // Diff_n output (connect directly to top-level port)
|
|
.I(I), // Buffer input
|
|
.T(T) // 3-state enable input
|
|
);
|
|
|
|
// End of OBUFTDS_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Bi-directional" treetype="folder">
|
|
<Template label="Single-ended Buffer (IOBUF)" treetype="template">
|
|
// IOBUF : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IOBUF_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IOBUF: Single-ended Bi-directional Buffer
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IOBUF #(
|
|
.DRIVE(12), // Specify the output drive strength
|
|
.IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for the buffer,
|
|
// "0"-"16" (Spartan-3A only)
|
|
.IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input register,
|
|
// "AUTO", "0"-"8" (Spartan-3A only)
|
|
.IOSTANDARD("DEFAULT"), // Specify the I/O standard
|
|
.SLEW("SLOW") // Specify the output slew rate
|
|
) IOBUF_inst (
|
|
.O(O), // Buffer output
|
|
.IO(IO), // Buffer inout port (connect directly to top-level port)
|
|
.I(I), // Buffer input
|
|
.T(T) // 3-state enable input, high=input, low=output
|
|
);
|
|
|
|
// End of IOBUF_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer (IOBUFDS)" treetype="template">
|
|
// IOBUFDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IOBUFDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IOBUFDS: Differential Bi-directional Buffer
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IOBUFDS #(
|
|
.IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for the buffer,
|
|
// "0"-"16" (Spartan-3A only)
|
|
.IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input register,
|
|
// "AUTO", "0"-"8" (Spartan-3A only)
|
|
.IOSTANDARD("DEFAULT") // Specify the I/O standard
|
|
) IOBUFDS_inst (
|
|
.O(O), // Buffer output
|
|
.IO(IO), // Diff_p inout (connect directly to top-level port)
|
|
.IOB(IOB), // Diff_n inout (connect directly to top-level port)
|
|
.I(I), // Buffer input
|
|
.T(T) // 3-state enable input, high=input, low=output
|
|
);
|
|
|
|
// End of IOBUFDS_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Weak drivers" treetype="folder">
|
|
<Template label="PULLUP" treetype="template">
|
|
// PULLUP : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (PULLUP_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design.
|
|
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// PULLUP: I/O Buffer Weak Pull-up
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
PULLUP PULLUP_inst (
|
|
.O(O) // Pullup output (connect directly to top-level port)
|
|
);
|
|
|
|
// End of PULLUP_inst instantiation
|
|
</Template>
|
|
<Template label="PULLDOWN" treetype="template">
|
|
// PULLDOWN : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (PULLDOWN_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// PULLDOWN: I/O Buffer Weak Pull-down
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
PULLDOWN PULLDOWN_inst (
|
|
.O(O) // Pulldown output (connect directly to top-level port)
|
|
);
|
|
|
|
// End of PULLDOWN_inst instantiation
|
|
</Template>
|
|
<Template label="KEEPER" treetype="template">
|
|
// KEEPER : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (KEEPER_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// KEEPER: I/O Buffer Weak Keeper
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
KEEPER KEEPER_inst (
|
|
.O(O) // Keeper output (connect directly to top-level port)
|
|
);
|
|
|
|
// End of KEEPER_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="DDR Registers" treetype="folder">
|
|
<Template label="Input DDR Register (IDDR2)" treetype="template">
|
|
// IDDR2 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IDDR2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IDDR2: Input Double Data Rate Input Register with Set, Reset
|
|
// and Clock Enable.
|
|
// Spartan-3E/3A/6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IDDR2 #(
|
|
.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
|
|
.INIT_Q0(1'b0), // Sets initial state of the Q0 output to 1'b0 or 1'b1
|
|
.INIT_Q1(1'b0), // Sets initial state of the Q1 output to 1'b0 or 1'b1
|
|
.SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
|
|
) IDDR2_inst (
|
|
.Q0(Q0), // 1-bit output captured with C0 clock
|
|
.Q1(Q1), // 1-bit output captured with C1 clock
|
|
.C0(C0), // 1-bit clock input
|
|
.C1(C1), // 1-bit clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.D(D), // 1-bit DDR data input
|
|
.R(R), // 1-bit reset input
|
|
.S(S) // 1-bit set input
|
|
);
|
|
|
|
// End of IDDR2_inst instantiation
|
|
</Template>
|
|
<Template label="Output DDR Register (ODDR2)" treetype="template">
|
|
// ODDR2 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ODDR2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ODDR2: Output Double Data Rate Output Register with Set, Reset
|
|
// and Clock Enable.
|
|
// Spartan-3E/3A/6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ODDR2 #(
|
|
.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
|
|
.INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1
|
|
.SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
|
|
) ODDR2_inst (
|
|
.Q(Q), // 1-bit DDR output data
|
|
.C0(C0), // 1-bit clock input
|
|
.C1(C1), // 1-bit clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.D0(D0), // 1-bit data input (associated with C0)
|
|
.D1(D1), // 1-bit data input (associated with C1)
|
|
.R(R), // 1-bit reset input
|
|
.S(S) // 1-bit set input
|
|
);
|
|
|
|
// End of ODDR2_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Registers & Latches" treetype="folder">
|
|
<SubFolder label="Double Data Rate (DDR)" treetype="folder">
|
|
<Template label="Input DDR Register (IDDR2)" treetype="template">
|
|
// IDDR2 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IDDR2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IDDR2: Input Double Data Rate Input Register with Set, Reset
|
|
// and Clock Enable.
|
|
// Spartan-3E/3A/6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IDDR2 #(
|
|
.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
|
|
.INIT_Q0(1'b0), // Sets initial state of the Q0 output to 1'b0 or 1'b1
|
|
.INIT_Q1(1'b0), // Sets initial state of the Q1 output to 1'b0 or 1'b1
|
|
.SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
|
|
) IDDR2_inst (
|
|
.Q0(Q0), // 1-bit output captured with C0 clock
|
|
.Q1(Q1), // 1-bit output captured with C1 clock
|
|
.C0(C0), // 1-bit clock input
|
|
.C1(C1), // 1-bit clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.D(D), // 1-bit DDR data input
|
|
.R(R), // 1-bit reset input
|
|
.S(S) // 1-bit set input
|
|
);
|
|
|
|
// End of IDDR2_inst instantiation
|
|
</Template>
|
|
<Template label="Output DDR Register (ODDR2)" treetype="template">
|
|
// ODDR2 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ODDR2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ODDR2: Output Double Data Rate Output Register with Set, Reset
|
|
// and Clock Enable.
|
|
// Spartan-3E/3A/6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ODDR2 #(
|
|
.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
|
|
.INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1
|
|
.SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
|
|
) ODDR2_inst (
|
|
.Q(Q), // 1-bit DDR output data
|
|
.C0(C0), // 1-bit clock input
|
|
.C1(C1), // 1-bit clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.D0(D0), // 1-bit data input (associated with C0)
|
|
.D1(D1), // 1-bit data input (associated with C1)
|
|
.R(R), // 1-bit reset input
|
|
.S(S) // 1-bit set input
|
|
);
|
|
|
|
// End of ODDR2_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Single Data Rate" treetype="folder">
|
|
<Template label="Posedge D-FF w/ Async Clear, and CE (FDCE)" treetype="template">
|
|
// FDCE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FDCE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FDCE: Single Data Rate D Flip-Flop with Asynchronous Clear and
|
|
// Clock Enable (posedge clk).
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FDCE #(
|
|
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
|
|
) FDCE_inst (
|
|
.Q(Q), // Data output
|
|
.C(C), // Clock input
|
|
.CE(CE), // Clock enable input
|
|
.CLR(CLR), // Asynchronous clear input
|
|
.D(D) // Data input
|
|
);
|
|
|
|
// End of FDCE_inst instantiation
|
|
</Template>
|
|
<Template label="Posedge D-FF w/ Async Clear, Set and CE (FDCPE)" treetype="template">
|
|
// FDCPE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FDCPE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FDCPE: Single Data Rate D Flip-Flop with Asynchronous Clear, Set and
|
|
// Clock Enable (posedge clk).
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FDCPE #(
|
|
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
|
|
) FDCPE_inst (
|
|
.Q(Q), // Data output
|
|
.C(C), // Clock input
|
|
.CE(CE), // Clock enable input
|
|
.CLR(CLR), // Asynchronous clear input
|
|
.D(D), // Data input
|
|
.PRE(PRE) // Asynchronous set input
|
|
);
|
|
|
|
// End of FDCPE_inst instantiation
|
|
</Template>
|
|
<Template label="Posedge D-FF w/ Sync Clear, Set and CE (FDRSE)" treetype="template">
|
|
// FDRSE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FDCRS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FDRSE: Single Data Rate D Flip-Flop with Synchronous Clear, Set and
|
|
// Clock Enable (posedge clk).
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FDRSE #(
|
|
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
|
|
) FDRSE_inst (
|
|
.Q(Q), // Data output
|
|
.C(C), // Clock input
|
|
.CE(CE), // Clock enable input
|
|
.D(D), // Data input
|
|
.R(R), // Synchronous reset input
|
|
.S(S) // Synchronous set input
|
|
);
|
|
|
|
// End of FDRSE_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Transparent Latch" treetype="folder">
|
|
<Template label="Latch with Async Reset, Set and Gate Enable (LDCPE)" treetype="template">
|
|
// LDCPE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LDCPE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LDCPE: Transparent latch with Asynchronous Reset, Preset and
|
|
// Gate Enable.
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LDCPE #(
|
|
.INIT(1'b0) // Initial value of latch (1'b0 or 1'b1)
|
|
) LDCPE_inst (
|
|
.Q(Q), // Data output
|
|
.CLR(CLR), // Asynchronous clear/reset input
|
|
.D(D), // Data input
|
|
.G(G), // Gate input
|
|
.GE(GE), // Gate enable input
|
|
.PRE(PRE) // Asynchronous preset/set input
|
|
);
|
|
|
|
// End of LDCPE_inst instantiation
|
|
</Template>
|
|
<Template label="Latch with Async Reset and Gate Enable (LDCE)" treetype="template">
|
|
// LDCE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LDCE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LDCE: Transparent latch with Asynchronous Reset and Gate Enable.
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LDCE #(
|
|
.INIT(1'b0) // Initial value of latch (1'b0 or 1'b1)
|
|
) LDCE_inst (
|
|
.Q(Q), // Data output
|
|
.CLR(CLR), // Asynchronous clear/reset input
|
|
.D(D), // Data input
|
|
.G(G), // Gate input
|
|
.GE(GE) // Gate enable input
|
|
);
|
|
|
|
// End of LDCE_inst instantiation
|
|
</Template>
|
|
<Template label="Latch with Async Set and Gate Enable (LDPE)" treetype="template">
|
|
// LDPE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LDPE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LDPE: Transparent latch with Asynchronous Preset and Gate Enable.
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LDPE #(
|
|
.INIT(1'b0) // Initial value of latch (1'b0 or 1'b1)
|
|
) LDPE_inst (
|
|
.Q(Q), // Data output
|
|
.PRE(PRE), // Asynchronous preset/set input
|
|
.D(D), // Data input
|
|
.G(G), // Gate input
|
|
.GE(GE) // Gate enable input
|
|
);
|
|
|
|
// End of LDPE_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Spartan-3E" treetype="folder">
|
|
<SubFolder label="Slice/CLB Primitives" treetype="folder">
|
|
<SubFolder label="Carry-Chain" treetype="folder">
|
|
<Template label="MUXCY" treetype="template">
|
|
// MUXCY : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXCY_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs and
|
|
// : and outputs of this primitive should be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXCY: Carry-Chain MUX with general output
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXCY MUXCY_inst (
|
|
.O(O), // Carry output signal
|
|
.CI(CI), // Carry input signal
|
|
.DI(DI), // Data input signal
|
|
.S(S) // MUX select, tie to '1' or LUT4 out
|
|
);
|
|
|
|
// End of MUXCY_inst instantiation
|
|
</Template>
|
|
<Template label="MUXCY_L" treetype="template">
|
|
// MUXCY_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXCY_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXCY_L: Carry-Chain MUX with local output
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXCY_L MUXCY_L_inst (
|
|
.LO(LO), // Carry local output signal
|
|
.CI(CI), // Carry input signal
|
|
.DI(DI), // Data input signal
|
|
.S(S) // MUX select, tie to '1' or LUT4 out
|
|
);
|
|
|
|
// End of MUXCY_L_inst instantiation
|
|
</Template>
|
|
<Template label="MUXCY_D" treetype="template">
|
|
// MUXCY_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXCY_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXCY_D: Carry-Chain MUX with general and local outputs
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXCY_D MUXCY_D_inst (
|
|
.LO(LO), // Carry local output signal
|
|
.O(O), // Carry general output signal
|
|
.CI(CI), // Carry input signal
|
|
.DI(DI), // Data input signal
|
|
.S(S) // MUX select, tie to '1' or LUT4 out
|
|
);
|
|
|
|
// End of MUXCY_D_inst instantiation
|
|
</Template>
|
|
<Template label="XORCY" treetype="template">
|
|
// XORCY : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (XORCY_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// XORCY: Carry-Chain XOR-gate with general output
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
XORCY XORCY_inst (
|
|
.O(O), // XOR output signal
|
|
.CI(CI), // Carry input signal
|
|
.LI(LI) // LUT4 input signal
|
|
);
|
|
|
|
// End of XORCY_inst instantiation
|
|
</Template>
|
|
<Template label="XORCY_L" treetype="template">
|
|
// XORCY_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (XORCY_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// XORCY_L: Carry-Chain XOR-gate with local (direct-connect) output
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
XORCY_L XORCY_L_inst (
|
|
.LO(LO), // XOR local output signal
|
|
.CI(CI), // Carry input signal
|
|
.LI(LI) // LUT4 input signal
|
|
);
|
|
|
|
// End of XORCY_L_inst instantiation
|
|
</Template>
|
|
<Template label="XORCY_D" treetype="template">
|
|
// XORCY_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (XORCY_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// XORCY_D: Carry-Chain XOR-gate with local and general outputs
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
XORCY_D XORCY_D_inst (
|
|
.LO(LO), // XOR local output signal
|
|
.O(O), // XOR general output signal
|
|
.CI(CI), // Carry input signal
|
|
.LI(LI) // LUT4 input signal
|
|
);
|
|
|
|
// End of XORCY_D_inst instantiation
|
|
</Template>
|
|
<Template label="MULT_AND" treetype="template">
|
|
// MULT_AND : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MULT_AND_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MULT_AND: 2-input AND gate connected to Carry chain
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MULT_AND MULT_AND_inst (
|
|
.LO(LO), // MULT_AND output (connect to MUXCY DI)
|
|
.I0(I0), // MULT_AND data[0] input
|
|
.I1(I1) // MULT_AND data[1] input
|
|
);
|
|
|
|
// End of MULT_AND_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="MUXFx" treetype="folder">
|
|
<Template label="MUXF5" treetype="template">
|
|
// MUXF5 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF5_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF5: Slice MUX to tie two LUT4's together with general output
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF5 MUXF5_inst (
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie directly to the output of LUT4)
|
|
.I1(I1), // Input (tie directoy to the output of LUT4)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF5_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF5_L" treetype="template">
|
|
// MUXF5_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF5_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF5_L: Slice MUX to tie two LUT4's together with local output
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF5_L MUXF5_L_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.I0(I0), // Input (tie directly to the output of LUT4)
|
|
.I1(I1), // Input (tie directoy to the output of LUT4)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF5_L_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF5_D" treetype="template">
|
|
// MUXF5_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF5_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF5_D: Slice MUX to tie two LUT4's together with general and local outputs
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF5_D MUXF5_D_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie directly to the output of LUT4)
|
|
.I1(I1), // Input (tie directoy to the output of LUT4)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF5_D_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF6" treetype="template">
|
|
// MUXF6 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF6_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF6: CLB MUX to tie two MUXF5's together with general output
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF6 MUXF6_inst (
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie to MUXF5 LO out)
|
|
.I1(I1), // Input (tie to MUXF5 LO out)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF6_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF6_L" treetype="template">
|
|
// MUXF6_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF6_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF6_L: CLB MUX to tie two MUXF5's together with local output
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF6_L MUXF6_L_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.I0(I0), // Input (tie to MUXF5 LO out)
|
|
.I1(I1), // Input (tie to MUXF5 LO out)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF6_L_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF6_D" treetype="template">
|
|
// MUXF6_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF6_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF6_D: CLB MUX to tie two MUXF5's together with general and local outputs
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF6_D MUXF6_D_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie to MUXF5 LO out)
|
|
.I1(I1), // Input (tie to MUXF5 LO out)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF6_D_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF7" treetype="template">
|
|
// MUXF7 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF7_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF7: CLB MUX to tie two MUXF6's together with general output
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF7 MUXF7_inst (
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie to MUXF6 LO out or LUT6 O6 pin)
|
|
.I1(I1), // Input (tie to MUXF6 LO out or LUT6 O6 pin)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF7_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF7_L" treetype="template">
|
|
// MUXF7_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF7_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF7_L: CLB MUX to tie two MUXF6's together with local output
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF7_L MUXF7_L_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.I0(I0), // Input (tie to MUXF6 LO out or LUT6 O6 pin)
|
|
.I1(I1), // Input (tie to MUXF6 LO out or LUT6 O6 pin)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF7_L_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF7_D" treetype="template">
|
|
// MUXF7_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF7_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF7_D: CLB MUX to tie two MUXF6's together with general and local outputs
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF7_D MUXF7_D_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie to MUXF6 LO out or LUT6 O6 pin)
|
|
.I1(I1), // Input (tie to MUXF6 LO out or LUT6 O6 pin)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF7_D_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF8" treetype="template">
|
|
// MUXF8 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF8_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF8: CLB MUX to tie two MUXF7's together with general output
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF8 MUXF8_inst (
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie to MUXF7 LO out)
|
|
.I1(I1), // Input (tie to MUXF7 LO out)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF8_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF8_L" treetype="template">
|
|
// MUXF8_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF8_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF8_L: CLB MUX to tie two MUXF7's together with local output
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF8_L MUXF8_L_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.I0(I0), // Input (tie to MUXF7 LO out)
|
|
.I1(I1), // Input (tie to MUXF7 LO out)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF8_L_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF8_D" treetype="template">
|
|
// MUXF8_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF8_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF8_D: CLB MUX to tie two MUXF7's together with general and local outputs
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF8_D MUXF8_D_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie to MUXF7 LO out)
|
|
.I1(I1), // Input (tie to MUXF7 LO out)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF8_D_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="LUTs" treetype="folder">
|
|
<SubFolder label="Info" treetype="folder">
|
|
<Template label="Info (LUT INIT)" treetype="template">
|
|
// The INIT parameter for the FPGA LUT primitive is what gives the LUT its
|
|
// logical value. By default this value is zero thus driving the output to a
|
|
// zero regardless of the input values (acting as a ground) however in most
|
|
// cases an new INIT value must be determined in order to specify the logic
|
|
// function for the LUT primitive. There are a few methods in which the LUT
|
|
// value can be determined and two of those methods will be discussed here.
|
|
//
|
|
// The Truth Table Method
|
|
// ----------------------
|
|
//
|
|
// A common method to determine the desired INIT value for a LUT is using a
|
|
// truth table. To do so, simply create a binary truth table of all possible
|
|
// inputs, specify the desired logic value of the output and then create the
|
|
// INIT string from those output values. An example is shown below:
|
|
//
|
|
// Example of determining an XOR INIT equation for a LUT4:
|
|
//
|
|
// _________________
|
|
// | I3 I2 I1 I0 | O |
|
|
// |-----------------|
|
|
// | 0 0 0 0 | 0 |\
|
|
// | 0 0 0 1 | 1 | \ = 4'b0110 = 4'h6 ---------------+
|
|
// | 0 0 1 0 | 1 | / |
|
|
// | 0 0 1 1 | 0 |/ |
|
|
// |-------------|---| |
|
|
// | 0 1 0 0 | 1 |\ |
|
|
// | 0 1 0 1 | 0 | \ = 4'b1001 = 4'h9 |
|
|
// | 0 1 1 0 | 0 | / |
|
|
// | 0 1 1 1 | 1 |/ |
|
|
// |-------------|---| INIT = 16'h6996
|
|
// | 1 0 0 0 | 1 |\ |
|
|
// | 1 0 0 1 | 0 | \ = 4'b0110 = 4'h9 |
|
|
// | 1 0 1 0 | 0 | / |
|
|
// | 1 0 1 1 | 1 |/ |
|
|
// |-------------|---| |
|
|
// | 1 1 0 0 | 0 |\ |
|
|
// | 1 1 0 1 | 1 | \ = 4'b1001 = 4'h6 ------------+
|
|
// | 1 1 1 0 | 1 | /
|
|
// | 1 1 1 1 | 0 |/
|
|
// -------------------
|
|
//
|
|
// Example of determining a 3-input AND gate:
|
|
//
|
|
// ______________
|
|
// | I2 I1 I0 | O |
|
|
// |--------------|
|
|
// | 0 0 0 | 0 |\
|
|
// | 0 0 1 | 0 | \ = 4'b0000 = 4'h0 --------------+
|
|
// | 0 1 0 | 0 | / |
|
|
// | 0 1 1 | 0 |/ |
|
|
// |----------|---| INIT = 8'h80
|
|
// | 1 0 0 | 0 |\ |
|
|
// | 1 0 1 | 0 | \ = 4'b1000 = 4'h8 -------------+
|
|
// | 1 1 0 | 0 | /
|
|
// | 1 1 1 | 1 |/
|
|
// ----------------
|
|
//
|
|
// The Equation Method
|
|
// -------------------
|
|
//
|
|
// Another method to determine the LUT value is to define parameters for each
|
|
// input to the LUT that correspond to their listed truth value and use those to
|
|
// build the logic equation you are after. This method is easier to understand
|
|
// once you have grasped the concept and more self-documenting that the above
|
|
// method however does require the code to first specify the appropriate
|
|
// parameters. See the example below.
|
|
//
|
|
// Example of specifying the equation (A and B) or (C and D) for a LUT4:
|
|
//
|
|
// The forllowing parameters are defined to allow for
|
|
// equation-based INIT specification.
|
|
parameter I0 = 16'haaaa;
|
|
parameter I1 = 16'hcccc;
|
|
parameter I2 = 16'hf0f0;
|
|
parameter I3 = 16'hff00;
|
|
|
|
// LUT4: 4-input Look-Up Table with general output
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT4 #(
|
|
.INIT((I0&I1)|(I2&I3)) // Specify LUT Contents
|
|
) LUT4_inst (
|
|
.O(O_LUT), // LUT general output
|
|
.I0(A), // LUT input
|
|
.I1(B), // LUT input
|
|
.I2(C), // LUT input
|
|
.I3(D) // LUT input
|
|
);
|
|
|
|
// End of LUT4_inst instantiation
|
|
|
|
// With the parameters specifying all possible cases for the truth table, a
|
|
// Verilog equation can be written to determine the end INIT value.
|
|
</Template>
|
|
<SubFolder label="INIT Parameters" treetype="folder">
|
|
<Template label="LUT1" treetype="template">
|
|
// The forllowing parameter is defined to allow for
|
|
// equation-based INIT specification for a LUT1.
|
|
parameter I0 = 2'b10;
|
|
</Template>
|
|
<Template label="LUT2" treetype="template">
|
|
// The forllowing parameters are defined to allow for
|
|
// equation-based INIT specification for a LUT2.
|
|
parameter I0 = 4'ha;
|
|
parameter I1 = 4'hc;
|
|
</Template>
|
|
<Template label="LUT3" treetype="template">
|
|
// The forllowing parameters are defined to allow for
|
|
// equation-based INIT specification for a LUT3.
|
|
parameter I0 = 8'haa;
|
|
parameter I1 = 8'hcc;
|
|
parameter I2 = 8'hf0;
|
|
</Template>
|
|
<Template label="LUT4" treetype="template">
|
|
// The forllowing parameters are defined to allow for
|
|
// equation-based INIT specification for a LUT4.
|
|
parameter I0 = 16'haaaa;
|
|
parameter I1 = 16'hcccc;
|
|
parameter I2 = 16'hf0f0;
|
|
parameter I3 = 16'hff00;
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="INIT Truth Tables" treetype="folder">
|
|
<Template label="LUT1" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT1
|
|
// ________
|
|
// | I0 | O |
|
|
// |--------|
|
|
// | 0 | ? |\
|
|
// | 1 | ? |/ = 2'b??
|
|
// ----------
|
|
</Template>
|
|
<Template label="LUT2" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT2
|
|
// ______________
|
|
// | I2 I1 I0 | O |
|
|
// |--------------|
|
|
// | 0 0 0 | ? |\
|
|
// | 0 0 1 | ? | \ = INIT = 4'b???? = 4'h?
|
|
// | 0 1 0 | ? | /
|
|
// | 0 1 1 | ? |/
|
|
// ---------- ---
|
|
</Template>
|
|
<Template label="LUT3" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT3
|
|
// ______________
|
|
// | I2 I1 I0 | O |
|
|
// |--------------|
|
|
// | 0 0 0 | ? |\
|
|
// | 0 0 1 | ? | \ = 4'b???? = 4'h? --------------+
|
|
// | 0 1 0 | ? | / |
|
|
// | 0 1 1 | ? |/ |
|
|
// |----------|---| INIT = 8'h??
|
|
// | 1 0 0 | ? |\ |
|
|
// | 1 0 1 | ? | \ = 4'b???? = 4'h? -------------+
|
|
// | 1 1 0 | ? | /
|
|
// | 1 1 1 | ? |/
|
|
// ----------------
|
|
</Template>
|
|
<Template label="LUT4" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT4
|
|
// _________________
|
|
// | I3 I2 I1 I0 | O |
|
|
// |-----------------|
|
|
// | 0 0 0 0 | ? |\
|
|
// | 0 0 0 1 | ? | \ = 4'b???? = 4'h? ---------------+
|
|
// | 0 0 1 0 | ? | / |
|
|
// | 0 0 1 1 | ? |/ |
|
|
// |-------------|---| |
|
|
// | 0 1 0 0 | ? |\ |
|
|
// | 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 1 0 | ? | / |
|
|
// | 0 1 1 1 | ? |/ |
|
|
// |-------------|---| INIT = 16'h????
|
|
// | 1 0 0 0 | ? |\ |
|
|
// | 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 1 0 | ? | / |
|
|
// | 1 0 1 1 | ? |/ |
|
|
// |-------------|---| |
|
|
// | 1 1 0 0 | ? |\ |
|
|
// | 1 1 0 1 | ? | \ = 4'b???? = 4'h? ------------+
|
|
// | 1 1 1 0 | ? | /
|
|
// | 1 1 1 1 | ? |/
|
|
// -------------------
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<Template label="LUT4" treetype="template">
|
|
// LUT4 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT4_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT4: 4-input Look-Up Table with general output
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT4 #(
|
|
.INIT(16'h0000) // Specify LUT Contents
|
|
) LUT4_inst (
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3) // LUT input
|
|
);
|
|
|
|
// End of LUT4_inst instantiation
|
|
</Template>
|
|
<Template label="LUT4_L" treetype="template">
|
|
// LUT4_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT4_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT4_L: 4-input Look-Up Table with local output
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT4_L #(
|
|
.INIT(16'h0000) // Specify LUT Contents
|
|
) LUT4_L_inst (
|
|
.LO(LO), // LUT local output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3) // LUT input
|
|
);
|
|
|
|
// End of LUT4_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT4_D" treetype="template">
|
|
// LUT4_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT4_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT4_D: 4-input Look-Up Table with general and local outputs
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT4_D #(
|
|
.INIT(16'h0000) // Specify LUT Contents
|
|
) LUT4_D_inst (
|
|
.LO(LO), // LUT local output
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3) // LUT input
|
|
);
|
|
|
|
// End of LUT4_D_inst instantiation
|
|
</Template>
|
|
<Template label="LUT3" treetype="template">
|
|
// LUT3 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT3_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT3: 3-input Look-Up Table with general output
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT3 #(
|
|
.INIT(8'h00) // Specify LUT Contents
|
|
) LUT3_inst (
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2) // LUT input
|
|
);
|
|
|
|
// End of LUT3_inst instantiation
|
|
</Template>
|
|
<Template label="LUT3_L" treetype="template">
|
|
// LUT3_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT3_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT3_L: 3-input Look-Up Table with local output
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT3_L #(
|
|
.INIT(8'h00) // Specify LUT Contents
|
|
) LUT3_L_inst (
|
|
.LO(LO), // LUT local output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2) // LUT input
|
|
);
|
|
|
|
// End of LUT3_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT3_D" treetype="template">
|
|
// LUT3_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT3_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT3_D: 3-input Look-Up Table with general and local outputs
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT3_D #(
|
|
.INIT(8'h00) // Specify LUT Contents
|
|
) LUT3_D_inst (
|
|
.LO(LO), // LUT local output
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2) // LUT input
|
|
);
|
|
|
|
// End of LUT3_D_inst instantiation
|
|
</Template>
|
|
<Template label="LUT2" treetype="template">
|
|
// LUT2 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT2: 2-input Look-Up Table with general output
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT2 #(
|
|
.INIT(4'h0) // Specify LUT Contents
|
|
) LUT2_inst (
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1) // LUT input
|
|
);
|
|
|
|
// End of LUT2_inst instantiation
|
|
</Template>
|
|
<Template label="LUT2_L" treetype="template">
|
|
// LUT2_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT2_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT2_L: 2-input Look-Up Table with local output
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT2_L #(
|
|
.INIT(4'h0) // Specify LUT Contents
|
|
) LUT2_L_inst (
|
|
.LO(LO), // LUT local output
|
|
.I0(I0), // LUT input
|
|
.I1(I1) // LUT input
|
|
);
|
|
|
|
// End of LUT2_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT2_D" treetype="template">
|
|
// LUT2_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT2_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT2_D: 2-input Look-Up Table with general and local outputs
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT2_D #(
|
|
.INIT(4'h0) // Specify LUT Contents
|
|
) LUT2_D_inst (
|
|
.LO(LO), // LUT local output
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1) // LUT input
|
|
);
|
|
|
|
// End of LUT2_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT1" treetype="template">
|
|
// LUT1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT1: 1-input Look-Up Table with general output
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT1 #(
|
|
.INIT(2'b00) // Specify LUT Contents
|
|
) LUT1_inst (
|
|
.O(O), // LUT general output
|
|
.I0(I0) // LUT input
|
|
);
|
|
|
|
// End of LUT1_inst instantiation
|
|
</Template>
|
|
<Template label="LUT1_L" treetype="template">
|
|
// LUT1_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT1_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT1_L: 1-input Look-Up Table with local output
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT1_L #(
|
|
.INIT(2'b00) // Specify LUT Contents
|
|
) LUT1_L_inst (
|
|
.LO(LO), // LUT local output
|
|
.I0(I0) // LUT input
|
|
);
|
|
|
|
// End of LUT1_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT1_D" treetype="template">
|
|
// LUT1_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT1_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT1_D: 1-input Look-Up Table with general and local outputs
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT1_D #(
|
|
.INIT(2'b00) // Specify LUT Contents
|
|
) LUT1_D_inst (
|
|
.LO(LO), // LUT local output
|
|
.O(O), // LUT general output
|
|
.I0(I0) // LUT input
|
|
);
|
|
|
|
// End of LUT1_D_inst instantiation
|
|
</Template>
|
|
<Template label="LUT Local Connect Buffer (BUFCF)" treetype="template">
|
|
// BUFCF : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFCF_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFCF: Fast connect buffer used to connect the outputs of the LUTs
|
|
// and some dedicated logic directly to the input of another LUT.
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFCF BUFCF_inst (
|
|
.O(O), // Connect to the output of a LUT
|
|
.I(I) // Connect to the input of a LUT
|
|
);
|
|
|
|
// End of BUFCF_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Shift Register LUT" treetype="folder">
|
|
<SubFolder label="Non-cascadable" treetype="folder">
|
|
<Template label="16-bit posedge SR (SRL16)" treetype="template">
|
|
// SRL16 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SRL16_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SRL16: 16-bit shift register LUT operating on posedge of clock
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SRL16 #(
|
|
.INIT(16'h0000) // Initial Value of Shift Register
|
|
) SRL16_inst (
|
|
.Q(Q), // SRL data output
|
|
.A0(A0), // Select[0] input
|
|
.A1(A1), // Select[1] input
|
|
.A2(A2), // Select[2] input
|
|
.A3(A3), // Select[3] input
|
|
.CLK(CLK), // Clock input
|
|
.D(D) // SRL data input
|
|
);
|
|
|
|
// End of SRL16_inst instantiation
|
|
</Template>
|
|
<Template label="16-bit negedge SR (SRL16_1)" treetype="template">
|
|
// SRL16_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SRL16_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SRL16_1: 16-bit shift register LUT operating on negedge of clock
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SRL16_1 #(
|
|
.INIT(16'h0000) // Initial Value of Shift Register
|
|
) SRL16_1_inst (
|
|
.Q(Q), // SRL data output
|
|
.A0(A0), // Select[0] input
|
|
.A1(A1), // Select[1] input
|
|
.A2(A2), // Select[2] input
|
|
.A3(A3), // Select[3] input
|
|
.CLK(CLK), // Clock input
|
|
.D(D) // SRL data input
|
|
);
|
|
|
|
// End of SRL16_1_inst instantiation
|
|
</Template>
|
|
<Template label="16-bit w/ CE posedge SR (SRL16E)" treetype="template">
|
|
// SRL16E : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SRL16E_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SRL16E: 16-bit shift register LUT with clock enable operating on posedge of clock
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SRL16E #(
|
|
.INIT(16'h0000) // Initial Value of Shift Register
|
|
) SRL16E_inst (
|
|
.Q(Q), // SRL data output
|
|
.A0(A0), // Select[0] input
|
|
.A1(A1), // Select[1] input
|
|
.A2(A2), // Select[2] input
|
|
.A3(A3), // Select[3] input
|
|
.CE(CE), // Clock enable input
|
|
.CLK(CLK), // Clock input
|
|
.D(D) // SRL data input
|
|
);
|
|
|
|
// End of SRL16E_inst instantiation
|
|
</Template>
|
|
<Template label="16-bit w/ CE negedge SR (SRL16E_1)" treetype="template">
|
|
// SRL16E_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SRL16E_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SRL16E_1: 16-bit shift register LUT with clock enable operating on negedge of clock
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SRL16E_1 #(
|
|
.INIT(16'h0000) // Initial Value of Shift Register
|
|
) SRL16E_1_inst (
|
|
.Q(Q), // SRL data output
|
|
.A0(A0), // Select[0] input
|
|
.A1(A1), // Select[1] input
|
|
.A2(A2), // Select[2] input
|
|
.A3(A3), // Select[3] input
|
|
.CE(CE), // Clock enable input
|
|
.CLK(CLK), // Clock input
|
|
.D(D) // SRL data input
|
|
);
|
|
|
|
// End of SRL16E_1_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Cascable" treetype="folder">
|
|
<Template label="16-bit posedge SR (SRLC16)" treetype="template">
|
|
// SRLC16 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SRLC16_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SRLC16: 16-bit cascadable shift register LUT operating on posedge of clock
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SRLC16 #(
|
|
.INIT(16'h0000) // Initial Value of Shift Register
|
|
) SRLC16_inst (
|
|
.Q(Q), // SRL data output
|
|
.Q15(Q15), // Carry output (connect to next SRL)
|
|
.A0(A0), // Select[0] input
|
|
.A1(A1), // Select[1] input
|
|
.A2(A2), // Select[2] input
|
|
.A3(A3), // Select[3] input
|
|
.CLK(CLK), // Clock input
|
|
.D(D) // SRL data input
|
|
);
|
|
|
|
// End of SRLC16_inst instantiation
|
|
</Template>
|
|
<Template label="16-bit negedge SR (SRLC16_1)" treetype="template">
|
|
// SRLC16_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SRLC16_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SRLC16_1: 16-bit cascadable shift register LUT operating on negedge of clock
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SRLC16_1 #(
|
|
.INIT(16'h0000) // Initial Value of Shift Register
|
|
) SRLC16_1_inst (
|
|
.Q(Q), // SRL data output
|
|
.Q15(Q15), // Carry output (connect to next SRL)
|
|
.A0(A0), // Select[0] input
|
|
.A1(A1), // Select[1] input
|
|
.A2(A2), // Select[2] input
|
|
.A3(A3), // Select[3] input
|
|
.CLK(CLK), // Clock input
|
|
.D(D) // SRL data input
|
|
);
|
|
|
|
// End of SRLC16_1_inst instantiation
|
|
</Template>
|
|
<Template label="16-bit w/ CE posedge SR (SRLC16E)" treetype="template">
|
|
// SRLC16E : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SRL16E_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SRLC16E: 16-bit cascadable shift register LUT with clock enable operating on posedge of clock
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SRLC16E #(
|
|
.INIT(16'h0000) // Initial Value of Shift Register
|
|
) SRLC16E_inst (
|
|
.Q(Q), // SRL data output
|
|
.Q15(Q15), // Carry output (connect to next SRL)
|
|
.A0(A0), // Select[0] input
|
|
.A1(A1), // Select[1] input
|
|
.A2(A2), // Select[2] input
|
|
.A3(A3), // Select[3] input
|
|
.CE(CE), // Clock enable input
|
|
.CLK(CLK), // Clock input
|
|
.D(D) // SRL data input
|
|
);
|
|
|
|
// End of SRLC16E_inst instantiation
|
|
</Template>
|
|
<Template label="16-bit w/ CE negedge SR (SRLC16E_1)" treetype="template">
|
|
// SRLC16E_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SRLC16E_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SRLC16E_1: 16-bit shift register LUT with clock enable operating on negedge of clock
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SRLC16E_1 #(
|
|
.INIT(16'h0000) // Initial Value of Shift Register
|
|
) SRLC16E_1_inst (
|
|
.Q(Q), // SRL data output
|
|
.Q15(Q15), // Carry output (connect to next SRL)
|
|
.A0(A0), // Select[0] input
|
|
.A1(A1), // Select[1] input
|
|
.A2(A2), // Select[2] input
|
|
.A3(A3), // Select[3] input
|
|
.CE(CE), // Clock enable input
|
|
.CLK(CLK), // Clock input
|
|
.D(D) // SRL data input
|
|
);
|
|
|
|
// End of SRLC16E_1_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Clock Components" treetype="folder">
|
|
<Template label="Digital Clock Manager (DCM_SP)" treetype="template">
|
|
// DCM_SP : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (DCM_SP_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Unused inputs
|
|
// : and outputs may be removed or commented out.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// DCM_SP: Digital Clock Manager Circuit
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
DCM_SP #(
|
|
.CLKDV_DIVIDE(2.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
|
|
// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
|
|
.CLKFX_DIVIDE(1), // Can be any integer from 1 to 32
|
|
.CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32
|
|
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
|
|
.CLKIN_PERIOD(0.0), // Specify period of input clock
|
|
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
|
|
.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X
|
|
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
|
|
// an integer from 0 to 15
|
|
.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
|
|
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
|
|
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
|
|
.STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
|
|
) DCM_SP_inst (
|
|
.CLK0(CLK0), // 0 degree DCM CLK output
|
|
.CLK180(CLK180), // 180 degree DCM CLK output
|
|
.CLK270(CLK270), // 270 degree DCM CLK output
|
|
.CLK2X(CLK2X), // 2X DCM CLK output
|
|
.CLK2X180(CLK2X180), // 2X, 180 degree DCM CLK out
|
|
.CLK90(CLK90), // 90 degree DCM CLK output
|
|
.CLKDV(CLKDV), // Divided DCM CLK out (CLKDV_DIVIDE)
|
|
.CLKFX(CLKFX), // DCM CLK synthesis out (M/D)
|
|
.CLKFX180(CLKFX180), // 180 degree CLK synthesis out
|
|
.LOCKED(LOCKED), // DCM LOCK status output
|
|
.PSDONE(PSDONE), // Dynamic phase adjust done output
|
|
.STATUS(STATUS), // 8-bit DCM status bits output
|
|
.CLKFB(CLKFB), // DCM clock feedback
|
|
.CLKIN(CLKIN), // Clock input (from IBUFG, BUFG or DCM)
|
|
.PSCLK(PSCLK), // Dynamic phase adjust clock input
|
|
.PSEN(PSEN), // Dynamic phase adjust enable input
|
|
.PSINCDEC(PSINCDEC), // Dynamic phase adjust increment/decrement
|
|
.RST(RST) // DCM asynchronous reset input
|
|
);
|
|
|
|
// End of DCM_SP_inst instantiation
|
|
</Template>
|
|
<SubFolder label="Clock Buffers" treetype="folder">
|
|
<Template label="Global Clock Buffer (BUFG)" treetype="template">
|
|
// BUFG : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFG_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFG: Global Clock Buffer (source by an internal signal)
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFG BUFG_inst (
|
|
.O(O), // Clock buffer output
|
|
.I(I) // Clock buffer input
|
|
);
|
|
|
|
// End of BUFG_inst instantiation
|
|
</Template>
|
|
<Template label="Single-ended input Global Clock Buffer (IBUFG)" treetype="template">
|
|
// IBUFG : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFG_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFG: Global Clock Buffer (sourced by an external pin)
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFG #(
|
|
.IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for
|
|
// the buffer: "0"-"12" (Spartan-3E)
|
|
.IOSTANDARD("DEFAULT")
|
|
) IBUFG_inst (
|
|
.O(O), // Clock buffer output
|
|
.I(I) // Clock buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUFG_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Input Global Clock Buffer (IBUFGDS)" treetype="template">
|
|
// IBUFGDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFGDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFGDS: Differential Global Clock Buffer (sourced by an external pin)
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFGDS #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination
|
|
.IOSTANDARD("DEFAULT"), // Specifies the I/O standard for this buffer
|
|
.IBUF_DELAY_VALUE("0") // Specify the amount of added input delay for
|
|
// the buffer: "0"-"12" (Spartan-3E)
|
|
) IBUFGDS_inst (
|
|
.O(O), // Clock buffer output
|
|
.I(I), // Diff_p clock buffer input
|
|
.IB(IB) // Diff_n clock buffer input
|
|
);
|
|
|
|
// End of IBUFGDS_inst instantiation
|
|
</Template>
|
|
<Template label="Global Clock Buffer w/ Enable (BUFGCE)" treetype="template">
|
|
// BUFGCE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFGCE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFGCE: Global Clock Buffer with Clock Enable (active high)
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFGCE BUFGCE_inst (
|
|
.O(O), // Clock buffer output
|
|
.CE(CE), // Clock enable input
|
|
.I(I) // Clock buffer input
|
|
);
|
|
|
|
// End of BUFGCE_inst instantiation
|
|
</Template>
|
|
<Template label="Global Clock Buffer w/ Enable (BUFGCE_1)" treetype="template">
|
|
// BUFGCE_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFGCE_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFGCE_1: Global Clock Buffer with Clock Enable (active low)
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFGCE_1 BUFGCE_1_inst (
|
|
.O(O), // Clock buffer output
|
|
.CE(CE), // Clock enable input
|
|
.I(I) // Clock buffer input
|
|
);
|
|
|
|
// End of BUFGCE_1_inst instantiation
|
|
// End of BUFIO_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Clock MUX" treetype="folder">
|
|
<Template label="Global Clock Buffer MUX (BUFGMUX)" treetype="template">
|
|
// BUFGMUX : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFGMUX_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFGMUX: Global Clock Buffer 2-to-1 MUX
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFGMUX BUFGMUX_inst (
|
|
.O(O), // Clock MUX output
|
|
.I0(I0), // Clock0 input
|
|
.I1(I1), // Clock1 input
|
|
.S(S) // Clock select input
|
|
);
|
|
|
|
// End of BUFGMUX_inst instantiation
|
|
</Template>
|
|
<Template label="Global Clock Buffer MUX (BUFGMUX_1)" treetype="template">
|
|
// BUFGMUX_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFGMUX_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFGMUX_1: Global Clock Buffer 2-to-1 MUX (inverted select)
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFGMUX_1 BUFGMUX_1_inst (
|
|
.O(O), // Clock MUX output
|
|
.I0(I0), // Clock0 input
|
|
.I1(I1), // Clock1 input
|
|
.S(S) // Clock select input
|
|
);
|
|
|
|
// End of BUFGMUX_1_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="RAM/ROM" treetype="folder">
|
|
<SubFolder label="Distributed ROM" treetype="folder">
|
|
<Template label="16 X 1 (ROM16X1)" treetype="template">
|
|
// ROM16X1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ROM16X1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ROM16X1: 16 x 1 Asynchronous Distributed (LUT) ROM
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ROM16X1 #(
|
|
.INIT(16'h0000) // Contents of ROM
|
|
) ROM16X1_inst (
|
|
.O(O), // ROM output
|
|
.A0(A0), // ROM address[0]
|
|
.A1(A1), // ROM address[1]
|
|
.A2(A2), // ROM address[2]
|
|
.A3(A3) // ROM address[3]
|
|
);
|
|
|
|
// End of ROM16X1_inst instantiation
|
|
</Template>
|
|
<Template label="32 X 1 (ROM32X1)" treetype="template">
|
|
// ROM32X1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ROM32X1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ROM32X1: 32 x 1 Asynchronous Distributed (LUT) ROM
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ROM32X1 #(
|
|
.INIT(32'h00000000) // Contents of ROM
|
|
) ROM32X1_inst (
|
|
.O(O), // ROM output
|
|
.A0(A0), // ROM address[0]
|
|
.A1(A1), // ROM address[1]
|
|
.A2(A2), // ROM address[2]
|
|
.A3(A3), // ROM address[3]
|
|
.A4(A4) // ROM address[4]
|
|
);
|
|
|
|
// End of ROM32X1_inst instantiation
|
|
</Template>
|
|
<Template label="64 X 1 (ROM64X1)" treetype="template">
|
|
// ROM64X1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ROM64X1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ROM64X1: 64 x 1 Asynchronous Distributed (LUT) ROM
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ROM64X1 #(
|
|
.INIT(64'h0000000000000000) // Contents of ROM
|
|
) ROM64X1_inst (
|
|
.O(O), // ROM output
|
|
.A0(A0), // ROM address[0]
|
|
.A1(A1), // ROM address[1]
|
|
.A2(A2), // ROM address[2]
|
|
.A3(A3), // ROM address[3]
|
|
.A4(A4), // ROM address[4]
|
|
.A5(A5) // ROM address[5]
|
|
);
|
|
|
|
// End of ROM64X1_inst instantiation
|
|
</Template>
|
|
<Template label="128 X 1 (ROM128X1)" treetype="template">
|
|
// ROM128X1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ROM128X1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ROM128X1: 128 x 1 Asynchronous Distributed (LUT) ROM
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ROM128X1 #(
|
|
.INIT(128'h00000000000000000000000000000000) // Contents of ROM
|
|
) ROM128X1_inst (
|
|
.O(O), // ROM output
|
|
.A0(A0), // ROM address[0]
|
|
.A1(A1), // ROM address[1]
|
|
.A2(A2), // ROM address[2]
|
|
.A3(A3), // ROM address[3]
|
|
.A4(A4), // ROM address[4]
|
|
.A5(A5), // ROM address[5]
|
|
.A6(A6) // ROM address[6]
|
|
);
|
|
|
|
// End of ROM128X1_inst instantiation
|
|
</Template>
|
|
<Template label="256 X 1 (ROM256X1)" treetype="template">
|
|
// ROM256X1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ROM256X1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ROM256X1: 256 x 1 Asynchronous Distributed (LUT) ROM
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ROM256X1 #(
|
|
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000) // Contents of ROM
|
|
) ROM256X1_inst (
|
|
.O(O), // ROM output
|
|
.A0(A0), // ROM address[0]
|
|
.A1(A1), // ROM address[1]
|
|
.A2(A2), // ROM address[2]
|
|
.A3(A3), // ROM address[3]
|
|
.A4(A4), // ROM address[4]
|
|
.A5(A5), // ROM address[5]
|
|
.A6(A6), // ROM address[6]
|
|
.A7(A7) // ROM address[7]
|
|
);
|
|
|
|
// End of ROM256X1_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Distributed RAM" treetype="folder">
|
|
<SubFolder label="Single-Port" treetype="folder">
|
|
<SubFolder label="16 Deep (4-bit address)" treetype="folder">
|
|
<Template label="16 x 1 posedge write (RAM16X1S)" treetype="template">
|
|
// RAM16X1S : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM16X1S_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM16X1S: 16 x 1 posedge write distributed (LUT) RAM
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM16X1S #(
|
|
.INIT(16'h0000) // Initial contents of RAM
|
|
) RAM16X1S_inst (
|
|
.O(O), // RAM output
|
|
.A0(A0), // RAM address[0] input
|
|
.A1(A1), // RAM address[1] input
|
|
.A2(A2), // RAM address[2] input
|
|
.A3(A3), // RAM address[3] input
|
|
.D(D), // RAM data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM16X1S_inst instantiation
|
|
</Template>
|
|
<Template label="16 x 1 negedge write (RAM16X1S_1)" treetype="template">
|
|
// RAM16X1S_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM16X1S_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM16X1S_1: 16 x 1 negedge write distributed (LUT) RAM
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM16X1S_1 #(
|
|
.INIT(16'h0000) // Initial contents of RAM
|
|
) RAM16X1S_1_inst (
|
|
.O(O), // RAM output
|
|
.A0(A0), // RAM address[0] input
|
|
.A1(A1), // RAM address[1] input
|
|
.A2(A2), // RAM address[2] input
|
|
.A3(A3), // RAM address[3] input
|
|
.D(D), // RAM data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM16X1S_1_inst instantiation
|
|
</Template>
|
|
<Template label="16 x 2 posedge write (RAM16X2S)" treetype="template">
|
|
// RAM16X2S : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM16X2S_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM16X2S: 16 x 2 posedge write distributed (LUT) RAM
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM16X2S #(
|
|
.INIT_00(16'h0000), // Initial contents of bit 0 of RAM
|
|
.INIT_01(16'h0000) // Initial contents of bit 1 of RAM
|
|
) RAM16X2S_inst (
|
|
.O0(O0), // RAM data[0] output
|
|
.O1(O1), // RAM data[1] output
|
|
.A0(A0), // RAM address[0] input
|
|
.A1(A1), // RAM address[1] input
|
|
.A2(A2), // RAM address[2] input
|
|
.A3(A3), // RAM address[3] input
|
|
.D0(D0), // RAM data[0] input
|
|
.D1(D1), // RAM data[1] input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM16X2S_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="32 Deep (5-bit address)" treetype="folder">
|
|
<Template label="32 x 1 posedge write (RAM32X1S)" treetype="template">
|
|
// RAM32X1S : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM32X1S_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM32X1S: 32 x 1 posedge write distributed (LUT) RAM
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM32X1S #(
|
|
.INIT(32'h00000000) // Initial contents of RAM
|
|
) RAM32X1S_inst (
|
|
.O(O), // RAM output
|
|
.A0(A0), // RAM address[0] input
|
|
.A1(A1), // RAM address[1] input
|
|
.A2(A2), // RAM address[2] input
|
|
.A3(A3), // RAM address[3] input
|
|
.A4(A4), // RAM address[4] input
|
|
.D(D), // RAM data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM32X1S_inst instantiation
|
|
</Template>
|
|
<Template label="32 x 1 negedge write (RAM32X1S_1)" treetype="template">
|
|
// RAM32X1S_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM32X1S_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM32X1S_1: 32 x 1 negedge write distributed (LUT) RAM
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM32X1S_1 #(
|
|
.INIT(32'h00000000) // Initial contents of RAM
|
|
)RAM32X1S_1_inst (
|
|
.O(O), // RAM output
|
|
.A0(A0), // RAM address[0] input
|
|
.A1(A1), // RAM address[1] input
|
|
.A2(A2), // RAM address[2] input
|
|
.A3(A3), // RAM address[3] input
|
|
.A4(A4), // RAM address[4] input
|
|
.D(D), // RAM data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM32X1S_1_inst instantiation
|
|
</Template>
|
|
<Template label="32 x 2 posedge write (RAM32X2S)" treetype="template">
|
|
// RAM32X2S : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM16X2S_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM32X2S: 32 x 2 posedge write distributed (LUT) RAM
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM32X2S #(
|
|
.INIT_00(32'h00000000), // INIT for bit 0 of RAM
|
|
.INIT_01(32'h00000000) // INIT for bit 1 of RAM
|
|
) RAM32X2S_inst (
|
|
.O0(O0), // RAM data[0] output
|
|
.O1(O1), // RAM data[1] output
|
|
.A0(A0), // RAM address[0] input
|
|
.A1(A1), // RAM address[1] input
|
|
.A2(A2), // RAM address[2] input
|
|
.A3(A3), // RAM address[3] input
|
|
.A4(A4), // RAM address[4] input
|
|
.D0(D0), // RAM data[0] input
|
|
.D1(D1), // RAM data[1] input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM32X2S_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="64 Deep (6-bit address)" treetype="folder">
|
|
<Template label="64 X 1 posedge write (RAM64X1S)" treetype="template">
|
|
// RAM64X1S : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM64X1S_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM64X1S: 64 x 1 positive edge write, asynchronous read single-port distributed RAM
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM64X1S #(
|
|
.INIT(64'h0000000000000000) // Initial contents of RAM
|
|
) RAM64X1S_inst (
|
|
.O(O), // 1-bit data output
|
|
.A0(A0), // Address[0] input bit
|
|
.A1(A1), // Address[1] input bit
|
|
.A2(A2), // Address[2] input bit
|
|
.A3(A3), // Address[3] input bit
|
|
.A4(A4), // Address[4] input bit
|
|
.A5(A5), // Address[5] input bit
|
|
.D(D), // 1-bit data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM64X1S_inst instantiation
|
|
</Template>
|
|
<Template label="64 X 1 negedge write (RAM64X1S_1)" treetype="template">
|
|
// RAM64X1S_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM64X1S_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM64X1S_1: 64 x 1 negative edge write, asynchronous read single-port distributed RAM
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM64X1S_1 #(
|
|
.INIT(64'h0000000000000000) // Initial contents of RAM
|
|
) RAM64X1S_1_inst (
|
|
.O(O), // 1-bit data output
|
|
.A0(A0), // Address[0] input bit
|
|
.A1(A1), // Address[1] input bit
|
|
.A2(A2), // Address[2] input bit
|
|
.A3(A3), // Address[3] input bit
|
|
.A4(A4), // Address[4] input bit
|
|
.A5(A5), // Address[5] input bit
|
|
.D(D), // 1-bit data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM64X1S_1_inst instantiation
|
|
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Dual-Port" treetype="folder">
|
|
<Template label="16 X 1 posedge write (RAM16X1D)" treetype="template">
|
|
// RAM16X1D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM16X1D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM16X1D: 16 x 1 positive edge write, asynchronous read dual-port distributed RAM
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM16X1D #(
|
|
.INIT(16'h0000) // Initial contents of RAM
|
|
) RAM16X1D_inst (
|
|
.DPO(DPO), // Read-only 1-bit data output for DPRA
|
|
.SPO(SPO), // Rw/ 1-bit data output for A0-A3
|
|
.A0(A0), // Rw/ address[0] input bit
|
|
.A1(A1), // Rw/ address[1] input bit
|
|
.A2(A2), // Rw/ address[2] input bit
|
|
.A3(A3), // Rw/ address[3] input bit
|
|
.D(D), // Write 1-bit data input
|
|
.DPRA0(DPRA0), // Read address[0] input bit
|
|
.DPRA1(DPRA1), // Read address[1] input bit
|
|
.DPRA2(DPRA2), // Read address[2] input bit
|
|
.DPRA3(DPRA3), // Read address[3] input bit
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM16X1D_inst instantiation
|
|
</Template>
|
|
<Template label="16 X 1 negedge write (RAM16X1D_1)" treetype="template">
|
|
// RAM16X1D_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM16X1D_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM16X1D_1: 16 x 1 negative edge write, asynchronous read dual-port distributed RAM
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM16X1D_1 #(
|
|
.INIT(16'h0000) // Initial contents of RAM
|
|
) RAM16X1D_1_inst (
|
|
.DPO(DPO), // Read-only 1-bit data output
|
|
.SPO(SPO), // Rw/ 1-bit data output
|
|
.A0(A0), // Rw/ address[0] input bit
|
|
.A1(A1), // Rw/ address[1] input bit
|
|
.A2(A2), // Rw/ address[2] input bit
|
|
.A3(A3), // Rw/ address[3] input bit
|
|
.D(D), // Write 1-bit data input
|
|
.DPRA0(DPRA0), // Read-only address[0] input bit
|
|
.DPRA1(DPRA1), // Read-only address[1] input bit
|
|
.DPRA2(DPRA2), // Read-only address[2] input bit
|
|
.DPRA3(DPRA3), // Read-only address[3] input bit
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM16X1D_1_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Block RAM" treetype="folder">
|
|
<SubFolder label="Single-Port" treetype="folder">
|
|
<Template label="16k x 1 (RAMB16_S1)" treetype="template">
|
|
// RAMB16_S1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S1: 16kx1 Single-Port RAM
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S1 #(
|
|
.INIT(1'b0), // Value of output RAM registers at startup
|
|
.SRVAL(1'b0), // Output value upon SSR assertion
|
|
.WRITE_MODE("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Address 0 to 4095
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 4096 to 8191
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 8192 to 12287
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 12288 to 16383
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S1_inst (
|
|
.DO(DO), // 1-bit Data Output
|
|
.ADDR(ADDR), // 14-bit Address Input
|
|
.CLK(CLK), // Clock
|
|
.DI(DI), // 1-bit Data Input
|
|
.EN(EN), // RAM Enable Input
|
|
.SSR(SSR), // Synchronous Set/Reset Input
|
|
.WE(WE) // Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S1_inst instantiation
|
|
</Template>
|
|
<Template label="1k x 16 + 2 Parity bits (RAMB16_S18)" treetype="template">
|
|
// RAMB16_S18 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S18_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S18: 1k x 16 + 2 Parity bits Single-Port RAM
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S18 #(
|
|
.INIT(18'h00000), // Value of output RAM registers at startup
|
|
.SRVAL(18'h000000), // Output value upon SSR assertion
|
|
.WRITE_MODE("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Address 0 to 255
|
|
.INIT_00(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_01(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_02(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_03(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_04(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_05(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_06(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_07(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_08(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_09(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_0A(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_0B(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_0C(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_0D(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_0E(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_0F(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
// Address 256 to 511
|
|
.INIT_10(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_11(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_12(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_13(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_14(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_15(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_16(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_17(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_18(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_19(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_1A(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_1B(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_1C(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_1D(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_1E(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_1F(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
// Address 512 to 767
|
|
.INIT_20(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_21(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_22(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_23(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_24(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_25(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_26(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_27(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_28(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_29(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_2A(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_2B(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_2C(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_2D(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_2E(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_2F(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
// Address 768 to 1023
|
|
.INIT_30(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_31(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_32(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_33(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_34(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_35(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_36(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_37(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_38(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_39(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_3A(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_3B(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_3C(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_3D(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_3E(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_3F(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
// Address 0 to 255
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 256 to 511
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 512 to 767
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 768 to 1023
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S18_inst (
|
|
.DO(DO), // 16-bit Data Output
|
|
.DOP(DOP), // 2-bit parity Output
|
|
.ADDR(ADDR), // 10-bit Address Input
|
|
.CLK(CLK), // Clock
|
|
.DI(DI), // 16-bit Data Input
|
|
.DIP(DIP), // 2-bit parity Input
|
|
.EN(EN), // RAM Enable Input
|
|
.SSR(SSR), // Synchronous Set/Reset Input
|
|
.WE(WE) // Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S18_inst instantiation
|
|
</Template>
|
|
<Template label="8k x 2 (RAMB16_S2)" treetype="template">
|
|
// RAMB16_S2 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S2: 8k x 2 Single-Port RAM
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S2 #(
|
|
.INIT(2'b00), // Value of output RAM registers at startup
|
|
.SRVAL(2'b00), // Output value upon SSR assertion
|
|
.WRITE_MODE("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Address 0 to 2047
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 2048 to 4095
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 4096 to 6143
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 6143 to 8191
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S2_inst (
|
|
.DO(DO), // 2-bit Data Output
|
|
.ADDR(ADDR), // 13-bit Address Input
|
|
.CLK(CLK), // Clock
|
|
.DI(DI), // 2-bit Data Input
|
|
.EN(EN), // RAM Enable Input
|
|
.SSR(SSR), // Synchronous Set/Reset Input
|
|
.WE(WE) // Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S2_inst instantiation
|
|
</Template>
|
|
<Template label="512 x 32 + 4 Parity bits (RAMB16_S36)" treetype="template">
|
|
// RAMB16_S36 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S36_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S36: 512 x 32 + 4 Parity bits Single-Port RAM
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S36 #(
|
|
.INIT(36'h000000000), // Value of output RAM registers at startup
|
|
.SRVAL(36'h000000000), // Output value upon SSR assertion
|
|
.WRITE_MODE("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Address 0 to 127
|
|
.INIT_00(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_01(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_02(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_03(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_04(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_05(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_06(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_07(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_08(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_09(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_0A(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_0B(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_0C(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_0D(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_0E(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_0F(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
// Address 128 to 255
|
|
.INIT_10(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_11(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_12(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_13(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_14(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_15(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_16(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_17(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_18(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_19(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_1A(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_1B(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_1C(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_1D(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_1E(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_1F(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
// Address 256 to 383
|
|
.INIT_20(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_21(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_22(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_23(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_24(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_25(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_26(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_27(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_28(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_29(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_2A(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_2B(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_2C(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_2D(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_2E(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_2F(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
// Address 384 to 511
|
|
.INIT_30(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_31(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_32(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_33(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_34(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_35(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_36(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_37(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_38(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_39(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_3A(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_3B(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_3C(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_3D(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_3E(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_3F(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
// Address 0 to 127
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 128 to 255
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 256 to 383
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 384 to 511
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S36_inst (
|
|
.DO(DO), // 32-bit Data Output
|
|
.DOP(DOP), // 4-bit parity Output
|
|
.ADDR(ADDR), // 9-bit Address Input
|
|
.CLK(CLK), // Clock
|
|
.DI(DI), // 32-bit Data Input
|
|
.DIP(DIP), // 4-bit parity Input
|
|
.EN(EN), // RAM Enable Input
|
|
.SSR(SSR), // Synchronous Set/Reset Input
|
|
.WE(WE) // Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S36_inst instantiation
|
|
</Template>
|
|
<Template label="4k x 4 (RAMB16_S4)" treetype="template">
|
|
// RAMB16_S4 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S4_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S4: 4k x 4 Single-Port RAM
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S4 #(
|
|
.INIT(4'h0), // Value of output RAM registers at startup
|
|
.SRVAL(4'h0), // Output value upon SSR assertion
|
|
.WRITE_MODE("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Address 0 to 1023
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 1024 to 2047
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 2048 to 3071
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 3072 to 4095
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S4_inst (
|
|
.DO(DO), // 4-bit Data Output
|
|
.ADDR(ADDR), // 12-bit Address Input
|
|
.CLK(CLK), // Clock
|
|
.DI(DI), // 4-bit Data Input
|
|
.EN(EN), // RAM Enable Input
|
|
.SSR(SSR), // Synchronous Set/Reset Input
|
|
.WE(WE) // Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S4_inst instantiation
|
|
</Template>
|
|
<Template label="2k x 8 + 1 Parity bit (RAMB16_S9)" treetype="template">
|
|
// RAMB16_S9 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S9_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S9: 2k x 8 + 1 Parity bit Single-Port RAM
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S9 #(
|
|
.INIT(9'h000), // Value of output RAM registers at startup
|
|
.SRVAL(9'h000), // Output value upon SSR assertion
|
|
.WRITE_MODE("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Address 0 to 511
|
|
.INIT_00(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_01(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_02(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_03(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_04(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_05(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_06(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_07(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_08(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_09(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_0A(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_0B(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_0C(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_0D(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_0E(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_0F(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
// Address 512 to 1023
|
|
.INIT_10(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_11(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_12(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_13(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_14(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_15(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_16(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_17(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_18(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_19(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_1A(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_1B(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_1C(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_1D(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_1E(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_1F(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
// Address 1024 to 1535
|
|
.INIT_20(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_21(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_22(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_23(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_24(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_25(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_26(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_27(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_28(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_29(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_2A(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_2B(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_2C(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_2D(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_2E(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_2F(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
// Address 1536 to 2047
|
|
.INIT_30(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_31(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_32(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_33(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_34(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_35(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_36(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_37(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_38(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_39(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_3A(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_3B(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_3C(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_3D(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_3E(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_3F(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
// Address 0 to 511
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 512 to 1023
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 1024 to 1535
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 1536 to 2047
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S9_inst (
|
|
.DO(DO), // 8-bit Data Output
|
|
.DOP(DOP), // 1-bit parity Output
|
|
.ADDR(ADDR), // 11-bit Address Input
|
|
.CLK(CLK), // Clock
|
|
.DI(DI), // 8-bit Data Input
|
|
.DIP(DIP), // 1-bit parity Input
|
|
.EN(EN), // RAM Enable Input
|
|
.SSR(SSR), // Synchronous Set/Reset Input
|
|
.WE(WE) // Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S9_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Dual-Port (Matched Port Widths)" treetype="folder">
|
|
<Template label="1k x 16 + 2 Parity bits (RAMB16_S18_S18)" treetype="template">
|
|
// RAMB16_S18_S18 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S18_S18_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S18_S18: 1k x 16 + 2 Parity bits Dual-Port RAM
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S18_S18 #(
|
|
.INIT_A(18'h00000), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(18'h00000), // Value of output RAM registers on Port B at startup
|
|
.SRVAL_A(18'h00000), // Port A output value upon SSR assertion
|
|
.SRVAL_B(18'h00000), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Address 0 to 255
|
|
.INIT_00(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_01(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_02(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_03(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_04(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_05(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_06(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_07(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_08(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_09(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_0A(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_0B(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_0C(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_0D(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_0E(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_0F(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
// Address 256 to 511
|
|
.INIT_10(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_11(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_12(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_13(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_14(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_15(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_16(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_17(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_18(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_19(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_1A(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_1B(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_1C(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_1D(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_1E(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_1F(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
// Address 512 to 767
|
|
.INIT_20(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_21(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_22(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_23(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_24(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_25(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_26(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_27(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_28(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_29(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_2A(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_2B(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_2C(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_2D(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_2E(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_2F(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
// Address 768 to 1023
|
|
.INIT_30(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_31(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_32(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_33(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_34(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_35(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_36(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_37(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_38(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_39(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_3A(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_3B(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_3C(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_3D(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_3E(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_3F(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
// Address 0 to 255
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 256 to 511
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 512 to 767
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 768 to 1023
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S18_S18_inst (
|
|
.DOA(DOA), // Port A 16-bit Data Output
|
|
.DOB(DOB), // Port B 16-bit Data Output
|
|
.DOPA(DOPA), // Port A 2-bit Parity Output
|
|
.DOPB(DOPB), // Port B 2-bit Parity Output
|
|
.ADDRA(ADDRA), // Port A 10-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 10-bit Address Input
|
|
.CLKA(CLKA), // Port A Clock
|
|
.CLKB(CLKB), // Port B Clock
|
|
.DIA(DIA), // Port A 16-bit Data Input
|
|
.DIB(DIB), // Port B 16-bit Data Input
|
|
.DIPA(DIPA), // Port A 2-bit parity Input
|
|
.DIPB(DIPB), // Port-B 2-bit parity Input
|
|
.ENA(ENA), // Port A RAM Enable Input
|
|
.ENB(ENB), // Port B RAM Enable Input
|
|
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A Write Enable Input
|
|
.WEB(WEB) // Port B Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S18_S18_inst instantiation
|
|
</Template>
|
|
<Template label="16k x 1 (RAMB16_S1_S1)" treetype="template">
|
|
// RAMB16_S1_S1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S1_S1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S1_S1: 16k x 1 Dual-Port RAM
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S1_S1 #(
|
|
.INIT_A(1'b0), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(1'b0), // Value of output RAM registers on Port B at startup
|
|
.SRVAL_A(1'b0), // Port A output value upon SSR assertion
|
|
.SRVAL_B(1'b0), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Address 0 to 4095
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 4096 to 8191
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 8192 to 12287
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 12288 to 16383
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S1_S1_inst (
|
|
.DOA(DOA), // Port A 1-bit Data Output
|
|
.DOB(DOB), // Port B 1-bit Data Output
|
|
.ADDRA(ADDRA), // Port A 14-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 14-bit Address Input
|
|
.CLKA(CLKA), // Port A Clock
|
|
.CLKB(CLKB), // Port B Clock
|
|
.DIA(DIA), // Port A 1-bit Data Input
|
|
.DIB(DIB), // Port B 1-bit Data Input
|
|
.ENA(ENA), // Port A RAM Enable Input
|
|
.ENB(ENB), // Port B RAM Enable Input
|
|
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A Write Enable Input
|
|
.WEB(WEB) // Port B Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S1_S1_inst instantiation
|
|
</Template>
|
|
<Template label="8k x 2 (RAMB16_S2_S2)" treetype="template">
|
|
// RAMB16_S2_S2 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S2_S2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S2_S2: 8k x 2 Dual-Port RAM
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S2_S2 #(
|
|
.INIT_A(2'b00), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(2'b00), // Value of output RAM registers on Port B at startup
|
|
.SRVAL_A(2'b00), // Port A output value upon SSR assertion
|
|
.SRVAL_B(2'b00), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
|
|
// Address 0 to 2047
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 2048 to 4095
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 4096 to 6143
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 6143 to 8191
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S2_S2_inst (
|
|
.DOA(DOA), // Port A 2-bit Data Output
|
|
.DOB(DOB), // Port B 2-bit Data Output
|
|
.ADDRA(ADDRA), // Port A 13-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 13-bit Address Input
|
|
.CLKA(CLKA), // Port A Clock
|
|
.CLKB(CLKB), // Port B Clock
|
|
.DIA(DIA), // Port A 2-bit Data Input
|
|
.DIB(DIB), // Port B 2-bit Data Input
|
|
.ENA(ENA), // Port A RAM Enable Input
|
|
.ENB(ENB), // Port B RAM Enable Input
|
|
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A Write Enable Input
|
|
.WEB(WEB) // Port B Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S2_S2_inst instantiation
|
|
</Template>
|
|
<Template label="512 x 32 + 4 Parity bits (RAMB16_S36_S36)" treetype="template">
|
|
// RAMB16_S36_S36 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S36_S36_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S36_S36: 512 x 32 + 4 Parity bits Dual-Port RAM
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S36_S36 #(
|
|
.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup
|
|
.SRVAL_A(36'h000000000), // Port A output value upon SSR assertion
|
|
.SRVAL_B(36'h000000000), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Address 0 to 127
|
|
.INIT_00(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_01(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_02(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_03(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_04(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_05(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_06(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_07(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_08(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_09(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_0A(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_0B(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_0C(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_0D(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_0E(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_0F(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
// Address 128 to 255
|
|
.INIT_10(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_11(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_12(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_13(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_14(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_15(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_16(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_17(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_18(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_19(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_1A(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_1B(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_1C(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_1D(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_1E(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_1F(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
// Address 256 to 383
|
|
.INIT_20(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_21(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_22(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_23(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_24(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_25(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_26(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_27(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_28(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_29(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_2A(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_2B(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_2C(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_2D(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_2E(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_2F(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
// Address 384 to 511
|
|
.INIT_30(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_31(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_32(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_33(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_34(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_35(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_36(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_37(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_38(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_39(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_3A(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_3B(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_3C(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_3D(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_3E(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_3F(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
// Address 0 to 127
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 128 to 255
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 256 to 383
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 384 to 511
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S36_S36_inst (
|
|
.DOA(DOA), // Port A 32-bit Data Output
|
|
.DOB(DOB), // Port B 32-bit Data Output
|
|
.DOPA(DOPA), // Port A 4-bit Parity Output
|
|
.DOPB(DOPB), // Port B 4-bit Parity Output
|
|
.ADDRA(ADDRA), // Port A 9-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 9-bit Address Input
|
|
.CLKA(CLKA), // Port A Clock
|
|
.CLKB(CLKB), // Port B Clock
|
|
.DIA(DIA), // Port A 32-bit Data Input
|
|
.DIB(DIB), // Port B 32-bit Data Input
|
|
.DIPA(DIPA), // Port A 4-bit parity Input
|
|
.DIPB(DIPB), // Port-B 4-bit parity Input
|
|
.ENA(ENA), // Port A RAM Enable Input
|
|
.ENB(ENB), // Port B RAM Enable Input
|
|
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A Write Enable Input
|
|
.WEB(WEB) // Port B Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S36_S36_inst instantiation
|
|
</Template>
|
|
<Template label="4k x 4 (RAMB16_S4_S4)" treetype="template">
|
|
// RAMB16_S4_S4 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S4_S4_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S4_S4: 4k x 4 Dual-Port RAM
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S4_S4 #(
|
|
.INIT_A(4'h0), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(4'h0), // Value of output RAM registers on Port B at startup
|
|
.SRVAL_A(4'h0), // Port A output value upon SSR assertion
|
|
.SRVAL_B(4'h0), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Address 0 to 1023
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 1024 to 2047
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 2048 to 3071
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 3072 to 4095
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S4_S4_inst (
|
|
.DOA(DOA), // Port A 4-bit Data Output
|
|
.DOB(DOB), // Port B 4-bit Data Output
|
|
.ADDRA(ADDRA), // Port A 12-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 12-bit Address Input
|
|
.CLKA(CLKA), // Port A Clock
|
|
.CLKB(CLKB), // Port B Clock
|
|
.DIA(DIA), // Port A 4-bit Data Input
|
|
.DIB(DIB), // Port B 4-bit Data Input
|
|
.ENA(ENA), // Port A RAM Enable Input
|
|
.ENB(ENB), // Port B RAM Enable Input
|
|
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A Write Enable Input
|
|
.WEB(WEB) // Port B Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S4_S4_inst instantiation
|
|
</Template>
|
|
<Template label="2k x 8 + 1 Parity bit (RAMB16_S9_S9)" treetype="template">
|
|
// RAMB16_S9_S9 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S9_S9_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S9_S9: 2k x 8 + 1 Parity bit Dual-Port RAM
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S9_S9 #(
|
|
.INIT_A(9'h000), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(9'h000), // Value of output RAM registers on Port B at startup
|
|
.SRVAL_A(9'h000), // Port A output value upon SSR assertion
|
|
.SRVAL_B(9'h000), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Address 0 to 511
|
|
.INIT_00(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_01(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_02(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_03(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_04(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_05(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_06(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_07(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_08(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_09(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_0A(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_0B(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_0C(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_0D(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_0E(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_0F(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
// Address 512 to 1023
|
|
.INIT_10(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_11(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_12(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_13(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_14(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_15(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_16(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_17(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_18(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_19(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_1A(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_1B(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_1C(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_1D(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_1E(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_1F(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
// Address 1024 to 1535
|
|
.INIT_20(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_21(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_22(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_23(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_24(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_25(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_26(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_27(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_28(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_29(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_2A(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_2B(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_2C(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_2D(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_2E(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_2F(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
// Address 1536 to 2047
|
|
.INIT_30(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_31(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_32(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_33(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_34(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_35(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_36(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_37(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_38(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_39(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_3A(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_3B(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_3C(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_3D(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_3E(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_3F(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
// Address 0 to 511
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 512 to 1023
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 1024 to 1535
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 1536 to 2047
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S9_S9_inst (
|
|
.DOA(DOA), // Port A 8-bit Data Output
|
|
.DOB(DOB), // Port B 8-bit Data Output
|
|
.DOPA(DOPA), // Port A 1-bit Parity Output
|
|
.DOPB(DOPB), // Port B 1-bit Parity Output
|
|
.ADDRA(ADDRA), // Port A 11-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 11-bit Address Input
|
|
.CLKA(CLKA), // Port A Clock
|
|
.CLKB(CLKB), // Port B Clock
|
|
.DIA(DIA), // Port A 8-bit Data Input
|
|
.DIB(DIB), // Port B 8-bit Data Input
|
|
.DIPA(DIPA), // Port A 1-bit parity Input
|
|
.DIPB(DIPB), // Port-B 1-bit parity Input
|
|
.ENA(ENA), // Port A RAM Enable Input
|
|
.ENB(ENB), // Port B RAM Enable Input
|
|
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A Write Enable Input
|
|
.WEB(WEB) // Port B Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S9_S9_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Dual-Port (Mis-matched Port Widths)" treetype="folder">
|
|
<Template label="1k/512 x 16/32 + 2/4 Parity bits (RAMB16_S18_S36)" treetype="template">
|
|
// RAMB16_S18_S36 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S18_S36_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S18_S36: 1k/512 x 16/32 + 2/4 Parity bits Dual-Port RAM
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S18_S36 #(
|
|
.INIT_A(18'h00000), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup
|
|
.SRVAL_A(18'h00000), // Port A output value upon SSR assertion
|
|
.SRVAL_B(36'h000000000), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Port A Address 0 to 255, Port B Address 0 to 127
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 256 to 511, Port B Address 128 to 255
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 512 to 767, Port B Address 256 to 383
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 768 to 1023, Port B Address 384 to 511
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
// Port A Address 0 to 255, Port B Address 0 to 127
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 256 to 511, Port B Address 128 to 255
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 512 to 767, Port B Address 256 to 383
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 768 to 1023, Port B Address 384 to 511
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S18_S36_inst (
|
|
.DOA(DOA), // Port A 16-bit Data Output
|
|
.DOB(DOB), // Port B 32-bit Data Output
|
|
.DOPA(DOPA), // Port A 2-bit Parity Output
|
|
.DOPB(DOPB), // Port B 4-bit Parity Output
|
|
.ADDRA(ADDRA), // Port A 10-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 9-bit Address Input
|
|
.CLKA(CLKA), // Port A Clock
|
|
.CLKB(CLKB), // Port B Clock
|
|
.DIA(DIA), // Port A 16-bit Data Input
|
|
.DIB(DIB), // Port B 32-bit Data Input
|
|
.DIPA(DIPA), // Port A 2-bit parity Input
|
|
.DIPB(DIPB), // Port-B 4-bit parity Input
|
|
.ENA(ENA), // Port A RAM Enable Input
|
|
.ENB(ENB), // Port B RAM Enable Input
|
|
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A Write Enable Input
|
|
.WEB(WEB) // Port B Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S18_S36_inst instantiation
|
|
</Template>
|
|
<Template label="16k/1k x 1/16 + 0/2 Parity bits (RAMB16_S1_S18)" treetype="template">
|
|
// RAMB16_S1_S18 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S1_S18_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S1_S18: 16k/1k x 1/16 + 0/2 Parity bits Dual-Port RAM
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S1_S18 #(
|
|
.INIT_A(1'b0), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(18'h00000), // Value of output RAM registers on Port B at startup
|
|
.SRVAL_A(1'b0), // Port A output value upon SSR assertion
|
|
.SRVAL_B(18'h00000), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Port A Address 0 to 4095, Port B Address 0 to 255
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 4096 to 8191, Port B Address 256 to 511
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 8192 to 12287, Port B Address 512 to 767
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 12288 to 16383, Port B Address 768 to 1023
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
// Port B Address 0 to 255
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 256 to 511
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 512 to 767
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 768 to 1023
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S1_S18_inst (
|
|
.DOA(DOA), // Port A 1-bit Data Output
|
|
.DOB(DOB), // Port B 16-bit Data Output
|
|
.DOPB(DOPB), // Port B 2-bit Parity Output
|
|
.ADDRA(ADDRA), // Port A 14-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 10-bit Address Input
|
|
.CLKA(CLKA), // Port A Clock
|
|
.CLKB(CLKB), // Port B Clock
|
|
.DIA(DIA), // Port A 1-bit Data Input
|
|
.DIB(DIB), // Port B 16-bit Data Input
|
|
.DIPB(DIPB), // Port-B 2-bit parity Input
|
|
.ENA(ENA), // Port A RAM Enable Input
|
|
.ENB(ENB), // Port B RAM Enable Input
|
|
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A Write Enable Input
|
|
.WEB(WEB) // Port B Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S1_S18_inst instantiation
|
|
</Template>
|
|
<Template label="16k/8k x 1/2 (RAMB16_S1_S2)" treetype="template">
|
|
// RAMB16_S1_S2 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S1_S2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S1_S2: 16k/8k x 1/2 Dual-Port RAM
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S1_S2 #(
|
|
.INIT_A(1'b0), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(2'b00), // Value of output RAM registers on Port B at startup
|
|
.SRVAL_A(1'b0), // Port A output value upon SSR assertion
|
|
.SRVAL_B(2'b00), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Port A Address 0 to 4095, Port B Address 0 to 2047
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 4096 to 8191, Port B Address 2048 to 4095
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 8192 to 12287, Port B Address 4095 to 6143
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 12288 to 16383, Port B Address 6144 to 8091
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S1_S2_inst (
|
|
.DOA(DOA), // Port A 1-bit Data Output
|
|
.DOB(DOB), // Port B 2-bit Data Output
|
|
.ADDRA(ADDRA), // Port A 14-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 13-bit Address Input
|
|
.CLKA(CLKA), // Port A Clock
|
|
.CLKB(CLKB), // Port B Clock
|
|
.DIA(DIA), // Port A 1-bit Data Input
|
|
.DIB(DIB), // Port B 2-bit Data Input
|
|
.ENA(ENA), // Port A RAM Enable Input
|
|
.ENB(ENB), // Port B RAM Enable Input
|
|
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A Write Enable Input
|
|
.WEB(WEB) // Port B Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S1_S2_inst instantiation
|
|
</Template>
|
|
<Template label="16k/512 x 1/32 + 0/4 Parity bits (RAMB16_S1_S36)" treetype="template">
|
|
// RAMB16_S1_S36 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S1_S36_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S1_S36: 16k/512 x 1/32 + 0/4 Parity bits Dual-Port RAM
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S1_S36 #(
|
|
.INIT_A(1'b0), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup
|
|
.SRVAL_A(1'b0), // Port A output value upon SSR assertion
|
|
.SRVAL_B(36'h000000000), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Port A Address 0 to 4095, Port B Address 0 to 127
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 4096 to 8191, Port B Address 128 to 255
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 8192 to 12287, Port B Address 256 to 383
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 12288 to 16383, Port B Address 384 to 512
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
// Port B Address 0 to 127
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 128 to 255
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 256 to 383
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 384 to 512
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S1_S36_inst (
|
|
.DOA(DOA), // Port A 1-bit Data Output
|
|
.DOB(DOB), // Port B 32-bit Data Output
|
|
.DOPB(DOPB), // Port B 4-bit Parity Output
|
|
.ADDRA(ADDRA), // Port A 14-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 9-bit Address Input
|
|
.CLKA(CLKA), // Port A Clock
|
|
.CLKB(CLKB), // Port B Clock
|
|
.DIA(DIA), // Port A 1-bit Data Input
|
|
.DIB(DIB), // Port B 32-bit Data Input
|
|
.DIPB(DIPB), // Port-B 4-bit parity Input
|
|
.ENA(ENA), // Port A RAM Enable Input
|
|
.ENB(ENB), // Port B RAM Enable Input
|
|
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A Write Enable Input
|
|
.WEB(WEB) // Port B Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S1_S36_inst instantiation
|
|
</Template>
|
|
<Template label="16k/4k x 1/4 (RAMB16_S1_S4)" treetype="template">
|
|
// RAMB16_S1_S4 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S1_S4_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S1_S4: 16k/4k x 1/4 Dual-Port RAM
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S1_S4 #(
|
|
.INIT_A(1'b0), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(4'h0), // Value of output RAM registers on Port B at startup
|
|
.SRVAL_A(1'b0), // Port A output value upon SSR assertion
|
|
.SRVAL_B(4'h0), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Port A Address 0 to 4095, Port B Address 0 to 1023
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 4096 to 8191, Port B Address 1024 to 2047
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 8192 to 12287, Port B Address 2048 to 3071
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 12288 to 16383, Port B Address 3072 to 4095
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S1_S4_inst (
|
|
.DOA(DOA), // Port A 1-bit Data Output
|
|
.DOB(DOB), // Port B 4-bit Data Output
|
|
.ADDRA(ADDRA), // Port A 14-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 12-bit Address Input
|
|
.CLKA(CLKA), // Port A Clock
|
|
.CLKB(CLKB), // Port B Clock
|
|
.DIA(DIA), // Port A 1-bit Data Input
|
|
.DIB(DIB), // Port B 4-bit Data Input
|
|
.ENA(ENA), // Port A RAM Enable Input
|
|
.ENB(ENB), // Port B RAM Enable Input
|
|
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A Write Enable Input
|
|
.WEB(WEB) // Port B Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S1_S4_inst instantiation
|
|
</Template>
|
|
<Template label="16k/2k x 1/8 + 0/1 Parity bit (RAMB16_S1_S9)" treetype="template">
|
|
|
|
// RAMB16_S1_S9 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S1_S9_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S1_S9: 16k/2k x 1/8 + 0/1 Parity bit Dual-Port RAM
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S1_S9 #(
|
|
.INIT_A(1'b0), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(9'h000), // Value of output RAM registers on Port B at startup
|
|
.SRVAL_A(1'b0), // Port A output value upon SSR assertion
|
|
.SRVAL_B(9'h000), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Port A Address 0 to 4095, Port B Address 0 to 511
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 4096 to 8191, Port B Address 512 to 1023
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 8192 to 12287, Port B Address 1024 to 1535
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 12288 to 16383, Port B Address 1535 to 2047
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
// Port B Address 0 to 511
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 512 to 1023
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 1024 to 1535
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 1535 to 2047
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S1_S9_inst (
|
|
.DOA(DOA), // Port A 1-bit Data Output
|
|
.DOB(DOB), // Port B 8-bit Data Output
|
|
.DOPB(DOPB), // Port B 1-bit Parity Output
|
|
.ADDRA(ADDRA), // Port A 14-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 11-bit Address Input
|
|
.CLKA(CLKA), // Port A Clock
|
|
.CLKB(CLKB), // Port B Clock
|
|
.DIA(DIA), // Port A 1-bit Data Input
|
|
.DIB(DIB), // Port B 8-bit Data Input
|
|
.DIPB(DIPB), // Port-B 1-bit parity Input
|
|
.ENA(ENA), // Port A RAM Enable Input
|
|
.ENB(ENB), // Port B RAM Enable Input
|
|
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A Write Enable Input
|
|
.WEB(WEB) // Port B Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S1_S9_inst instantiation
|
|
</Template>
|
|
<Template label="8k/512 x 2/32 + 0/4 Parity bits (RAMB16_S2_S36)" treetype="template">
|
|
// RAMB16_S2_S36 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S2_S36_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S2_S36: 8k/512 x 2/32 + 0/4 Parity bits Dual-Port RAM
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S2_S36 #(
|
|
.INIT_A(2'b00), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup
|
|
.SRVAL_A(2'b00), // Port A output value upon SSR assertion
|
|
.SRVAL_B(36'h000000000), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Port A Address 0 to 2047, Port B Address 0 to 127
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 2048 to 4095, Port B Address 128 to 255
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 4096 to 6143, Port B Address 256 to 383
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 6144 to 8191, Port B Address 384 to 511
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
// Port B Address 0 to 127
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 128 to 255
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 256 to 383
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 384 to 511
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S2_S36_inst (
|
|
.DOA(DOA), // Port A 2-bit Data Output
|
|
.DOB(DOB), // Port B 32-bit Data Output
|
|
.DOPB(DOPB), // Port B 4-bit Parity Output
|
|
.ADDRA(ADDRA), // Port A 13-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 9-bit Address Input
|
|
.CLKA(CLKA), // Port A Clock
|
|
.CLKB(CLKB), // Port B Clock
|
|
.DIA(DIA), // Port A 2-bit Data Input
|
|
.DIB(DIB), // Port B 32-bit Data Input
|
|
.DIPB(DIPB), // Port-B 4-bit parity Input
|
|
.ENA(ENA), // Port A RAM Enable Input
|
|
.ENB(ENB), // Port B RAM Enable Input
|
|
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A Write Enable Input
|
|
.WEB(WEB) // Port B Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S2_S36_inst instantiation
|
|
</Template>
|
|
<Template label="8k/4k x 2/4 (RAMB16_S2_S4)" treetype="template">
|
|
// RAMB16_S2_S4 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S2_S4_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S2_S4: 8k/4k x 2/4 Dual-Port RAM
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S2_S4 #(
|
|
.INIT_A(2'b00), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(4'h0), // Value of output RAM registers on Port B at startup
|
|
.SRVAL_A(2'b00), // Port A output value upon SSR assertion
|
|
.SRVAL_B(4'h0), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Port A Address 0 to 2047, Port B Address 0 to 1023
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 2048 to 4095, Port B Address 1024 to 2047
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 4096 to 6143, Port B Address 2048 to 3071
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 6144 to 8191, Port B Address 3072 to 4095
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S2_S4_inst (
|
|
.DOA(DOA), // Port A 2-bit Data Output
|
|
.DOB(DOB), // Port B 4-bit Data Output
|
|
.ADDRA(ADDRA), // Port A 13-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 12-bit Address Input
|
|
.CLKA(CLKA), // Port A Clock
|
|
.CLKB(CLKB), // Port B Clock
|
|
.DIA(DIA), // Port A 2-bit Data Input
|
|
.DIB(DIB), // Port B 4-bit Data Input
|
|
.ENA(ENA), // Port A RAM Enable Input
|
|
.ENB(ENB), // Port B RAM Enable Input
|
|
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A Write Enable Input
|
|
.WEB(WEB) // Port B Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S2_S4_inst instantiation
|
|
</Template>
|
|
<Template label="8k/2k x 2/8 + 0/1 Parity bit (RAMB16_S2_S9)" treetype="template">
|
|
// RAMB16_S2_S9 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S2_S9_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S2_S9: 8k/2k x 2/8 + 0/1 Parity bit Dual-Port RAM
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S2_S9 #(
|
|
.INIT_A(2'b00), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(9'h000), // Value of output RAM registers on Port B at startup
|
|
.SRVAL_A(2'b00), // Port A output value upon SSR assertion
|
|
.SRVAL_B(9'h000), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Port A Address 0 to 2047, Port B Address 0 to 511
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 2048 to 4095, Port B Address 512 to 1023
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 4096 to 6143, Port B Address 1024 to 1535
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 6144 to 8191, Port B Address 1536 to 2047
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
// Port B Address 0 to 511
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 512 to 1023
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 1024 to 1535
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 1536 to 2047
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S2_S9_inst (
|
|
.DOA(DOA), // Port A 2-bit Data Output
|
|
.DOB(DOB), // Port B 8-bit Data Output
|
|
.DOPB(DOPB), // Port B 1-bit Parity Output
|
|
.ADDRA(ADDRA), // Port A 13-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 11-bit Address Input
|
|
.CLKA(CLKA), // Port A Clock
|
|
.CLKB(CLKB), // Port B Clock
|
|
.DIA(DIA), // Port A 2-bit Data Input
|
|
.DIB(DIB), // Port B 8-bit Data Input
|
|
.DIPB(DIPB), // Port-B 1-bit parity Input
|
|
.ENA(ENA), // Port A RAM Enable Input
|
|
.ENB(ENB), // Port B RAM Enable Input
|
|
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A Write Enable Input
|
|
.WEB(WEB) // Port B Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S2_S9_inst instantiation
|
|
</Template>
|
|
<Template label="8k/1k x 2/16 + 0/2 Parity bit (RAMB16_S2_S18)" treetype="template">
|
|
// RAMB16_S2_S18 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S2_S18_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S2_S18: 8k/1k x 2/16 + 0/2 Parity bits Dual-Port RAM
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S2_S18 #(
|
|
.INIT_A(2'b00), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(9'h000), // Value of output RAM registers on Port B at startup
|
|
.SRVAL_A(2'b00), // Port A output value upon SSR assertion
|
|
.SRVAL_B(9'h000), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Port A Address 0 to 2047, Port B Address 0 to 255
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 2048 to 4095, Port B Address 256 to 511
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 4096 to 6143, Port B Address 512 to 767
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 6144 to 8191, Port B Address 768 to 1023
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
// Port B Address 0 to 255
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 256 to 511
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 512 to 767
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 768 to 1023
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S2_S18_inst (
|
|
.DOA(DOA), // Port A 2-bit Data Output
|
|
.DOB(DOB), // Port B 16-bit Data Output
|
|
.DOPB(DOPB), // Port B 2-bit Parity Output
|
|
.ADDRA(ADDRA), // Port A 13-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 10-bit Address Input
|
|
.CLKA(CLKA), // Port A Clock
|
|
.CLKB(CLKB), // Port B Clock
|
|
.DIA(DIA), // Port A 2-bit Data Input
|
|
.DIB(DIB), // Port B 16-bit Data Input
|
|
.DIPB(DIPB), // Port-B 2-bit parity Input
|
|
.ENA(ENA), // Port A RAM Enable Input
|
|
.ENB(ENB), // Port B RAM Enable Input
|
|
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A Write Enable Input
|
|
.WEB(WEB) // Port B Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S2_S18_inst instantiation
|
|
</Template>
|
|
<Template label="4k/1k x 4/16 + 0/2 Parity bits (RAMB16_S4_S18)" treetype="template">
|
|
// RAMB16_S4_S18 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S4_S18_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S4_S18: 4k/1k x 4/16 + 0/2 Parity bits Dual-Port RAM
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S4_S18 #(
|
|
.INIT_A(4'h0), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(18'h00000), // Value of output RAM registers on Port B at startup
|
|
.SRVAL_A(4'h0), // Port A output value upon SSR assertion
|
|
.SRVAL_B(18'h00000), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Port A Address 0 to 1023, Port B Address 0 to 255
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 1024 to 2047, Port B Address 256 to 511
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 2048 to 3071, Port B Address 512 to 767
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 3072 to 4095, Port B Address 768 to 1023
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
// Port A Address 0 to 1023, Port B Address 0 to 255
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 1024 to 2047, Port B Address 256 to 511
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 2048 to 3071, Port B Address 512 to 767
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 3072 to 4095, Port B Address 768 to 1023
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S4_S18_inst (
|
|
.DOA(DOA), // Port A 4-bit Data Output
|
|
.DOB(DOB), // Port B 16-bit Data Output
|
|
.DOPB(DOPB), // Port B 2-bit Parity Output
|
|
.ADDRA(ADDRA), // Port A 12-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 10-bit Address Input
|
|
.CLKA(CLKA), // Port A Clock
|
|
.CLKB(CLKB), // Port B Clock
|
|
.DIA(DIA), // Port A 4-bit Data Input
|
|
.DIB(DIB), // Port B 16-bit Data Input
|
|
.DIPB(DIPB), // Port-B 2-bit parity Input
|
|
.ENA(ENA), // Port A RAM Enable Input
|
|
.ENB(ENB), // Port B RAM Enable Input
|
|
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A Write Enable Input
|
|
.WEB(WEB) // Port B Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S4_S18_inst instantiation
|
|
</Template>
|
|
<Template label="4k/512 x 4/32 + 0/4 Parity bits (RAMB16_S4_S36)" treetype="template">
|
|
// RAMB16_S4_S36 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S4_S36_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S4_S36: 4k/512 x 4/32 + 0/4 Parity bits Dual-Port RAM
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S4_S36 #(
|
|
.INIT_A(4'h0), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup
|
|
.SRVAL_A(4'h0), // Port A output value upon SSR assertion
|
|
.SRVAL_B(36'h000000000), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Port A Address 0 to 1023, Port B Address 0 to 127
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 1024 to 2047, Port B Address 128 to 255
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 2048 to 3071, Port B Address 256 to 383
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 3072 to 4095, Port B Address 384 to 511
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
// Port A Address 0 to 1023, Port B Address 0 to 127
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 1024 to 2047, Port B Address 128 to 255
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 2048 to 3071, Port B Address 256 to 383
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 3072 to 4095, Port B Address 384 to 511
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S4_S36_inst (
|
|
.DOA(DOA), // Port A 4-bit Data Output
|
|
.DOB(DOB), // Port B 32-bit Data Output
|
|
.DOPB(DOPB), // Port B 4-bit Parity Output
|
|
.ADDRA(ADDRA), // Port A 12-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 9-bit Address Input
|
|
.CLKA(CLKA), // Port A Clock
|
|
.CLKB(CLKB), // Port B Clock
|
|
.DIA(DIA), // Port A 4-bit Data Input
|
|
.DIB(DIB), // Port B 32-bit Data Input
|
|
.DIPB(DIPB), // Port-B 4-bit parity Input
|
|
.ENA(ENA), // Port A RAM Enable Input
|
|
.ENB(ENB), // Port B RAM Enable Input
|
|
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A Write Enable Input
|
|
.WEB(WEB) // Port B Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S4_S36_inst instantiation
|
|
</Template>
|
|
<Template label="4k/2k x 4/8 + 0/1 Parity bit (RAMB16_S4_S9)" treetype="template">
|
|
// RAMB16_S4_S9 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S4_S9_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S4_S9: 4k/2k x 4/8 + 0/1 Parity bit Dual-Port RAM
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S4_S9 #(
|
|
.INIT_A(4'h0), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(9'h000), // Value of output RAM registers on Port B at startup
|
|
.SRVAL_A(4'h0), // Port A output value upon SSR assertion
|
|
.SRVAL_B(9'h000), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Port A Address 0 to 1023, Port B Address 0 to 511
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 1024 to 2047, Port B Address 512 to 1023
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 2048 to 3071, Port B Address 1024 to 1535
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 3072 to 4095, Port B Address 1536 to 2047
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
// Port B Address 0 to 511
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 512 to 1023
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 1024 to 1535
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 1536 to 2047
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S4_S9_inst (
|
|
.DOA(DOA), // Port A 4-bit Data Output
|
|
.DOB(DOB), // Port B 8-bit Data Output
|
|
.DOPB(DOPB), // Port B 1-bit Parity Output
|
|
.ADDRA(ADDRA), // Port A 12-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 11-bit Address Input
|
|
.CLKA(CLKA), // Port A Clock
|
|
.CLKB(CLKB), // Port B Clock
|
|
.DIA(DIA), // Port A 4-bit Data Input
|
|
.DIB(DIB), // Port B 8-bit Data Input
|
|
.DIPB(DIPB), // Port-B 1-bit parity Input
|
|
.ENA(ENA), // Port A RAM Enable Input
|
|
.ENB(ENB), // Port B RAM Enable Input
|
|
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A Write Enable Input
|
|
.WEB(WEB) // Port B Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S4_S9_inst instantiation
|
|
</Template>
|
|
<Template label="2k/1k x 8/16 + 1/2 Parity bits (RAMB16_S9_S18)" treetype="template">
|
|
// RAMB16_S9_S18 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S9_S18_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S9_S18: 2k/1k x 8/16 + 1/2 Parity bits Parity bits Dual-Port RAM
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S9_S18 #(
|
|
.INIT_A(9'h000), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(18'h00000), // Value of output RAM registers on Port B at startup
|
|
.SRVAL_A(9'h000), // Port A output value upon SSR assertion
|
|
.SRVAL_B(18'h00000), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Port A Address 0 to 511, Port B Address 0 to 255
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 512 to 1023, Port B Address 256 to 511
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 1024 to 1535, Port B Address 512 to 767
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 1536 to 2047, Port B Address 768 to 1024
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
// Port A Address 0 to 511, Port B Address 0 to 255
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 512 to 1023, Port B Address 256 to 511
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 1024 to 1535, Port B Address 512 to 767
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 1536 to 2047, Port B Address 768 to 1024
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S9_S18_inst (
|
|
.DOA(DOA), // Port A 8-bit Data Output
|
|
.DOB(DOB), // Port B 16-bit Data Output
|
|
.DOPA(DOPA), // Port A 1-bit Parity Output
|
|
.DOPB(DOPB), // Port B 2-bit Parity Output
|
|
.ADDRA(ADDRA), // Port A 11-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 10-bit Address Input
|
|
.CLKA(CLKA), // Port A Clock
|
|
.CLKB(CLKB), // Port B Clock
|
|
.DIA(DIA), // Port A 8-bit Data Input
|
|
.DIB(DIB), // Port B 16-bit Data Input
|
|
.DIPA(DIPA), // Port A 1-bit parity Input
|
|
.DIPB(DIPB), // Port-B 2-bit parity Input
|
|
.ENA(ENA), // Port A RAM Enable Input
|
|
.ENB(ENB), // Port B RAM Enable Input
|
|
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A Write Enable Input
|
|
.WEB(WEB) // Port B Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S9_S18_inst instantiation
|
|
</Template>
|
|
<Template label="2k/512 x 8/32 + 1/4 Parity (RAMB16_S9_S36)" treetype="template">
|
|
// RAMB16_S9_S36 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S9_S36_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S9_S36: 2k/512 x 8/32 + 1/4 Parity bits Parity bits Dual-Port RAM
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S9_S36 #(
|
|
.INIT_A(9'h000), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup
|
|
.SRVAL_A(9'h000), // Port A output value upon SSR assertion
|
|
.SRVAL_B(36'h000000000), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Port A Address 0 to 511, Port B Address 0 to 127
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 512 to 1023, Port B Address 128 to 255
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 1024 to 1535, Port B Address 255 to 383
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 1536 to 2047, Port B Address 384 to 511
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
// Port A Address 0 to 511, Port B Address 0 to 127
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 512 to 1023, Port B Address 128 to 255
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 1024 to 1535, Port B Address 256 to 383
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 1536 to 2047, Port B Address 384 to 511
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S9_S36_inst (
|
|
.DOA(DOA), // Port A 8-bit Data Output
|
|
.DOB(DOB), // Port B 32-bit Data Output
|
|
.DOPA(DOPA), // Port A 1-bit Parity Output
|
|
.DOPB(DOPB), // Port B 4-bit Parity Output
|
|
.ADDRA(ADDRA), // Port A 11-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 9-bit Address Input
|
|
.CLKA(CLKA), // Port A Clock
|
|
.CLKB(CLKB), // Port B Clock
|
|
.DIA(DIA), // Port A 8-bit Data Input
|
|
.DIB(DIB), // Port B 32-bit Data Input
|
|
.DIPA(DIPA), // Port A 1-bit parity Input
|
|
.DIPB(DIPB), // Port-B 4-bit parity Input
|
|
.ENA(ENA), // Port A RAM Enable Input
|
|
.ENB(ENB), // Port B RAM Enable Input
|
|
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A Write Enable Input
|
|
.WEB(WEB) // Port B Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S9_S36_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Arithmetic Functions" treetype="folder">
|
|
<Template label="18X18 Asynchronous Multiplier (MULT18X18)" treetype="template">
|
|
// MULT18X18 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MULT18X18_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MULT18X18: 18 x 18 signed asynchronous multiplier
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MULT18X18 MULT18X18_inst (
|
|
.P(P), // 36-bit multiplier output
|
|
.A(A), // 18-bit multiplier input
|
|
.B(B) // 18-bit multiplier input
|
|
);
|
|
|
|
// End of MULT18X18_inst instantiation
|
|
</Template>
|
|
<Template label="18X18 Synchronous Multiplier (MULT18X18S)" treetype="template">
|
|
// MULT18X18S : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MULT18X18S_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MULT18X18S: 18 x 18 signed synchronous multiplier
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MULT18X18S MULT18X18S_inst (
|
|
.P(P), // 36-bit multiplier output
|
|
.A(A), // 18-bit multiplier input
|
|
.B(B), // 18-bit multiplier input
|
|
.C(C), // Clock input
|
|
.CE(CE), // Clock enable input
|
|
.R(R) // Synchronous reset input
|
|
);
|
|
|
|
// End of MULT18X18S_inst instantiation
|
|
</Template>
|
|
<Template label="18X18 Cascadable Multiplier (MULT18X18SIO)" treetype="template">
|
|
// MULT18X18SIO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MULT18X18SIO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MULT18X18SIO: 18 x 18 cascadable, signed synchronous/asynchronous multiplier
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MULT18X18SIO #(
|
|
.AREG(1), // Enable the input registers on the A port (1=on, 0=off)
|
|
.BREG(1), // Enable the input registers on the B port (1=on, 0=off)
|
|
.B_INPUT("DIRECT"), // B cascade input "DIRECT" or "CASCADE"
|
|
.PREG(1) // Enable the input registers on the P port (1=on, 0=off)
|
|
) MULT18X18SIO_inst (
|
|
.BCOUT(BCOUT), // 18-bit cascade output
|
|
.P(P), // 36-bit multiplier output
|
|
.A(A), // 18-bit multiplier input
|
|
.B(B), // 18-bit multiplier input
|
|
.BCIN(BCIN), // 18-bit cascade input
|
|
.CEA(CEA), // Clock enable input for the A port
|
|
.CEB(CEB), // Clock enable input for the B port
|
|
.CEP(CEP), // Clock enable input for the P port
|
|
.CLK(CLK), // Clock input
|
|
.RSTA(RSTA), // Synchronous reset input for the A port
|
|
.RSTB(RSTB), // Synchronous reset input for the B port
|
|
.RSTP(RSTP) // Synchronous reset input for the P port
|
|
);
|
|
|
|
// End of MULT18X18SIO_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Config/BSCAN Components" treetype="folder">
|
|
<Template label="Startup Block (STARTUP_SPARTAN3E)" treetype="template">
|
|
// STARTUP_SPARTAN3E : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (STARTUP_SPARTAN3E_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// STARTUP_SPARTAN3E: Startup primitive for GSR, GTS, startup sequence control
|
|
// and Multi-Boot Configuration Trigger. Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
STARTUP_SPARTAN3E STARTUP_SPARTAN3E_inst (
|
|
.CLK(CLK), // Clock input for start-up sequence
|
|
.GSR(GSR_PORT), // Global Set/Reset input (GSR cannot be used as a port name)
|
|
.GTS(GTS_PORT), // Global 3-state input (GTS cannot be used as a port name)
|
|
.MBT(MBT) // Multi-Boot Trigger input
|
|
);
|
|
|
|
// End of STARTUP_SPARTAN3E_inst instantiation
|
|
</Template>
|
|
<Template label="Boundary Scan (BSCAN_SPARTAN3)" treetype="template">
|
|
// BSCAN_SPARTAN3 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BSCAN_SPARTAN3_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BSCAN_SPARTAN3: Boundary Scan primitive for connecting internal logic to
|
|
// JTAG interface.
|
|
// Spartan-3E/3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BSCAN_SPARTAN3 BSCAN_SPARTAN3_inst (
|
|
.CAPTURE(CAPTURE), // CAPTURE output from TAP controller
|
|
.DRCK1(DRCK1), // Data register output for USER1 functions
|
|
.DRCK2(DRCK2), // Data register output for USER2 functions
|
|
.RESET(RESET), // Reset output from TAP controller
|
|
.SEL1(SEL1), // USER1 active output
|
|
.SEL2(SEL2), // USER2 active output
|
|
.SHIFT(SHIFT), // SHIFT output from TAP controller
|
|
.TDI(TDI), // TDI output from TAP controller
|
|
.UPDATE(UPDATE), // UPDATE output from TAP controller
|
|
.TDO1(TDO1), // Data input for USER1 function
|
|
.TDO2(TDO2) // Data input for USER2 function
|
|
);
|
|
|
|
// End of BSCAN_SPARTAN3_inst instantiation
|
|
</Template>
|
|
<Template label="Register Capture (CAPTURE_SPARTAN3)" treetype="template">
|
|
// CAPTURE_SPARTAN3 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (CAPTURE_SPARTAN3_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// CAPTURE_SPARTAN3: Register State Capture for Bitstream Readback
|
|
// Spartan-3E/3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
CAPTURE_SPARTAN3 CAPTURE_SPARTAN3_inst (
|
|
.CAP(CAP), // Capture input
|
|
.CLK(CLK) // Clock input
|
|
);
|
|
|
|
// End of CAPTURE_SPARTAN3_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="I/O Components" treetype="folder">
|
|
<SubFolder label="Input" treetype="folder">
|
|
<Template label="Single-ended Buffer (IBUF)" treetype="template">
|
|
// IBUF : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUF_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUF: Single-ended Input Buffer
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUF #(
|
|
.IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for
|
|
// the buffer: "0"-"12" (Spartan-3E)
|
|
.IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input
|
|
// register: "AUTO", "0"-"6" (Spartan-3E)
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
)IBUF_inst (
|
|
.O(O), // Buffer output
|
|
.I(I) // Buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUF_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer (IBUFDS)" treetype="template">
|
|
// IBUFDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFDS: Differential Input Buffer
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFDS #(
|
|
.IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for
|
|
// the buffer: "0"-"12" (Spartan-3E)
|
|
.IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input
|
|
// register: "AUTO", "0"-"6" (Spartan-3E)
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
) IBUFDS_inst (
|
|
.O(O), // Buffer output
|
|
.I(I), // Diff_p buffer input (connect directly to top-level port)
|
|
.IB(IB) // Diff_n buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUFDS_inst instantiation
|
|
</Template>
|
|
<Template label="Single-ended Global Clock (IBUFG)" treetype="template">
|
|
// IBUFG : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFG_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFG: Single-ended global clock input buffer
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFG #(
|
|
.IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for
|
|
// the buffer: "0"-"12" (Spartan-3E)
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
) IBUFG_inst (
|
|
.O(O), // Clock buffer output
|
|
.I(I) // Clock buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUFG_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Global Clock (IBUFGDS)" treetype="template">
|
|
// IBUFGDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFGDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFGDS: Differential Global Clock Input Buffer
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFGDS #(
|
|
.IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for
|
|
// the buffer, "0"-"12" (Spartan-3E)
|
|
.DIFF_TERM("FALSE"), // Differential Termination
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
) IBUFGDS_inst (
|
|
.O(O), // Clock buffer output
|
|
.I(I), // Diff_p clock buffer input (connect directly to top-level port)
|
|
.IB(IB) // Diff_n clock buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUFGDS_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Output" treetype="folder">
|
|
<Template label="Single-ended Buffer (OBUF)" treetype="template">
|
|
// OBUF : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OBUF_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OBUF: Single-ended Output Buffer
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OBUF #(
|
|
.DRIVE(12), // Specify the output drive strength
|
|
.IOSTANDARD("DEFAULT"), // Specify the output I/O standard
|
|
.SLEW("SLOW") // Specify the output slew rate
|
|
) OBUF_inst (
|
|
.O(O), // Buffer output (connect directly to top-level port)
|
|
.I(I) // Buffer input
|
|
);
|
|
|
|
// End of OBUF_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer (OBUFDS)" treetype="template">
|
|
|
|
// OBUFDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OBUFDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OBUFDS: Differential Output Buffer
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OBUFDS #(
|
|
.IOSTANDARD("DEFAULT") // Specify the output I/O standard
|
|
) OBUFDS_inst (
|
|
.O(O), // Diff_p output (connect directly to top-level port)
|
|
.OB(OB), // Diff_n output (connect directly to top-level port)
|
|
.I(I) // Buffer input
|
|
);
|
|
|
|
// End of OBUFDS_inst instantiation
|
|
</Template>
|
|
<Template label="Single-ended 3-state Buffer (OBUFT)" treetype="template">
|
|
// OBUFT : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OBUFT_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OBUFT: Single-ended 3-state Output Buffer
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OBUFT #(
|
|
.DRIVE(12), // Specify the output drive strength
|
|
.IOSTANDARD("DEFAULT"), // Specify the output I/O standard
|
|
.SLEW("SLOW") // Specify the output slew rate
|
|
) OBUFT_inst (
|
|
.O(O), // Buffer output (connect directly to top-level port)
|
|
.I(I), // Buffer input
|
|
.T(T) // 3-state enable input
|
|
);
|
|
|
|
// End of OBUFT_inst instantiation
|
|
</Template>
|
|
<Template label="Differential 3-state Buffer (OBUFTDS)" treetype="template">
|
|
// OBUFTDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OBUFTDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OBUFTDS: Differential 3-state Output Buffer
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OBUFTDS #(
|
|
.IOSTANDARD("DEFAULT") // Specify the output I/O standard
|
|
) OBUFTDS_inst (
|
|
.O(O), // Diff_p output (connect directly to top-level port)
|
|
.OB(OB), // Diff_n output (connect directly to top-level port)
|
|
.I(I), // Buffer input
|
|
.T(T) // 3-state enable input
|
|
);
|
|
|
|
// End of OBUFTDS_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Bi-directional" treetype="folder">
|
|
<Template label="Single-ended Buffer (IOBUF)" treetype="template">
|
|
// IOBUF : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IOBUF_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IOBUF: Single-ended Bi-directional Buffer
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IOBUF #(
|
|
.DRIVE(12), // Specify the output drive strength
|
|
.IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for the buffer,
|
|
// "0"-"12" (Spartan-3E only)
|
|
.IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input register,
|
|
// "AUTO", "0"-"6" (Spartan-3E only)
|
|
.IOSTANDARD("DEFAULT"), // Specify the I/O standard
|
|
.SLEW("SLOW") // Specify the output slew rate
|
|
) IOBUF_inst (
|
|
.O(O), // Buffer output
|
|
.IO(IO), // Buffer inout port (connect directly to top-level port)
|
|
.I(I), // Buffer input
|
|
.T(T) // 3-state enable input, high=input, low=output
|
|
);
|
|
|
|
// End of IOBUF_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer (IOBUFDS)" treetype="template">
|
|
// IOBUFDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IOBUFDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IOBUFDS: Differential Bi-directional Buffer
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IOBUFDS #(
|
|
.IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for the buffer,
|
|
// "0"-"12" (Spartan-3E only)
|
|
.IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input register,
|
|
// "AUTO", "0"-"6" (Spartan-3E only)
|
|
.IOSTANDARD("DEFAULT") // Specify the I/O standard
|
|
) IOBUFDS_inst (
|
|
.O(O), // Buffer output
|
|
.IO(IO), // Diff_p inout (connect directly to top-level port)
|
|
.IOB(IOB), // Diff_n inout (connect directly to top-level port)
|
|
.I(I), // Buffer input
|
|
.T(T) // 3-state enable input, high=input, low=output
|
|
);
|
|
|
|
// End of IOBUFDS_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Weak drivers" treetype="folder">
|
|
<Template label="PULLUP" treetype="template">
|
|
// PULLUP : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (PULLUP_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design.
|
|
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// PULLUP: I/O Buffer Weak Pull-up
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
PULLUP PULLUP_inst (
|
|
.O(O) // Pullup output (connect directly to top-level port)
|
|
);
|
|
|
|
// End of PULLUP_inst instantiation
|
|
</Template>
|
|
<Template label="PULLDOWN" treetype="template">
|
|
// PULLDOWN : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (PULLDOWN_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// PULLDOWN: I/O Buffer Weak Pull-down
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
PULLDOWN PULLDOWN_inst (
|
|
.O(O) // Pulldown output (connect directly to top-level port)
|
|
);
|
|
|
|
// End of PULLDOWN_inst instantiation
|
|
</Template>
|
|
<Template label="KEEPER" treetype="template">
|
|
// KEEPER : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (KEEPER_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// KEEPER: I/O Buffer Weak Keeper
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
KEEPER KEEPER_inst (
|
|
.O(O) // Keeper output (connect directly to top-level port)
|
|
);
|
|
|
|
// End of KEEPER_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="DDR Registers" treetype="folder">
|
|
<Template label="Input DDR Register (IDDR2)" treetype="template">
|
|
// IDDR2 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IDDR2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IDDR2: Input Double Data Rate Input Register with Set, Reset
|
|
// and Clock Enable.
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IDDR2 #(
|
|
.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
|
|
.INIT_Q0(1'b0), // Sets initial state of the Q0 output to 1'b0 or 1'b1
|
|
.INIT_Q1(1'b0), // Sets initial state of the Q1 output to 1'b0 or 1'b1
|
|
.SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
|
|
) IDDR2_inst (
|
|
.Q0(Q0), // 1-bit output captured with C0 clock
|
|
.Q1(Q1), // 1-bit output captured with C1 clock
|
|
.C0(C0), // 1-bit clock input
|
|
.C1(C1), // 1-bit clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.D(D), // 1-bit DDR data input
|
|
.R(R), // 1-bit reset input
|
|
.S(S) // 1-bit set input
|
|
);
|
|
|
|
// End of IDDR2_inst instantiation
|
|
</Template>
|
|
<Template label="Output DDR Register (ODDR2)" treetype="template">
|
|
// ODDR2 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ODDR2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ODDR2: Output Double Data Rate Output Register with Set, Reset
|
|
// and Clock Enable.
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ODDR2 #(
|
|
.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
|
|
.INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1
|
|
.SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
|
|
) ODDR2_inst (
|
|
.Q(Q), // 1-bit DDR output data
|
|
.C0(C0), // 1-bit clock input
|
|
.C1(C1), // 1-bit clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.D0(D0), // 1-bit data input (associated with C0)
|
|
.D1(D1), // 1-bit data input (associated with C1)
|
|
.R(R), // 1-bit reset input
|
|
.S(S) // 1-bit set input
|
|
);
|
|
|
|
// End of ODDR2_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Registers & Latches" treetype="folder">
|
|
<SubFolder label="Double Data Rate (DDR)" treetype="folder">
|
|
<Template label="Input DDR Register (IDDR2)" treetype="template">
|
|
// IDDR2 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IDDR2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IDDR2: Input Double Data Rate Input Register with Set, Reset
|
|
// and Clock Enable.
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IDDR2 #(
|
|
.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
|
|
.INIT_Q0(1'b0), // Sets initial state of the Q0 output to 1'b0 or 1'b1
|
|
.INIT_Q1(1'b0), // Sets initial state of the Q1 output to 1'b0 or 1'b1
|
|
.SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
|
|
) IDDR2_inst (
|
|
.Q0(Q0), // 1-bit output captured with C0 clock
|
|
.Q1(Q1), // 1-bit output captured with C1 clock
|
|
.C0(C0), // 1-bit clock input
|
|
.C1(C1), // 1-bit clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.D(D), // 1-bit DDR data input
|
|
.R(R), // 1-bit reset input
|
|
.S(S) // 1-bit set input
|
|
);
|
|
|
|
// End of IDDR2_inst instantiation
|
|
</Template>
|
|
<Template label="Output DDR Register (ODDR2)" treetype="template">
|
|
// ODDR2 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ODDR2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ODDR2: Output Double Data Rate Output Register with Set, Reset
|
|
// and Clock Enable.
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ODDR2 #(
|
|
.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
|
|
.INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1
|
|
.SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
|
|
) ODDR2_inst (
|
|
.Q(Q), // 1-bit DDR output data
|
|
.C0(C0), // 1-bit clock input
|
|
.C1(C1), // 1-bit clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.D0(D0), // 1-bit data input (associated with C0)
|
|
.D1(D1), // 1-bit data input (associated with C1)
|
|
.R(R), // 1-bit reset input
|
|
.S(S) // 1-bit set input
|
|
);
|
|
|
|
// End of ODDR2_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Single Data Rate" treetype="folder">
|
|
<Template label="Posedge D-FF w/ Async Clear, and CE (FDCE)" treetype="template">
|
|
// FDCE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FDCE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FDCE: Single Data Rate D Flip-Flop with Asynchronous Clear and
|
|
// Clock Enable (posedge clk).
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FDCE #(
|
|
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
|
|
) FDCE_inst (
|
|
.Q(Q), // Data output
|
|
.C(C), // Clock input
|
|
.CE(CE), // Clock enable input
|
|
.CLR(CLR), // Asynchronous clear input
|
|
.D(D) // Data input
|
|
);
|
|
|
|
// End of FDCE_inst instantiation
|
|
</Template>
|
|
<Template label="Posedge D-FF w/ Async Clear, Set and CE (FDCPE)" treetype="template">
|
|
// FDCPE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FDCPE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FDCPE: Single Data Rate D Flip-Flop with Asynchronous Clear, Set and
|
|
// Clock Enable (posedge clk).
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FDCPE #(
|
|
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
|
|
) FDCPE_inst (
|
|
.Q(Q), // Data output
|
|
.C(C), // Clock input
|
|
.CE(CE), // Clock enable input
|
|
.CLR(CLR), // Asynchronous clear input
|
|
.D(D), // Data input
|
|
.PRE(PRE) // Asynchronous set input
|
|
);
|
|
|
|
// End of FDCPE_inst instantiation
|
|
</Template>
|
|
<Template label="Posedge D-FF w/ Sync Clear, Set and CE (FDRSE)" treetype="template">
|
|
// FDRSE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FDCRS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FDRSE: Single Data Rate D Flip-Flop with Synchronous Clear, Set and
|
|
// Clock Enable (posedge clk).
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FDRSE #(
|
|
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
|
|
) FDRSE_inst (
|
|
.Q(Q), // Data output
|
|
.C(C), // Clock input
|
|
.CE(CE), // Clock enable input
|
|
.D(D), // Data input
|
|
.R(R), // Synchronous reset input
|
|
.S(S) // Synchronous set input
|
|
);
|
|
|
|
// End of FDRSE_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Transparent Latch" treetype="folder">
|
|
<Template label="Latch with Async Reset, Set and Gate Enable (LDCPE)" treetype="template">
|
|
// LDCPE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LDCPE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LDCPE: Transparent latch with Asynchronous Reset, Preset and
|
|
// Gate Enable.
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LDCPE #(
|
|
.INIT(1'b0) // Initial value of latch (1'b0 or 1'b1)
|
|
) LDCPE_inst (
|
|
.Q(Q), // Data output
|
|
.CLR(CLR), // Asynchronous clear/reset input
|
|
.D(D), // Data input
|
|
.G(G), // Gate input
|
|
.GE(GE), // Gate enable input
|
|
.PRE(PRE) // Asynchronous preset/set input
|
|
);
|
|
|
|
// End of LDCPE_inst instantiation
|
|
</Template>
|
|
<Template label="Latch with Async Reset and Gate Enable (LDCE)" treetype="template">
|
|
// LDCE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LDCE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LDCE: Transparent latch with Asynchronous Reset and Gate Enable.
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LDCE #(
|
|
.INIT(1'b0) // Initial value of latch (1'b0 or 1'b1)
|
|
) LDCE_inst (
|
|
.Q(Q), // Data output
|
|
.CLR(CLR), // Asynchronous clear/reset input
|
|
.D(D), // Data input
|
|
.G(G), // Gate input
|
|
.GE(GE) // Gate enable input
|
|
);
|
|
|
|
// End of LDCE_inst instantiation
|
|
</Template>
|
|
<Template label="Latch with Async Set and Gate Enable (LDPE)" treetype="template">
|
|
// LDPE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LDPE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LDPE: Transparent latch with Asynchronous Preset and Gate Enable.
|
|
// Spartan-3E
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LDPE #(
|
|
.INIT(1'b0) // Initial value of latch (1'b0 or 1'b1)
|
|
) LDPE_inst (
|
|
.Q(Q), // Data output
|
|
.PRE(PRE), // Asynchronous preset/set input
|
|
.D(D), // Data input
|
|
.G(G), // Gate input
|
|
.GE(GE) // Gate enable input
|
|
);
|
|
|
|
// End of LDPE_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Spartan-3" treetype="folder">
|
|
<SubFolder label="Slice/CLB Primitives" treetype="folder">
|
|
<SubFolder label="Carry-Chain" treetype="folder">
|
|
<Template label="MUXCY" treetype="template">
|
|
// MUXCY : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXCY_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs and
|
|
// : and outputs of this primitive should be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXCY: Carry-Chain MUX with general output
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXCY MUXCY_inst (
|
|
.O(O), // Carry output signal
|
|
.CI(CI), // Carry input signal
|
|
.DI(DI), // Data input signal
|
|
.S(S) // MUX select, tie to '1' or LUT4 out
|
|
);
|
|
|
|
// End of MUXCY_inst instantiation
|
|
</Template>
|
|
<Template label="MUXCY_L" treetype="template">
|
|
// MUXCY_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXCY_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXCY_L: Carry-Chain MUX with local output
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXCY_L MUXCY_L_inst (
|
|
.LO(LO), // Carry local output signal
|
|
.CI(CI), // Carry input signal
|
|
.DI(DI), // Data input signal
|
|
.S(S) // MUX select, tie to '1' or LUT4 out
|
|
);
|
|
|
|
// End of MUXCY_L_inst instantiation
|
|
</Template>
|
|
<Template label="MUXCY_D" treetype="template">
|
|
// MUXCY_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXCY_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXCY_D: Carry-Chain MUX with general and local outputs
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXCY_D MUXCY_D_inst (
|
|
.LO(LO), // Carry local output signal
|
|
.O(O), // Carry general output signal
|
|
.CI(CI), // Carry input signal
|
|
.DI(DI), // Data input signal
|
|
.S(S) // MUX select, tie to '1' or LUT4 out
|
|
);
|
|
|
|
// End of MUXCY_D_inst instantiation
|
|
</Template>
|
|
<Template label="XORCY" treetype="template">
|
|
// XORCY : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (XORCY_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// XORCY: Carry-Chain XOR-gate with general output
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
XORCY XORCY_inst (
|
|
.O(O), // XOR output signal
|
|
.CI(CI), // Carry input signal
|
|
.LI(LI) // LUT4 input signal
|
|
);
|
|
|
|
// End of XORCY_inst instantiation
|
|
</Template>
|
|
<Template label="XORCY_L" treetype="template">
|
|
// XORCY_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (XORCY_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// XORCY_L: Carry-Chain XOR-gate with local (direct-connect) output
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
XORCY_L XORCY_L_inst (
|
|
.LO(LO), // XOR local output signal
|
|
.CI(CI), // Carry input signal
|
|
.LI(LI) // LUT4 input signal
|
|
);
|
|
|
|
// End of XORCY_L_inst instantiation
|
|
</Template>
|
|
<Template label="XORCY_D" treetype="template">
|
|
// XORCY_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (XORCY_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// XORCY_D: Carry-Chain XOR-gate with local and general outputs
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
XORCY_D XORCY_D_inst (
|
|
.LO(LO), // XOR local output signal
|
|
.O(O), // XOR general output signal
|
|
.CI(CI), // Carry input signal
|
|
.LI(LI) // LUT4 input signal
|
|
);
|
|
|
|
// End of XORCY_D_inst instantiation
|
|
</Template>
|
|
<Template label="MULT_AND" treetype="template">
|
|
// MULT_AND : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MULT_AND_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MULT_AND: 2-input AND gate connected to Carry chain
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MULT_AND MULT_AND_inst (
|
|
.LO(LO), // MULT_AND output (connect to MUXCY DI)
|
|
.I0(I0), // MULT_AND data[0] input
|
|
.I1(I1) // MULT_AND data[1] input
|
|
);
|
|
|
|
// End of MULT_AND_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="MUXFx" treetype="folder">
|
|
<Template label="MUXF5" treetype="template">
|
|
// MUXF5 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF5_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF5: Slice MUX to tie two LUT4's together with general output
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF5 MUXF5_inst (
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie directly to the output of LUT4)
|
|
.I1(I1), // Input (tie directoy to the output of LUT4)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF5_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF5_L" treetype="template">
|
|
// MUXF5_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF5_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF5_L: Slice MUX to tie two LUT4's together with local output
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF5_L MUXF5_L_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.I0(I0), // Input (tie directly to the output of LUT4)
|
|
.I1(I1), // Input (tie directoy to the output of LUT4)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF5_L_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF5_D" treetype="template">
|
|
// MUXF5_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF5_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF5_D: Slice MUX to tie two LUT4's together with general and local outputs
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF5_D MUXF5_D_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie directly to the output of LUT4)
|
|
.I1(I1), // Input (tie directoy to the output of LUT4)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF5_D_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF6" treetype="template">
|
|
// MUXF6 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF6_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF6: CLB MUX to tie two MUXF5's together with general output
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF6 MUXF6_inst (
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie to MUXF5 LO out)
|
|
.I1(I1), // Input (tie to MUXF5 LO out)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF6_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF6_L" treetype="template">
|
|
// MUXF6_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF6_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF6_L: CLB MUX to tie two MUXF5's together with local output
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF6_L MUXF6_L_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.I0(I0), // Input (tie to MUXF5 LO out)
|
|
.I1(I1), // Input (tie to MUXF5 LO out)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF6_L_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF6_D" treetype="template">
|
|
// MUXF6_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF6_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF6_D: CLB MUX to tie two MUXF5's together with general and local outputs
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF6_D MUXF6_D_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie to MUXF5 LO out)
|
|
.I1(I1), // Input (tie to MUXF5 LO out)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF6_D_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF7" treetype="template">
|
|
// MUXF7 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF7_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF7: CLB MUX to tie two MUXF6's together with general output
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF7 MUXF7_inst (
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie to MUXF6 LO out or LUT6 O6 pin)
|
|
.I1(I1), // Input (tie to MUXF6 LO out or LUT6 O6 pin)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF7_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF7_L" treetype="template">
|
|
// MUXF7_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF7_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF7_L: CLB MUX to tie two MUXF6's together with local output
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF7_L MUXF7_L_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.I0(I0), // Input (tie to MUXF6 LO out or LUT6 O6 pin)
|
|
.I1(I1), // Input (tie to MUXF6 LO out or LUT6 O6 pin)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF7_L_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF7_D" treetype="template">
|
|
// MUXF7_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF7_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF7_D: CLB MUX to tie two MUXF6's together with general and local outputs
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF7_D MUXF7_D_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie to MUXF6 LO out or LUT6 O6 pin)
|
|
.I1(I1), // Input (tie to MUXF6 LO out or LUT6 O6 pin)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF7_D_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF8" treetype="template">
|
|
// MUXF8 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF8_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF8: CLB MUX to tie two MUXF7's together with general output
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF8 MUXF8_inst (
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie to MUXF7 LO out)
|
|
.I1(I1), // Input (tie to MUXF7 LO out)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF8_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF8_L" treetype="template">
|
|
// MUXF8_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF8_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF8_L: CLB MUX to tie two MUXF7's together with local output
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF8_L MUXF8_L_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.I0(I0), // Input (tie to MUXF7 LO out)
|
|
.I1(I1), // Input (tie to MUXF7 LO out)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF8_L_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF8_D" treetype="template">
|
|
// MUXF8_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF8_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF8_D: CLB MUX to tie two MUXF7's together with general and local outputs
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF8_D MUXF8_D_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie to MUXF7 LO out)
|
|
.I1(I1), // Input (tie to MUXF7 LO out)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF8_D_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="LUTs" treetype="folder">
|
|
<SubFolder label="Info" treetype="folder">
|
|
<Template label="Info (LUT INIT)" treetype="template">
|
|
// The INIT parameter for the FPGA LUT primitive is what gives the LUT its
|
|
// logical value. By default this value is zero thus driving the output to a
|
|
// zero regardless of the input values (acting as a ground) however in most
|
|
// cases an new INIT value must be determined in order to specify the logic
|
|
// function for the LUT primitive. There are a few methods in which the LUT
|
|
// value can be determined and two of those methods will be discussed here.
|
|
//
|
|
// The Truth Table Method
|
|
// ----------------------
|
|
//
|
|
// A common method to determine the desired INIT value for a LUT is using a
|
|
// truth table. To do so, simply create a binary truth table of all possible
|
|
// inputs, specify the desired logic value of the output and then create the
|
|
// INIT string from those output values. An example is shown below:
|
|
//
|
|
// Example of determining an XOR INIT equation for a LUT4:
|
|
//
|
|
// _________________
|
|
// | I3 I2 I1 I0 | O |
|
|
// |-----------------|
|
|
// | 0 0 0 0 | 0 |\
|
|
// | 0 0 0 1 | 1 | \ = 4'b0110 = 4'h6 ---------------+
|
|
// | 0 0 1 0 | 1 | / |
|
|
// | 0 0 1 1 | 0 |/ |
|
|
// |-------------|---| |
|
|
// | 0 1 0 0 | 1 |\ |
|
|
// | 0 1 0 1 | 0 | \ = 4'b1001 = 4'h9 |
|
|
// | 0 1 1 0 | 0 | / |
|
|
// | 0 1 1 1 | 1 |/ |
|
|
// |-------------|---| INIT = 16'h6996
|
|
// | 1 0 0 0 | 1 |\ |
|
|
// | 1 0 0 1 | 0 | \ = 4'b0110 = 4'h9 |
|
|
// | 1 0 1 0 | 0 | / |
|
|
// | 1 0 1 1 | 1 |/ |
|
|
// |-------------|---| |
|
|
// | 1 1 0 0 | 0 |\ |
|
|
// | 1 1 0 1 | 1 | \ = 4'b1001 = 4'h6 ------------+
|
|
// | 1 1 1 0 | 1 | /
|
|
// | 1 1 1 1 | 0 |/
|
|
// -------------------
|
|
//
|
|
// Example of determining a 3-input AND gate:
|
|
//
|
|
// ______________
|
|
// | I2 I1 I0 | O |
|
|
// |--------------|
|
|
// | 0 0 0 | 0 |\
|
|
// | 0 0 1 | 0 | \ = 4'b0000 = 4'h0 --------------+
|
|
// | 0 1 0 | 0 | / |
|
|
// | 0 1 1 | 0 |/ |
|
|
// |----------|---| INIT = 8'h80
|
|
// | 1 0 0 | 0 |\ |
|
|
// | 1 0 1 | 0 | \ = 4'b1000 = 4'h8 -------------+
|
|
// | 1 1 0 | 0 | /
|
|
// | 1 1 1 | 1 |/
|
|
// ----------------
|
|
//
|
|
// The Equation Method
|
|
// -------------------
|
|
//
|
|
// Another method to determine the LUT value is to define parameters for each
|
|
// input to the LUT that correspond to their listed truth value and use those to
|
|
// build the logic equation you are after. This method is easier to understand
|
|
// once you have grasped the concept and more self-documenting that the above
|
|
// method however does require the code to first specify the appropriate
|
|
// parameters. See the example below.
|
|
//
|
|
// Example of specifying the equation (A and B) or (C and D) for a LUT4:
|
|
//
|
|
// The forllowing parameters are defined to allow for
|
|
// equation-based INIT specification.
|
|
parameter I0 = 16'haaaa;
|
|
parameter I1 = 16'hcccc;
|
|
parameter I2 = 16'hf0f0;
|
|
parameter I3 = 16'hff00;
|
|
|
|
// LUT4: 4-input Look-Up Table with general output
|
|
// for use with all FPGAs.
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT4 #(
|
|
.INIT((I0&I1)|(I2&I3)) // Specify LUT Contents
|
|
) LUT4_inst (
|
|
.O(O_LUT), // LUT general output
|
|
.I0(A), // LUT input
|
|
.I1(B), // LUT input
|
|
.I2(C), // LUT input
|
|
.I3(D) // LUT input
|
|
);
|
|
|
|
// End of LUT4_inst instantiation
|
|
|
|
// With the parameters specifying all possible cases for the truth table, a
|
|
// Verilog equation can be written to determine the end INIT value.
|
|
</Template>
|
|
<SubFolder label="INIT Parameters" treetype="folder">
|
|
<Template label="LUT1" treetype="template">
|
|
// The forllowing parameter is defined to allow for
|
|
// equation-based INIT specification for a LUT1.
|
|
parameter I0 = 2'b10;
|
|
</Template>
|
|
<Template label="LUT2" treetype="template">
|
|
// The forllowing parameters are defined to allow for
|
|
// equation-based INIT specification for a LUT2.
|
|
parameter I0 = 4'ha;
|
|
parameter I1 = 4'hc;
|
|
</Template>
|
|
<Template label="LUT3" treetype="template">
|
|
// The forllowing parameters are defined to allow for
|
|
// equation-based INIT specification for a LUT3.
|
|
parameter I0 = 8'haa;
|
|
parameter I1 = 8'hcc;
|
|
parameter I2 = 8'hf0;
|
|
</Template>
|
|
<Template label="LUT4" treetype="template">
|
|
// The forllowing parameters are defined to allow for
|
|
// equation-based INIT specification for a LUT4.
|
|
parameter I0 = 16'haaaa;
|
|
parameter I1 = 16'hcccc;
|
|
parameter I2 = 16'hf0f0;
|
|
parameter I3 = 16'hff00;
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="INIT Truth Tables" treetype="folder">
|
|
<Template label="LUT1" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT1
|
|
// ________
|
|
// | I0 | O |
|
|
// |--------|
|
|
// | 0 | ? |\
|
|
// | 1 | ? |/ = 2'b??
|
|
// ----------
|
|
</Template>
|
|
<Template label="LUT2" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT2
|
|
// ______________
|
|
// | I2 I1 I0 | O |
|
|
// |--------------|
|
|
// | 0 0 0 | ? |\
|
|
// | 0 0 1 | ? | \ = INIT = 4'b???? = 4'h?
|
|
// | 0 1 0 | ? | /
|
|
// | 0 1 1 | ? |/
|
|
// ---------- ---
|
|
</Template>
|
|
<Template label="LUT3" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT3
|
|
// ______________
|
|
// | I2 I1 I0 | O |
|
|
// |--------------|
|
|
// | 0 0 0 | ? |\
|
|
// | 0 0 1 | ? | \ = 4'b???? = 4'h? --------------+
|
|
// | 0 1 0 | ? | / |
|
|
// | 0 1 1 | ? |/ |
|
|
// |----------|---| INIT = 8'h??
|
|
// | 1 0 0 | ? |\ |
|
|
// | 1 0 1 | ? | \ = 4'b???? = 4'h? -------------+
|
|
// | 1 1 0 | ? | /
|
|
// | 1 1 1 | ? |/
|
|
// ----------------
|
|
</Template>
|
|
<Template label="LUT4" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT4
|
|
// _________________
|
|
// | I3 I2 I1 I0 | O |
|
|
// |-----------------|
|
|
// | 0 0 0 0 | ? |\
|
|
// | 0 0 0 1 | ? | \ = 4'b???? = 4'h? ---------------+
|
|
// | 0 0 1 0 | ? | / |
|
|
// | 0 0 1 1 | ? |/ |
|
|
// |-------------|---| |
|
|
// | 0 1 0 0 | ? |\ |
|
|
// | 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 1 0 | ? | / |
|
|
// | 0 1 1 1 | ? |/ |
|
|
// |-------------|---| INIT = 16'h????
|
|
// | 1 0 0 0 | ? |\ |
|
|
// | 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 1 0 | ? | / |
|
|
// | 1 0 1 1 | ? |/ |
|
|
// |-------------|---| |
|
|
// | 1 1 0 0 | ? |\ |
|
|
// | 1 1 0 1 | ? | \ = 4'b???? = 4'h? ------------+
|
|
// | 1 1 1 0 | ? | /
|
|
// | 1 1 1 1 | ? |/
|
|
// -------------------
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<Template label="LUT4" treetype="template">
|
|
// LUT4 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT4_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT4: 4-input Look-Up Table with general output
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT4 #(
|
|
.INIT(16'h0000) // Specify LUT Contents
|
|
) LUT4_inst (
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3) // LUT input
|
|
);
|
|
|
|
// End of LUT4_inst instantiation
|
|
</Template>
|
|
<Template label="LUT4_L" treetype="template">
|
|
// LUT4_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT4_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT4_L: 4-input Look-Up Table with local output
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT4_L #(
|
|
.INIT(16'h0000) // Specify LUT Contents
|
|
) LUT4_L_inst (
|
|
.LO(LO), // LUT local output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3) // LUT input
|
|
);
|
|
|
|
// End of LUT4_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT4_D" treetype="template">
|
|
// LUT4_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT4_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT4_D: 4-input Look-Up Table with general and local outputs
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT4_D #(
|
|
.INIT(16'h0000) // Specify LUT Contents
|
|
) LUT4_D_inst (
|
|
.LO(LO), // LUT local output
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3) // LUT input
|
|
);
|
|
|
|
// End of LUT4_D_inst instantiation
|
|
</Template>
|
|
<Template label="LUT3" treetype="template">
|
|
// LUT3 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT3_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT3: 3-input Look-Up Table with general output
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT3 #(
|
|
.INIT(8'h00) // Specify LUT Contents
|
|
) LUT3_inst (
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2) // LUT input
|
|
);
|
|
|
|
// End of LUT3_inst instantiation
|
|
</Template>
|
|
<Template label="LUT3_L" treetype="template">
|
|
// LUT3_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT3_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT3_L: 3-input Look-Up Table with local output
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT3_L #(
|
|
.INIT(8'h00) // Specify LUT Contents
|
|
) LUT3_L_inst (
|
|
.LO(LO), // LUT local output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2) // LUT input
|
|
);
|
|
|
|
// End of LUT3_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT3_D" treetype="template">
|
|
// LUT3_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT3_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT3_D: 3-input Look-Up Table with general and local outputs
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT3_D #(
|
|
.INIT(8'h00) // Specify LUT Contents
|
|
) LUT3_D_inst (
|
|
.LO(LO), // LUT local output
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2) // LUT input
|
|
);
|
|
|
|
// End of LUT3_D_inst instantiation
|
|
</Template>
|
|
<Template label="LUT2" treetype="template">
|
|
// LUT2 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT2: 2-input Look-Up Table with general output
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT2 #(
|
|
.INIT(4'h0) // Specify LUT Contents
|
|
) LUT2_inst (
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1) // LUT input
|
|
);
|
|
|
|
// End of LUT2_inst instantiation
|
|
</Template>
|
|
<Template label="LUT2_L" treetype="template">
|
|
// LUT2_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT2_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT2_L: 2-input Look-Up Table with local output
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT2_L #(
|
|
.INIT(4'h0) // Specify LUT Contents
|
|
) LUT2_L_inst (
|
|
.LO(LO), // LUT local output
|
|
.I0(I0), // LUT input
|
|
.I1(I1) // LUT input
|
|
);
|
|
|
|
// End of LUT2_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT2_D" treetype="template">
|
|
// LUT2_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT2_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT2_D: 2-input Look-Up Table with general and local outputs
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT2_D #(
|
|
.INIT(4'h0) // Specify LUT Contents
|
|
) LUT2_D_inst (
|
|
.LO(LO), // LUT local output
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1) // LUT input
|
|
);
|
|
|
|
// End of LUT2_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT1" treetype="template">
|
|
// LUT1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT1: 1-input Look-Up Table with general output
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT1 #(
|
|
.INIT(2'b00) // Specify LUT Contents
|
|
) LUT1_inst (
|
|
.O(O), // LUT general output
|
|
.I0(I0) // LUT input
|
|
);
|
|
|
|
// End of LUT1_inst instantiation
|
|
</Template>
|
|
<Template label="LUT1_L" treetype="template">
|
|
// LUT1_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT1_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT1_L: 1-input Look-Up Table with local output
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT1_L #(
|
|
.INIT(2'b00) // Specify LUT Contents
|
|
) LUT1_L_inst (
|
|
.LO(LO), // LUT local output
|
|
.I0(I0) // LUT input
|
|
);
|
|
|
|
// End of LUT1_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT1_D" treetype="template">
|
|
// LUT1_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT1_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT1_D: 1-input Look-Up Table with general and local outputs
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT1_D #(
|
|
.INIT(2'b00) // Specify LUT Contents
|
|
) LUT1_D_inst (
|
|
.LO(LO), // LUT local output
|
|
.O(O), // LUT general output
|
|
.I0(I0) // LUT input
|
|
);
|
|
|
|
// End of LUT1_D_inst instantiation
|
|
</Template>
|
|
<Template label="LUT Local Connect Buffer (BUFCF)" treetype="template">
|
|
// BUFCF : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFCF_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFCF: Fast connect buffer used to connect the outputs of the LUTs
|
|
// and some dedicated logic directly to the input of another LUT.
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFCF BUFCF_inst (
|
|
.O(O), // Connect to the output of a LUT
|
|
.I(I) // Connect to the input of a LUT
|
|
);
|
|
|
|
// End of BUFCF_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Shift Register LUT" treetype="folder">
|
|
<SubFolder label="Non-cascadable" treetype="folder">
|
|
<Template label="16-bit posedge SR (SRL16)" treetype="template">
|
|
// SRL16 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SRL16_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SRL16: 16-bit shift register LUT operating on posedge of clock
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SRL16 #(
|
|
.INIT(16'h0000) // Initial Value of Shift Register
|
|
) SRL16_inst (
|
|
.Q(Q), // SRL data output
|
|
.A0(A0), // Select[0] input
|
|
.A1(A1), // Select[1] input
|
|
.A2(A2), // Select[2] input
|
|
.A3(A3), // Select[3] input
|
|
.CLK(CLK), // Clock input
|
|
.D(D) // SRL data input
|
|
);
|
|
|
|
// End of SRL16_inst instantiation
|
|
</Template>
|
|
<Template label="16-bit negedge SR (SRL16_1)" treetype="template">
|
|
// SRL16_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SRL16_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SRL16_1: 16-bit shift register LUT operating on negedge of clock
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SRL16_1 #(
|
|
.INIT(16'h0000) // Initial Value of Shift Register
|
|
) SRL16_1_inst (
|
|
.Q(Q), // SRL data output
|
|
.A0(A0), // Select[0] input
|
|
.A1(A1), // Select[1] input
|
|
.A2(A2), // Select[2] input
|
|
.A3(A3), // Select[3] input
|
|
.CLK(CLK), // Clock input
|
|
.D(D) // SRL data input
|
|
);
|
|
|
|
// End of SRL16_1_inst instantiation
|
|
</Template>
|
|
<Template label="16-bit w/ CE posedge SR (SRL16E)" treetype="template">
|
|
// SRL16E : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SRL16E_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SRL16E: 16-bit shift register LUT with clock enable operating on posedge of clock
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SRL16E #(
|
|
.INIT(16'h0000) // Initial Value of Shift Register
|
|
) SRL16E_inst (
|
|
.Q(Q), // SRL data output
|
|
.A0(A0), // Select[0] input
|
|
.A1(A1), // Select[1] input
|
|
.A2(A2), // Select[2] input
|
|
.A3(A3), // Select[3] input
|
|
.CE(CE), // Clock enable input
|
|
.CLK(CLK), // Clock input
|
|
.D(D) // SRL data input
|
|
);
|
|
|
|
// End of SRL16E_inst instantiation
|
|
</Template>
|
|
<Template label="16-bit w/ CE negedge SR (SRL16E_1)" treetype="template">
|
|
// SRL16E_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SRL16E_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SRL16E_1: 16-bit shift register LUT with clock enable operating on negedge of clock
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SRL16E_1 #(
|
|
.INIT(16'h0000) // Initial Value of Shift Register
|
|
) SRL16E_1_inst (
|
|
.Q(Q), // SRL data output
|
|
.A0(A0), // Select[0] input
|
|
.A1(A1), // Select[1] input
|
|
.A2(A2), // Select[2] input
|
|
.A3(A3), // Select[3] input
|
|
.CE(CE), // Clock enable input
|
|
.CLK(CLK), // Clock input
|
|
.D(D) // SRL data input
|
|
);
|
|
|
|
// End of SRL16E_1_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Cascable" treetype="folder">
|
|
<Template label="16-bit posedge SR (SRLC16)" treetype="template">
|
|
// SRLC16 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SRLC16_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SRLC16: 16-bit cascadable shift register LUT operating on posedge of clock
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SRLC16 #(
|
|
.INIT(16'h0000) // Initial Value of Shift Register
|
|
) SRLC16_inst (
|
|
.Q(Q), // SRL data output
|
|
.Q15(Q15), // Carry output (connect to next SRL)
|
|
.A0(A0), // Select[0] input
|
|
.A1(A1), // Select[1] input
|
|
.A2(A2), // Select[2] input
|
|
.A3(A3), // Select[3] input
|
|
.CLK(CLK), // Clock input
|
|
.D(D) // SRL data input
|
|
);
|
|
|
|
// End of SRLC16_inst instantiation
|
|
</Template>
|
|
<Template label="16-bit negedge SR (SRLC16_1)" treetype="template">
|
|
// SRLC16_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SRLC16_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SRLC16_1: 16-bit cascadable shift register LUT operating on negedge of clock
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SRLC16_1 #(
|
|
.INIT(16'h0000) // Initial Value of Shift Register
|
|
) SRLC16_1_inst (
|
|
.Q(Q), // SRL data output
|
|
.Q15(Q15), // Carry output (connect to next SRL)
|
|
.A0(A0), // Select[0] input
|
|
.A1(A1), // Select[1] input
|
|
.A2(A2), // Select[2] input
|
|
.A3(A3), // Select[3] input
|
|
.CLK(CLK), // Clock input
|
|
.D(D) // SRL data input
|
|
);
|
|
|
|
// End of SRLC16_1_inst instantiation
|
|
</Template>
|
|
<Template label="16-bit w/ CE posedge SR (SRLC16E)" treetype="template">
|
|
// SRLC16E : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SRL16E_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SRLC16E: 16-bit cascadable shift register LUT with clock enable operating on posedge of clock
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SRLC16E #(
|
|
.INIT(16'h0000) // Initial Value of Shift Register
|
|
) SRLC16E_inst (
|
|
.Q(Q), // SRL data output
|
|
.Q15(Q15), // Carry output (connect to next SRL)
|
|
.A0(A0), // Select[0] input
|
|
.A1(A1), // Select[1] input
|
|
.A2(A2), // Select[2] input
|
|
.A3(A3), // Select[3] input
|
|
.CE(CE), // Clock enable input
|
|
.CLK(CLK), // Clock input
|
|
.D(D) // SRL data input
|
|
);
|
|
|
|
// End of SRLC16E_inst instantiation
|
|
</Template>
|
|
<Template label="16-bit w/ CE negedge SR (SRLC16E_1)" treetype="template">
|
|
// SRLC16E_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SRLC16E_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SRLC16E_1: 16-bit shift register LUT with clock enable operating on negedge of clock
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SRLC16E_1 #(
|
|
.INIT(16'h0000) // Initial Value of Shift Register
|
|
) SRLC16E_1_inst (
|
|
.Q(Q), // SRL data output
|
|
.Q15(Q15), // Carry output (connect to next SRL)
|
|
.A0(A0), // Select[0] input
|
|
.A1(A1), // Select[1] input
|
|
.A2(A2), // Select[2] input
|
|
.A3(A3), // Select[3] input
|
|
.CE(CE), // Clock enable input
|
|
.CLK(CLK), // Clock input
|
|
.D(D) // SRL data input
|
|
);
|
|
|
|
// End of SRLC16E_1_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Clock Components" treetype="folder">
|
|
<Template label="Digital Clock Manager (DCM)" treetype="template">
|
|
// DCM : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (DCM_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Unused inputs
|
|
// : and outputs may be removed or commented out.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// DCM: Digital Clock Manager Circuit
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
DCM #(
|
|
.SIM_MODE("SAFE"), // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details
|
|
.CLKDV_DIVIDE(2.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
|
|
// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
|
|
.CLKFX_DIVIDE(1), // Can be any integer from 1 to 32
|
|
.CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32
|
|
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
|
|
.CLKIN_PERIOD(0.0), // Specify period of input clock
|
|
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
|
|
.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X
|
|
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
|
|
// an integer from 0 to 15
|
|
.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
|
|
.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
|
|
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
|
|
.FACTORY_JF(16'hC080), // FACTORY JF values
|
|
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
|
|
.STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
|
|
) DCM_inst (
|
|
.CLK0(CLK0), // 0 degree DCM CLK output
|
|
.CLK180(CLK180), // 180 degree DCM CLK output
|
|
.CLK270(CLK270), // 270 degree DCM CLK output
|
|
.CLK2X(CLK2X), // 2X DCM CLK output
|
|
.CLK2X180(CLK2X180), // 2X, 180 degree DCM CLK out
|
|
.CLK90(CLK90), // 90 degree DCM CLK output
|
|
.CLKDV(CLKDV), // Divided DCM CLK out (CLKDV_DIVIDE)
|
|
.CLKFX(CLKFX), // DCM CLK synthesis out (M/D)
|
|
.CLKFX180(CLKFX180), // 180 degree CLK synthesis out
|
|
.LOCKED(LOCKED), // DCM LOCK status output
|
|
.PSDONE(PSDONE), // Dynamic phase adjust done output
|
|
.STATUS(STATUS), // 8-bit DCM status bits output
|
|
.CLKFB(CLKFB), // DCM clock feedback
|
|
.CLKIN(CLKIN), // Clock input (from IBUFG, BUFG or DCM)
|
|
.PSCLK(PSCLK), // Dynamic phase adjust clock input
|
|
.PSEN(PSEN), // Dynamic phase adjust enable input
|
|
.PSINCDEC(PSINCDEC), // Dynamic phase adjust increment/decrement
|
|
.RST(RST) // DCM asynchronous reset input
|
|
);
|
|
|
|
// End of DCM_inst instantiation
|
|
</Template>
|
|
<SubFolder label="Clock Buffers" treetype="folder">
|
|
<Template label="Global Clock Buffer (BUFG)" treetype="template">
|
|
// BUFG : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFG_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFG: Global Clock Buffer (source by an internal signal)
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFG BUFG_inst (
|
|
.O(O), // Clock buffer output
|
|
.I(I) // Clock buffer input
|
|
);
|
|
|
|
// End of BUFG_inst instantiation
|
|
</Template>
|
|
<Template label="Single-ended input Global Clock Buffer (IBUFG)" treetype="template">
|
|
// IBUFG : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFG_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFG: Global Clock Buffer (sourced by an external pin)
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFG #(
|
|
.IOSTANDARD("DEFAULT")
|
|
) IBUFG_inst (
|
|
.O(O), // Clock buffer output
|
|
.I(I) // Clock buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUFG_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Input Global Clock Buffer (IBUFGDS)" treetype="template">
|
|
// IBUFGDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFGDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFGDS: Differential Global Clock Buffer (sourced by an external pin)
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFGDS #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination
|
|
.IOSTANDARD("DEFAULT") // Specifies the I/O standard for this buffer
|
|
) IBUFGDS_inst (
|
|
.O(O), // Clock buffer output
|
|
.I(I), // Diff_p clock buffer input
|
|
.IB(IB) // Diff_n clock buffer input
|
|
);
|
|
|
|
// End of IBUFGDS_inst instantiation
|
|
</Template>
|
|
<Template label="Global Clock Buffer w/ Enable (BUFGCE)" treetype="template">
|
|
// BUFGCE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFGCE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFGCE: Global Clock Buffer with Clock Enable (active high)
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFGCE BUFGCE_inst (
|
|
.O(O), // Clock buffer output
|
|
.CE(CE), // Clock enable input
|
|
.I(I) // Clock buffer input
|
|
);
|
|
|
|
// End of BUFGCE_inst instantiation
|
|
</Template>
|
|
<Template label="Global Clock Buffer w/ Enable (BUFGCE_1)" treetype="template">
|
|
// BUFGCE_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFGCE_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFGCE_1: Global Clock Buffer with Clock Enable (active low)
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFGCE_1 BUFGCE_1_inst (
|
|
.O(O), // Clock buffer output
|
|
.CE(CE), // Clock enable input
|
|
.I(I) // Clock buffer input
|
|
);
|
|
|
|
// End of BUFGCE_1_inst instantiation
|
|
// End of BUFIO_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Clock MUX" treetype="folder">
|
|
<Template label="Global Clock Buffer MUX (BUFGMUX)" treetype="template">
|
|
// BUFGMUX : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFGMUX_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFGMUX: Global Clock Buffer 2-to-1 MUX
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFGMUX BUFGMUX_inst (
|
|
.O(O), // Clock MUX output
|
|
.I0(I0), // Clock0 input
|
|
.I1(I1), // Clock1 input
|
|
.S(S) // Clock select input
|
|
);
|
|
|
|
// End of BUFGMUX_inst instantiation
|
|
</Template>
|
|
<Template label="Global Clock Buffer MUX (BUFGMUX_1)" treetype="template">
|
|
// BUFGMUX_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFGMUX_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFGMUX_1: Global Clock Buffer 2-to-1 MUX (inverted select)
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFGMUX_1 BUFGMUX_1_inst (
|
|
.O(O), // Clock MUX output
|
|
.I0(I0), // Clock0 input
|
|
.I1(I1), // Clock1 input
|
|
.S(S) // Clock select input
|
|
);
|
|
|
|
// End of BUFGMUX_1_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="RAM/ROM" treetype="folder">
|
|
<SubFolder label="Distributed ROM" treetype="folder">
|
|
<Template label="16 X 1 (ROM16X1)" treetype="template">
|
|
// ROM16X1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ROM16X1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ROM16X1: 16 x 1 Asynchronous Distributed (LUT) ROM
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ROM16X1 #(
|
|
.INIT(16'h0000) // Contents of ROM
|
|
) ROM16X1_inst (
|
|
.O(O), // ROM output
|
|
.A0(A0), // ROM address[0]
|
|
.A1(A1), // ROM address[1]
|
|
.A2(A2), // ROM address[2]
|
|
.A3(A3) // ROM address[3]
|
|
);
|
|
|
|
// End of ROM16X1_inst instantiation
|
|
</Template>
|
|
<Template label="32 X 1 (ROM32X1)" treetype="template">
|
|
// ROM32X1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ROM32X1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ROM32X1: 32 x 1 Asynchronous Distributed (LUT) ROM
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ROM32X1 #(
|
|
.INIT(32'h00000000) // Contents of ROM
|
|
) ROM32X1_inst (
|
|
.O(O), // ROM output
|
|
.A0(A0), // ROM address[0]
|
|
.A1(A1), // ROM address[1]
|
|
.A2(A2), // ROM address[2]
|
|
.A3(A3), // ROM address[3]
|
|
.A4(A4) // ROM address[4]
|
|
);
|
|
|
|
// End of ROM32X1_inst instantiation
|
|
</Template>
|
|
<Template label="64 X 1 (ROM64X1)" treetype="template">
|
|
// ROM64X1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ROM64X1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ROM64X1: 64 x 1 Asynchronous Distributed (LUT) ROM
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ROM64X1 #(
|
|
.INIT(64'h0000000000000000) // Contents of ROM
|
|
) ROM64X1_inst (
|
|
.O(O), // ROM output
|
|
.A0(A0), // ROM address[0]
|
|
.A1(A1), // ROM address[1]
|
|
.A2(A2), // ROM address[2]
|
|
.A3(A3), // ROM address[3]
|
|
.A4(A4), // ROM address[4]
|
|
.A5(A5) // ROM address[5]
|
|
);
|
|
|
|
// End of ROM64X1_inst instantiation
|
|
</Template>
|
|
<Template label="128 X 1 (ROM128X1)" treetype="template">
|
|
// ROM128X1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ROM128X1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ROM128X1: 128 x 1 Asynchronous Distributed (LUT) ROM
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ROM128X1 #(
|
|
.INIT(128'h00000000000000000000000000000000) // Contents of ROM
|
|
) ROM128X1_inst (
|
|
.O(O), // ROM output
|
|
.A0(A0), // ROM address[0]
|
|
.A1(A1), // ROM address[1]
|
|
.A2(A2), // ROM address[2]
|
|
.A3(A3), // ROM address[3]
|
|
.A4(A4), // ROM address[4]
|
|
.A5(A5), // ROM address[5]
|
|
.A6(A6) // ROM address[6]
|
|
);
|
|
|
|
// End of ROM128X1_inst instantiation
|
|
</Template>
|
|
<Template label="256 X 1 (ROM256X1)" treetype="template">
|
|
// ROM256X1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ROM256X1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ROM256X1: 256 x 1 Asynchronous Distributed (LUT) ROM
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ROM256X1 #(
|
|
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000) // Contents of ROM
|
|
) ROM256X1_inst (
|
|
.O(O), // ROM output
|
|
.A0(A0), // ROM address[0]
|
|
.A1(A1), // ROM address[1]
|
|
.A2(A2), // ROM address[2]
|
|
.A3(A3), // ROM address[3]
|
|
.A4(A4), // ROM address[4]
|
|
.A5(A5), // ROM address[5]
|
|
.A6(A6), // ROM address[6]
|
|
.A7(A7) // ROM address[7]
|
|
);
|
|
|
|
// End of ROM256X1_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Distributed RAM" treetype="folder">
|
|
<SubFolder label="Single-Port" treetype="folder">
|
|
<SubFolder label="16 Deep (4-bit address)" treetype="folder">
|
|
<Template label="16 x 1 posedge write (RAM16X1S)" treetype="template">
|
|
// RAM16X1S : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM16X1S_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM16X1S: 16 x 1 posedge write distributed (LUT) RAM
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM16X1S #(
|
|
.INIT(16'h0000) // Initial contents of RAM
|
|
) RAM16X1S_inst (
|
|
.O(O), // RAM output
|
|
.A0(A0), // RAM address[0] input
|
|
.A1(A1), // RAM address[1] input
|
|
.A2(A2), // RAM address[2] input
|
|
.A3(A3), // RAM address[3] input
|
|
.D(D), // RAM data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM16X1S_inst instantiation
|
|
</Template>
|
|
<Template label="16 x 1 negedge write (RAM16X1S_1)" treetype="template">
|
|
// RAM16X1S_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM16X1S_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM16X1S_1: 16 x 1 negedge write distributed (LUT) RAM
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM16X1S_1 #(
|
|
.INIT(16'h0000) // Initial contents of RAM
|
|
) RAM16X1S_1_inst (
|
|
.O(O), // RAM output
|
|
.A0(A0), // RAM address[0] input
|
|
.A1(A1), // RAM address[1] input
|
|
.A2(A2), // RAM address[2] input
|
|
.A3(A3), // RAM address[3] input
|
|
.D(D), // RAM data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM16X1S_1_inst instantiation
|
|
</Template>
|
|
<Template label="16 x 2 posedge write (RAM16X2S)" treetype="template">
|
|
// RAM16X2S : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM16X2S_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM16X2S: 16 x 2 posedge write distributed (LUT) RAM
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM16X2S #(
|
|
.INIT_00(16'h0000), // Initial contents of bit 0 of RAM
|
|
.INIT_01(16'h0000) // Initial contents of bit 1 of RAM
|
|
) RAM16X2S_inst (
|
|
.O0(O0), // RAM data[0] output
|
|
.O1(O1), // RAM data[1] output
|
|
.A0(A0), // RAM address[0] input
|
|
.A1(A1), // RAM address[1] input
|
|
.A2(A2), // RAM address[2] input
|
|
.A3(A3), // RAM address[3] input
|
|
.D0(D0), // RAM data[0] input
|
|
.D1(D1), // RAM data[1] input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM16X2S_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="32 Deep (5-bit address)" treetype="folder">
|
|
<Template label="32 x 1 posedge write (RAM32X1S)" treetype="template">
|
|
// RAM32X1S : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM32X1S_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM32X1S: 32 x 1 posedge write distributed (LUT) RAM
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM32X1S #(
|
|
.INIT(32'h00000000) // Initial contents of RAM
|
|
) RAM32X1S_inst (
|
|
.O(O), // RAM output
|
|
.A0(A0), // RAM address[0] input
|
|
.A1(A1), // RAM address[1] input
|
|
.A2(A2), // RAM address[2] input
|
|
.A3(A3), // RAM address[3] input
|
|
.A4(A4), // RAM address[4] input
|
|
.D(D), // RAM data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM32X1S_inst instantiation
|
|
</Template>
|
|
<Template label="32 x 1 negedge write (RAM32X1S_1)" treetype="template">
|
|
// RAM32X1S_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM32X1S_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM32X1S_1: 32 x 1 negedge write distributed (LUT) RAM
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM32X1S_1 #(
|
|
.INIT(32'h00000000) // Initial contents of RAM
|
|
)RAM32X1S_1_inst (
|
|
.O(O), // RAM output
|
|
.A0(A0), // RAM address[0] input
|
|
.A1(A1), // RAM address[1] input
|
|
.A2(A2), // RAM address[2] input
|
|
.A3(A3), // RAM address[3] input
|
|
.A4(A4), // RAM address[4] input
|
|
.D(D), // RAM data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM32X1S_1_inst instantiation
|
|
</Template>
|
|
<Template label="32 x 2 posedge write (RAM32X2S)" treetype="template">
|
|
// RAM32X2S : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM16X2S_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM32X2S: 32 x 2 posedge write distributed (LUT) RAM
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM32X2S #(
|
|
.INIT_00(32'h00000000), // INIT for bit 0 of RAM
|
|
.INIT_01(32'h00000000) // INIT for bit 1 of RAM
|
|
) RAM32X2S_inst (
|
|
.O0(O0), // RAM data[0] output
|
|
.O1(O1), // RAM data[1] output
|
|
.A0(A0), // RAM address[0] input
|
|
.A1(A1), // RAM address[1] input
|
|
.A2(A2), // RAM address[2] input
|
|
.A3(A3), // RAM address[3] input
|
|
.A4(A4), // RAM address[4] input
|
|
.D0(D0), // RAM data[0] input
|
|
.D1(D1), // RAM data[1] input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM32X2S_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="64 Deep (6-bit address)" treetype="folder">
|
|
<Template label="64 X 1 posedge write (RAM64X1S)" treetype="template">
|
|
// RAM64X1S : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM64X1S_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM64X1S: 64 x 1 positive edge write, asynchronous read single-port distributed RAM
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM64X1S #(
|
|
.INIT(64'h0000000000000000) // Initial contents of RAM
|
|
) RAM64X1S_inst (
|
|
.O(O), // 1-bit data output
|
|
.A0(A0), // Address[0] input bit
|
|
.A1(A1), // Address[1] input bit
|
|
.A2(A2), // Address[2] input bit
|
|
.A3(A3), // Address[3] input bit
|
|
.A4(A4), // Address[4] input bit
|
|
.A5(A5), // Address[5] input bit
|
|
.D(D), // 1-bit data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM64X1S_inst instantiation
|
|
</Template>
|
|
<Template label="64 X 1 negedge write (RAM64X1S_1)" treetype="template">
|
|
// RAM64X1S_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM64X1S_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM64X1S_1: 64 x 1 negative edge write, asynchronous read single-port distributed RAM
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM64X1S_1 #(
|
|
.INIT(64'h0000000000000000) // Initial contents of RAM
|
|
) RAM64X1S_1_inst (
|
|
.O(O), // 1-bit data output
|
|
.A0(A0), // Address[0] input bit
|
|
.A1(A1), // Address[1] input bit
|
|
.A2(A2), // Address[2] input bit
|
|
.A3(A3), // Address[3] input bit
|
|
.A4(A4), // Address[4] input bit
|
|
.A5(A5), // Address[5] input bit
|
|
.D(D), // 1-bit data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM64X1S_1_inst instantiation
|
|
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Dual-Port" treetype="folder">
|
|
<Template label="16 X 1 posedge write (RAM16X1D)" treetype="template">
|
|
// RAM16X1D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM16X1D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM16X1D: 16 x 1 positive edge write, asynchronous read dual-port distributed RAM
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM16X1D #(
|
|
.INIT(16'h0000) // Initial contents of RAM
|
|
) RAM16X1D_inst (
|
|
.DPO(DPO), // Read-only 1-bit data output for DPRA
|
|
.SPO(SPO), // Rw/ 1-bit data output for A0-A3
|
|
.A0(A0), // Rw/ address[0] input bit
|
|
.A1(A1), // Rw/ address[1] input bit
|
|
.A2(A2), // Rw/ address[2] input bit
|
|
.A3(A3), // Rw/ address[3] input bit
|
|
.D(D), // Write 1-bit data input
|
|
.DPRA0(DPRA0), // Read address[0] input bit
|
|
.DPRA1(DPRA1), // Read address[1] input bit
|
|
.DPRA2(DPRA2), // Read address[2] input bit
|
|
.DPRA3(DPRA3), // Read address[3] input bit
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM16X1D_inst instantiation
|
|
</Template>
|
|
<Template label="16 X 1 negedge write (RAM16X1D_1)" treetype="template">
|
|
// RAM16X1D_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM16X1D_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM16X1D_1: 16 x 1 negative edge write, asynchronous read dual-port distributed RAM
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM16X1D_1 #(
|
|
.INIT(16'h0000) // Initial contents of RAM
|
|
) RAM16X1D_1_inst (
|
|
.DPO(DPO), // Read-only 1-bit data output
|
|
.SPO(SPO), // Rw/ 1-bit data output
|
|
.A0(A0), // Rw/ address[0] input bit
|
|
.A1(A1), // Rw/ address[1] input bit
|
|
.A2(A2), // Rw/ address[2] input bit
|
|
.A3(A3), // Rw/ address[3] input bit
|
|
.D(D), // Write 1-bit data input
|
|
.DPRA0(DPRA0), // Read-only address[0] input bit
|
|
.DPRA1(DPRA1), // Read-only address[1] input bit
|
|
.DPRA2(DPRA2), // Read-only address[2] input bit
|
|
.DPRA3(DPRA3), // Read-only address[3] input bit
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM16X1D_1_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Block RAM" treetype="folder">
|
|
<SubFolder label="Single-Port" treetype="folder">
|
|
<Template label="16k x 1 (RAMB16_S1)" treetype="template">
|
|
// RAMB16_S1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S1: 16kx1 Single-Port RAM
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S1 #(
|
|
.INIT(1'b0), // Value of output RAM registers at startup
|
|
.SRVAL(1'b0), // Output value upon SSR assertion
|
|
.WRITE_MODE("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Address 0 to 4095
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 4096 to 8191
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 8192 to 12287
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 12288 to 16383
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S1_inst (
|
|
.DO(DO), // 1-bit Data Output
|
|
.ADDR(ADDR), // 14-bit Address Input
|
|
.CLK(CLK), // Clock
|
|
.DI(DI), // 1-bit Data Input
|
|
.EN(EN), // RAM Enable Input
|
|
.SSR(SSR), // Synchronous Set/Reset Input
|
|
.WE(WE) // Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S1_inst instantiation
|
|
</Template>
|
|
<Template label="1k x 16 + 2 Parity bits (RAMB16_S18)" treetype="template">
|
|
// RAMB16_S18 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S18_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S18: 1k x 16 + 2 Parity bits Single-Port RAM
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S18 #(
|
|
.INIT(18'h00000), // Value of output RAM registers at startup
|
|
.SRVAL(18'h000000), // Output value upon SSR assertion
|
|
.WRITE_MODE("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Address 0 to 255
|
|
.INIT_00(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_01(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_02(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_03(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_04(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_05(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_06(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_07(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_08(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_09(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_0A(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_0B(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_0C(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_0D(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_0E(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_0F(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
// Address 256 to 511
|
|
.INIT_10(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_11(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_12(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_13(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_14(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_15(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_16(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_17(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_18(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_19(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_1A(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_1B(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_1C(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_1D(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_1E(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_1F(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
// Address 512 to 767
|
|
.INIT_20(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_21(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_22(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_23(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_24(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_25(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_26(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_27(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_28(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_29(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_2A(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_2B(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_2C(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_2D(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_2E(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_2F(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
// Address 768 to 1023
|
|
.INIT_30(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_31(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_32(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_33(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_34(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_35(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_36(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_37(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_38(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_39(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_3A(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_3B(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_3C(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_3D(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_3E(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_3F(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
// Address 0 to 255
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 256 to 511
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 512 to 767
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 768 to 1023
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S18_inst (
|
|
.DO(DO), // 16-bit Data Output
|
|
.DOP(DOP), // 2-bit parity Output
|
|
.ADDR(ADDR), // 10-bit Address Input
|
|
.CLK(CLK), // Clock
|
|
.DI(DI), // 16-bit Data Input
|
|
.DIP(DIP), // 2-bit parity Input
|
|
.EN(EN), // RAM Enable Input
|
|
.SSR(SSR), // Synchronous Set/Reset Input
|
|
.WE(WE) // Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S18_inst instantiation
|
|
</Template>
|
|
<Template label="8k x 2 (RAMB16_S2)" treetype="template">
|
|
// RAMB16_S2 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S2: 8k x 2 Single-Port RAM
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S2 #(
|
|
.INIT(2'b00), // Value of output RAM registers at startup
|
|
.SRVAL(2'b00), // Output value upon SSR assertion
|
|
.WRITE_MODE("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Address 0 to 2047
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 2048 to 4095
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 4096 to 6143
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 6143 to 8191
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S2_inst (
|
|
.DO(DO), // 2-bit Data Output
|
|
.ADDR(ADDR), // 13-bit Address Input
|
|
.CLK(CLK), // Clock
|
|
.DI(DI), // 2-bit Data Input
|
|
.EN(EN), // RAM Enable Input
|
|
.SSR(SSR), // Synchronous Set/Reset Input
|
|
.WE(WE) // Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S2_inst instantiation
|
|
</Template>
|
|
<Template label="512 x 32 + 4 Parity bits (RAMB16_S36)" treetype="template">
|
|
// RAMB16_S36 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S36_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S36: 512 x 32 + 4 Parity bits Single-Port RAM
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S36 #(
|
|
.INIT(36'h000000000), // Value of output RAM registers at startup
|
|
.SRVAL(36'h000000000), // Output value upon SSR assertion
|
|
.WRITE_MODE("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Address 0 to 127
|
|
.INIT_00(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_01(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_02(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_03(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_04(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_05(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_06(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_07(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_08(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_09(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_0A(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_0B(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_0C(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_0D(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_0E(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_0F(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
// Address 128 to 255
|
|
.INIT_10(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_11(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_12(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_13(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_14(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_15(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_16(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_17(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_18(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_19(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_1A(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_1B(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_1C(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_1D(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_1E(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_1F(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
// Address 256 to 383
|
|
.INIT_20(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_21(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_22(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_23(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_24(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_25(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_26(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_27(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_28(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_29(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_2A(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_2B(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_2C(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_2D(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_2E(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_2F(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
// Address 384 to 511
|
|
.INIT_30(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_31(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_32(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_33(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_34(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_35(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_36(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_37(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_38(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_39(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_3A(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_3B(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_3C(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_3D(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_3E(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_3F(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
// Address 0 to 127
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 128 to 255
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 256 to 383
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 384 to 511
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S36_inst (
|
|
.DO(DO), // 32-bit Data Output
|
|
.DOP(DOP), // 4-bit parity Output
|
|
.ADDR(ADDR), // 9-bit Address Input
|
|
.CLK(CLK), // Clock
|
|
.DI(DI), // 32-bit Data Input
|
|
.DIP(DIP), // 4-bit parity Input
|
|
.EN(EN), // RAM Enable Input
|
|
.SSR(SSR), // Synchronous Set/Reset Input
|
|
.WE(WE) // Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S36_inst instantiation
|
|
</Template>
|
|
<Template label="4k x 4 (RAMB16_S4)" treetype="template">
|
|
// RAMB16_S4 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S4_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S4: 4k x 4 Single-Port RAM
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S4 #(
|
|
.INIT(4'h0), // Value of output RAM registers at startup
|
|
.SRVAL(4'h0), // Output value upon SSR assertion
|
|
.WRITE_MODE("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Address 0 to 1023
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 1024 to 2047
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 2048 to 3071
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 3072 to 4095
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S4_inst (
|
|
.DO(DO), // 4-bit Data Output
|
|
.ADDR(ADDR), // 12-bit Address Input
|
|
.CLK(CLK), // Clock
|
|
.DI(DI), // 4-bit Data Input
|
|
.EN(EN), // RAM Enable Input
|
|
.SSR(SSR), // Synchronous Set/Reset Input
|
|
.WE(WE) // Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S4_inst instantiation
|
|
</Template>
|
|
<Template label="2k x 8 + 1 Parity bit (RAMB16_S9)" treetype="template">
|
|
// RAMB16_S9 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S9_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S9: 2k x 8 + 1 Parity bit Single-Port RAM
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S9 #(
|
|
.INIT(9'h000), // Value of output RAM registers at startup
|
|
.SRVAL(9'h000), // Output value upon SSR assertion
|
|
.WRITE_MODE("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Address 0 to 511
|
|
.INIT_00(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_01(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_02(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_03(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_04(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_05(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_06(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_07(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_08(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_09(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_0A(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_0B(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_0C(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_0D(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_0E(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_0F(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
// Address 512 to 1023
|
|
.INIT_10(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_11(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_12(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_13(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_14(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_15(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_16(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_17(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_18(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_19(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_1A(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_1B(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_1C(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_1D(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_1E(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_1F(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
// Address 1024 to 1535
|
|
.INIT_20(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_21(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_22(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_23(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_24(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_25(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_26(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_27(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_28(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_29(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_2A(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_2B(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_2C(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_2D(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_2E(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_2F(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
// Address 1536 to 2047
|
|
.INIT_30(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_31(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_32(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_33(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_34(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_35(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_36(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_37(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_38(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_39(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_3A(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_3B(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_3C(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_3D(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_3E(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_3F(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
// Address 0 to 511
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 512 to 1023
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 1024 to 1535
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 1536 to 2047
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S9_inst (
|
|
.DO(DO), // 8-bit Data Output
|
|
.DOP(DOP), // 1-bit parity Output
|
|
.ADDR(ADDR), // 11-bit Address Input
|
|
.CLK(CLK), // Clock
|
|
.DI(DI), // 8-bit Data Input
|
|
.DIP(DIP), // 1-bit parity Input
|
|
.EN(EN), // RAM Enable Input
|
|
.SSR(SSR), // Synchronous Set/Reset Input
|
|
.WE(WE) // Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S9_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Dual-Port (Matched Port Widths)" treetype="folder">
|
|
<Template label="1k x 16 + 2 Parity bits (RAMB16_S18_S18)" treetype="template">
|
|
// RAMB16_S18_S18 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S18_S18_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S18_S18: 1k x 16 + 2 Parity bits Dual-Port RAM
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S18_S18 #(
|
|
.INIT_A(18'h00000), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(18'h00000), // Value of output RAM registers on Port B at startup
|
|
.SRVAL_A(18'h00000), // Port A output value upon SSR assertion
|
|
.SRVAL_B(18'h00000), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Address 0 to 255
|
|
.INIT_00(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_01(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_02(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_03(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_04(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_05(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_06(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_07(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_08(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_09(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_0A(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_0B(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_0C(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_0D(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_0E(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_0F(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
// Address 256 to 511
|
|
.INIT_10(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_11(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_12(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_13(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_14(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_15(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_16(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_17(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_18(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_19(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_1A(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_1B(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_1C(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_1D(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_1E(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_1F(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
// Address 512 to 767
|
|
.INIT_20(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_21(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_22(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_23(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_24(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_25(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_26(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_27(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_28(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_29(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_2A(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_2B(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_2C(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_2D(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_2E(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_2F(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
// Address 768 to 1023
|
|
.INIT_30(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_31(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_32(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_33(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_34(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_35(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_36(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_37(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_38(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_39(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_3A(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_3B(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_3C(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_3D(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_3E(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
.INIT_3F(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
// Address 0 to 255
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 256 to 511
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 512 to 767
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 768 to 1023
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S18_S18_inst (
|
|
.DOA(DOA), // Port A 16-bit Data Output
|
|
.DOB(DOB), // Port B 16-bit Data Output
|
|
.DOPA(DOPA), // Port A 2-bit Parity Output
|
|
.DOPB(DOPB), // Port B 2-bit Parity Output
|
|
.ADDRA(ADDRA), // Port A 10-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 10-bit Address Input
|
|
.CLKA(CLKA), // Port A Clock
|
|
.CLKB(CLKB), // Port B Clock
|
|
.DIA(DIA), // Port A 16-bit Data Input
|
|
.DIB(DIB), // Port B 16-bit Data Input
|
|
.DIPA(DIPA), // Port A 2-bit parity Input
|
|
.DIPB(DIPB), // Port-B 2-bit parity Input
|
|
.ENA(ENA), // Port A RAM Enable Input
|
|
.ENB(ENB), // Port B RAM Enable Input
|
|
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A Write Enable Input
|
|
.WEB(WEB) // Port B Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S18_S18_inst instantiation
|
|
</Template>
|
|
<Template label="16k x 1 (RAMB16_S1_S1)" treetype="template">
|
|
// RAMB16_S1_S1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S1_S1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S1_S1: 16k x 1 Dual-Port RAM
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S1_S1 #(
|
|
.INIT_A(1'b0), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(1'b0), // Value of output RAM registers on Port B at startup
|
|
.SRVAL_A(1'b0), // Port A output value upon SSR assertion
|
|
.SRVAL_B(1'b0), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Address 0 to 4095
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 4096 to 8191
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 8192 to 12287
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 12288 to 16383
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S1_S1_inst (
|
|
.DOA(DOA), // Port A 1-bit Data Output
|
|
.DOB(DOB), // Port B 1-bit Data Output
|
|
.ADDRA(ADDRA), // Port A 14-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 14-bit Address Input
|
|
.CLKA(CLKA), // Port A Clock
|
|
.CLKB(CLKB), // Port B Clock
|
|
.DIA(DIA), // Port A 1-bit Data Input
|
|
.DIB(DIB), // Port B 1-bit Data Input
|
|
.ENA(ENA), // Port A RAM Enable Input
|
|
.ENB(ENB), // Port B RAM Enable Input
|
|
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A Write Enable Input
|
|
.WEB(WEB) // Port B Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S1_S1_inst instantiation
|
|
</Template>
|
|
<Template label="8k x 2 (RAMB16_S2_S2)" treetype="template">
|
|
// RAMB16_S2_S2 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S2_S2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S2_S2: 8k x 2 Dual-Port RAM
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S2_S2 #(
|
|
.INIT_A(2'b00), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(2'b00), // Value of output RAM registers on Port B at startup
|
|
.SRVAL_A(2'b00), // Port A output value upon SSR assertion
|
|
.SRVAL_B(2'b00), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
|
|
// Address 0 to 2047
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 2048 to 4095
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 4096 to 6143
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 6143 to 8191
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S2_S2_inst (
|
|
.DOA(DOA), // Port A 2-bit Data Output
|
|
.DOB(DOB), // Port B 2-bit Data Output
|
|
.ADDRA(ADDRA), // Port A 13-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 13-bit Address Input
|
|
.CLKA(CLKA), // Port A Clock
|
|
.CLKB(CLKB), // Port B Clock
|
|
.DIA(DIA), // Port A 2-bit Data Input
|
|
.DIB(DIB), // Port B 2-bit Data Input
|
|
.ENA(ENA), // Port A RAM Enable Input
|
|
.ENB(ENB), // Port B RAM Enable Input
|
|
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A Write Enable Input
|
|
.WEB(WEB) // Port B Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S2_S2_inst instantiation
|
|
</Template>
|
|
<Template label="512 x 32 + 4 Parity bits (RAMB16_S36_S36)" treetype="template">
|
|
// RAMB16_S36_S36 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S36_S36_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S36_S36: 512 x 32 + 4 Parity bits Dual-Port RAM
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S36_S36 #(
|
|
.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup
|
|
.SRVAL_A(36'h000000000), // Port A output value upon SSR assertion
|
|
.SRVAL_B(36'h000000000), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Address 0 to 127
|
|
.INIT_00(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_01(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_02(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_03(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_04(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_05(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_06(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_07(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_08(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_09(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_0A(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_0B(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_0C(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_0D(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_0E(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_0F(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
// Address 128 to 255
|
|
.INIT_10(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_11(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_12(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_13(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_14(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_15(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_16(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_17(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_18(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_19(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_1A(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_1B(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_1C(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_1D(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_1E(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_1F(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
// Address 256 to 383
|
|
.INIT_20(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_21(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_22(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_23(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_24(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_25(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_26(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_27(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_28(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_29(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_2A(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_2B(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_2C(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_2D(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_2E(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_2F(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
// Address 384 to 511
|
|
.INIT_30(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_31(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_32(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_33(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_34(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_35(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_36(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_37(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_38(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_39(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_3A(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_3B(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_3C(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_3D(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_3E(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_3F(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
// Address 0 to 127
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 128 to 255
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 256 to 383
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 384 to 511
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S36_S36_inst (
|
|
.DOA(DOA), // Port A 32-bit Data Output
|
|
.DOB(DOB), // Port B 32-bit Data Output
|
|
.DOPA(DOPA), // Port A 4-bit Parity Output
|
|
.DOPB(DOPB), // Port B 4-bit Parity Output
|
|
.ADDRA(ADDRA), // Port A 9-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 9-bit Address Input
|
|
.CLKA(CLKA), // Port A Clock
|
|
.CLKB(CLKB), // Port B Clock
|
|
.DIA(DIA), // Port A 32-bit Data Input
|
|
.DIB(DIB), // Port B 32-bit Data Input
|
|
.DIPA(DIPA), // Port A 4-bit parity Input
|
|
.DIPB(DIPB), // Port-B 4-bit parity Input
|
|
.ENA(ENA), // Port A RAM Enable Input
|
|
.ENB(ENB), // Port B RAM Enable Input
|
|
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A Write Enable Input
|
|
.WEB(WEB) // Port B Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S36_S36_inst instantiation
|
|
</Template>
|
|
<Template label="4k x 4 (RAMB16_S4_S4)" treetype="template">
|
|
// RAMB16_S4_S4 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S4_S4_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S4_S4: 4k x 4 Dual-Port RAM
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S4_S4 #(
|
|
.INIT_A(4'h0), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(4'h0), // Value of output RAM registers on Port B at startup
|
|
.SRVAL_A(4'h0), // Port A output value upon SSR assertion
|
|
.SRVAL_B(4'h0), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Address 0 to 1023
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 1024 to 2047
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 2048 to 3071
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 3072 to 4095
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S4_S4_inst (
|
|
.DOA(DOA), // Port A 4-bit Data Output
|
|
.DOB(DOB), // Port B 4-bit Data Output
|
|
.ADDRA(ADDRA), // Port A 12-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 12-bit Address Input
|
|
.CLKA(CLKA), // Port A Clock
|
|
.CLKB(CLKB), // Port B Clock
|
|
.DIA(DIA), // Port A 4-bit Data Input
|
|
.DIB(DIB), // Port B 4-bit Data Input
|
|
.ENA(ENA), // Port A RAM Enable Input
|
|
.ENB(ENB), // Port B RAM Enable Input
|
|
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A Write Enable Input
|
|
.WEB(WEB) // Port B Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S4_S4_inst instantiation
|
|
</Template>
|
|
<Template label="2k x 8 + 1 Parity bit (RAMB16_S9_S9)" treetype="template">
|
|
// RAMB16_S9_S9 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S9_S9_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S9_S9: 2k x 8 + 1 Parity bit Dual-Port RAM
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S9_S9 #(
|
|
.INIT_A(9'h000), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(9'h000), // Value of output RAM registers on Port B at startup
|
|
.SRVAL_A(9'h000), // Port A output value upon SSR assertion
|
|
.SRVAL_B(9'h000), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Address 0 to 511
|
|
.INIT_00(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_01(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_02(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_03(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_04(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_05(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_06(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_07(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_08(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_09(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_0A(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_0B(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_0C(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_0D(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_0E(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_0F(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
// Address 512 to 1023
|
|
.INIT_10(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_11(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_12(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_13(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_14(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_15(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_16(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_17(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_18(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_19(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_1A(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_1B(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_1C(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_1D(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_1E(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_1F(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
// Address 1024 to 1535
|
|
.INIT_20(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_21(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_22(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_23(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_24(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_25(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_26(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_27(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_28(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_29(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_2A(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_2B(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_2C(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_2D(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_2E(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_2F(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
// Address 1536 to 2047
|
|
.INIT_30(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_31(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_32(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_33(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_34(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_35(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_36(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_37(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_38(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_39(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_3A(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_3B(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_3C(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_3D(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_3E(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INIT_3F(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
// Address 0 to 511
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 512 to 1023
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 1024 to 1535
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Address 1536 to 2047
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S9_S9_inst (
|
|
.DOA(DOA), // Port A 8-bit Data Output
|
|
.DOB(DOB), // Port B 8-bit Data Output
|
|
.DOPA(DOPA), // Port A 1-bit Parity Output
|
|
.DOPB(DOPB), // Port B 1-bit Parity Output
|
|
.ADDRA(ADDRA), // Port A 11-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 11-bit Address Input
|
|
.CLKA(CLKA), // Port A Clock
|
|
.CLKB(CLKB), // Port B Clock
|
|
.DIA(DIA), // Port A 8-bit Data Input
|
|
.DIB(DIB), // Port B 8-bit Data Input
|
|
.DIPA(DIPA), // Port A 1-bit parity Input
|
|
.DIPB(DIPB), // Port-B 1-bit parity Input
|
|
.ENA(ENA), // Port A RAM Enable Input
|
|
.ENB(ENB), // Port B RAM Enable Input
|
|
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A Write Enable Input
|
|
.WEB(WEB) // Port B Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S9_S9_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Dual-Port (Mis-matched Port Widths)" treetype="folder">
|
|
<Template label="1k/512 x 16/32 + 2/4 Parity bits (RAMB16_S18_S36)" treetype="template">
|
|
// RAMB16_S18_S36 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S18_S36_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S18_S36: 1k/512 x 16/32 + 2/4 Parity bits Dual-Port RAM
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S18_S36 #(
|
|
.INIT_A(18'h00000), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup
|
|
.SRVAL_A(18'h00000), // Port A output value upon SSR assertion
|
|
.SRVAL_B(36'h000000000), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Port A Address 0 to 255, Port B Address 0 to 127
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 256 to 511, Port B Address 128 to 255
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 512 to 767, Port B Address 256 to 383
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 768 to 1023, Port B Address 384 to 511
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
// Port A Address 0 to 255, Port B Address 0 to 127
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 256 to 511, Port B Address 128 to 255
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 512 to 767, Port B Address 256 to 383
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 768 to 1023, Port B Address 384 to 511
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S18_S36_inst (
|
|
.DOA(DOA), // Port A 16-bit Data Output
|
|
.DOB(DOB), // Port B 32-bit Data Output
|
|
.DOPA(DOPA), // Port A 2-bit Parity Output
|
|
.DOPB(DOPB), // Port B 4-bit Parity Output
|
|
.ADDRA(ADDRA), // Port A 10-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 9-bit Address Input
|
|
.CLKA(CLKA), // Port A Clock
|
|
.CLKB(CLKB), // Port B Clock
|
|
.DIA(DIA), // Port A 16-bit Data Input
|
|
.DIB(DIB), // Port B 32-bit Data Input
|
|
.DIPA(DIPA), // Port A 2-bit parity Input
|
|
.DIPB(DIPB), // Port-B 4-bit parity Input
|
|
.ENA(ENA), // Port A RAM Enable Input
|
|
.ENB(ENB), // Port B RAM Enable Input
|
|
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A Write Enable Input
|
|
.WEB(WEB) // Port B Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S18_S36_inst instantiation
|
|
</Template>
|
|
<Template label="16k/1k x 1/16 + 0/2 Parity bits (RAMB16_S1_S18)" treetype="template">
|
|
// RAMB16_S1_S18 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S1_S18_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S1_S18: 16k/1k x 1/16 + 0/2 Parity bits Dual-Port RAM
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S1_S18 #(
|
|
.INIT_A(1'b0), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(18'h00000), // Value of output RAM registers on Port B at startup
|
|
.SRVAL_A(1'b0), // Port A output value upon SSR assertion
|
|
.SRVAL_B(18'h00000), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Port A Address 0 to 4095, Port B Address 0 to 255
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 4096 to 8191, Port B Address 256 to 511
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 8192 to 12287, Port B Address 512 to 767
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 12288 to 16383, Port B Address 768 to 1023
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
// Port B Address 0 to 255
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 256 to 511
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 512 to 767
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 768 to 1023
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S1_S18_inst (
|
|
.DOA(DOA), // Port A 1-bit Data Output
|
|
.DOB(DOB), // Port B 16-bit Data Output
|
|
.DOPB(DOPB), // Port B 2-bit Parity Output
|
|
.ADDRA(ADDRA), // Port A 14-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 10-bit Address Input
|
|
.CLKA(CLKA), // Port A Clock
|
|
.CLKB(CLKB), // Port B Clock
|
|
.DIA(DIA), // Port A 1-bit Data Input
|
|
.DIB(DIB), // Port B 16-bit Data Input
|
|
.DIPB(DIPB), // Port-B 2-bit parity Input
|
|
.ENA(ENA), // Port A RAM Enable Input
|
|
.ENB(ENB), // Port B RAM Enable Input
|
|
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A Write Enable Input
|
|
.WEB(WEB) // Port B Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S1_S18_inst instantiation
|
|
</Template>
|
|
<Template label="16k/8k x 1/2 (RAMB16_S1_S2)" treetype="template">
|
|
// RAMB16_S1_S2 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S1_S2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S1_S2: 16k/8k x 1/2 Dual-Port RAM
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S1_S2 #(
|
|
.INIT_A(1'b0), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(2'b00), // Value of output RAM registers on Port B at startup
|
|
.SRVAL_A(1'b0), // Port A output value upon SSR assertion
|
|
.SRVAL_B(2'b00), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Port A Address 0 to 4095, Port B Address 0 to 2047
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 4096 to 8191, Port B Address 2048 to 4095
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 8192 to 12287, Port B Address 4095 to 6143
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 12288 to 16383, Port B Address 6144 to 8091
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S1_S2_inst (
|
|
.DOA(DOA), // Port A 1-bit Data Output
|
|
.DOB(DOB), // Port B 2-bit Data Output
|
|
.ADDRA(ADDRA), // Port A 14-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 13-bit Address Input
|
|
.CLKA(CLKA), // Port A Clock
|
|
.CLKB(CLKB), // Port B Clock
|
|
.DIA(DIA), // Port A 1-bit Data Input
|
|
.DIB(DIB), // Port B 2-bit Data Input
|
|
.ENA(ENA), // Port A RAM Enable Input
|
|
.ENB(ENB), // Port B RAM Enable Input
|
|
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A Write Enable Input
|
|
.WEB(WEB) // Port B Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S1_S2_inst instantiation
|
|
</Template>
|
|
<Template label="16k/512 x 1/32 + 0/4 Parity bits (RAMB16_S1_S36)" treetype="template">
|
|
// RAMB16_S1_S36 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S1_S36_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S1_S36: 16k/512 x 1/32 + 0/4 Parity bits Dual-Port RAM
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S1_S36 #(
|
|
.INIT_A(1'b0), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup
|
|
.SRVAL_A(1'b0), // Port A output value upon SSR assertion
|
|
.SRVAL_B(36'h000000000), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Port A Address 0 to 4095, Port B Address 0 to 127
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 4096 to 8191, Port B Address 128 to 255
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 8192 to 12287, Port B Address 256 to 383
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 12288 to 16383, Port B Address 384 to 512
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
// Port B Address 0 to 127
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 128 to 255
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 256 to 383
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 384 to 512
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S1_S36_inst (
|
|
.DOA(DOA), // Port A 1-bit Data Output
|
|
.DOB(DOB), // Port B 32-bit Data Output
|
|
.DOPB(DOPB), // Port B 4-bit Parity Output
|
|
.ADDRA(ADDRA), // Port A 14-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 9-bit Address Input
|
|
.CLKA(CLKA), // Port A Clock
|
|
.CLKB(CLKB), // Port B Clock
|
|
.DIA(DIA), // Port A 1-bit Data Input
|
|
.DIB(DIB), // Port B 32-bit Data Input
|
|
.DIPB(DIPB), // Port-B 4-bit parity Input
|
|
.ENA(ENA), // Port A RAM Enable Input
|
|
.ENB(ENB), // Port B RAM Enable Input
|
|
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A Write Enable Input
|
|
.WEB(WEB) // Port B Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S1_S36_inst instantiation
|
|
</Template>
|
|
<Template label="16k/4k x 1/4 (RAMB16_S1_S4)" treetype="template">
|
|
// RAMB16_S1_S4 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S1_S4_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S1_S4: 16k/4k x 1/4 Dual-Port RAM
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S1_S4 #(
|
|
.INIT_A(1'b0), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(4'h0), // Value of output RAM registers on Port B at startup
|
|
.SRVAL_A(1'b0), // Port A output value upon SSR assertion
|
|
.SRVAL_B(4'h0), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Port A Address 0 to 4095, Port B Address 0 to 1023
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 4096 to 8191, Port B Address 1024 to 2047
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 8192 to 12287, Port B Address 2048 to 3071
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 12288 to 16383, Port B Address 3072 to 4095
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S1_S4_inst (
|
|
.DOA(DOA), // Port A 1-bit Data Output
|
|
.DOB(DOB), // Port B 4-bit Data Output
|
|
.ADDRA(ADDRA), // Port A 14-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 12-bit Address Input
|
|
.CLKA(CLKA), // Port A Clock
|
|
.CLKB(CLKB), // Port B Clock
|
|
.DIA(DIA), // Port A 1-bit Data Input
|
|
.DIB(DIB), // Port B 4-bit Data Input
|
|
.ENA(ENA), // Port A RAM Enable Input
|
|
.ENB(ENB), // Port B RAM Enable Input
|
|
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A Write Enable Input
|
|
.WEB(WEB) // Port B Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S1_S4_inst instantiation
|
|
</Template>
|
|
<Template label="16k/2k x 1/8 + 0/1 Parity bit (RAMB16_S1_S9)" treetype="template">
|
|
|
|
// RAMB16_S1_S9 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S1_S9_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S1_S9: 16k/2k x 1/8 + 0/1 Parity bit Dual-Port RAM
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S1_S9 #(
|
|
.INIT_A(1'b0), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(9'h000), // Value of output RAM registers on Port B at startup
|
|
.SRVAL_A(1'b0), // Port A output value upon SSR assertion
|
|
.SRVAL_B(9'h000), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Port A Address 0 to 4095, Port B Address 0 to 511
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 4096 to 8191, Port B Address 512 to 1023
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 8192 to 12287, Port B Address 1024 to 1535
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 12288 to 16383, Port B Address 1535 to 2047
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
// Port B Address 0 to 511
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 512 to 1023
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 1024 to 1535
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 1535 to 2047
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S1_S9_inst (
|
|
.DOA(DOA), // Port A 1-bit Data Output
|
|
.DOB(DOB), // Port B 8-bit Data Output
|
|
.DOPB(DOPB), // Port B 1-bit Parity Output
|
|
.ADDRA(ADDRA), // Port A 14-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 11-bit Address Input
|
|
.CLKA(CLKA), // Port A Clock
|
|
.CLKB(CLKB), // Port B Clock
|
|
.DIA(DIA), // Port A 1-bit Data Input
|
|
.DIB(DIB), // Port B 8-bit Data Input
|
|
.DIPB(DIPB), // Port-B 1-bit parity Input
|
|
.ENA(ENA), // Port A RAM Enable Input
|
|
.ENB(ENB), // Port B RAM Enable Input
|
|
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A Write Enable Input
|
|
.WEB(WEB) // Port B Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S1_S9_inst instantiation
|
|
</Template>
|
|
<Template label="8k/512 x 2/32 + 0/4 Parity bits (RAMB16_S2_S36)" treetype="template">
|
|
// RAMB16_S2_S36 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S2_S36_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S2_S36: 8k/512 x 2/32 + 0/4 Parity bits Dual-Port RAM
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S2_S36 #(
|
|
.INIT_A(2'b00), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup
|
|
.SRVAL_A(2'b00), // Port A output value upon SSR assertion
|
|
.SRVAL_B(36'h000000000), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Port A Address 0 to 2047, Port B Address 0 to 127
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 2048 to 4095, Port B Address 128 to 255
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 4096 to 6143, Port B Address 256 to 383
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 6144 to 8191, Port B Address 384 to 511
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
// Port B Address 0 to 127
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 128 to 255
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 256 to 383
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 384 to 511
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S2_S36_inst (
|
|
.DOA(DOA), // Port A 2-bit Data Output
|
|
.DOB(DOB), // Port B 32-bit Data Output
|
|
.DOPB(DOPB), // Port B 4-bit Parity Output
|
|
.ADDRA(ADDRA), // Port A 13-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 9-bit Address Input
|
|
.CLKA(CLKA), // Port A Clock
|
|
.CLKB(CLKB), // Port B Clock
|
|
.DIA(DIA), // Port A 2-bit Data Input
|
|
.DIB(DIB), // Port B 32-bit Data Input
|
|
.DIPB(DIPB), // Port-B 4-bit parity Input
|
|
.ENA(ENA), // Port A RAM Enable Input
|
|
.ENB(ENB), // Port B RAM Enable Input
|
|
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A Write Enable Input
|
|
.WEB(WEB) // Port B Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S2_S36_inst instantiation
|
|
</Template>
|
|
<Template label="8k/4k x 2/4 (RAMB16_S2_S4)" treetype="template">
|
|
// RAMB16_S2_S4 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S2_S4_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S2_S4: 8k/4k x 2/4 Dual-Port RAM
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S2_S4 #(
|
|
.INIT_A(2'b00), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(4'h0), // Value of output RAM registers on Port B at startup
|
|
.SRVAL_A(2'b00), // Port A output value upon SSR assertion
|
|
.SRVAL_B(4'h0), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Port A Address 0 to 2047, Port B Address 0 to 1023
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 2048 to 4095, Port B Address 1024 to 2047
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 4096 to 6143, Port B Address 2048 to 3071
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 6144 to 8191, Port B Address 3072 to 4095
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S2_S4_inst (
|
|
.DOA(DOA), // Port A 2-bit Data Output
|
|
.DOB(DOB), // Port B 4-bit Data Output
|
|
.ADDRA(ADDRA), // Port A 13-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 12-bit Address Input
|
|
.CLKA(CLKA), // Port A Clock
|
|
.CLKB(CLKB), // Port B Clock
|
|
.DIA(DIA), // Port A 2-bit Data Input
|
|
.DIB(DIB), // Port B 4-bit Data Input
|
|
.ENA(ENA), // Port A RAM Enable Input
|
|
.ENB(ENB), // Port B RAM Enable Input
|
|
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A Write Enable Input
|
|
.WEB(WEB) // Port B Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S2_S4_inst instantiation
|
|
</Template>
|
|
<Template label="8k/2k x 2/8 + 0/1 Parity bit (RAMB16_S2_S9)" treetype="template">
|
|
// RAMB16_S2_S9 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S2_S9_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S2_S9: 8k/2k x 2/8 + 0/1 Parity bit Dual-Port RAM
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S2_S9 #(
|
|
.INIT_A(2'b00), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(9'h000), // Value of output RAM registers on Port B at startup
|
|
.SRVAL_A(2'b00), // Port A output value upon SSR assertion
|
|
.SRVAL_B(9'h000), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Port A Address 0 to 2047, Port B Address 0 to 511
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 2048 to 4095, Port B Address 512 to 1023
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 4096 to 6143, Port B Address 1024 to 1535
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 6144 to 8191, Port B Address 1536 to 2047
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
// Port B Address 0 to 511
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 512 to 1023
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 1024 to 1535
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 1536 to 2047
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S2_S9_inst (
|
|
.DOA(DOA), // Port A 2-bit Data Output
|
|
.DOB(DOB), // Port B 8-bit Data Output
|
|
.DOPB(DOPB), // Port B 1-bit Parity Output
|
|
.ADDRA(ADDRA), // Port A 13-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 11-bit Address Input
|
|
.CLKA(CLKA), // Port A Clock
|
|
.CLKB(CLKB), // Port B Clock
|
|
.DIA(DIA), // Port A 2-bit Data Input
|
|
.DIB(DIB), // Port B 8-bit Data Input
|
|
.DIPB(DIPB), // Port-B 1-bit parity Input
|
|
.ENA(ENA), // Port A RAM Enable Input
|
|
.ENB(ENB), // Port B RAM Enable Input
|
|
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A Write Enable Input
|
|
.WEB(WEB) // Port B Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S2_S9_inst instantiation
|
|
</Template>
|
|
<Template label="8k/1k x 2/16 + 0/2 Parity bit (RAMB16_S2_S18)" treetype="template">
|
|
// RAMB16_S2_S18 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S2_S18_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S2_S18: 8k/1k x 2/16 + 0/2 Parity bits Dual-Port RAM
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S2_S18 #(
|
|
.INIT_A(2'b00), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(9'h000), // Value of output RAM registers on Port B at startup
|
|
.SRVAL_A(2'b00), // Port A output value upon SSR assertion
|
|
.SRVAL_B(9'h000), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Port A Address 0 to 2047, Port B Address 0 to 255
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 2048 to 4095, Port B Address 256 to 511
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 4096 to 6143, Port B Address 512 to 767
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 6144 to 8191, Port B Address 768 to 1023
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
// Port B Address 0 to 255
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 256 to 511
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 512 to 767
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 768 to 1023
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S2_S18_inst (
|
|
.DOA(DOA), // Port A 2-bit Data Output
|
|
.DOB(DOB), // Port B 16-bit Data Output
|
|
.DOPB(DOPB), // Port B 2-bit Parity Output
|
|
.ADDRA(ADDRA), // Port A 13-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 10-bit Address Input
|
|
.CLKA(CLKA), // Port A Clock
|
|
.CLKB(CLKB), // Port B Clock
|
|
.DIA(DIA), // Port A 2-bit Data Input
|
|
.DIB(DIB), // Port B 16-bit Data Input
|
|
.DIPB(DIPB), // Port-B 2-bit parity Input
|
|
.ENA(ENA), // Port A RAM Enable Input
|
|
.ENB(ENB), // Port B RAM Enable Input
|
|
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A Write Enable Input
|
|
.WEB(WEB) // Port B Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S2_S18_inst instantiation
|
|
</Template>
|
|
<Template label="4k/1k x 4/16 + 0/2 Parity bits (RAMB16_S4_S18)" treetype="template">
|
|
// RAMB16_S4_S18 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S4_S18_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S4_S18: 4k/1k x 4/16 + 0/2 Parity bits Dual-Port RAM
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S4_S18 #(
|
|
.INIT_A(4'h0), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(18'h00000), // Value of output RAM registers on Port B at startup
|
|
.SRVAL_A(4'h0), // Port A output value upon SSR assertion
|
|
.SRVAL_B(18'h00000), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Port A Address 0 to 1023, Port B Address 0 to 255
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 1024 to 2047, Port B Address 256 to 511
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 2048 to 3071, Port B Address 512 to 767
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 3072 to 4095, Port B Address 768 to 1023
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
// Port A Address 0 to 1023, Port B Address 0 to 255
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 1024 to 2047, Port B Address 256 to 511
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 2048 to 3071, Port B Address 512 to 767
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 3072 to 4095, Port B Address 768 to 1023
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S4_S18_inst (
|
|
.DOA(DOA), // Port A 4-bit Data Output
|
|
.DOB(DOB), // Port B 16-bit Data Output
|
|
.DOPB(DOPB), // Port B 2-bit Parity Output
|
|
.ADDRA(ADDRA), // Port A 12-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 10-bit Address Input
|
|
.CLKA(CLKA), // Port A Clock
|
|
.CLKB(CLKB), // Port B Clock
|
|
.DIA(DIA), // Port A 4-bit Data Input
|
|
.DIB(DIB), // Port B 16-bit Data Input
|
|
.DIPB(DIPB), // Port-B 2-bit parity Input
|
|
.ENA(ENA), // Port A RAM Enable Input
|
|
.ENB(ENB), // Port B RAM Enable Input
|
|
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A Write Enable Input
|
|
.WEB(WEB) // Port B Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S4_S18_inst instantiation
|
|
</Template>
|
|
<Template label="4k/512 x 4/32 + 0/4 Parity bits (RAMB16_S4_S36)" treetype="template">
|
|
// RAMB16_S4_S36 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S4_S36_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S4_S36: 4k/512 x 4/32 + 0/4 Parity bits Dual-Port RAM
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S4_S36 #(
|
|
.INIT_A(4'h0), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup
|
|
.SRVAL_A(4'h0), // Port A output value upon SSR assertion
|
|
.SRVAL_B(36'h000000000), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Port A Address 0 to 1023, Port B Address 0 to 127
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 1024 to 2047, Port B Address 128 to 255
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 2048 to 3071, Port B Address 256 to 383
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 3072 to 4095, Port B Address 384 to 511
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
// Port A Address 0 to 1023, Port B Address 0 to 127
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 1024 to 2047, Port B Address 128 to 255
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 2048 to 3071, Port B Address 256 to 383
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 3072 to 4095, Port B Address 384 to 511
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S4_S36_inst (
|
|
.DOA(DOA), // Port A 4-bit Data Output
|
|
.DOB(DOB), // Port B 32-bit Data Output
|
|
.DOPB(DOPB), // Port B 4-bit Parity Output
|
|
.ADDRA(ADDRA), // Port A 12-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 9-bit Address Input
|
|
.CLKA(CLKA), // Port A Clock
|
|
.CLKB(CLKB), // Port B Clock
|
|
.DIA(DIA), // Port A 4-bit Data Input
|
|
.DIB(DIB), // Port B 32-bit Data Input
|
|
.DIPB(DIPB), // Port-B 4-bit parity Input
|
|
.ENA(ENA), // Port A RAM Enable Input
|
|
.ENB(ENB), // Port B RAM Enable Input
|
|
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A Write Enable Input
|
|
.WEB(WEB) // Port B Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S4_S36_inst instantiation
|
|
</Template>
|
|
<Template label="4k/2k x 4/8 + 0/1 Parity bit (RAMB16_S4_S9)" treetype="template">
|
|
// RAMB16_S4_S9 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S4_S9_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S4_S9: 4k/2k x 4/8 + 0/1 Parity bit Dual-Port RAM
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S4_S9 #(
|
|
.INIT_A(4'h0), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(9'h000), // Value of output RAM registers on Port B at startup
|
|
.SRVAL_A(4'h0), // Port A output value upon SSR assertion
|
|
.SRVAL_B(9'h000), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Port A Address 0 to 1023, Port B Address 0 to 511
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 1024 to 2047, Port B Address 512 to 1023
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 2048 to 3071, Port B Address 1024 to 1535
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 3072 to 4095, Port B Address 1536 to 2047
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
// Port B Address 0 to 511
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 512 to 1023
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 1024 to 1535
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port B Address 1536 to 2047
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S4_S9_inst (
|
|
.DOA(DOA), // Port A 4-bit Data Output
|
|
.DOB(DOB), // Port B 8-bit Data Output
|
|
.DOPB(DOPB), // Port B 1-bit Parity Output
|
|
.ADDRA(ADDRA), // Port A 12-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 11-bit Address Input
|
|
.CLKA(CLKA), // Port A Clock
|
|
.CLKB(CLKB), // Port B Clock
|
|
.DIA(DIA), // Port A 4-bit Data Input
|
|
.DIB(DIB), // Port B 8-bit Data Input
|
|
.DIPB(DIPB), // Port-B 1-bit parity Input
|
|
.ENA(ENA), // Port A RAM Enable Input
|
|
.ENB(ENB), // Port B RAM Enable Input
|
|
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A Write Enable Input
|
|
.WEB(WEB) // Port B Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S4_S9_inst instantiation
|
|
</Template>
|
|
<Template label="2k/1k x 8/16 + 1/2 Parity bits (RAMB16_S9_S18)" treetype="template">
|
|
// RAMB16_S9_S18 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S9_S18_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S9_S18: 2k/1k x 8/16 + 1/2 Parity bits Parity bits Dual-Port RAM
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S9_S18 #(
|
|
.INIT_A(9'h000), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(18'h00000), // Value of output RAM registers on Port B at startup
|
|
.SRVAL_A(9'h000), // Port A output value upon SSR assertion
|
|
.SRVAL_B(18'h00000), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Port A Address 0 to 511, Port B Address 0 to 255
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 512 to 1023, Port B Address 256 to 511
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 1024 to 1535, Port B Address 512 to 767
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 1536 to 2047, Port B Address 768 to 1024
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
// Port A Address 0 to 511, Port B Address 0 to 255
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 512 to 1023, Port B Address 256 to 511
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 1024 to 1535, Port B Address 512 to 767
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 1536 to 2047, Port B Address 768 to 1024
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S9_S18_inst (
|
|
.DOA(DOA), // Port A 8-bit Data Output
|
|
.DOB(DOB), // Port B 16-bit Data Output
|
|
.DOPA(DOPA), // Port A 1-bit Parity Output
|
|
.DOPB(DOPB), // Port B 2-bit Parity Output
|
|
.ADDRA(ADDRA), // Port A 11-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 10-bit Address Input
|
|
.CLKA(CLKA), // Port A Clock
|
|
.CLKB(CLKB), // Port B Clock
|
|
.DIA(DIA), // Port A 8-bit Data Input
|
|
.DIB(DIB), // Port B 16-bit Data Input
|
|
.DIPA(DIPA), // Port A 1-bit parity Input
|
|
.DIPB(DIPB), // Port-B 2-bit parity Input
|
|
.ENA(ENA), // Port A RAM Enable Input
|
|
.ENB(ENB), // Port B RAM Enable Input
|
|
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A Write Enable Input
|
|
.WEB(WEB) // Port B Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S9_S18_inst instantiation
|
|
</Template>
|
|
<Template label="2k/512 x 8/32 + 1/4 Parity (RAMB16_S9_S36)" treetype="template">
|
|
// RAMB16_S9_S36 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_S9_S36_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16_S9_S36: 2k/512 x 8/32 + 1/4 Parity bits Parity bits Dual-Port RAM
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16_S9_S36 #(
|
|
.INIT_A(9'h000), // Value of output RAM registers on Port A at startup
|
|
.INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup
|
|
.SRVAL_A(9'h000), // Port A output value upon SSR assertion
|
|
.SRVAL_B(36'h000000000), // Port B output value upon SSR assertion
|
|
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
|
|
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
// Port A Address 0 to 511, Port B Address 0 to 127
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 512 to 1023, Port B Address 128 to 255
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 1024 to 1535, Port B Address 255 to 383
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 1536 to 2047, Port B Address 384 to 511
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
// Port A Address 0 to 511, Port B Address 0 to 127
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 512 to 1023, Port B Address 128 to 255
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 1024 to 1535, Port B Address 256 to 383
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// Port A Address 1536 to 2047, Port B Address 384 to 511
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_S9_S36_inst (
|
|
.DOA(DOA), // Port A 8-bit Data Output
|
|
.DOB(DOB), // Port B 32-bit Data Output
|
|
.DOPA(DOPA), // Port A 1-bit Parity Output
|
|
.DOPB(DOPB), // Port B 4-bit Parity Output
|
|
.ADDRA(ADDRA), // Port A 11-bit Address Input
|
|
.ADDRB(ADDRB), // Port B 9-bit Address Input
|
|
.CLKA(CLKA), // Port A Clock
|
|
.CLKB(CLKB), // Port B Clock
|
|
.DIA(DIA), // Port A 8-bit Data Input
|
|
.DIB(DIB), // Port B 32-bit Data Input
|
|
.DIPA(DIPA), // Port A 1-bit parity Input
|
|
.DIPB(DIPB), // Port-B 4-bit parity Input
|
|
.ENA(ENA), // Port A RAM Enable Input
|
|
.ENB(ENB), // Port B RAM Enable Input
|
|
.SSRA(SSRA), // Port A Synchronous Set/Reset Input
|
|
.SSRB(SSRB), // Port B Synchronous Set/Reset Input
|
|
.WEA(WEA), // Port A Write Enable Input
|
|
.WEB(WEB) // Port B Write Enable Input
|
|
);
|
|
|
|
// End of RAMB16_S9_S36_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Arithmetic Functions" treetype="folder">
|
|
<Template label="18X18 Asynchronous Multiplier (MULT18X18)" treetype="template">
|
|
// MULT18X18 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MULT18X18_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MULT18X18: 18 x 18 signed asynchronous multiplier
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MULT18X18 MULT18X18_inst (
|
|
.P(P), // 36-bit multiplier output
|
|
.A(A), // 18-bit multiplier input
|
|
.B(B) // 18-bit multiplier input
|
|
);
|
|
|
|
// End of MULT18X18_inst instantiation
|
|
</Template>
|
|
<Template label="18X18 Synchronous Multiplier (MULT18X18S)" treetype="template">
|
|
// MULT18X18S : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MULT18X18S_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MULT18X18S: 18 x 18 signed synchronous multiplier
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MULT18X18S MULT18X18S_inst (
|
|
.P(P), // 36-bit multiplier output
|
|
.A(A), // 18-bit multiplier input
|
|
.B(B), // 18-bit multiplier input
|
|
.C(C), // Clock input
|
|
.CE(CE), // Clock enable input
|
|
.R(R) // Synchronous reset input
|
|
);
|
|
|
|
// End of MULT18X18S_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Config/BSCAN Components" treetype="folder">
|
|
<Template label="Startup Block (STARTUP_SPARTAN3)" treetype="template">
|
|
// STARTUP_SPARTAN3 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (STARTUP_SPARTAN3_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// STARTUP_SPARTAN3: Startup primitive for GSR, GTS or startup sequence control
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
STARTUP_SPARTAN3 STARTUP_SPARTAN3_inst (
|
|
.CLK(CLK), // Clock input for start-up sequence
|
|
.GSR(GSR_PORT), // Global Set/Reset input (GSR cannot be used as a port name)
|
|
.GTS(GTS_PORT) // Global 3-state input (GTS cannot be used as a port name)
|
|
);
|
|
|
|
// End of STARTUP_SPARTAN3_inst instantiation
|
|
</Template>
|
|
<Template label="Boundary Scan (BSCAN_SPARTAN3)" treetype="template">
|
|
// BSCAN_SPARTAN3 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BSCAN_SPARTAN3_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BSCAN_SPARTAN3: Boundary Scan primitive for connecting internal logic to
|
|
// JTAG interface.
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BSCAN_SPARTAN3 BSCAN_SPARTAN3_inst (
|
|
.CAPTURE(CAPTURE), // CAPTURE output from TAP controller
|
|
.DRCK1(DRCK1), // Data register output for USER1 functions
|
|
.DRCK2(DRCK2), // Data register output for USER2 functions
|
|
.RESET(RESET), // Reset output from TAP controller
|
|
.SEL1(SEL1), // USER1 active output
|
|
.SEL2(SEL2), // USER2 active output
|
|
.SHIFT(SHIFT), // SHIFT output from TAP controller
|
|
.TDI(TDI), // TDI output from TAP controller
|
|
.UPDATE(UPDATE), // UPDATE output from TAP controller
|
|
.TDO1(TDO1), // Data input for USER1 function
|
|
.TDO2(TDO2) // Data input for USER2 function
|
|
);
|
|
|
|
// End of BSCAN_SPARTAN3_inst instantiation
|
|
</Template>
|
|
<Template label="Register Capture (CAPTURE_SPARTAN3)" treetype="template">
|
|
// CAPTURE_SPARTAN3 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (CAPTURE_SPARTAN3_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// CAPTURE_SPARTAN3: Register State Capture for Bitstream Readback
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
CAPTURE_SPARTAN3 CAPTURE_SPARTAN3_inst (
|
|
.CAP(CAP), // Capture input
|
|
.CLK(CLK) // Clock input
|
|
);
|
|
|
|
// End of CAPTURE_SPARTAN3_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="I/O Components" treetype="folder">
|
|
<SubFolder label="Input" treetype="folder">
|
|
<Template label="Single-ended Buffer (IBUF)" treetype="template">
|
|
// IBUF : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUF_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUF: Single-ended Input Buffer
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUF #(
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
)IBUF_inst (
|
|
.O(O), // Buffer output
|
|
.I(I) // Buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUF_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer (IBUFDS)" treetype="template">
|
|
// IBUFDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFDS: Differential Input Buffer
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFDS #(
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
) IBUFDS_inst (
|
|
.O(O), // Buffer output
|
|
.I(I), // Diff_p buffer input (connect directly to top-level port)
|
|
.IB(IB) // Diff_n buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUFDS_inst instantiation
|
|
</Template>
|
|
<Template label="Single-ended Global Clock (IBUFG)" treetype="template">
|
|
// IBUFG : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFG_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFG: Single-ended global clock input buffer
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFG #(
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
) IBUFG_inst (
|
|
.O(O), // Clock buffer output
|
|
.I(I) // Clock buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUFG_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Global Clock (IBUFGDS)" treetype="template">
|
|
// IBUFGDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFGDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFGDS: Differential Global Clock Input Buffer
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFGDS #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
) IBUFGDS_inst (
|
|
.O(O), // Clock buffer output
|
|
.I(I), // Diff_p clock buffer input (connect directly to top-level port)
|
|
.IB(IB) // Diff_n clock buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUFGDS_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Output" treetype="folder">
|
|
<Template label="Single-ended Buffer (OBUF)" treetype="template">
|
|
// OBUF : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OBUF_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OBUF: Single-ended Output Buffer
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OBUF #(
|
|
.DRIVE(12), // Specify the output drive strength
|
|
.IOSTANDARD("DEFAULT"), // Specify the output I/O standard
|
|
.SLEW("SLOW") // Specify the output slew rate
|
|
) OBUF_inst (
|
|
.O(O), // Buffer output (connect directly to top-level port)
|
|
.I(I) // Buffer input
|
|
);
|
|
|
|
// End of OBUF_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer (OBUFDS)" treetype="template">
|
|
|
|
// OBUFDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OBUFDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OBUFDS: Differential Output Buffer
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OBUFDS #(
|
|
.IOSTANDARD("DEFAULT") // Specify the output I/O standard
|
|
) OBUFDS_inst (
|
|
.O(O), // Diff_p output (connect directly to top-level port)
|
|
.OB(OB), // Diff_n output (connect directly to top-level port)
|
|
.I(I) // Buffer input
|
|
);
|
|
|
|
// End of OBUFDS_inst instantiation
|
|
</Template>
|
|
<Template label="Single-ended 3-state Buffer (OBUFT)" treetype="template">
|
|
// OBUFT : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OBUFT_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OBUFT: Single-ended 3-state Output Buffer
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OBUFT #(
|
|
.DRIVE(12), // Specify the output drive strength
|
|
.IOSTANDARD("DEFAULT"), // Specify the output I/O standard
|
|
.SLEW("SLOW") // Specify the output slew rate
|
|
) OBUFT_inst (
|
|
.O(O), // Buffer output (connect directly to top-level port)
|
|
.I(I), // Buffer input
|
|
.T(T) // 3-state enable input
|
|
);
|
|
|
|
// End of OBUFT_inst instantiation
|
|
</Template>
|
|
<Template label="Differential 3-state Buffer (OBUFTDS)" treetype="template">
|
|
// OBUFTDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OBUFTDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OBUFTDS: Differential 3-state Output Buffer
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OBUFTDS #(
|
|
.IOSTANDARD("DEFAULT") // Specify the output I/O standard
|
|
) OBUFTDS_inst (
|
|
.O(O), // Diff_p output (connect directly to top-level port)
|
|
.OB(OB), // Diff_n output (connect directly to top-level port)
|
|
.I(I), // Buffer input
|
|
.T(T) // 3-state enable input
|
|
);
|
|
|
|
// End of OBUFTDS_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Bi-directional" treetype="folder">
|
|
<Template label="Single-ended Buffer (IOBUF)" treetype="template">
|
|
// IOBUF : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IOBUF_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IOBUF: Single-ended Bi-directional Buffer
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IOBUF #(
|
|
.DRIVE(12), // Specify the output drive strength
|
|
.IOSTANDARD("DEFAULT"), // Specify the I/O standard
|
|
.SLEW("SLOW") // Specify the output slew rate
|
|
) IOBUF_inst (
|
|
.O(O), // Buffer output
|
|
.IO(IO), // Buffer inout port (connect directly to top-level port)
|
|
.I(I), // Buffer input
|
|
.T(T) // 3-state enable input, high=input, low=output
|
|
);
|
|
|
|
// End of IOBUF_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer (IOBUFDS)" treetype="template">
|
|
// IOBUFDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IOBUFDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IOBUFDS: Differential Bi-directional Buffer
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IOBUFDS #(
|
|
.IOSTANDARD("DEFAULT") // Specify the I/O standard
|
|
) IOBUFDS_inst (
|
|
.O(O), // Buffer output
|
|
.IO(IO), // Diff_p inout (connect directly to top-level port)
|
|
.IOB(IOB), // Diff_n inout (connect directly to top-level port)
|
|
.I(I), // Buffer input
|
|
.T(T) // 3-state enable input, high=input, low=output
|
|
);
|
|
|
|
// End of IOBUFDS_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Weak drivers" treetype="folder">
|
|
<Template label="PULLUP" treetype="template">
|
|
// PULLUP : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (PULLUP_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design.
|
|
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// PULLUP: I/O Buffer Weak Pull-up
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
PULLUP PULLUP_inst (
|
|
.O(O) // Pullup output (connect directly to top-level port)
|
|
);
|
|
|
|
// End of PULLUP_inst instantiation
|
|
</Template>
|
|
<Template label="PULLDOWN" treetype="template">
|
|
// PULLDOWN : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (PULLDOWN_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// PULLDOWN: I/O Buffer Weak Pull-down
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
PULLDOWN PULLDOWN_inst (
|
|
.O(O) // Pulldown output (connect directly to top-level port)
|
|
);
|
|
|
|
// End of PULLDOWN_inst instantiation
|
|
</Template>
|
|
<Template label="KEEPER" treetype="template">
|
|
// KEEPER : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (KEEPER_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// KEEPER: I/O Buffer Weak Keeper
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
KEEPER KEEPER_inst (
|
|
.O(O) // Keeper output (connect directly to top-level port)
|
|
);
|
|
|
|
// End of KEEPER_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="DDR Registers" treetype="folder">
|
|
<SubFolder label="Input" treetype="folder">
|
|
<Template label="Async set, reset and CE (IFDDRCPE)" treetype="template">
|
|
// IFDDRCPE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IFDDRCPE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IFDDRCPE: Double Data Rate Input Register with Async. Clear, Async. Preset
|
|
// and Clock Enable.
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IFDDRCPE IFDDRCPE_inst (
|
|
.Q0(Q0), // Posedge data output
|
|
.Q1(Q1), // Negedge data output
|
|
.C0(C0), // 0 degree clock input
|
|
.C1(C1), // 180 degree clock input
|
|
.CE(CE), // Clock enable input
|
|
.CLR(CLR), // Asynchronous reset input
|
|
.D(D), // Data input (connect directly to top-level port)
|
|
.PRE(PRE) // Asynchronous preset input
|
|
);
|
|
|
|
// End of IFDDRCPE_inst instantiation
|
|
</Template>
|
|
<Template label="Sync set, reset and CE (IFDDRRSE)" treetype="template">
|
|
// IFDDRRSE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IFDDRRSE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IFDDRRSE: Double Data Rate Input Register with Sync. Clear, Sync. Preset
|
|
// and Clock Enable.
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IFDDRRSE IFDDRRSE_inst (
|
|
.Q0(Q0), // Posedge data output
|
|
.Q1(Q1), // Negedge data output
|
|
.C0(C0), // 0 degree clock input
|
|
.C1(C1), // 180 degree clock input
|
|
.CE(CE), // Clock enable input
|
|
.D(D), // Data input (connect directly to top-level port)
|
|
.R(R), // Synchronous reset input
|
|
.S(S) // Synchronous preset input
|
|
);
|
|
|
|
// End of IFDDRRSE_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Output" treetype="folder">
|
|
<Template label="Async set, reset and CE (OFDDRCPE)" treetype="template">
|
|
// OFDDRCPE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OFDDRCPE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OFDDRCPE: Double Data Rate Output Register with Async. Clear, Async. Preset
|
|
// and Clock Enable.
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OFDDRCPE OFDDRCPE_inst (
|
|
.Q(Q), // Data output (connect directly to top-level port)
|
|
.C0(C0), // 0 degree clock input
|
|
.C1(C1), // 180 degree clock input
|
|
.CE(CE), // Clock enable input
|
|
.CLR(CLR), // Asynchronous reset input
|
|
.D0(D0), // Posedge data input
|
|
.D1(D1), // Negedge data input
|
|
.PRE(PRE) // Asynchronous preset input
|
|
);
|
|
|
|
// End of OFDDRCPE_inst instantiation
|
|
</Template>
|
|
<Template label="Sync set, reset and CE (OFDDRRSE)" treetype="template">
|
|
// OFDDRRSE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OFDDRRSE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OFDDRRSE: Double Data Rate Input Register with Sync. Clear, Sync. Preset
|
|
// and Clock Enable.
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OFDDRRSE OFDDRRSE_inst (
|
|
.Q(Q), // Data output (connect directly to top-level port)
|
|
.C0(C0), // 0 degree clock input
|
|
.C1(C1), // 180 degree clock input
|
|
.CE(CE), // Clock enable input
|
|
.D0(D0), // Posedge data input
|
|
.D1(D1), // Negedge data input
|
|
.R(R), // Synchronous reset input
|
|
.S(S) // Synchronous preset input
|
|
);
|
|
|
|
// End of OFDDRRSE_inst instantiation
|
|
</Template>
|
|
<Template label="Async set, reset and CE w/ 3-state (OFDDRTCPE)" treetype="template">
|
|
// OFDDRTCPE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OFDDRTCPE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OFDDRTCPE: Double Data Rate Output Register with Async. Clear, Async. Preset
|
|
// and Clock Enable with 3-state.
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OFDDRTCPE OFDDRTCPE_inst (
|
|
.O(O), // Data output (connect directly to top-level port)
|
|
.C0(C0), // 0 degree clock input
|
|
.C1(C1), // 180 degree clock input
|
|
.CE(CE), // Clock enable input
|
|
.CLR(CLR), // Asynchronous reset input
|
|
.D0(D0), // Posedge data input
|
|
.D1(D1), // Negedge data input
|
|
.PRE(PRE), // Asynchronous preset input
|
|
.T(T) // 3-state enable input
|
|
);
|
|
|
|
// End of OFDDRTCPE_inst instantiation
|
|
</Template>
|
|
<Template label="Sync set, reset and CE w/ 3-state (OFDDRTRSE)" treetype="template">
|
|
// OFDDRTRSE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OFDDRTRSE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OFDDRTRSE: Double Data Rate Input Register with Sync. Clear, Sync. Preset
|
|
// and Clock Enable with 3-state.
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OFDDRTRSE OFDDRTRSE_inst (
|
|
.Q(Q), // Data output (connect directly to top-level port)
|
|
.C0(C0), // 0 degree clock input
|
|
.C1(C1), // 180 degree clock input
|
|
.CE(CE), // Clock enable input
|
|
.D0(D0), // Posedge data input
|
|
.D1(D1), // Negedge data input
|
|
.R(R), // Synchronous reset input
|
|
.S(S), // Synchronous preset input
|
|
.T(T) // 3-state enable input
|
|
);
|
|
|
|
// End of OFDDRTRSE_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Registers & Latches" treetype="folder">
|
|
<SubFolder label="Single Data Rate" treetype="folder">
|
|
<Template label="Posedge D-FF w/ Async Clear, and CE (FDCE)" treetype="template">
|
|
// FDCE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FDCE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FDCE: Single Data Rate D Flip-Flop with Asynchronous Clear and
|
|
// Clock Enable (posedge clk).
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FDCE #(
|
|
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
|
|
) FDCE_inst (
|
|
.Q(Q), // Data output
|
|
.C(C), // Clock input
|
|
.CE(CE), // Clock enable input
|
|
.CLR(CLR), // Asynchronous clear input
|
|
.D(D) // Data input
|
|
);
|
|
|
|
// End of FDCE_inst instantiation
|
|
|
|
</Template>
|
|
<Template label="Posedge D-FF w/ Async Clear, Set and CE (FDCPE)" treetype="template">
|
|
// FDCPE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FDCPE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FDCPE: Single Data Rate D Flip-Flop with Asynchronous Clear, Set and
|
|
// Clock Enable (posedge clk).
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FDCPE #(
|
|
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
|
|
) FDCPE_inst (
|
|
.Q(Q), // Data output
|
|
.C(C), // Clock input
|
|
.CE(CE), // Clock enable input
|
|
.CLR(CLR), // Asynchronous clear input
|
|
.D(D), // Data input
|
|
.PRE(PRE) // Asynchronous set input
|
|
);
|
|
|
|
// End of FDCPE_inst instantiation
|
|
</Template>
|
|
<Template label="Posedge D-FF w/ Sync Clear, Set and CE (FDRSE)" treetype="template">
|
|
// FDRSE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FDCRS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FDRSE: Single Data Rate D Flip-Flop with Synchronous Clear, Set and
|
|
// Clock Enable (posedge clk).
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FDRSE #(
|
|
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
|
|
) FDRSE_inst (
|
|
.Q(Q), // Data output
|
|
.C(C), // Clock input
|
|
.CE(CE), // Clock enable input
|
|
.D(D), // Data input
|
|
.R(R), // Synchronous reset input
|
|
.S(S) // Synchronous set input
|
|
);
|
|
|
|
// End of FDRSE_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Transparent Latch" treetype="folder">
|
|
<Template label="Latch with Async Reset, Set and Gate Enable (LDCPE)" treetype="template">
|
|
// LDCPE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LDCPE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LDCPE: Transparent latch with Asynchronous Reset, Preset and
|
|
// Gate Enable.
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LDCPE #(
|
|
.INIT(1'b0) // Initial value of latch (1'b0 or 1'b1)
|
|
) LDCPE_inst (
|
|
.Q(Q), // Data output
|
|
.CLR(CLR), // Asynchronous clear/reset input
|
|
.D(D), // Data input
|
|
.G(G), // Gate input
|
|
.GE(GE), // Gate enable input
|
|
.PRE(PRE) // Asynchronous preset/set input
|
|
);
|
|
|
|
// End of LDCPE_inst instantiation
|
|
</Template>
|
|
<Template label="Latch with Async Reset and Gate Enable (LDCE)" treetype="template">
|
|
// LDCE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LDCE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LDCE: Transparent latch with Asynchronous Reset and Gate Enable.
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LDCE #(
|
|
.INIT(1'b0) // Initial value of latch (1'b0 or 1'b1)
|
|
) LDCE_inst (
|
|
.Q(Q), // Data output
|
|
.CLR(CLR), // Asynchronous clear/reset input
|
|
.D(D), // Data input
|
|
.G(G), // Gate input
|
|
.GE(GE) // Gate enable input
|
|
);
|
|
|
|
// End of LDCE_inst instantiation
|
|
</Template>
|
|
<Template label="Latch with Async Set and Gate Enable (LDPE)" treetype="template">
|
|
// LDPE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LDPE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LDPE: Transparent latch with Asynchronous Preset and Gate Enable.
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LDPE #(
|
|
.INIT(1'b0) // Initial value of latch (1'b0 or 1'b1)
|
|
) LDPE_inst (
|
|
.Q(Q), // Data output
|
|
.PRE(PRE), // Asynchronous preset/set input
|
|
.D(D), // Data input
|
|
.G(G), // Gate input
|
|
.GE(GE) // Gate enable input
|
|
);
|
|
|
|
// End of LDPE_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Spartan-6" treetype="folder">
|
|
<SubFolder label="Config/BSCAN Components" treetype="folder">
|
|
<Template label="JTAG Boundary Scan Logic Control Circuit (BSCAN_SPARTAN6)" treetype="template">
|
|
// BSCAN_SPARTAN6 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BSCAN_SPARTAN6_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BSCAN_SPARTAN6: JTAG Boundary Scan Logic Control Circuit
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BSCAN_SPARTAN6 #(
|
|
.JTAG_CHAIN(1) // Value for USER command. Possible values: (1,2,3 or 4).
|
|
)
|
|
BSCAN_SPARTAN6_inst (
|
|
.CAPTURE(CAPTURE), // 1-bit output: CAPTURE output from TAP controller.
|
|
.DRCK(DRCK), // 1-bit output: Data register output for USER functions.
|
|
.RESET(RESET), // 1-bit output: Reset output for TAP controller.
|
|
.RUNTEST(RUNTEST), // 1-bit output: Output signal that gets asserted when TAP controller is in Run Test
|
|
// Idle state.
|
|
|
|
.SEL(SEL), // 1-bit output: USER active output.
|
|
.SHIFT(SHIFT), // 1-bit output: SHIFT output from TAP controller.
|
|
.TCK(TCK), // 1-bit output: Scan Clock output. Fabric connection to TAP Clock pin.
|
|
.TDI(TDI), // 1-bit output: TDI output from TAP controller.
|
|
.TMS(TMS), // 1-bit output: Test Mode Select output. Fabric connection to TAP.
|
|
.UPDATE(UPDATE), // 1-bit output: UPDATE output from TAP controller
|
|
.TDO(TDO) // 1-bit input: Data input for USER function.
|
|
);
|
|
|
|
// End of BSCAN_SPARTAN6_inst instantiation
|
|
</Template>
|
|
<Template label="Device DNA Data Access Port (DNA_PORT)" treetype="template">
|
|
// DNA_PORT : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (DNA_PORT_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// DNA_PORT: Device DNA Data Access Port
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
DNA_PORT #(
|
|
.SIM_DNA_VALUE(57'h000000000000000) // Specifies the Pre-programmed factory ID value
|
|
)
|
|
DNA_PORT_inst (
|
|
.DOUT(DOUT), // 1-bit output: DNA output data
|
|
.CLK(CLK), // 1-bit input: Clock input
|
|
.DIN(DIN), // 1-bit input: User data input pin
|
|
.READ(READ), // 1-bit input: Active high load DNA, active low read input
|
|
.SHIFT(SHIFT) // 1-bit input: Active high shift enable input
|
|
);
|
|
|
|
// End of DNA_PORT_inst instantiation
|
|
</Template>
|
|
<Template label="Internal Configuration Access Port (ICAP_SPARTAN6)" treetype="template">
|
|
// ICAP_SPARTAN6 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ICAP_SPARTAN6_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ICAP_SPARTAN6: Internal Configuration Access Port
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ICAP_SPARTAN6 #(
|
|
.DEVICE_ID(0'h4000093), // Specifies the pre-programmed Device ID value
|
|
.SIM_CFG_FILE_NAME("NONE") // Specifies the Raw Bitstream (RBT) file to be parsed by the simulation
|
|
// model
|
|
)
|
|
ICAP_SPARTAN6_inst (
|
|
.BUSY(BUSY), // 1-bit output: Busy/Ready output
|
|
.O(O), // 16-bit output: Configuartion data output bus
|
|
.CE(CE), // 1-bit input: Active-Low ICAP Enable input
|
|
.CLK(CLK), // 1-bit input: Clock input
|
|
.I(I), // 16-bit input: Configuration data input bus
|
|
.WRITE(WRITE) // 1-bit input: Read/Write control input
|
|
);
|
|
|
|
// End of ICAP_SPARTAN6_inst instantiation
|
|
</Template>
|
|
<Template label="Post-configuration CRC error detection (POST_CRC_INTERNAL)" treetype="template">
|
|
// POST_CRC_INTERNAL : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (POST_CRC_INTERNAL_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// POST_CRC_INTERNAL: Post-configuration CRC error detection
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
POST_CRC_INTERNAL POST_CRC_INTERNAL_inst (
|
|
.CRCERROR(CRCERROR) // 1-bit output: Post-configuration CRC error output
|
|
);
|
|
|
|
// End of POST_CRC_INTERNAL_inst instantiation
|
|
</Template>
|
|
<Template label="STARTUP Block (STARTUP_SPARTAN6)" treetype="template">
|
|
// STARTUP_SPARTAN6 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (STARTUP_SPARTAN6_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// STARTUP_SPARTAN6: STARTUP Block
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
STARTUP_SPARTAN6 STARTUP_SPARTAN6_inst (
|
|
.CFGCLK(CFGCLK), // 1-bit output: Configuration logic main clock output.
|
|
.CFGMCLK(CFGMCLK), // 1-bit output: Configuration internal oscillator clock output.
|
|
.EOS(EOS), // 1-bit output: Active high output signal indicates the End Of Configuration.
|
|
.CLK(CLK), // 1-bit input: User startup-clock input
|
|
.GSR(GSR), // 1-bit input: Global Set/Reset input (GSR cannot be used for the port name)
|
|
.GTS(GTS), // 1-bit input: Global 3-state input (GTS cannot be used for the port name)
|
|
.KEYCLEARB(KEYCLEARB) // 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM)
|
|
);
|
|
|
|
// End of STARTUP_SPARTAN6_inst instantiation
|
|
</Template>
|
|
<Template label="Suspend Mode Access (SUSPEND_SYNC)" treetype="template">
|
|
// SUSPEND_SYNC : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SUSPEND_SYNC_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SUSPEND_SYNC: Suspend Mode Access
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SUSPEND_SYNC SUSPEND_SYNC_inst (
|
|
.SREQ(SREQ), // 1-bit output: Suspend request output
|
|
.CLK(CLK), // 1-bit input: User clock input
|
|
.SACK(SACK) // 1-bit input: SUSPEND acknowledgement output
|
|
);
|
|
|
|
// End of SUSPEND_SYNC_inst instantiation
|
|
</Template>
|
|
<Template label="SelectMap Configuration Simulation Model (SIM_CONFIG_S6)" treetype="template">
|
|
// SIM_CONFIG_S6 : In order to incorporate this function into the testbench (not the design),
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SIM_CONFIG_S6_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SIM_CONFIG_S6: Behavioral Simulation-only Model of FPGA SelectMap Configuration
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SIM_CONFIG_S6 #(
|
|
.DEVICE_ID(32'h00000000) // Specify DEVICE_ID
|
|
) SIM_CONFIG_S6_inst (
|
|
.BUSY(BUSY), // 1-bit output Busy pin
|
|
.CSOB(CSOB), // 1-bit output chip select pin
|
|
.DONE(DONE), // 1-bit bi-directional Done pin
|
|
.CCLK(CCLK), // 1-bit input configuration clock
|
|
.CSIB(CSIB), // 1-bit input chip select
|
|
.D(D), // 16-bit bi-directional configuration data
|
|
.INITB(INITB), // 1-bit bi-directional INIT status pin
|
|
.M(M), // 2-bit input Mode pins
|
|
.PROGB(PROGB), // 1-bit input Program pin
|
|
.RDWRB(RDWRB) // 1-bit input Read/write pin
|
|
);
|
|
|
|
// End of SIM_CONFIG_S6_inst instantiation
|
|
</Template>
|
|
<Template label="Serial Configuration Simulation Model (SIM_CONFIG_S6_SERIAL)" treetype="template">
|
|
// SIM_CONFIG_S6_SERIAL : In order to incorporate this function into the testbench (not the design),
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SIM_CONFIG_S6_SERIAL_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SIM_CONFIG_S6_SERIAL: Behavioral Simulation-only Model of FPGA Serial Configuration
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SIM_CONFIG_S6_SERIAL #(
|
|
.DEVICE_ID(32'h00000000) // Specify DEVICE_ID
|
|
) SIM_CONFIG_S6_SERIAL_inst (
|
|
.DONE(DONE), // 1-bit bi-directional Done pin
|
|
.CCLK(CCLK), // 1-bit input configuration clock
|
|
.DIN(DIN), // 1-bit input configuration data
|
|
.INITB(INITB), // 1-bit bi-directional INIT status pin
|
|
.M(M), // 2-bit input Mode pins
|
|
.PROGB(PROGB) // 1-bit input Program pin
|
|
);
|
|
|
|
// End of SIM_CONFIG_S6_SERIAL_inst instantiation
|
|
</Template>
|
|
<Template label="JTAG Simulation Model (JTAG_SIM_SPARTAN6)" treetype="template">
|
|
// JTAG_SIM_SPARTAN6 : In order to use this simulation model, the
|
|
// Verilog : forllowing instance declaration needs to be placed
|
|
// instance : in the testbench code to simulate the design. This
|
|
// declaration : should not be instnatiated into synthesizable design code.
|
|
// code : None of the ports need to be connected to the design
|
|
// : as communication is handled through the glbl.v module.
|
|
// : All ports can be connected to reg/wires in the testbench.
|
|
// : Only one JTAG_SIM_SPARTAN6 should be instantiated per design.
|
|
// : All inputs and outputs should be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// JTAG_SIM_SPARTAN6: JTAG Interface Simulation Model
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
JTAG_SIM_SPARTAN6 #(
|
|
.PART_NAME("LX4") // Specify target S6 device. Possible values are:
|
|
// "LX4","LX150","LX150T","LX16","LX4","LX45","LX45T"
|
|
) JTAG_SIM_SPARTAN6_inst (
|
|
.TDO(TDO), // 1-bit JTAG data output
|
|
.TCK(TCK), // 1-bit Clock input
|
|
.TDI(TDI), // 1-bit JTAG data input
|
|
.TMS(TMS) // 1-bit JTAG command input
|
|
);
|
|
|
|
// End of JTAG_SIM_SPARTAN6_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Clock Components" treetype="folder">
|
|
<Template label="Global Clock Buffer with Clock Enable and Output State 1 (BUFGCE_1)" treetype="template">
|
|
// BUFGCE_1 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFGCE_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFGCE_1: Global Clock Buffer with Clock Enable and Output State 1
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFGCE_1 BUFGCE_1_inst (
|
|
.O(O), // 1-bit output: Clock buffer output
|
|
.CE(CE), // 1-bit input: Clock buffer select
|
|
.I(I) // 1-bit input: Clock buffer input (S=0)
|
|
);
|
|
|
|
// End of BUFGCE_1_inst instantiation
|
|
</Template>
|
|
<Template label="Global Clock Buffer with Clock Enable (BUFGCE)" treetype="template">
|
|
// BUFGCE : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFGCE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFGCE: Global Clock Buffer with Clock Enable
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFGCE BUFGCE_inst (
|
|
.O(O), // 1-bit output: Clock buffer output
|
|
.CE(CE), // 1-bit input: Clock buffer select
|
|
.I(I) // 1-bit input: Clock buffer input (S=0)
|
|
);
|
|
|
|
// End of BUFGCE_inst instantiation
|
|
</Template>
|
|
<Template label="Global Clock Mux Buffer with Output State 1 (BUFGMUX_1)" treetype="template">
|
|
// BUFGMUX_1 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFGMUX_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFGMUX_1: Global Clock Mux Buffer with Output State 1
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFGMUX_1 #(
|
|
.CLK_SEL_TYPE("SYNC") // Glitchles ("SYNC") or fast ("ASYNC") clock switch-over
|
|
)
|
|
BUFGMUX_1_inst (
|
|
.O(O), // 1-bit output: Clock buffer output
|
|
.I0(I0), // 1-bit input: Clock buffer input
|
|
.I1(I1), // 1-bit input: Clock buffer input
|
|
.S(S) // 1-bit input: Clock buffer select
|
|
);
|
|
|
|
// End of BUFGMUX_1_inst instantiation
|
|
</Template>
|
|
<Template label="Global Clock Mux Buffer (BUFGMUX)" treetype="template">
|
|
// BUFGMUX : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFGMUX_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFGMUX: Global Clock Mux Buffer
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFGMUX #(
|
|
.CLK_SEL_TYPE("SYNC") // Glitchles ("SYNC") or fast ("ASYNC") clock switch-over
|
|
)
|
|
BUFGMUX_inst (
|
|
.O(O), // 1-bit output: Clock buffer output
|
|
.I0(I0), // 1-bit input: Clock buffer input (S=0)
|
|
.I1(I1), // 1-bit input: Clock buffer input (S=1)
|
|
.S(S) // 1-bit input: Clock buffer select
|
|
);
|
|
|
|
// End of BUFGMUX_inst instantiation
|
|
</Template>
|
|
<Template label="Global Clock Buffer (BUFG)" treetype="template">
|
|
// BUFG : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFG_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFG: Global Clock Buffer
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFG BUFG_inst (
|
|
.O(O), // 1-bit output: Clock buffer output
|
|
.I(I) // 1-bit input: Clock buffer input
|
|
);
|
|
|
|
// End of BUFG_inst instantiation
|
|
</Template>
|
|
<Template label="HROW Clock Buffer for a Single Clocking Region (BUFH)" treetype="template">
|
|
// BUFH : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFH_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFH: HROW Clock Buffer for a Single Clocking Region
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFH BUFH_inst (
|
|
.O(O), // 1-bit output: Clock output
|
|
.I(I) // 1-bit input: Clock input
|
|
);
|
|
|
|
// End of BUFH_inst instantiation
|
|
</Template>
|
|
<Template label="Dual Input Differential Clock Buffer (BUFIO2_2CLK)" treetype="template">
|
|
// BUFIO2_2CLK : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFIO2_2CLK_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFIO2_2CLK: Dual Input Differential Clock Buffer
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFIO2_2CLK #(
|
|
.DIVIDE(3) // DIVCLK divider (3-8)
|
|
)
|
|
BUFIO2_2CLK_inst (
|
|
.DIVCLK(DIVCLK), // 1-bit output: Divided clock output
|
|
.IOCLK(IOCLK), // 1-bit output: I/O output clock
|
|
.SERDESSTROBE(SERDESSTROBE), // 1-bit output: Output SERDES strobe (connect to ISERDES2/OSERDES2)
|
|
.I(I), // 1-bit input: Clock input (connect to IBUFG)
|
|
.IB(IB) // 1-bit input: Secondary clock input
|
|
);
|
|
|
|
// End of BUFIO2_2CLK_inst instantiation
|
|
</Template>
|
|
<Template label="DCM/PLL Feedback Clock Buffer (BUFIO2FB)" treetype="template">
|
|
// BUFIO2FB : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFIO2FB_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFIO2FB: DCM/PLL Feedback Clock Buffer
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFIO2FB #(
|
|
.DIVIDE_BYPASS("TRUE") // Bypass divider (TRUE/FALSE)
|
|
)
|
|
BUFIO2FB_inst (
|
|
.O(O), // 1-bit output: Output feedback clock (connect to feedback input of DCM/PLL)
|
|
.I(I) // 1-bit input: Feedback clock input (connect to input port)
|
|
);
|
|
|
|
// End of BUFIO2FB_inst instantiation
|
|
</Template>
|
|
<Template label="I/O Clock Buffer (BUFIO2)" treetype="template">
|
|
// BUFIO2 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFIO2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFIO2: I/O Clock Buffer
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFIO2 #(
|
|
.DIVIDE(1), // DIVCLK divider (1,3-8)
|
|
.DIVIDE_BYPASS("TRUE"), // Bypass the divider circuitry (TRUE/FALSE)
|
|
.I_INVERT("FALSE"), // Invert clock (TRUE/FALSE)
|
|
.USE_DOUBLER("FALSE") // Use doubler circuitry (TRUE/FALSE)
|
|
)
|
|
BUFIO2_inst (
|
|
.DIVCLK(DIVCLK), // 1-bit output: Divided clock output
|
|
.IOCLK(IOCLK), // 1-bit output: I/O output clock
|
|
.SERDESSTROBE(SERDESSTROBE), // 1-bit output: Output SERDES strobe (connect to ISERDES2/OSERDES2)
|
|
.I(I) // 1-bit input: Clock input (connect to IBUFG)
|
|
);
|
|
|
|
// End of BUFIO2_inst instantiation
|
|
</Template>
|
|
<Template label="High-speed I/O PLL clock buffer (BUFPLL)" treetype="template">
|
|
// BUFPLL : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFPLL_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFPLL: High-speed I/O PLL clock buffer
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFPLL #(
|
|
.DIVIDE(1), // DIVCLK divider (1-8)
|
|
.ENABLE_SYNC("TRUE") // Enable synchrnonization between PLL and GCLK (TRUE/FALSE)
|
|
)
|
|
BUFPLL_inst (
|
|
.IOCLK(IOCLK), // 1-bit output: Output I/O clock
|
|
.LOCK(LOCK), // 1-bit output: Synchronized LOCK output
|
|
.SERDESSTROBE(SERDESSTROBE), // 1-bit output: Output SERDES strobe (connect to ISERDES2/OSERDES2)
|
|
.GCLK(GCLK), // 1-bit input: BUFG clock input
|
|
.LOCKED(LOCKED), // 1-bit input: LOCKED input from PLL
|
|
.PLLIN(PLLIN) // 1-bit input: Clock input from PLL
|
|
);
|
|
|
|
// End of BUFPLL_inst instantiation
|
|
</Template>
|
|
<Template label="Digital Clock Manager Frequency Alligned Clock Generator (DCM_CLKGEN)" treetype="template">
|
|
// DCM_CLKGEN : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (DCM_CLKGEN_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// DCM_CLKGEN: Frequency Aligned Digital Clock Manager
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
DCM_CLKGEN #(
|
|
.CLKFXDV_DIVIDE(2), // CLKFXDV divide value (2, 4, 8, 16, 32)
|
|
.CLKFX_DIVIDE(1), // Divide value - D - (1-256)
|
|
.CLKFX_MD_MAX(0.0), // Specify maximum M/D ratio for timing anlysis
|
|
.CLKFX_MULTIPLY(4), // Multiply value - M - (2-256)
|
|
.CLKIN_PERIOD(0.0), // Input clock period specified in nS
|
|
.SPREAD_SPECTRUM("NONE"), // Spread Spectrum mode "NONE", "CENTER_LOW_SPREAD", "CENTER_HIGH_SPREAD",
|
|
// "VIDEO_LINK_M0", "VIDEO_LINK_M1" or "VIDEO_LINK_M2"
|
|
.STARTUP_WAIT("FALSE") // Delay config DONE until DCM_CLKGEN LOCKED (TRUE/FALSE)
|
|
)
|
|
DCM_CLKGEN_inst (
|
|
.CLKFX(CLKFX), // 1-bit output: Generated clock output
|
|
.CLKFX180(CLKFX180), // 1-bit output: Generated clock output 180 degree out of phase from CLKFX.
|
|
.CLKFXDV(CLKFXDV), // 1-bit output: Divided clock output
|
|
.LOCKED(LOCKED), // 1-bit output: Locked output
|
|
.PROGDONE(PROGDONE), // 1-bit output: Active high output to indicate the successful re-programming
|
|
.STATUS(STATUS), // 2-bit output: DCM_CLKGEN status
|
|
.CLKIN(CLKIN), // 1-bit input: Input clock
|
|
.FREEZEDCM(FREEZEDCM), // 1-bit input: Prevents frequency adjustments to input clock
|
|
.PROGCLK(PROGCLK), // 1-bit input: Clock input for M/D reconfiguration
|
|
.PROGDATA(PROGDATA), // 1-bit input: Serial data input for M/D reconfiguration
|
|
.PROGEN(PROGEN), // 1-bit input: Active high program enable
|
|
.RST(RST) // 1-bit input: Reset input pin
|
|
);
|
|
|
|
// End of DCM_CLKGEN_inst instantiation
|
|
</Template>
|
|
<Template label="Spartan Digital Clock Manager (DCM_SP)" treetype="template">
|
|
// DCM_SP : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (DCM_SP_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// DCM_SP: Digital Clock Manager
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
DCM_SP #(
|
|
.CLKDV_DIVIDE(2.0), // CLKDV divide value
|
|
// (1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,7,7.5,8,9,10,11,12,13,14,15,16).
|
|
.CLKFX_DIVIDE(1), // Divide value on CLKFX outputs - D - (1-32)
|
|
.CLKFX_MULTIPLY(4), // Multiply value on CLKFX outputs - M - (2-32)
|
|
.CLKIN_DIVIDE_BY_2("FALSE"), // CLKIN divide by two (TRUE/FALSE)
|
|
.CLKIN_PERIOD(10.0), // Input clock period specified in nS
|
|
.CLKOUT_PHASE_SHIFT("NONE"), // Output phase shift (NONE, FIXED, VARIABLE)
|
|
.CLK_FEEDBACK("1X"), // Feedback source (NONE, 1X, 2X)
|
|
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SYSTEM_SYNCHRNOUS or SOURCE_SYNCHRONOUS
|
|
.DFS_FREQUENCY_MODE("LOW"), // Unsupported - Do not change value
|
|
.DLL_FREQUENCY_MODE("LOW"), // Unsupported - Do not change value
|
|
.DSS_MODE("NONE"), // Unsupported - Do not change value
|
|
.DUTY_CYCLE_CORRECTION("TRUE"), // Unsupported - Do not change value
|
|
.FACTORY_JF(16'hc080), // Unsupported - Do not change value
|
|
.PHASE_SHIFT(0), // Amount of fixed phase shift (-255 to 255)
|
|
.STARTUP_WAIT("FALSE") // Delay config DONE until DCM_SP LOCKED (TRUE/FALSE)
|
|
)
|
|
DCM_SP_inst (
|
|
.CLK0(CLK0), // 1-bit output: 0 degree clock output
|
|
.CLK180(CLK180), // 1-bit output: 180 degree clock output
|
|
.CLK270(CLK270), // 1-bit output: 270 degree clock output
|
|
.CLK2X(CLK2X), // 1-bit output: 2X clock frequency clock output
|
|
.CLK2X180(CLK2X180), // 1-bit output: 2X clock frequency, 180 degree clock output
|
|
.CLK90(CLK90), // 1-bit output: 90 degree clock output
|
|
.CLKDV(CLKDV), // 1-bit output: Divided clock output
|
|
.CLKFX(CLKFX), // 1-bit output: Digital Frequency Synthesizer output (DFS)
|
|
.CLKFX180(CLKFX180), // 1-bit output: 180 degree CLKFX output
|
|
.LOCKED(LOCKED), // 1-bit output: DCM_SP Lock Output
|
|
.PSDONE(PSDONE), // 1-bit output: Phase shift done output
|
|
.STATUS(STATUS), // 8-bit output: DCM_SP status output
|
|
.CLKFB(CLKFB), // 1-bit input: Clock feedback input
|
|
.CLKIN(CLKIN), // 1-bit input: Clock input
|
|
.DSSEN(DSSEN), // 1-bit input: Unsupported, specify to GND.
|
|
.PSCLK(PSCLK), // 1-bit input: Phase shift clock input
|
|
.PSEN(PSEN), // 1-bit input: Phase shift enable
|
|
.PSINCDEC(PSINCDEC), // 1-bit input: Phase shift increment/decrement input
|
|
.RST(RST) // 1-bit input: Active high reset input
|
|
);
|
|
|
|
// End of DCM_SP_inst instantiation
|
|
</Template>
|
|
<Template label="Base Phase Locked Loop (PLL_BASE)" treetype="template">
|
|
// PLL_BASE : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (PLL_BASE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// PLL_BASE: Phase Locked Loop (PLL) Clock Management Component
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
PLL_BASE #(
|
|
.BANDWIDTH("OPTIMIZED"), // "HIGH", "LOW" or "OPTIMIZED"
|
|
.CLKFBOUT_MULT(1), // Multiply value for all CLKOUT clock outputs (1-64)
|
|
.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of the clock feedback output (0.0-360.0).
|
|
.CLKIN_PERIOD(0.0), // Input clock period in ns to ps resolution (i.e. 33.333 is 30
|
|
// MHz).
|
|
// CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for CLKOUT# clock output (1-128)
|
|
.CLKOUT0_DIVIDE(1),
|
|
.CLKOUT1_DIVIDE(1),
|
|
.CLKOUT2_DIVIDE(1),
|
|
.CLKOUT3_DIVIDE(1),
|
|
.CLKOUT4_DIVIDE(1),
|
|
.CLKOUT5_DIVIDE(1),
|
|
// CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for CLKOUT# clock output (0.01-0.99).
|
|
.CLKOUT0_DUTY_CYCLE(0.5),
|
|
.CLKOUT1_DUTY_CYCLE(0.5),
|
|
.CLKOUT2_DUTY_CYCLE(0.5),
|
|
.CLKOUT3_DUTY_CYCLE(0.5),
|
|
.CLKOUT4_DUTY_CYCLE(0.5),
|
|
.CLKOUT5_DUTY_CYCLE(0.5),
|
|
// CLKOUT0_PHASE - CLKOUT5_PHASE: Output phase relationship for CLKOUT# clock output (-360.0-360.0).
|
|
.CLKOUT0_PHASE(0.0),
|
|
.CLKOUT1_PHASE(0.0),
|
|
.CLKOUT2_PHASE(0.0),
|
|
.CLKOUT3_PHASE(0.0),
|
|
.CLKOUT4_PHASE(0.0),
|
|
.CLKOUT5_PHASE(0.0),
|
|
.CLK_FEEDBACK("CLKFBOUT"), // Clock source to drive CLKFBIN ("CLKFBOUT" or "CLKOUT0")
|
|
.COMPENSATION("SYSTEM_SYNCHRONOUS"), // "SYSTEM_SYNCHRONOUS", "SOURCE_SYNCHRONOUS", "EXTERNAL"
|
|
.DIVCLK_DIVIDE(1), // Division value for all output clocks (1-52)
|
|
.REF_JITTER(0.1), // Reference Clock Jitter in UI (0.000-0.999).
|
|
.RESET_ON_LOSS_OF_LOCK("FALSE") // Must be set to FALSE
|
|
)
|
|
PLL_BASE_inst (
|
|
.CLKFBOUT(CLKFBOUT), // 1-bit output: PLL_BASE feedback output
|
|
// CLKOUT0 - CLKOUT5: 1-bit (each) output: Clock outputs
|
|
.CLKOUT0(CLKOUT0),
|
|
.CLKOUT1(CLKOUT1),
|
|
.CLKOUT2(CLKOUT2),
|
|
.CLKOUT3(CLKOUT3),
|
|
.CLKOUT4(CLKOUT4),
|
|
.CLKOUT5(CLKOUT5),
|
|
.LOCKED(LOCKED), // 1-bit output: PLL_BASE lock status output
|
|
.CLKFBIN(CLKFBIN), // 1-bit input: Feedback clock input
|
|
.CLKIN(CLKIN), // 1-bit input: Clock input
|
|
.RST(RST) // 1-bit input: Reset input
|
|
);
|
|
|
|
// End of PLL_BASE_inst instantiation
|
|
</Template>
|
|
<Template label="Single-ended input Global Clock Buffer (IBUFG)" treetype="template">
|
|
// IBUFG : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFG_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFG: Global Clock Buffer (sourced by an external pin)
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFG #(
|
|
.IOSTANDARD("DEFAULT")
|
|
) IBUFG_inst (
|
|
.O(O), // Clock buffer output
|
|
.I(I) // Clock buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUFG_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Input Global Clock Buffer (IBUFGDS)" treetype="template">
|
|
// IBUFGDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFGDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFGDS: Differential Global Clock Buffer (sourced by an external pin)
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFGDS #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination
|
|
.IOSTANDARD("DEFAULT") // Specifies the I/O standard for this buffer
|
|
) IBUFGDS_inst (
|
|
.O(O), // Clock buffer output
|
|
.I(I), // Diff_p clock buffer input
|
|
.IB(IB) // Diff_n clock buffer input
|
|
);
|
|
|
|
// End of IBUFGDS_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Global Clock Buffer with Differential Output (IBUFGDS_DIFF_OUT)" treetype="template">
|
|
// IBUFGDS_DIFF_OUT : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFGDS_DIFF_OUT_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFGDS_DIFF_OUT: Differential Global Clock Buffer with Differential Output
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFGDS_DIFF_OUT #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination, "TRUE"/"FALSE"
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
) IBUFGDS_DIFF_OUT_inst (
|
|
.O(O), // Buffer diff_p output
|
|
.OB(OB), // Buffer diff_n output
|
|
.I(I), // Diff_p buffer input (connect directly to top-level port)
|
|
.IB(IB) // Diff_n buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUFGDS_DIFF_OUT_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Arithmetic Functions" treetype="folder">
|
|
<Template label="48-bit Multi-Functional Arithmetic Block (DSP48A1)" treetype="template">
|
|
// DSP48A1 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (DSP48A1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// DSP48A1: 48-bit Multi-Functional Arithmetic Block
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
DSP48A1 #(
|
|
.A0REG(0), // First stage A input pipeline register (0/1)
|
|
.A1REG(1), // Second stage A input pipeline register (0/1)
|
|
.B0REG(0), // First stage B input pipeline register (0/1)
|
|
.B1REG(1), // Second stage B input pipeline register (0/1)
|
|
.CARRYINREG(1), // CARRYIN input pipeline register (0/1)
|
|
.CARRYINSEL("OPMODE5"), // Specify carry-in source, "CARRYIN" or "OPMODE5"
|
|
.CARRYOUTREG(1), // CARRYOUT output pipeline register (0/1)
|
|
.CREG(1), // C input pipeline register (0/1)
|
|
.DREG(1), // D pre-adder input pipeline register (0/1)
|
|
.MREG(1), // M pipeline register (0/1)
|
|
.OPMODEREG(1), // Enable=1/disable=0 OPMODE input pipeline registers
|
|
.PREG(1), // P output pipeline register (0/1)
|
|
.RSTTYPE("SYNC") // Specify reset type, "SYNC" or "ASYNC"
|
|
)
|
|
DSP48A1_inst (
|
|
// Cascade Ports: 18-bit (each) output: Ports to cascade from one DSP48 to another
|
|
.BCOUT(BCOUT), // 18-bit output: B port cascade output
|
|
.PCOUT(PCOUT), // 48-bit output: P cascade output (if used, connect to PCIN of another DSP48A1)
|
|
// Data Ports: 1-bit (each) output: Data input and output ports
|
|
.CARRYOUT(CARRYOUT), // 1-bit output: carry output (if used, connect to CARRYIN pin of another
|
|
// DSP48A1)
|
|
|
|
.CARRYOUTF(CARRYOUTF), // 1-bit output: fabric carry output
|
|
.M(M), // 36-bit output: fabric multiplier data output
|
|
.P(P), // 48-bit output: data output
|
|
// Cascade Ports: 48-bit (each) input: Ports to cascade from one DSP48 to another
|
|
.PCIN(PCIN), // 48-bit input: P cascade input (if used, connect to PCOUT of another DSP48A1)
|
|
// Control Input Ports: 1-bit (each) input: Clocking and operation mode
|
|
.CLK(CLK), // 1-bit input: clock input
|
|
.OPMODE(OPMODE), // 8-bit input: operation mode input
|
|
// Data Ports: 18-bit (each) input: Data input and output ports
|
|
.A(A), // 18-bit input: A data input
|
|
.B(B), // 18-bit input: B data input (connected to fabric or BCOUT of adjacent DSP48A1)
|
|
.C(C), // 48-bit input: C data input
|
|
.CARRYIN(CARRYIN), // 1-bit input: carry input signal (if used, connect to CARRYOUT pin of another
|
|
// DSP48A1)
|
|
|
|
.D(D), // 18-bit input: B pre-adder data input
|
|
// Reset/Clock Enable Input Ports: 1-bit (each) input: Reset and enable input ports
|
|
.CEA(CEA), // 1-bit input: active high clock enable input for A registers
|
|
.CEB(CEB), // 1-bit input: active high clock enable input for B registers
|
|
.CEC(CEC), // 1-bit input: active high clock enable input for C registers
|
|
.CECARRYIN(CECARRYIN), // 1-bit input: active high clock enable input for CARRYIN registers
|
|
.CED(CED), // 1-bit input: active high clock enable input for D registers
|
|
.CEM(CEM), // 1-bit input: active high clock enable input for multiplier registers
|
|
.CEOPMODE(CEOPMODE), // 1-bit input: active high clock enable input for OPMODE registers
|
|
.CEP(CEP), // 1-bit input: active high clock enable input for P registers
|
|
.RSTA(RSTA), // 1-bit input: reset input for A pipeline registers
|
|
.RSTB(RSTB), // 1-bit input: reset input for B pipeline registers
|
|
.RSTC(RSTC), // 1-bit input: reset input for C pipeline registers
|
|
.RSTCARRYIN(RSTCARRYIN), // 1-bit input: reset input for CARRYIN pipeline registers
|
|
.RSTD(RSTD), // 1-bit input: reset input for D pipeline registers
|
|
.RSTM(RSTM), // 1-bit input: reset input for M pipeline registers
|
|
.RSTOPMODE(RSTOPMODE), // 1-bit input: reset input for OPMODE pipeline registers
|
|
.RSTP(RSTP) // 1-bit input: reset input for P pipeline registers
|
|
);
|
|
|
|
// End of DSP48A1_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="I/O Components" treetype="folder">
|
|
<Template label="Input and Output Fixed or Variable Delay Element (IODELAY2)" treetype="template">
|
|
// IODELAY2 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IODELAY2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IODELAY2: Input and Output Fixed or Variable Delay Element
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IODELAY2 #(
|
|
.COUNTER_WRAPAROUND("WRAPAROUND"), // "STAY_AT_LIMIT" or "WRAPAROUND"
|
|
.DATA_RATE("SDR"), // "SDR" or "DDR"
|
|
.DELAY_SRC("IO"), // "IO", "ODATAIN" or "IDATAIN"
|
|
.IDELAY2_VALUE(0), // Delay value when IDELAY_MODE="PCI" (0-255)
|
|
.IDELAY_MODE("NORMAL"), // "NORMAL" or "PCI"
|
|
.IDELAY_TYPE("DEFAULT"), // "FIXED", "DEFAULT", "VARIABLE_FROM_ZERO", "VARIABLE_FROM_HALF_MAX"
|
|
// or "DIFF_PHASE_DETECTOR"
|
|
.IDELAY_VALUE(0), // Amount of taps for fixed input delay (0-255)
|
|
.ODELAY_VALUE(0), // Amount of taps fixed output delay (0-255)
|
|
.SERDES_MODE("NONE"), // "NONE", "MASTER" or "SLAVE"
|
|
.SIM_TAPDELAY_VALUE(75) // Per tap delay used for simulation in ps
|
|
)
|
|
IODELAY2_inst (
|
|
.BUSY(BUSY), // 1-bit output: Busy output after CAL
|
|
.DATAOUT(DATAOUT), // 1-bit output: Delayed data output to ISERDES/input register
|
|
.DATAOUT2(DATAOUT2), // 1-bit output: Delayed data output to general FPGA fabric
|
|
.DOUT(DOUT), // 1-bit output: Delayed data output
|
|
.TOUT(TOUT), // 1-bit output: Delayed 3-state output
|
|
.CAL(CAL), // 1-bit input: Initiate calibration input
|
|
.CE(CE), // 1-bit input: Enable INC input
|
|
.CLK(CLK), // 1-bit input: Clock input
|
|
.IDATAIN(IDATAIN), // 1-bit input: Data input (connect to top-level port or I/O buffer)
|
|
.INC(INC), // 1-bit input: Increment / decrement input
|
|
.IOCLK0(IOCLK0), // 1-bit input: Input from the I/O clock network
|
|
.IOCLK1(IOCLK1), // 1-bit input: Input from the I/O clock network
|
|
.ODATAIN(ODATAIN), // 1-bit input: Output data input from output register or OSERDES2.
|
|
.RST(RST), // 1-bit input: Reset to zero or 1/2 of total delay period
|
|
.T(T) // 1-bit input: 3-state input signal
|
|
);
|
|
|
|
// End of IODELAY2_inst instantiation
|
|
</Template>
|
|
<Template label="Input SERial/DESerializer (ISERDES2)" treetype="template">
|
|
// ISERDES2 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ISERDES2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ISERDES2: Input SERial/DESerializer
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ISERDES2 #(
|
|
.BITSLIP_ENABLE("FALSE"), // Enable Bitslip Functionality (TRUE/FALSE)
|
|
.DATA_RATE("SDR"), // Data-rate ("SDR" or "DDR")
|
|
.DATA_WIDTH(1), // Parallel data width selection (2-8)
|
|
.INTERFACE_TYPE("NETWORKING"), // "NETWORKING", "NETWORKING_PIPELINED" or "RETIMED"
|
|
.SERDES_MODE("NONE") // "NONE", "MASTER" or "SLAVE"
|
|
)
|
|
ISERDES2_inst (
|
|
.CFB0(CFB0), // 1-bit output: Clock feed-through route output
|
|
.CFB1(CFB1), // 1-bit output: Clock feed-through route output
|
|
.DFB(DFB), // 1-bit output: Feed-through clock output
|
|
.FABRICOUT(FABRICOUT), // 1-bit output: Unsynchrnonized data output
|
|
.INCDEC(INCDEC), // 1-bit output: Phase detector output
|
|
// Q1 - Q4: 1-bit (each) output: Registered outputs to FPGA logic
|
|
.Q1(Q1),
|
|
.Q2(Q2),
|
|
.Q3(Q3),
|
|
.Q4(Q4),
|
|
.SHIFTOUT(SHIFTOUT), // 1-bit output: Cascade output signal for master/slave I/O
|
|
.VALID(VALID), // 1-bit output: Output status of the phase detector
|
|
.BITSLIP(BITSLIP), // 1-bit input: Bitslip enable input
|
|
.CE0(CE0), // 1-bit input: Clock enable input
|
|
.CLK0(CLK0), // 1-bit input: I/O clock network input
|
|
.CLK1(CLK1), // 1-bit input: Secondary I/O clock network input
|
|
.CLKDIV(CLKDIV), // 1-bit input: FPGA logic domain clock input
|
|
.D(D), // 1-bit input: Input data
|
|
.IOCE(IOCE), // 1-bit input: Data strobe input
|
|
.RST(RST), // 1-bit input: Asynchronous reset input
|
|
.SHIFTIN(SHIFTIN) // 1-bit input: Cascade input signal for master/slave I/O
|
|
);
|
|
|
|
// End of ISERDES2_inst instantiation
|
|
</Template>
|
|
<Template label="Output SERial/DESerializer (OSERDES2)" treetype="template">
|
|
// OSERDES2 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OSERDES2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OSERDES2: Output SERial/DESerializer
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OSERDES2 #(
|
|
.BYPASS_GCLK_FF("FALSE"), // Bypass CLKDIV syncronization registers (TRUE/FALSE)
|
|
.DATA_RATE_OQ("DDR"), // Output Data Rate ("SDR" or "DDR")
|
|
.DATA_RATE_OT("DDR"), // 3-state Data Rate ("SDR" or "DDR")
|
|
.DATA_WIDTH(2), // Parallel data width (2-8)
|
|
.OUTPUT_MODE("SINGLE_ENDED"), // "SINGLE_ENDED" or "DIFFERENTIAL"
|
|
.SERDES_MODE("NONE"), // "NONE", "MASTER" or "SLAVE"
|
|
.TRAIN_PATTERN(0) // Training Pattern (0-15)
|
|
)
|
|
OSERDES2_inst (
|
|
.OQ(OQ), // 1-bit output: Data output to pad or IODELAY2
|
|
.SHIFTOUT1(SHIFTOUT1), // 1-bit output: Cascade data output
|
|
.SHIFTOUT2(SHIFTOUT2), // 1-bit output: Cascade 3-state output
|
|
.SHIFTOUT3(SHIFTOUT3), // 1-bit output: Cascade differential data output
|
|
.SHIFTOUT4(SHIFTOUT4), // 1-bit output: Cascade differential 3-state output
|
|
.TQ(TQ), // 1-bit output: 3-state output to pad or IODELAY2
|
|
.CLK0(CLK0), // 1-bit input: I/O clock input
|
|
.CLK1(CLK1), // 1-bit input: Secondary I/O clock input
|
|
.CLKDIV(CLKDIV), // 1-bit input: Logic domain clock input
|
|
// D1 - D4: 1-bit (each) input: Parallel data inputs
|
|
.D1(D1),
|
|
.D2(D2),
|
|
.D3(D3),
|
|
.D4(D4),
|
|
.IOCE(IOCE), // 1-bit input: Data strobe input
|
|
.OCE(OCE), // 1-bit input: Clock enable input
|
|
.RST(RST), // 1-bit input: Asynchrnous reset input
|
|
.SHIFTIN1(SHIFTIN1), // 1-bit input: Cascade data input
|
|
.SHIFTIN2(SHIFTIN2), // 1-bit input: Cascade 3-state input
|
|
.SHIFTIN3(SHIFTIN3), // 1-bit input: Cascade differential data input
|
|
.SHIFTIN4(SHIFTIN4), // 1-bit input: Cascade differential 3-state input
|
|
// T1 - T4: 1-bit (each) input: 3-state control inputs
|
|
.T1(T1),
|
|
.T2(T2),
|
|
.T3(T3),
|
|
.T4(T4),
|
|
.TCE(TCE), // 1-bit input: 3-state clock enable input
|
|
.TRAIN(TRAIN) // 1-bit input: Training pattern enable input
|
|
);
|
|
|
|
// End of OSERDES2_inst instantiation
|
|
</Template>
|
|
<SubFolder label="Input" treetype="folder">
|
|
<Template label="Single-ended Buffer (IBUF)" treetype="template">
|
|
// IBUF : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUF_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUF: Single-ended Input Buffer
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUF #(
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
)IBUF_inst (
|
|
.O(O), // Buffer output
|
|
.I(I) // Buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUF_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer (IBUFDS)" treetype="template">
|
|
// IBUFDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFDS: Differential Input Buffer
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFDS #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
) IBUFDS_inst (
|
|
.O(O), // Buffer output
|
|
.I(I), // Diff_p buffer input (connect directly to top-level port)
|
|
.IB(IB) // Diff_n buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUFDS_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer with Differential Output (IBUFDS_DIFF_OUT)" treetype="template">
|
|
// IBUFDS_DIFF_OUT : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFDS_DIFF_OUT_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFDS_DIFF_OUT: Differential Input Buffer with Differential Output
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFDS_DIFF_OUT #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination, "TRUE"/"FALSE"
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
) IBUFDS_DIFF_OUT_inst (
|
|
.O(O), // Buffer diff_p output
|
|
.OB(OB), // Buffer diff_n output
|
|
.I(I), // Diff_p buffer input (connect directly to top-level port)
|
|
.IB(IB) // Diff_n buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUFDS_DIFF_OUT_inst instantiation
|
|
</Template>
|
|
<Template label="Single-ended Global Clock (IBUFG)" treetype="template">
|
|
// IBUFG : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFG_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFG: Single-ended global clock input buffer
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFG #(
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
) IBUFG_inst (
|
|
.O(O), // Clock buffer output
|
|
.I(I) // Clock buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUFG_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Global Clock (IBUFGDS)" treetype="template">
|
|
// IBUFGDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFGDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFGDS: Differential Global Clock Input Buffer
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFGDS #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
) IBUFGDS_inst (
|
|
.O(O), // Clock buffer output
|
|
.I(I), // Diff_p clock buffer input (connect directly to top-level port)
|
|
.IB(IB) // Diff_n clock buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUFGDS_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Global Clock Buffer with Differential Output (IBUFGDS_DIFF_OUT)" treetype="template">
|
|
// IBUFGDS_DIFF_OUT : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFGDS_DIFF_OUT_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFGDS_DIFF_OUT: Differential Global Clock Buffer with Differential Output
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFGDS_DIFF_OUT #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination, "TRUE"/"FALSE"
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
) IBUFGDS_DIFF_OUT_inst (
|
|
.O(O), // Buffer diff_p output
|
|
.OB(OB), // Buffer diff_n output
|
|
.I(I), // Diff_p buffer input (connect directly to top-level port)
|
|
.IB(IB) // Diff_n buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUFGDS_DIFF_OUT_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Output" treetype="folder">
|
|
<Template label="Single-ended Buffer (OBUF)" treetype="template">
|
|
// OBUF : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OBUF_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OBUF: Single-ended Output Buffer
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OBUF #(
|
|
.DRIVE(12), // Specify the output drive strength
|
|
.IOSTANDARD("DEFAULT"), // Specify the output I/O standard
|
|
.SLEW("SLOW") // Specify the output slew rate
|
|
) OBUF_inst (
|
|
.O(O), // Buffer output (connect directly to top-level port)
|
|
.I(I) // Buffer input
|
|
);
|
|
|
|
// End of OBUF_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer (OBUFDS)" treetype="template">
|
|
|
|
// OBUFDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OBUFDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OBUFDS: Differential Output Buffer
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OBUFDS #(
|
|
.IOSTANDARD("DEFAULT") // Specify the output I/O standard
|
|
) OBUFDS_inst (
|
|
.O(O), // Diff_p output (connect directly to top-level port)
|
|
.OB(OB), // Diff_n output (connect directly to top-level port)
|
|
.I(I) // Buffer input
|
|
);
|
|
|
|
// End of OBUFDS_inst instantiation
|
|
</Template>
|
|
<Template label="Single-ended 3-state Buffer (OBUFT)" treetype="template">
|
|
// OBUFT : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OBUFT_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OBUFT: Single-ended 3-state Output Buffer
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OBUFT #(
|
|
.DRIVE(12), // Specify the output drive strength
|
|
.IOSTANDARD("DEFAULT"), // Specify the output I/O standard
|
|
.SLEW("SLOW") // Specify the output slew rate
|
|
) OBUFT_inst (
|
|
.O(O), // Buffer output (connect directly to top-level port)
|
|
.I(I), // Buffer input
|
|
.T(T) // 3-state enable input
|
|
);
|
|
|
|
// End of OBUFT_inst instantiation
|
|
</Template>
|
|
<Template label="Differential 3-state Buffer (OBUFTDS)" treetype="template">
|
|
// OBUFTDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OBUFTDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OBUFTDS: Differential 3-state Output Buffer
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OBUFTDS #(
|
|
.IOSTANDARD("DEFAULT") // Specify the output I/O standard
|
|
) OBUFTDS_inst (
|
|
.O(O), // Diff_p output (connect directly to top-level port)
|
|
.OB(OB), // Diff_n output (connect directly to top-level port)
|
|
.I(I), // Buffer input
|
|
.T(T) // 3-state enable input
|
|
);
|
|
|
|
// End of OBUFTDS_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Bi-directional" treetype="folder">
|
|
<Template label="Single-ended Buffer (IOBUF)" treetype="template">
|
|
// IOBUF : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IOBUF_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IOBUF: Single-ended Bi-directional Buffer
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IOBUF #(
|
|
.DRIVE(12), // Specify the output drive strength
|
|
.IOSTANDARD("DEFAULT"), // Specify the I/O standard
|
|
.SLEW("SLOW") // Specify the output slew rate
|
|
) IOBUF_inst (
|
|
.O(O), // Buffer output
|
|
.IO(IO), // Buffer inout port (connect directly to top-level port)
|
|
.I(I), // Buffer input
|
|
.T(T) // 3-state enable input, high=input, low=output
|
|
);
|
|
|
|
// End of IOBUF_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer (IOBUFDS)" treetype="template">
|
|
// IOBUFDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IOBUFDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IOBUFDS: Differential Bi-directional Buffer
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IOBUFDS #(
|
|
.IOSTANDARD("BLVDS_25") // Specify the I/O standard
|
|
) IOBUFDS_inst (
|
|
.O(O), // Buffer output
|
|
.IO(IO), // Diff_p inout (connect directly to top-level port)
|
|
.IOB(IOB), // Diff_n inout (connect directly to top-level port)
|
|
.I(I), // Buffer input
|
|
.T(T) // 3-state enable input, high=input, low=output
|
|
);
|
|
|
|
// End of IOBUFDS_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Weak drivers" treetype="folder">
|
|
<Template label="PULLUP" treetype="template">
|
|
// PULLUP : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (PULLUP_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design.
|
|
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// PULLUP: I/O Buffer Weak Pull-up
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
PULLUP PULLUP_inst (
|
|
.O(O) // Pullup output (connect directly to top-level port)
|
|
);
|
|
|
|
// End of PULLUP_inst instantiation
|
|
</Template>
|
|
<Template label="PULLDOWN" treetype="template">
|
|
// PULLDOWN : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (PULLDOWN_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// PULLDOWN: I/O Buffer Weak Pull-down
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
PULLDOWN PULLDOWN_inst (
|
|
.O(O) // Pulldown output (connect directly to top-level port)
|
|
);
|
|
|
|
// End of PULLDOWN_inst instantiation
|
|
</Template>
|
|
<Template label="KEEPER" treetype="template">
|
|
// KEEPER : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (KEEPER_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// KEEPER: I/O Buffer Weak Keeper
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
KEEPER KEEPER_inst (
|
|
.O(O) // Keeper output (connect directly to top-level port)
|
|
);
|
|
|
|
// End of KEEPER_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="DDR Registers" treetype="folder">
|
|
<Template label="Input DDR Register (IDDR2)" treetype="template">
|
|
// IDDR2 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IDDR2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IDDR2: Input Double Data Rate Input Register with Set, Reset
|
|
// and Clock Enable.
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IDDR2 #(
|
|
.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
|
|
.INIT_Q0(1'b0), // Sets initial state of the Q0 output to 1'b0 or 1'b1
|
|
.INIT_Q1(1'b0), // Sets initial state of the Q1 output to 1'b0 or 1'b1
|
|
.SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
|
|
) IDDR2_inst (
|
|
.Q0(Q0), // 1-bit output captured with C0 clock
|
|
.Q1(Q1), // 1-bit output captured with C1 clock
|
|
.C0(C0), // 1-bit clock input
|
|
.C1(C1), // 1-bit clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.D(D), // 1-bit DDR data input
|
|
.R(R), // 1-bit reset input
|
|
.S(S) // 1-bit set input
|
|
);
|
|
|
|
// End of IDDR2_inst instantiation
|
|
</Template>
|
|
<Template label="Output DDR Register (ODDR2)" treetype="template">
|
|
// ODDR2 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ODDR2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ODDR2: Output Double Data Rate Output Register with Set, Reset
|
|
// and Clock Enable.
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ODDR2 #(
|
|
.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
|
|
.INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1
|
|
.SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
|
|
) ODDR2_inst (
|
|
.Q(Q), // 1-bit DDR output data
|
|
.C0(C0), // 1-bit clock input
|
|
.C1(C1), // 1-bit clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.D0(D0), // 1-bit data input (associated with C0)
|
|
.D1(D1), // 1-bit data input (associated with C1)
|
|
.R(R), // 1-bit reset input
|
|
.S(S) // 1-bit set input
|
|
);
|
|
|
|
// End of ODDR2_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="RAM/ROM" treetype="folder">
|
|
<Template label="16k-bit Data and 2k-bit Parity Configurable Synchronous Dual Port Block RAM with Optional Output Registers (RAMB16BWER)" treetype="template">
|
|
// RAMB16BWER : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16BWER_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16BWER: 16k-bit Data and 2k-bit Parity Configurable Synchronous Dual Port Block RAM with Optional Output Registers
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16BWER #(
|
|
// DATA_WIDTH_A/DATA_WIDTH_B: 0, 1, 2, 4, 9, 18, or 36
|
|
.DATA_WIDTH_A(0),
|
|
.DATA_WIDTH_B(0),
|
|
// DOA_REG/DOB_REG: Optional output register (0 or 1)
|
|
.DOA_REG(0),
|
|
.DOB_REG(0),
|
|
// EN_RSTRAM_A/EN_RSTRAM_B: Enable/disable RST
|
|
.EN_RSTRAM_A("TRUE"),
|
|
.EN_RSTRAM_B("TRUE"),
|
|
// INITP_00 to INITP_07: Initial memory contents.
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// INIT_00 to INIT_3F: Initial memory contents.
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// INIT_A/INIT_B: Initial values on output port
|
|
.INIT_A(36'h000000000),
|
|
.INIT_B(36'h000000000),
|
|
// INIT_FILE: Optional file used to specify initial RAM contents
|
|
.INIT_FILE("NONE"),
|
|
// RSTTYPE: "SYNC" or "ASYNC"
|
|
.RSTTYPE("SYNC"),
|
|
// RST_PRIORITY_A/RST_PRIORITY_B: "CE" or "SR"
|
|
.RST_PRIORITY_A("CE"),
|
|
.RST_PRIORITY_B("CE"),
|
|
// SIM_COLLISION_CHECK: Collision check enable "ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE"
|
|
.SIM_COLLISION_CHECK("ALL"),
|
|
// SIM_DEVICE: Must be set to "SPARTAN6" for proper simulation behavior
|
|
.SIM_DEVICE("SPARTAN3ADSP"),
|
|
// SRVAL_A/SRVAL_B: Set/Reset value for RAM output
|
|
.SRVAL_A(36'h000000000),
|
|
.SRVAL_B(36'h000000000),
|
|
// WRITE_MODE_A/WRITE_MODE_B: "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
|
|
.WRITE_MODE_A("WRITE_FIRST"),
|
|
.WRITE_MODE_B("WRITE_FIRST")
|
|
)
|
|
RAMB16BWER_inst (
|
|
// Port A Data: 32-bit (each) output: Port A data
|
|
.DOA(DOA), // 32-bit output: A port data output
|
|
.DOPA(DOPA), // 4-bit output: A port parity output
|
|
// Port B Data: 32-bit (each) output: Port B data
|
|
.DOB(DOB), // 32-bit output: B port data output
|
|
.DOPB(DOPB), // 4-bit output: B port parity output
|
|
// Port A Address/Control Signals: 14-bit (each) input: Port A address and control signals
|
|
.ADDRA(ADDRA), // 14-bit input: A port address input
|
|
.CLKA(CLKA), // 1-bit input: A port clock input
|
|
.ENA(ENA), // 1-bit input: A port enable input
|
|
.REGCEA(REGCEA), // 1-bit input: A port register clock enable input
|
|
.RSTA(RSTA), // 1-bit input: A port register set/reset input
|
|
.WEA(WEA), // 4-bit input: Port A byte-wide write enable input
|
|
// Port A Data: 32-bit (each) input: Port A data
|
|
.DIA(DIA), // 32-bit input: A port data input
|
|
.DIPA(DIPA), // 4-bit input: A port parity input
|
|
// Port B Address/Control Signals: 14-bit (each) input: Port B address and control signals
|
|
.ADDRB(ADDRB), // 14-bit input: B port address input
|
|
.CLKB(CLKB), // 1-bit input: B port clock input
|
|
.ENB(ENB), // 1-bit input: B port enable input
|
|
.REGCEB(REGCEB), // 1-bit input: B port register clock enable input
|
|
.RSTB(RSTB), // 1-bit input: B port register set/reset input
|
|
.WEB(WEB), // 4-bit input: Port B byte-wide write enable input
|
|
// Port B Data: 32-bit (each) input: Port B data
|
|
.DIB(DIB), // 32-bit input: B port data input
|
|
.DIPB(DIPB) // 4-bit input: B port parity input
|
|
);
|
|
|
|
// End of RAMB16BWER_inst instantiation
|
|
</Template>
|
|
<Template label="8k-bit Data and 1k-bit Parity Configurable Synchronous Block RAM (RAMB8BWER)" treetype="template">
|
|
// RAMB8BWER : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB8BWER_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB8BWER: 8k-bit Data and 1k-bit Parity Configurable Synchronous Block RAM
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB8BWER #(
|
|
// DATA_WIDTH_A/DATA_WIDTH_B: 'If RAM_MODE="TDP": 0, 1, 2, 4, 9 or 18; If RAM_MODE="SDP": 36'
|
|
.DATA_WIDTH_A(0),
|
|
.DATA_WIDTH_B(0),
|
|
// DOA_REG/DOB_REG: Optional output register (0 or 1)
|
|
.DOA_REG(0),
|
|
.DOB_REG(0),
|
|
// EN_RSTRAM_A/EN_RSTRAM_B: Enable/disable RST
|
|
.EN_RSTRAM_A("TRUE"),
|
|
.EN_RSTRAM_B("TRUE"),
|
|
// INITP_00 to INITP_03: Initial memory contents.
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// INIT_00 to INIT_1F: Initial memory contents.
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// INIT_A/INIT_B: Initial values on output port
|
|
.INIT_A(18'h00000),
|
|
.INIT_B(18'h00000),
|
|
// INIT_FILE: Not Supported
|
|
.INIT_FILE("NONE"), // Do not modify
|
|
// RAM_MODE: "SDP" or "TDP"
|
|
.RAM_MODE("TDP"),
|
|
// RSTTYPE: "SYNC" or "ASYNC"
|
|
.RSTTYPE("SYNC"),
|
|
// RST_PRIORITY_A/RST_PRIORITY_B: "CE" or "SR"
|
|
.RST_PRIORITY_A("CE"),
|
|
.RST_PRIORITY_B("CE"),
|
|
// SIM_COLLISION_CHECK: Collision check enable "ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE"
|
|
.SIM_COLLISION_CHECK("ALL"),
|
|
// SRVAL_A/SRVAL_B: Set/Reset value for RAM output
|
|
.SRVAL_A(18'h00000),
|
|
.SRVAL_B(18'h00000),
|
|
// WRITE_MODE_A/WRITE_MODE_B: "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
|
|
.WRITE_MODE_A("WRITE_FIRST"),
|
|
.WRITE_MODE_B("WRITE_FIRST")
|
|
)
|
|
RAMB8BWER_inst (
|
|
// Port A Data: 16-bit (each) output: Port A data
|
|
.DOADO(DOADO), // 16-bit output: A port data/LSB data output
|
|
.DOPADOP(DOPADOP), // 2-bit output: A port parity/LSB parity output
|
|
// Port B Data: 16-bit (each) output: Port B data
|
|
.DOBDO(DOBDO), // 16-bit output: B port data/MSB data output
|
|
.DOPBDOP(DOPBDOP), // 2-bit output: B port parity/MSB parity output
|
|
// Port A Address/Control Signals: 13-bit (each) input: Port A address and control signals (write port
|
|
// when RAM_MODE="SDP")
|
|
.ADDRAWRADDR(ADDRAWRADDR), // 13-bit input: A port address/Write address input
|
|
.CLKAWRCLK(CLKAWRCLK), // 1-bit input: A port clock/Write clock input
|
|
.ENAWREN(ENAWREN), // 1-bit input: A port enable/Write enable input
|
|
.REGCEA(REGCEA), // 1-bit input: A port register enable input
|
|
.RSTA(RSTA), // 1-bit input: A port set/reset input
|
|
.WEAWEL(WEAWEL), // 2-bit input: A port write enable input
|
|
// Port A Data: 16-bit (each) input: Port A data
|
|
.DIADI(DIADI), // 16-bit input: A port data/LSB data input
|
|
.DIPADIP(DIPADIP), // 2-bit input: A port parity/LSB parity input
|
|
// Port B Address/Control Signals: 13-bit (each) input: Port B address and control signals (read port
|
|
// when RAM_MODE="SDP")
|
|
.ADDRBRDADDR(ADDRBRDADDR), // 13-bit input: B port address/Read address input
|
|
.CLKBRDCLK(CLKBRDCLK), // 1-bit input: B port clock/Read clock input
|
|
.ENBRDEN(ENBRDEN), // 1-bit input: B port enable/Read enable input
|
|
.REGCEBREGCE(REGCEBREGCE), // 1-bit input: B port register enable/Register enable input
|
|
.RSTBRST(RSTBRST), // 1-bit input: B port set/reset input
|
|
.WEBWEU(WEBWEU), // 2-bit input: B port write enable input
|
|
// Port B Data: 16-bit (each) input: Port B data
|
|
.DIBDI(DIBDI), // 16-bit input: B port data/MSB data input
|
|
.DIPBDIP(DIPBDIP) // 2-bit input: B port parity/MSB parity input
|
|
);
|
|
|
|
// End of RAMB8BWER_inst instantiation
|
|
</Template>
|
|
<SubFolder label="Distributed ROM" treetype="folder">
|
|
<Template label="32 X 1 (ROM32X1)" treetype="template">
|
|
// ROM32X1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ROM32X1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ROM32X1: 32 x 1 Asynchronous Distributed (LUT) ROM
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ROM32X1 #(
|
|
.INIT(32'h00000000) // Contents of ROM
|
|
) ROM32X1_inst (
|
|
.O(O), // ROM output
|
|
.A0(A0), // ROM address[0]
|
|
.A1(A1), // ROM address[1]
|
|
.A2(A2), // ROM address[2]
|
|
.A3(A3), // ROM address[3]
|
|
.A4(A4) // ROM address[4]
|
|
);
|
|
|
|
// End of ROM32X1_inst instantiation
|
|
</Template>
|
|
<Template label="64 X 1 (ROM64X1)" treetype="template">
|
|
// ROM64X1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ROM64X1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ROM64X1: 64 x 1 Asynchronous Distributed (LUT) ROM
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ROM64X1 #(
|
|
.INIT(64'h0000000000000000) // Contents of ROM
|
|
) ROM64X1_inst (
|
|
.O(O), // ROM output
|
|
.A0(A0), // ROM address[0]
|
|
.A1(A1), // ROM address[1]
|
|
.A2(A2), // ROM address[2]
|
|
.A3(A3), // ROM address[3]
|
|
.A4(A4), // ROM address[4]
|
|
.A5(A5) // ROM address[5]
|
|
);
|
|
|
|
// End of ROM64X1_inst instantiation
|
|
</Template>
|
|
<Template label="128 X 1 (ROM128X1)" treetype="template">
|
|
// ROM128X1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ROM128X1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ROM128X1: 128 x 1 Asynchronous Distributed (LUT) ROM
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ROM128X1 #(
|
|
.INIT(128'h00000000000000000000000000000000) // Contents of ROM
|
|
) ROM128X1_inst (
|
|
.O(O), // ROM output
|
|
.A0(A0), // ROM address[0]
|
|
.A1(A1), // ROM address[1]
|
|
.A2(A2), // ROM address[2]
|
|
.A3(A3), // ROM address[3]
|
|
.A4(A4), // ROM address[4]
|
|
.A5(A5), // ROM address[5]
|
|
.A6(A6) // ROM address[6]
|
|
);
|
|
|
|
// End of ROM128X1_inst instantiation
|
|
</Template>
|
|
<Template label="256 X 1 (ROM256X1)" treetype="template">
|
|
// ROM256X1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ROM256X1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ROM256X1: 256 x 1 Asynchronous Distributed (LUT) ROM
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ROM256X1 #(
|
|
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000) // Contents of ROM
|
|
) ROM256X1_inst (
|
|
.O(O), // ROM output
|
|
.A0(A0), // ROM address[0]
|
|
.A1(A1), // ROM address[1]
|
|
.A2(A2), // ROM address[2]
|
|
.A3(A3), // ROM address[3]
|
|
.A4(A4), // ROM address[4]
|
|
.A5(A5), // ROM address[5]
|
|
.A6(A6), // ROM address[6]
|
|
.A7(A7) // ROM address[7]
|
|
);
|
|
|
|
// End of ROM256X1_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Distributed RAM" treetype="folder">
|
|
<SubFolder label="Single-Port" treetype="folder">
|
|
<SubFolder label="32 Deep (5-bit address)" treetype="folder">
|
|
<Template label="32 x 1 posedge write (RAM32X1S)" treetype="template">
|
|
// RAM32X1S : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM32X1S_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM32X1S: 32 x 1 posedge write distributed (LUT) RAM
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM32X1S #(
|
|
.INIT(32'h00000000) // Initial contents of RAM
|
|
) RAM32X1S_inst (
|
|
.O(O), // RAM output
|
|
.A0(A0), // RAM address[0] input
|
|
.A1(A1), // RAM address[1] input
|
|
.A2(A2), // RAM address[2] input
|
|
.A3(A3), // RAM address[3] input
|
|
.A4(A4), // RAM address[4] input
|
|
.D(D), // RAM data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM32X1S_inst instantiation
|
|
</Template>
|
|
<Template label="32 x 1 negedge write (RAM32X1S_1)" treetype="template">
|
|
// RAM32X1S_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM32X1S_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM32X1S_1: 32 x 1 negedge write distributed (LUT) RAM
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM32X1S_1 #(
|
|
.INIT(32'h00000000) // Initial contents of RAM
|
|
)RAM32X1S_1_inst (
|
|
.O(O), // RAM output
|
|
.A0(A0), // RAM address[0] input
|
|
.A1(A1), // RAM address[1] input
|
|
.A2(A2), // RAM address[2] input
|
|
.A3(A3), // RAM address[3] input
|
|
.A4(A4), // RAM address[4] input
|
|
.D(D), // RAM data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM32X1S_1_inst instantiation
|
|
</Template>
|
|
<Template label="32 x 2 posedge write (RAM32X2S)" treetype="template">
|
|
// RAM32X2S : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM16X2S_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM32X2S: 32 x 2 posedge write distributed (LUT) RAM
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM32X2S #(
|
|
.INIT_00(32'h00000000), // INIT for bit 0 of RAM
|
|
.INIT_01(32'h00000000) // INIT for bit 1 of RAM
|
|
) RAM32X2S_inst (
|
|
.O0(O0), // RAM data[0] output
|
|
.O1(O1), // RAM data[1] output
|
|
.A0(A0), // RAM address[0] input
|
|
.A1(A1), // RAM address[1] input
|
|
.A2(A2), // RAM address[2] input
|
|
.A3(A3), // RAM address[3] input
|
|
.A4(A4), // RAM address[4] input
|
|
.D0(D0), // RAM data[0] input
|
|
.D1(D1), // RAM data[1] input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM32X2S_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="64 Deep (6-bit address)" treetype="folder">
|
|
<Template label="64 X 1 posedge write (RAM64X1S)" treetype="template">
|
|
// RAM64X1S : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM64X1S_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM64X1S: 64 x 1 positive edge write, asynchronous read single-port distributed RAM
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM64X1S #(
|
|
.INIT(64'h0000000000000000) // Initial contents of RAM
|
|
) RAM64X1S_inst (
|
|
.O(O), // 1-bit data output
|
|
.A0(A0), // Address[0] input bit
|
|
.A1(A1), // Address[1] input bit
|
|
.A2(A2), // Address[2] input bit
|
|
.A3(A3), // Address[3] input bit
|
|
.A4(A4), // Address[4] input bit
|
|
.A5(A5), // Address[5] input bit
|
|
.D(D), // 1-bit data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM64X1S_inst instantiation
|
|
</Template>
|
|
<Template label="64 X 1 negedge write (RAM64X1S_1)" treetype="template">
|
|
// RAM64X1S_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM64X1S_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM64X1S_1: 64 x 1 negative edge write, asynchronous read single-port distributed RAM
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM64X1S_1 #(
|
|
.INIT(64'h0000000000000000) // Initial contents of RAM
|
|
) RAM64X1S_1_inst (
|
|
.O(O), // 1-bit data output
|
|
.A0(A0), // Address[0] input bit
|
|
.A1(A1), // Address[1] input bit
|
|
.A2(A2), // Address[2] input bit
|
|
.A3(A3), // Address[3] input bit
|
|
.A4(A4), // Address[4] input bit
|
|
.A5(A5), // Address[5] input bit
|
|
.D(D), // 1-bit data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM64X1S_1_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="128 Deep (7-bit address)" treetype="folder">
|
|
<Template label="128 X 1 posedge write (RAM128X1S)" treetype="template">
|
|
// RAM128X1S : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM128X1S_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM128X1S: 128 x 1 positive edge write, asynchronous read single-port distributed RAM
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM128X1S #(
|
|
.INIT(128'h00000000000000000000000000000000) // Initial contents of RAM
|
|
) RAM128X1S_inst (
|
|
.O(O), // 1-bit data output
|
|
.A0(A0), // Address[0] input bit
|
|
.A1(A1), // Address[1] input bit
|
|
.A2(A2), // Address[2] input bit
|
|
.A3(A3), // Address[3] input bit
|
|
.A4(A4), // Address[4] input bit
|
|
.A5(A5), // Address[5] input bit
|
|
.A6(A6), // Address[6] input bit
|
|
.D(D), // 1-bit data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM128X1S_inst instantiation
|
|
</Template>
|
|
<Template label="128 X 1 negedge write (RAM128X1S_1)" treetype="template">
|
|
// RAM128X1S_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM128X1S_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM128X1S_1: 128 x 1 negative edge write, asynchronous read single-port distributed RAM
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM128X1S_1 #(
|
|
.INIT(128'h00000000000000000000000000000000) // Initial contents of RAM
|
|
) RAM128X1S_1_inst (
|
|
.O(O), // 1-bit data output
|
|
.A0(A0), // Address[0] input bit
|
|
.A1(A1), // Address[1] input bit
|
|
.A2(A2), // Address[2] input bit
|
|
.A3(A3), // Address[3] input bit
|
|
.A4(A4), // Address[4] input bit
|
|
.A5(A5), // Address[5] input bit
|
|
.A6(A6), // Address[6] input bit
|
|
.D(D), // 1-bit data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM128X1S_1_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="256 Deep (8-bit address)" treetype="folder">
|
|
<Template label="256 X 1 posedge write (RAM256X1S)" treetype="template">
|
|
// RAM256X1S : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM256X1S_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM256X1S: 256-deep by 1-wide positive edge write, asynchronous read
|
|
// single-port distributed LUT RAM
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM256X1S #(
|
|
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAM256X1S_inst (
|
|
.O(O), // Read/write port 1-bit output
|
|
.A(A), // Read/write port 8-bit address input
|
|
.WE(WE), // Write enable input
|
|
.WCLK(WCLK), // Write clock input
|
|
.D(D) // RAM data input
|
|
);
|
|
|
|
// End of RAM256X1S_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Dual-Port" treetype="folder">
|
|
<Template label="32 X 1 posedge write (RAM32X1D)" treetype="template">
|
|
// RAM32X1D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM32X1D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM32X1D: 32 x 1 positive edge write, asynchronous read dual-port distributed RAM
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM32X1D #(
|
|
.INIT(32'h00000000) // Initial contents of RAM
|
|
) RAM32X1D_inst (
|
|
.DPO(DPO), // Read-only 1-bit data output
|
|
.SPO(SPO), // Rw/ 1-bit data output
|
|
.A0(A0), // Rw/ address[0] input bit
|
|
.A1(A1), // Rw/ address[1] input bit
|
|
.A2(A2), // Rw/ address[2] input bit
|
|
.A3(A3), // Rw/ address[3] input bit
|
|
.A4(A4), // Rw/ address[4] input bit
|
|
.D(D), // Write 1-bit data input
|
|
.DPRA0(DPRA0), // Read-only address[0] input bit
|
|
.DPRA1(DPRA1), // Read-only address[1] input bit
|
|
.DPRA2(DPRA2), // Read-only address[2] input bit
|
|
.DPRA3(DPRA3), // Read-only address[3] input bit
|
|
.DPRA4(DPRA4), // Read-only address[4] input bit
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM32X1D_inst instantiation
|
|
</Template>
|
|
<Template label="32 X 1 negedge write (RAM32X1D_1)" treetype="template">
|
|
// RAM32X1D_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM32X1D_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM32X1D_1: 32 x 1 negative edge write, asynchronous read dual-port distributed RAM
|
|
// Virtex-5/6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM32X1D_1 #(
|
|
.INIT(32'h00000000) // Initial contents of RAM
|
|
) RAM32X1D_1_inst (
|
|
.DPO(DPO), // Read-only 1-bit data output
|
|
.SPO(SPO), // Rw/ 1-bit data output
|
|
.A0(A0), // Rw/ address[0] input bit
|
|
.A1(A1), // Rw/ address[1] input bit
|
|
.A2(A2), // Rw/ address[2] input bit
|
|
.A3(A3), // Rw/ address[3] input bit
|
|
.A4(A4), // Rw/ address[4] input bit
|
|
.D(D), // Write 1-bit data input
|
|
.DPRA0(DPRA0), // Read-only address[0] input bit
|
|
.DPRA1(DPRA1), // Read-only address[1] input bit
|
|
.DPRA2(DPRA2), // Read-only address[2] input bit
|
|
.DPRA3(DPRA3), // Read-only address[3] input bit
|
|
.DPRA4(DPRA4), // Read-only address[4] input bit
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM32X1D_1_inst instantiation
|
|
</Template>
|
|
<Template label="64 X 1 posedge write (RAM64X1D)" treetype="template">
|
|
// RAM64X1D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM64X1D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM64X1D: 64 x 1 positive edge write, asynchronous read dual-port distributed RAM
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM64X1D #(
|
|
.INIT(64'h0000000000000000) // Initial contents of RAM
|
|
) RAM64X1D_inst (
|
|
.DPO(DPO), // Read-only 1-bit data output
|
|
.SPO(SPO), // Rw/ 1-bit data output
|
|
.A0(A0), // Rw/ address[0] input bit
|
|
.A1(A1), // Rw/ address[1] input bit
|
|
.A2(A2), // Rw/ address[2] input bit
|
|
.A3(A3), // Rw/ address[3] input bit
|
|
.A4(A4), // Rw/ address[4] input bit
|
|
.A5(A5), // Rw/ address[5] input bit
|
|
.D(D), // Write 1-bit data input
|
|
.DPRA0(DPRA0), // Read-only address[0] input bit
|
|
.DPRA1(DPRA1), // Read-only address[1] input bit
|
|
.DPRA2(DPRA2), // Read-only address[2] input bit
|
|
.DPRA3(DPRA3), // Read-only address[3] input bit
|
|
.DPRA4(DPRA4), // Read-only address[4] input bit
|
|
.DPRA5(DPRA5), // Read-only address[5] input bit
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM64X1D_inst instantiation
|
|
|
|
</Template>
|
|
<Template label="128 X 1 posedge write (RAM128X1D)" treetype="template">
|
|
// RAM128X1D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM128X1D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM128X1D: 128-deep by 1-wide positive edge write, asynchronous read
|
|
// dual-port distributed LUT RAM
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM128X1D #(
|
|
.INIT(128'h00000000000000000000000000000000)
|
|
) RAM128X1D_inst (
|
|
.DPO(DPO), // Read port 1-bit output
|
|
.SPO(SPO), // Read/write port 1-bit output
|
|
.A(A), // Read/write port 7-bit address input
|
|
.D(D), // RAM data input
|
|
.DPRA(DPRA), // Read port 7-bit address input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM128X1D_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Multi-Port" treetype="folder">
|
|
<Template label="32 X 8 (RAM32M)" treetype="template">
|
|
// RAM32M : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM32M_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM32M: 32-deep by 8-wide Multi Port LUT RAM
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM32M #(
|
|
.INIT_A(64'h0000000000000000), // Initial contents of A Port
|
|
.INIT_B(64'h0000000000000000), // Initial contents of B Port
|
|
.INIT_C(64'h0000000000000000), // Initial contents of C Port
|
|
.INIT_D(64'h0000000000000000) // Initial contents of D Port
|
|
) RAM32M_inst (
|
|
.DOA(DOA), // Read port A 2-bit output
|
|
.DOB(DOB), // Read port B 2-bit output
|
|
.DOC(DOC), // Read port C 2-bit output
|
|
.DOD(DOD), // Read/write port D 2-bit output
|
|
.ADDRA(ADDRA), // Read port A 5-bit address input
|
|
.ADDRB(ADDRB), // Read port B 5-bit address input
|
|
.ADDRC(ADDRC), // Read port C 5-bit address input
|
|
.ADDRD(ADDRD), // Read/write port D 5-bit address input
|
|
.DIA(DIA), // RAM 2-bit data write input addressed by ADDRD,
|
|
// read addressed by ADDRA
|
|
.DIB(DIB), // RAM 2-bit data write input addressed by ADDRD,
|
|
// read addressed by ADDRB
|
|
.DIC(DIC), // RAM 2-bit data write input addressed by ADDRD,
|
|
// read addressed by ADDRC
|
|
.DID(DID), // RAM 2-bit data write input addressed by ADDRD,
|
|
// read addressed by ADDRD
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM32M_inst instantiation
|
|
</Template>
|
|
<Template label="64 X 4 (RAM64M)" treetype="template">
|
|
// RAM64M : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM64M_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM64M: 64-deep by 4-wide Multi Port LUT RAM
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM64M #(
|
|
.INIT_A(64'h0000000000000000), // Initial contents of A Port
|
|
.INIT_B(64'h0000000000000000), // Initial contents of B Port
|
|
.INIT_C(64'h0000000000000000), // Initial contents of C Port
|
|
.INIT_D(64'h0000000000000000) // Initial contents of D Port
|
|
) RAM64M_inst (
|
|
.DOA(DOA), // Read port A 1-bit output
|
|
.DOB(DOB), // Read port B 1-bit output
|
|
.DOC(DOC), // Read port C 1-bit output
|
|
.DOD(DOD), // Read/write port D 1-bit output
|
|
.DIA(DIA), // RAM 1-bit data write input addressed by ADDRD,
|
|
// read addressed by ADDRA
|
|
.DIB(DIB), // RAM 1-bit data write input addressed by ADDRD,
|
|
// read addressed by ADDRB
|
|
.DIC(DIC), // RAM 1-bit data write input addressed by ADDRD,
|
|
// read addressed by ADDRC
|
|
.DID(DID), // RAM 1-bit data write input addressed by ADDRD,
|
|
// read addressed by ADDRD
|
|
.ADDRA(ADDRA), // Read port A 6-bit address input
|
|
.ADDRB(ADDRB), // Read port B 6-bit address input
|
|
.ADDRC(ADDRC), // Read port C 6-bit address input
|
|
.ADDRD(ADDRD), // Read/write port D 6-bit address input
|
|
.WE(WE), // Write enable input
|
|
.WCLK(WCLK) // Write clock input
|
|
);
|
|
|
|
// End of RAM64M_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Slice/CLB Primitives" treetype="folder">
|
|
<SubFolder label="MUXFx" treetype="folder">
|
|
<Template label="MUXF7" treetype="template">
|
|
// MUXF7 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF7_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF7: CLB MUX to tie two LUT6's together with general output
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF7 MUXF7_inst (
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie to LUT6 O6 pin)
|
|
.I1(I1), // Input (tie to LUT6 O6 pin)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF7_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF7_L" treetype="template">
|
|
// MUXF7_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF7_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF7_L: CLB MUX to tie two LUT6's together with local output
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF7_L MUXF7_L_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.I0(I0), // Input (tie to LUT6 O6 pin)
|
|
.I1(I1), // Input (tie to LUT6 O6 pin)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF7_L_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF7_D" treetype="template">
|
|
// MUXF7_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF7_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF7_D: CLB MUX to tie two LUT6's together with general and local outputs
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF7_D MUXF7_D_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie to LUT6 O6 pin)
|
|
.I1(I1), // Input (tie to LUT6 O6 pin)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF7_D_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF8" treetype="template">
|
|
// MUXF8 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF8_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF8: CLB MUX to tie two MUXF7's together with general output
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF8 MUXF8_inst (
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie to MUXF7 LO out)
|
|
.I1(I1), // Input (tie to MUXF7 LO out)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF8_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF8_L" treetype="template">
|
|
// MUXF8_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF8_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF8_L: CLB MUX to tie two MUXF7's together with local output
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF8_L MUXF8_L_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.I0(I0), // Input (tie to MUXF7 LO out)
|
|
.I1(I1), // Input (tie to MUXF7 LO out)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF8_L_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF8_D" treetype="template">
|
|
// MUXF8_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF8_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF8_D: CLB MUX to tie two MUXF7's together with general and local outputs
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF8_D MUXF8_D_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie to MUXF7 LO out)
|
|
.I1(I1), // Input (tie to MUXF7 LO out)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF8_D_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="LUTs" treetype="folder">
|
|
<SubFolder label="Info" treetype="folder">
|
|
<Template label="Info (LUT INIT)" treetype="template">
|
|
// The INIT parameter for the FPGA LUT primitive is what gives the LUT its
|
|
// logical value. By default this value is zero thus driving the output to a
|
|
// zero regardless of the input values (acting as a ground) however in most
|
|
// cases an new INIT value must be determined in order to specify the logic
|
|
// function for the LUT primitive. There are a few methods in which the LUT
|
|
// value can be determined and two of those methods will be discussed here.
|
|
//
|
|
// The Truth Table Method
|
|
// ----------------------
|
|
//
|
|
// A common method to determine the desired INIT value for a LUT is using a
|
|
// truth table. To do so, simply create a binary truth table of all possible
|
|
// inputs, specify the desired logic value of the output and then create the
|
|
// INIT string from those output values. An example is shown below:
|
|
//
|
|
// Example of determining an XOR INIT equation for a LUT4:
|
|
//
|
|
// _________________
|
|
// | I3 I2 I1 I0 | O |
|
|
// |-----------------|
|
|
// | 0 0 0 0 | 0 |\
|
|
// | 0 0 0 1 | 1 | \ = 4'b0110 = 4'h6 ---------------+
|
|
// | 0 0 1 0 | 1 | / |
|
|
// | 0 0 1 1 | 0 |/ |
|
|
// |-------------|---| |
|
|
// | 0 1 0 0 | 1 |\ |
|
|
// | 0 1 0 1 | 0 | \ = 4'b1001 = 4'h9 |
|
|
// | 0 1 1 0 | 0 | / |
|
|
// | 0 1 1 1 | 1 |/ |
|
|
// |-------------|---| INIT = 16'h6996
|
|
// | 1 0 0 0 | 1 |\ |
|
|
// | 1 0 0 1 | 0 | \ = 4'b0110 = 4'h9 |
|
|
// | 1 0 1 0 | 0 | / |
|
|
// | 1 0 1 1 | 1 |/ |
|
|
// |-------------|---| |
|
|
// | 1 1 0 0 | 0 |\ |
|
|
// | 1 1 0 1 | 1 | \ = 4'b1001 = 4'h6 ------------+
|
|
// | 1 1 1 0 | 1 | /
|
|
// | 1 1 1 1 | 0 |/
|
|
// -------------------
|
|
//
|
|
// Example of determining a 3-input AND gate:
|
|
//
|
|
// ______________
|
|
// | I2 I1 I0 | O |
|
|
// |--------------|
|
|
// | 0 0 0 | 0 |\
|
|
// | 0 0 1 | 0 | \ = 4'b0000 = 4'h0 --------------+
|
|
// | 0 1 0 | 0 | / |
|
|
// | 0 1 1 | 0 |/ |
|
|
// |----------|---| INIT = 8'h80
|
|
// | 1 0 0 | 0 |\ |
|
|
// | 1 0 1 | 0 | \ = 4'b1000 = 4'h8 -------------+
|
|
// | 1 1 0 | 0 | /
|
|
// | 1 1 1 | 1 |/
|
|
// ----------------
|
|
//
|
|
// The Equation Method
|
|
// -------------------
|
|
//
|
|
// Another method to determine the LUT value is to define parameters for each
|
|
// input to the LUT that correspond to their listed truth value and use those to
|
|
// build the logic equation you are after. This method is easier to understand
|
|
// once you have grasped the concept and more self-documenting that the above
|
|
// method however does require the code to first specify the appropriate
|
|
// parameters. See the example below.
|
|
//
|
|
// Example of specifying the equation (A and B) or (C and D) for a LUT4:
|
|
//
|
|
// The forllowing parameters are defined to allow for
|
|
// equation-based INIT specification.
|
|
parameter I0 = 16'haaaa;
|
|
parameter I1 = 16'hcccc;
|
|
parameter I2 = 16'hf0f0;
|
|
parameter I3 = 16'hff00;
|
|
|
|
// LUT4: 4-input Look-Up Table with general output
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT4 #(
|
|
.INIT((I0&I1)|(I2&I3)) // Specify LUT Contents
|
|
) LUT4_inst (
|
|
.O(O_LUT), // LUT general output
|
|
.I0(A), // LUT input
|
|
.I1(B), // LUT input
|
|
.I2(C), // LUT input
|
|
.I3(D) // LUT input
|
|
);
|
|
|
|
// End of LUT4_inst instantiation
|
|
|
|
// With the parameters specifying all possible cases for the truth table, a
|
|
// Verilog equation can be written to determine the end INIT value.
|
|
</Template>
|
|
<SubFolder label="INIT Parameters" treetype="folder">
|
|
<Template label="LUT1" treetype="template">
|
|
// The forllowing parameter is defined to allow for
|
|
// equation-based INIT specification for a LUT1.
|
|
parameter I0 = 2'b10;
|
|
</Template>
|
|
<Template label="LUT2" treetype="template">
|
|
// The forllowing parameters are defined to allow for
|
|
// equation-based INIT specification for a LUT2.
|
|
parameter I0 = 4'ha;
|
|
parameter I1 = 4'hc;
|
|
</Template>
|
|
<Template label="LUT3" treetype="template">
|
|
// The forllowing parameters are defined to allow for
|
|
// equation-based INIT specification for a LUT3.
|
|
parameter I0 = 8'haa;
|
|
parameter I1 = 8'hcc;
|
|
parameter I2 = 8'hf0;
|
|
</Template>
|
|
<Template label="LUT4" treetype="template">
|
|
// The forllowing parameters are defined to allow for
|
|
// equation-based INIT specification for a LUT4.
|
|
parameter I0 = 16'haaaa;
|
|
parameter I1 = 16'hcccc;
|
|
parameter I2 = 16'hf0f0;
|
|
parameter I3 = 16'hff00;
|
|
</Template>
|
|
<Template label="LUT5" treetype="template">
|
|
// The forllowing parameters are defined to allow for
|
|
// equation-based INIT specification for a LUT5.
|
|
parameter I0 = 32'haaaaaaaa;
|
|
parameter I1 = 32'hcccccccc;
|
|
parameter I2 = 32'hf0f0f0f0;
|
|
parameter I3 = 32'hff00ff00;
|
|
parameter I4 = 32'hffff0000;
|
|
</Template>
|
|
<Template label="LUT6" treetype="template">
|
|
// The forllowing parameters are defined to allow for
|
|
// equation-based INIT specification for a LUT6.
|
|
parameter I0 = 64'haaaaaaaaaaaaaaaa;
|
|
parameter I1 = 64'hcccccccccccccccc;
|
|
parameter I2 = 64'hf0f0f0f0f0f0f0f0;
|
|
parameter I3 = 64'hff00ff00ff00ff00;
|
|
parameter I4 = 64'hffff0000ffff0000;
|
|
parameter I5 = 64'hffffffff00000000;
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="INIT Truth Tables" treetype="folder">
|
|
<Template label="LUT1" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT1
|
|
// ________
|
|
// | I0 | O |
|
|
// |--------|
|
|
// | 0 | ? |\
|
|
// | 1 | ? |/ = 2'b??
|
|
// ----------
|
|
</Template>
|
|
<Template label="LUT2" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT2
|
|
// ______________
|
|
// | I2 I1 I0 | O |
|
|
// |--------------|
|
|
// | 0 0 0 | ? |\
|
|
// | 0 0 1 | ? | \ = INIT = 4'b???? = 4'h?
|
|
// | 0 1 0 | ? | /
|
|
// | 0 1 1 | ? |/
|
|
// ---------- ---
|
|
</Template>
|
|
<Template label="LUT3" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT3
|
|
// ______________
|
|
// | I2 I1 I0 | O |
|
|
// |--------------|
|
|
// | 0 0 0 | ? |\
|
|
// | 0 0 1 | ? | \ = 4'b???? = 4'h? --------------+
|
|
// | 0 1 0 | ? | / |
|
|
// | 0 1 1 | ? |/ |
|
|
// |----------|---| INIT = 8'h??
|
|
// | 1 0 0 | ? |\ |
|
|
// | 1 0 1 | ? | \ = 4'b???? = 4'h? -------------+
|
|
// | 1 1 0 | ? | /
|
|
// | 1 1 1 | ? |/
|
|
// ----------------
|
|
</Template>
|
|
<Template label="LUT4" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT4
|
|
// _________________
|
|
// | I3 I2 I1 I0 | O |
|
|
// |-----------------|
|
|
// | 0 0 0 0 | ? |\
|
|
// | 0 0 0 1 | ? | \ = 4'b???? = 4'h? ---------------+
|
|
// | 0 0 1 0 | ? | / |
|
|
// | 0 0 1 1 | ? |/ |
|
|
// |-------------|---| |
|
|
// | 0 1 0 0 | ? |\ |
|
|
// | 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 1 0 | ? | / |
|
|
// | 0 1 1 1 | ? |/ |
|
|
// |-------------|---| INIT = 16'h????
|
|
// | 1 0 0 0 | ? |\ |
|
|
// | 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 1 0 | ? | / |
|
|
// | 1 0 1 1 | ? |/ |
|
|
// |-------------|---| |
|
|
// | 1 1 0 0 | ? |\ |
|
|
// | 1 1 0 1 | ? | \ = 4'b???? = 4'h? ------------+
|
|
// | 1 1 1 0 | ? | /
|
|
// | 1 1 1 1 | ? |/
|
|
// -------------------
|
|
</Template>
|
|
<Template label="LUT5" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT5
|
|
// ____________________
|
|
// | I4 I3 I2 I1 I0 | O |
|
|
// |--------------------|
|
|
// | 0 0 0 0 0 | ? |\
|
|
// | 0 0 0 0 1 | ? | \ = 4'b???? = 4'h? -------------------+
|
|
// | 0 0 0 1 0 | ? | / |
|
|
// | 0 0 0 1 1 | ? |/ |
|
|
// |----------------|---| |
|
|
// | 0 0 1 0 0 | ? |\ |
|
|
// | 0 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 0 1 1 0 | ? | / |
|
|
// | 0 0 1 1 1 | ? |/ |
|
|
// |----------------|---| |
|
|
// | 0 1 0 0 0 | ? |\ |
|
|
// | 0 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 0 1 0 | ? | / |
|
|
// | 0 1 0 1 1 | ? |/ |
|
|
// |----------------|---| |
|
|
// | 0 1 1 0 0 | ? |\ |
|
|
// | 0 1 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 1 1 0 | ? | / |
|
|
// | 0 1 1 1 1 | ? |/ |
|
|
// ---------------------- INIT = 32'h????????
|
|
// | 1 0 0 0 0 | ? |\ |
|
|
// | 1 0 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 0 1 0 | ? | / |
|
|
// | 1 0 0 1 1 | ? |/ |
|
|
// |----------------|---| |
|
|
// | 1 0 1 0 0 | ? |\ |
|
|
// | 1 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 1 1 0 | ? | / |
|
|
// | 1 0 1 1 1 | ? |/ |
|
|
// |----------------|---| |
|
|
// | 1 1 0 0 0 | ? |\ |
|
|
// | 1 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 1 0 1 0 | ? | / |
|
|
// | 1 1 0 1 1 | ? |/ |
|
|
// |----------------|---| |
|
|
// | 1 1 1 0 0 | ? |\ |
|
|
// | 1 1 1 0 1 | ? | \ = 4'b???? = 4'h? ------------+
|
|
// | 1 1 1 1 0 | ? | /
|
|
// | 1 1 1 1 1 | ? |/
|
|
// ----------------------
|
|
</Template>
|
|
<Template label="LUT6" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT6
|
|
// _______________________
|
|
// | I5 I4 I3 I2 I1 I0 | O |
|
|
// |-----------------------|
|
|
// | 0 0 0 0 0 0 | ? |\
|
|
// | 0 0 0 0 0 1 | ? | \ = 4'b???? = 4'h? -------------------+
|
|
// | 0 0 0 0 1 0 | ? | / |
|
|
// | 0 0 0 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 0 0 0 1 0 0 | ? |\ |
|
|
// | 0 0 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 0 0 1 1 0 | ? | / |
|
|
// | 0 0 0 1 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 0 0 1 0 0 0 | ? |\ |
|
|
// | 0 0 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 0 1 0 1 0 | ? | / |
|
|
// | 0 0 1 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 0 0 1 1 0 0 | ? |\ |
|
|
// | 0 0 1 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 0 1 1 1 0 | ? | / |
|
|
// | 0 0 1 1 1 1 | ? |/ |
|
|
// ------------------------- |
|
|
// | 0 1 0 0 0 0 | ? |\ |
|
|
// | 0 1 0 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 0 0 1 0 | ? | / |
|
|
// | 0 1 0 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 0 1 0 1 0 0 | ? |\ |
|
|
// | 0 1 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 0 1 1 0 | ? | / |
|
|
// | 0 1 0 1 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 0 1 1 0 0 0 | ? |\ |
|
|
// | 0 1 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 1 0 1 0 | ? | / |
|
|
// | 0 1 1 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 0 1 1 1 0 0 | ? |\ |
|
|
// | 0 1 1 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 1 1 1 0 | ? | / |
|
|
// | 0 1 1 1 1 1 | ? |/ |
|
|
// ------------------------ INIT = 64'h????????????????
|
|
// | 1 0 0 0 0 0 | ? |\ |
|
|
// | 1 0 0 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 0 0 1 0 | ? | / |
|
|
// | 1 0 0 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 0 0 1 0 0 | ? |\ |
|
|
// | 1 0 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 0 1 1 0 | ? | / |
|
|
// | 1 0 0 1 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 0 1 0 0 0 | ? |\ |
|
|
// | 1 0 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 1 0 1 0 | ? | / |
|
|
// | 1 0 1 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 0 1 1 0 0 | ? |\ |
|
|
// | 1 0 1 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 1 1 1 0 | ? | / |
|
|
// | 1 0 1 1 1 1 | ? |/ |
|
|
// ------------------------- |
|
|
// | 1 1 0 0 0 0 | ? |\ |
|
|
// | 1 1 0 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 1 0 0 1 0 | ? | / |
|
|
// | 1 1 0 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 1 0 1 0 0 | ? |\ |
|
|
// | 1 1 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 1 0 1 1 0 | ? | / |
|
|
// | 1 1 0 1 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 1 1 0 0 0 | ? |\ |
|
|
// | 1 1 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 1 1 0 1 0 | ? | / |
|
|
// | 1 1 1 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 1 1 1 0 0 | ? |\ |
|
|
// | 1 1 1 1 0 1 | ? | \ = 4'b???? = 4'h? ----+
|
|
// | 1 1 1 1 1 0 | ? | /
|
|
// | 1 1 1 1 1 1 | ? |/
|
|
// ------------------------
|
|
</Template>
|
|
<Template label="LUT6_2" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT6_2
|
|
// _____________________________
|
|
// | I5 I4 I3 I2 I1 I0 | O6 | O5 |
|
|
// |-----------------------------|
|
|
// | 0 0 0 0 0 0 | ? |\
|
|
// | 0 0 0 0 0 1 | ? | \ = 4'b???? = 4'h? -------------+
|
|
// | 0 0 0 0 1 0 | ? | / |
|
|
// | 0 0 0 0 1 1 | ? |/ |
|
|
// |-------------------|---------| |
|
|
// | 0 0 0 1 0 0 | ? |\ |
|
|
// | 0 0 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 0 0 1 1 0 | ? | / |
|
|
// | 0 0 0 1 1 1 | ? |/ |
|
|
// |-------------------|---------| |
|
|
// | 0 0 1 0 0 0 | ? |\ |
|
|
// | 0 0 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 0 1 0 1 0 | ? | / |
|
|
// | 0 0 1 0 1 1 | ? |/ |
|
|
// |-------------------|---------| |
|
|
// | 0 0 1 1 0 0 | ? |\ |
|
|
// | 0 0 1 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 0 1 1 1 0 | ? | / |
|
|
// | 0 0 1 1 1 1 | ? |/ |
|
|
// ------------------------------- |
|
|
// | 0 1 0 0 0 0 | ? |\ |
|
|
// | 0 1 0 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 0 0 1 0 | ? | / |
|
|
// | 0 1 0 0 1 1 | ? |/ |
|
|
// |-------------------|---------| |
|
|
// | 0 1 0 1 0 0 | ? |\ |
|
|
// | 0 1 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 0 1 1 0 | ? | / |
|
|
// | 0 1 0 1 1 1 | ? |/ |
|
|
// |-------------------|---------| |
|
|
// | 0 1 1 0 0 0 | ? |\ |
|
|
// | 0 1 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 1 0 1 0 | ? | / |
|
|
// | 0 1 1 0 1 1 | ? |/ |
|
|
// |-------------------|---------| |
|
|
// | 0 1 1 1 0 0 | ? |\ |
|
|
// | 0 1 1 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 1 1 1 0 | ? | / |
|
|
// | 0 1 1 1 1 1 | ? |/ |
|
|
// ------------------------------ INIT = 64'h????????????????
|
|
// | 1 0 0 0 0 0 | ? |\ |
|
|
// | 1 0 0 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 0 0 1 0 | ? | / |
|
|
// | 1 0 0 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 0 0 1 0 0 | ? |\ |
|
|
// | 1 0 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 0 1 1 0 | ? | / |
|
|
// | 1 0 0 1 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 0 1 0 0 0 | ? |\ |
|
|
// | 1 0 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 1 0 1 0 | ? | / |
|
|
// | 1 0 1 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 0 1 1 0 0 | ? |\ |
|
|
// | 1 0 1 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 1 1 1 0 | ? | / |
|
|
// | 1 0 1 1 1 1 | ? |/ |
|
|
// ------------------------- |
|
|
// | 1 1 0 0 0 0 | ? |\ |
|
|
// | 1 1 0 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 1 0 0 1 0 | ? | / |
|
|
// | 1 1 0 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 1 0 1 0 0 | ? |\ |
|
|
// | 1 1 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 1 0 1 1 0 | ? | / |
|
|
// | 1 1 0 1 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 1 1 0 0 0 | ? |\ |
|
|
// | 1 1 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 1 1 0 1 0 | ? | / |
|
|
// | 1 1 1 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 1 1 1 0 0 | ? |\ |
|
|
// | 1 1 1 1 0 1 | ? | \ = 4'b???? = 4'h? ----+
|
|
// | 1 1 1 1 1 0 | ? | /
|
|
// | 1 1 1 1 1 1 | ? |/
|
|
// ------------------------
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<Template label="LUT4" treetype="template">
|
|
// LUT4 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT4_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT4: 4-input Look-Up Table with general output
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT4 #(
|
|
.INIT(16'h0000) // Specify LUT Contents
|
|
) LUT4_inst (
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3) // LUT input
|
|
);
|
|
|
|
// End of LUT4_inst instantiation
|
|
</Template>
|
|
<Template label="LUT4_L" treetype="template">
|
|
// LUT4_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT4_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT4_L: 4-input Look-Up Table with local output
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT4_L #(
|
|
.INIT(16'h0000) // Specify LUT Contents
|
|
) LUT4_L_inst (
|
|
.LO(LO), // LUT local output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3) // LUT input
|
|
);
|
|
|
|
// End of LUT4_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT4_D" treetype="template">
|
|
// LUT4_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT4_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT4_D: 4-input Look-Up Table with general and local outputs
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT4_D #(
|
|
.INIT(16'h0000) // Specify LUT Contents
|
|
) LUT4_D_inst (
|
|
.LO(LO), // LUT local output
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3) // LUT input
|
|
);
|
|
|
|
// End of LUT4_D_inst instantiation
|
|
</Template>
|
|
<Template label="LUT3" treetype="template">
|
|
// LUT3 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT3_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT3: 3-input Look-Up Table with general output
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT3 #(
|
|
.INIT(8'h00) // Specify LUT Contents
|
|
) LUT3_inst (
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2) // LUT input
|
|
);
|
|
|
|
// End of LUT3_inst instantiation
|
|
</Template>
|
|
<Template label="LUT3_L" treetype="template">
|
|
// LUT3_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT3_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT3_L: 3-input Look-Up Table with local output
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT3_L #(
|
|
.INIT(8'h00) // Specify LUT Contents
|
|
) LUT3_L_inst (
|
|
.LO(LO), // LUT local output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2) // LUT input
|
|
);
|
|
|
|
// End of LUT3_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT3_D" treetype="template">
|
|
// LUT3_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT3_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT3_D: 3-input Look-Up Table with general and local outputs
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT3_D #(
|
|
.INIT(8'h00) // Specify LUT Contents
|
|
) LUT3_D_inst (
|
|
.LO(LO), // LUT local output
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2) // LUT input
|
|
);
|
|
|
|
// End of LUT3_D_inst instantiation
|
|
</Template>
|
|
<Template label="LUT2" treetype="template">
|
|
// LUT2 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT2: 2-input Look-Up Table with general output
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT2 #(
|
|
.INIT(4'h0) // Specify LUT Contents
|
|
) LUT2_inst (
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1) // LUT input
|
|
);
|
|
|
|
// End of LUT2_inst instantiation
|
|
</Template>
|
|
<Template label="LUT2_L" treetype="template">
|
|
// LUT2_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT2_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT2_L: 2-input Look-Up Table with local output
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT2_L #(
|
|
.INIT(4'h0) // Specify LUT Contents
|
|
) LUT2_L_inst (
|
|
.LO(LO), // LUT local output
|
|
.I0(I0), // LUT input
|
|
.I1(I1) // LUT input
|
|
);
|
|
|
|
// End of LUT2_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT2_D" treetype="template">
|
|
// LUT2_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT2_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT2_D: 2-input Look-Up Table with general and local outputs
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT2_D #(
|
|
.INIT(4'h0) // Specify LUT Contents
|
|
) LUT2_D_inst (
|
|
.LO(LO), // LUT local output
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1) // LUT input
|
|
);
|
|
|
|
// End of LUT2_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT1" treetype="template">
|
|
// LUT1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT1: 1-input Look-Up Table with general output
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT1 #(
|
|
.INIT(2'b00) // Specify LUT Contents
|
|
) LUT1_inst (
|
|
.O(O), // LUT general output
|
|
.I0(I0) // LUT input
|
|
);
|
|
|
|
// End of LUT1_inst instantiation
|
|
</Template>
|
|
<Template label="LUT1_L" treetype="template">
|
|
// LUT1_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT1_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT1_L: 1-input Look-Up Table with local output
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT1_L #(
|
|
.INIT(2'b00) // Specify LUT Contents
|
|
) LUT1_L_inst (
|
|
.LO(LO), // LUT local output
|
|
.I0(I0) // LUT input
|
|
);
|
|
|
|
// End of LUT1_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT1_D" treetype="template">
|
|
// LUT1_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT1_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT1_D: 1-input Look-Up Table with general and local outputs
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT1_D #(
|
|
.INIT(2'b00) // Specify LUT Contents
|
|
) LUT1_D_inst (
|
|
.LO(LO), // LUT local output
|
|
.O(O), // LUT general output
|
|
.I0(I0) // LUT input
|
|
);
|
|
|
|
// End of LUT1_D_inst instantiation
|
|
</Template>
|
|
<Template label="Reconfigurable LUT (CFGLUT5)" treetype="template">
|
|
// CFGLUT5 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (CFGLUT5_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// CFGLUT5: Reconfigurable 5-input LUT
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
CFGLUT5 #(
|
|
.INIT(32'h00000000) // Specify initial LUT contents
|
|
) CFGLUT5_inst (
|
|
.CDO(CDO), // Reconfiguration cascade output
|
|
.O5(O5), // 4-LUT output
|
|
.O6(O6), // 5-LUT output
|
|
.CDI(CDI), // Reconfiguration data input
|
|
.CE(CE), // Reconfiguration enable input
|
|
.CLK(CLK), // Clock input
|
|
.I0(I0), // Logic data input
|
|
.I1(I1), // Logic data input
|
|
.I2(I2), // Logic data input
|
|
.I3(I3), // Logic data input
|
|
.I4(I4) // Logic data input
|
|
);
|
|
|
|
// End of CFGLUT5_inst instantiation
|
|
</Template>
|
|
<Template label="LUT5" treetype="template">
|
|
// LUT5 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT5_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT5: 5-input Look-Up Table with general output
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT5 #(
|
|
.INIT(32'h00000000) // Specify LUT Contents
|
|
) LUT5_inst (
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3), // LUT input
|
|
.I4(I4) // LUT input
|
|
);
|
|
|
|
// End of LUT5_inst instantiation
|
|
</Template>
|
|
<Template label="LUT5_L" treetype="template">
|
|
// LUT5_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT5_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT5_L: 5-input Look-Up Table with local output
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT5_L #(
|
|
.INIT(32'h0000000) // Specify LUT Contents
|
|
) LUT5_L_inst (
|
|
.LO(LO), // LUT local output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3), // LUT input
|
|
.I4(I4) // LUT input
|
|
);
|
|
|
|
// End of LUT5_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT5_D" treetype="template">
|
|
// LUT5_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT5_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT5_D: 5-input Look-Up Table with general and local outputs
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT5_D #(
|
|
.INIT(32'h0000000) // Specify LUT Contents
|
|
) LUT5_D_inst (
|
|
.LO(LO), // LUT local output
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3), // LUT input
|
|
.I4(I4) // LUT input
|
|
);
|
|
|
|
// End of LUT5_D_inst instantiation
|
|
</Template>
|
|
<Template label="LUT6" treetype="template">
|
|
// LUT6 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT6_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT6: 6-input Look-Up Table with general output
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT6 #(
|
|
.INIT(64'h0000000000000000) // Specify LUT Contents
|
|
) LUT6_inst (
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3), // LUT input
|
|
.I4(I4), // LUT input
|
|
.I5(I5) // LUT input
|
|
);
|
|
|
|
// End of LUT6_inst instantiation
|
|
</Template>
|
|
<Template label="LUT6_L" treetype="template">
|
|
// LUT6_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT6_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT6_L: 6-input Look-Up Table with local output
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT6_L #(
|
|
.INIT(64'h0000000000000000) // Specify LUT Contents
|
|
) LUT6_L_inst (
|
|
.LO(LO), // LUT local output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3), // LUT input
|
|
.I4(I4), // LUT input
|
|
.I5(I5) // LUT input
|
|
);
|
|
|
|
// End of LUT6_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT6_D" treetype="template">
|
|
// LUT6_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT6_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT6_D: 6-input Look-Up Table with general and local outputs
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT6_D #(
|
|
.INIT(64'h0000000000000000) // Specify LUT Contents
|
|
) LUT6_D_inst (
|
|
.LO(LO), // LUT local output
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3), // LUT input
|
|
.I4(I4), // LUT input
|
|
.I5(I5) // LUT input
|
|
);
|
|
|
|
// End of LUT6_D_inst instantiation
|
|
</Template>
|
|
<Template label="LUT6_2" treetype="template">
|
|
// LUT6_2 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT6_2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT6_2: 6-input, 2 output Look-Up Table
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT6_2 #(
|
|
.INIT(64'h0000000000000000) // Specify LUT Contents
|
|
) LUT6_2_inst (
|
|
.O6(O6), // 1-bit LUT6 output
|
|
.O5(O5), // 1-bit lower LUT5 output
|
|
.I0(I0), // 1-bit LUT input
|
|
.I1(I1), // 1-bit LUT input
|
|
.I2(I2), // 1-bit LUT input
|
|
.I3(I3), // 1-bit LUT input
|
|
.I4(I4), // 1-bit LUT input
|
|
.I5(I5) // 1-bit LUT input (fast MUX select only available to O6 output)
|
|
);
|
|
|
|
// End of LUT6_2_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Shift Register LUT" treetype="folder">
|
|
<Template label="16-bit w/ CE posedge SR (SRL16E)" treetype="template">
|
|
// SRL16E : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SRL16E_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SRL16E: 16-bit shift register LUT with clock enable operating on posedge of clock
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SRL16E #(
|
|
.INIT(16'h0000) // Initial Value of Shift Register
|
|
) SRL16E_inst (
|
|
.Q(Q), // SRL data output
|
|
.A0(A0), // Select[0] input
|
|
.A1(A1), // Select[1] input
|
|
.A2(A2), // Select[2] input
|
|
.A3(A3), // Select[3] input
|
|
.CE(CE), // Clock enable input
|
|
.CLK(CLK), // Clock input
|
|
.D(D) // SRL data input
|
|
);
|
|
|
|
// End of SRL16E_inst instantiation
|
|
</Template>
|
|
<Template label="32-bit w/ CE posedge SR (SRLC32E)" treetype="template">
|
|
// SRLC32E : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SRL32E_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SRLC32E: 32-bit variable length cascadable shift register LUT
|
|
// with clock enable
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SRLC32E #(
|
|
.INIT(32'h00000000) // Initial Value of Shift Register
|
|
) SRLC32E_inst (
|
|
.Q(Q), // SRL data output
|
|
.Q31(Q31), // SRL cascade output pin
|
|
.A(A), // 5-bit shift depth select input
|
|
.CE(CE), // Clock enable input
|
|
.CLK(CLK), // Clock input
|
|
.D(D) // SRL data input
|
|
);
|
|
|
|
// End of SRLC32E_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<Template label="Carry (CARRY4)" treetype="template">
|
|
// CARRY4 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (CARRY4_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs and
|
|
// : and outputs of this primitive should be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// CARRY4: Fast Carry Logic Component
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
CARRY4 CARRY4_inst (
|
|
.CO(CO), // 4-bit carry out
|
|
.O(O), // 4-bit carry chain XOR data out
|
|
.CI(CI), // 1-bit carry cascade input
|
|
.CYINIT(CYINIT), // 1-bit carry initialization
|
|
.DI(DI), // 4-bit carry-MUX data in
|
|
.S(S) // 4-bit carry-MUX select input
|
|
);
|
|
|
|
// End of CARRY4_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Registers & Latches" treetype="folder">
|
|
<SubFolder label="Double Data Rate (DDR)" treetype="folder">
|
|
<Template label="Input DDR Register (IDDR2)" treetype="template">
|
|
// IDDR2 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IDDR2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IDDR2: Input Double Data Rate Input Register with Set, Reset
|
|
// and Clock Enable.
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IDDR2 #(
|
|
.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
|
|
.INIT_Q0(1'b0), // Sets initial state of the Q0 output to 1'b0 or 1'b1
|
|
.INIT_Q1(1'b0), // Sets initial state of the Q1 output to 1'b0 or 1'b1
|
|
.SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
|
|
) IDDR2_inst (
|
|
.Q0(Q0), // 1-bit output captured with C0 clock
|
|
.Q1(Q1), // 1-bit output captured with C1 clock
|
|
.C0(C0), // 1-bit clock input
|
|
.C1(C1), // 1-bit clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.D(D), // 1-bit DDR data input
|
|
.R(R), // 1-bit reset input
|
|
.S(S) // 1-bit set input
|
|
);
|
|
|
|
// End of IDDR2_inst instantiation
|
|
</Template>
|
|
<Template label="Output DDR Register (ODDR2)" treetype="template">
|
|
// ODDR2 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ODDR2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ODDR2: Output Double Data Rate Output Register with Set, Reset
|
|
// and Clock Enable.
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ODDR2 #(
|
|
.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
|
|
.INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1
|
|
.SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
|
|
) ODDR2_inst (
|
|
.Q(Q), // 1-bit DDR output data
|
|
.C0(C0), // 1-bit clock input
|
|
.C1(C1), // 1-bit clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.D0(D0), // 1-bit data input (associated with C0)
|
|
.D1(D1), // 1-bit data input (associated with C1)
|
|
.R(R), // 1-bit reset input
|
|
.S(S) // 1-bit set input
|
|
);
|
|
|
|
// End of ODDR2_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Single Data Rate" treetype="folder">
|
|
<Template label="Posedge D-FF w/ Async Clear and CE (FDCE)" treetype="template">
|
|
// FDCE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FDCE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FDCE: Single Data Rate D Flip-Flop with Asynchronous Clear and
|
|
// Clock Enable (posedge clk).
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FDCE FDCE_inst (
|
|
.Q(Q), // 1-bit Data output
|
|
.C(C), // 1-bit Clock input
|
|
.CE(CE), // 1-bit Clock enable input
|
|
.CLR(CLR), // 1-bit Asynchronous clear input
|
|
.D(D) // 1-bit Data input
|
|
);
|
|
|
|
// End of FDCE_inst instantiation
|
|
</Template>
|
|
<Template label="Posedge D-FF w/ Async Preset and CE (FDPE)" treetype="template">
|
|
// FDPE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FDPE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FDPE: Single Data Rate D Flip-Flop with Asynchronous Preset and
|
|
// Clock Enable (posedge clk).
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FDPE FDPE_inst (
|
|
.Q(Q), // 1-bit Data output
|
|
.C(C), // 1-bit Clock input
|
|
.CE(CE), // 1-bit Clock enable input
|
|
.PRE(PRE), // 1-bit Asynchronous preset input
|
|
.D(D) // 1-bit Data input
|
|
);
|
|
|
|
// End of FDPE_inst instantiation
|
|
</Template>
|
|
<Template label="Posedge D-FF w/ Sync Reset and CE (FDRE)" treetype="template">
|
|
// FDRE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FDRE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FDRE: Single Data Rate D Flip-Flop with Synchronous Reset and
|
|
// Clock Enable (posedge clk).
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FDRE FDRE_inst (
|
|
.Q(Q), // 1-bit Data output
|
|
.C(C), // 1-bit Clock input
|
|
.CE(CE), // 1-bit Clock enable input
|
|
.R(R), // 1-bit Synchronous reset input
|
|
.D(D) // 1-bit Data input
|
|
);
|
|
|
|
// End of FDRE_inst instantiation
|
|
</Template>
|
|
<Template label="Posedge D-FF w/ Sync Set and CE (FDSE)" treetype="template">
|
|
// FDSE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FDSE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FDSE: Single Data Rate D Flip-Flop with Synchronous Set and
|
|
// Clock Enable (posedge clk).
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FDSE FDSE_inst (
|
|
.Q(Q), // 1-bit Data output
|
|
.C(C), // 1-bit Clock input
|
|
.CE(CE), // 1-bit Clock enable input
|
|
.S(S), // 1-bit Synchronous set input
|
|
.D(D) // 1-bit Data input
|
|
);
|
|
|
|
// End of FDSE_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Transparent Latch" treetype="folder">
|
|
<Template label="Latch with Async Reset and Gate Enable (LDCE)" treetype="template">
|
|
// LDCE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LDCE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LDCE: Transparent latch with Asynchronous Reset and Gate Enable.
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LDCE LDCE_inst (
|
|
.Q(Q), // Data output
|
|
.CLR(CLR), // Asynchronous clear/reset input
|
|
.D(D), // Data input
|
|
.G(G), // Gate input
|
|
.GE(GE) // Gate enable input
|
|
);
|
|
|
|
// End of LDCE_inst instantiation
|
|
</Template>
|
|
<Template label="Latch with Async Set and Gate Enable (LDPE)" treetype="template">
|
|
// LDPE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LDPE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LDPE: Transparent latch with Asynchronous Preset and Gate Enable.
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LDPE LDPE_inst (
|
|
.Q(Q), // Data output
|
|
.PRE(PRE), // Asynchronous preset/set input
|
|
.D(D), // Data input
|
|
.G(G), // Gate input
|
|
.GE(GE) // Gate enable input
|
|
);
|
|
|
|
// End of LDPE_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Virtex-4" treetype="folder">
|
|
<SubFolder label="Slice/CLB Primitives" treetype="folder">
|
|
<SubFolder label="Carry-Chain" treetype="folder">
|
|
<Template label="MUXCY" treetype="template">
|
|
// MUXCY : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXCY_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs and
|
|
// : and outputs of this primitive should be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXCY: Carry-Chain MUX with general output
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXCY MUXCY_inst (
|
|
.O(O), // Carry output signal
|
|
.CI(CI), // Carry input signal
|
|
.DI(DI), // Data input signal
|
|
.S(S) // MUX select, tie to '1' or LUT4 out
|
|
);
|
|
|
|
// End of MUXCY_inst instantiation
|
|
</Template>
|
|
<Template label="MUXCY_L" treetype="template">
|
|
// MUXCY_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXCY_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXCY_L: Carry-Chain MUX with local output
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXCY_L MUXCY_L_inst (
|
|
.LO(LO), // Carry local output signal
|
|
.CI(CI), // Carry input signal
|
|
.DI(DI), // Data input signal
|
|
.S(S) // MUX select, tie to '1' or LUT4 out
|
|
);
|
|
|
|
// End of MUXCY_L_inst instantiation
|
|
</Template>
|
|
<Template label="MUXCY_D" treetype="template">
|
|
// MUXCY_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXCY_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXCY_D: Carry-Chain MUX with general and local outputs
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXCY_D MUXCY_D_inst (
|
|
.LO(LO), // Carry local output signal
|
|
.O(O), // Carry general output signal
|
|
.CI(CI), // Carry input signal
|
|
.DI(DI), // Data input signal
|
|
.S(S) // MUX select, tie to '1' or LUT4 out
|
|
);
|
|
|
|
// End of MUXCY_D_inst instantiation
|
|
</Template>
|
|
<Template label="XORCY" treetype="template">
|
|
// XORCY : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (XORCY_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// XORCY: Carry-Chain XOR-gate with general output
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
XORCY XORCY_inst (
|
|
.O(O), // XOR output signal
|
|
.CI(CI), // Carry input signal
|
|
.LI(LI) // LUT4 input signal
|
|
);
|
|
|
|
// End of XORCY_inst instantiation
|
|
</Template>
|
|
<Template label="XORCY_L" treetype="template">
|
|
// XORCY_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (XORCY_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// XORCY_L: Carry-Chain XOR-gate with local (direct-connect) output
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
XORCY_L XORCY_L_inst (
|
|
.LO(LO), // XOR local output signal
|
|
.CI(CI), // Carry input signal
|
|
.LI(LI) // LUT4 input signal
|
|
);
|
|
|
|
// End of XORCY_L_inst instantiation
|
|
</Template>
|
|
<Template label="XORCY_D" treetype="template">
|
|
// XORCY_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (XORCY_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// XORCY_D: Carry-Chain XOR-gate with local and general outputs
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
XORCY_D XORCY_D_inst (
|
|
.LO(LO), // XOR local output signal
|
|
.O(O), // XOR general output signal
|
|
.CI(CI), // Carry input signal
|
|
.LI(LI) // LUT4 input signal
|
|
);
|
|
|
|
// End of XORCY_D_inst instantiation
|
|
</Template>
|
|
<Template label="MULT_AND" treetype="template">
|
|
// MULT_AND : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MULT_AND_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MULT_AND: 2-input AND gate connected to Carry chain
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MULT_AND MULT_AND_inst (
|
|
.LO(LO), // MULT_AND output (connect to MUXCY DI)
|
|
.I0(I0), // MULT_AND data[0] input
|
|
.I1(I1) // MULT_AND data[1] input
|
|
);
|
|
|
|
// End of MULT_AND_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="MUXFx" treetype="folder">
|
|
<Template label="MUXF5" treetype="template">
|
|
// MUXF5 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF5_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF5: Slice MUX to tie two LUT4's together with general output
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF5 MUXF5_inst (
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie directly to the output of LUT4)
|
|
.I1(I1), // Input (tie directoy to the output of LUT4)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF5_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF5_L" treetype="template">
|
|
// MUXF5_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF5_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF5_L: Slice MUX to tie two LUT4's together with local output
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF5_L MUXF5_L_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.I0(I0), // Input (tie directly to the output of LUT4)
|
|
.I1(I1), // Input (tie directoy to the output of LUT4)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF5_L_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF5_D" treetype="template">
|
|
// MUXF5_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF5_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF5_D: Slice MUX to tie two LUT4's together with general and local outputs
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF5_D MUXF5_D_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie directly to the output of LUT4)
|
|
.I1(I1), // Input (tie directoy to the output of LUT4)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF5_D_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF6" treetype="template">
|
|
// MUXF6 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF6_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF6: CLB MUX to tie two MUXF5's together with general output
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF6 MUXF6_inst (
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie to MUXF5 LO out)
|
|
.I1(I1), // Input (tie to MUXF5 LO out)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF6_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF6_L" treetype="template">
|
|
// MUXF6_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF6_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF6_L: CLB MUX to tie two MUXF5's together with local output
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF6_L MUXF6_L_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.I0(I0), // Input (tie to MUXF5 LO out)
|
|
.I1(I1), // Input (tie to MUXF5 LO out)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF6_L_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF6_D" treetype="template">
|
|
// MUXF6_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF6_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF6_D: CLB MUX to tie two MUXF5's together with general and local outputs
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF6_D MUXF6_D_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie to MUXF5 LO out)
|
|
.I1(I1), // Input (tie to MUXF5 LO out)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF6_D_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF7" treetype="template">
|
|
// MUXF7 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF7_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF7: CLB MUX to tie two MUXF6's together with general output
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF7 MUXF7_inst (
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie to MUXF6 LO out or LUT6 O6 pin)
|
|
.I1(I1), // Input (tie to MUXF6 LO out or LUT6 O6 pin)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF7_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF7_L" treetype="template">
|
|
// MUXF7_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF7_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF7_L: CLB MUX to tie two MUXF6's together with local output
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF7_L MUXF7_L_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.I0(I0), // Input (tie to MUXF6 LO out or LUT6 O6 pin)
|
|
.I1(I1), // Input (tie to MUXF6 LO out or LUT6 O6 pin)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF7_L_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF7_D" treetype="template">
|
|
// MUXF7_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF7_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF7_D: CLB MUX to tie two MUXF6's together with general and local outputs
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF7_D MUXF7_D_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie to MUXF6 LO out or LUT6 O6 pin)
|
|
.I1(I1), // Input (tie to MUXF6 LO out or LUT6 O6 pin)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF7_D_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF8" treetype="template">
|
|
// MUXF8 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF8_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF8: CLB MUX to tie two MUXF7's together with general output
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF8 MUXF8_inst (
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie to MUXF7 LO out)
|
|
.I1(I1), // Input (tie to MUXF7 LO out)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF8_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF8_L" treetype="template">
|
|
// MUXF8_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF8_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF8_L: CLB MUX to tie two MUXF7's together with local output
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF8_L MUXF8_L_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.I0(I0), // Input (tie to MUXF7 LO out)
|
|
.I1(I1), // Input (tie to MUXF7 LO out)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF8_L_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF8_D" treetype="template">
|
|
// MUXF8_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF8_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF8_D: CLB MUX to tie two MUXF7's together with general and local outputs
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF8_D MUXF8_D_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie to MUXF7 LO out)
|
|
.I1(I1), // Input (tie to MUXF7 LO out)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF8_D_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="LUTs" treetype="folder">
|
|
<SubFolder label="Info" treetype="folder">
|
|
<Template label="Info (LUT INIT)" treetype="template">
|
|
// The INIT parameter for the FPGA LUT primitive is what gives the LUT its
|
|
// logical value. By default this value is zero thus driving the output to a
|
|
// zero regardless of the input values (acting as a ground) however in most
|
|
// cases an new INIT value must be determined in order to specify the logic
|
|
// function for the LUT primitive. There are a few methods in which the LUT
|
|
// value can be determined and two of those methods will be discussed here.
|
|
//
|
|
// The Truth Table Method
|
|
// ----------------------
|
|
//
|
|
// A common method to determine the desired INIT value for a LUT is using a
|
|
// truth table. To do so, simply create a binary truth table of all possible
|
|
// inputs, specify the desired logic value of the output and then create the
|
|
// INIT string from those output values. An example is shown below:
|
|
//
|
|
// Example of determining an XOR INIT equation for a LUT4:
|
|
//
|
|
// _________________
|
|
// | I3 I2 I1 I0 | O |
|
|
// |-----------------|
|
|
// | 0 0 0 0 | 0 |\
|
|
// | 0 0 0 1 | 1 | \ = 4'b0110 = 4'h6 ---------------+
|
|
// | 0 0 1 0 | 1 | / |
|
|
// | 0 0 1 1 | 0 |/ |
|
|
// |-------------|---| |
|
|
// | 0 1 0 0 | 1 |\ |
|
|
// | 0 1 0 1 | 0 | \ = 4'b1001 = 4'h9 |
|
|
// | 0 1 1 0 | 0 | / |
|
|
// | 0 1 1 1 | 1 |/ |
|
|
// |-------------|---| INIT = 16'h6996
|
|
// | 1 0 0 0 | 1 |\ |
|
|
// | 1 0 0 1 | 0 | \ = 4'b0110 = 4'h9 |
|
|
// | 1 0 1 0 | 0 | / |
|
|
// | 1 0 1 1 | 1 |/ |
|
|
// |-------------|---| |
|
|
// | 1 1 0 0 | 0 |\ |
|
|
// | 1 1 0 1 | 1 | \ = 4'b1001 = 4'h6 ------------+
|
|
// | 1 1 1 0 | 1 | /
|
|
// | 1 1 1 1 | 0 |/
|
|
// -------------------
|
|
//
|
|
// Example of determining a 3-input AND gate:
|
|
//
|
|
// ______________
|
|
// | I2 I1 I0 | O |
|
|
// |--------------|
|
|
// | 0 0 0 | 0 |\
|
|
// | 0 0 1 | 0 | \ = 4'b0000 = 4'h0 --------------+
|
|
// | 0 1 0 | 0 | / |
|
|
// | 0 1 1 | 0 |/ |
|
|
// |----------|---| INIT = 8'h80
|
|
// | 1 0 0 | 0 |\ |
|
|
// | 1 0 1 | 0 | \ = 4'b1000 = 4'h8 -------------+
|
|
// | 1 1 0 | 0 | /
|
|
// | 1 1 1 | 1 |/
|
|
// ----------------
|
|
//
|
|
// The Equation Method
|
|
// -------------------
|
|
//
|
|
// Another method to determine the LUT value is to define parameters for each
|
|
// input to the LUT that correspond to their listed truth value and use those to
|
|
// build the logic equation you are after. This method is easier to understand
|
|
// once you have grasped the concept and more self-documenting that the above
|
|
// method however does require the code to first specify the appropriate
|
|
// parameters. See the example below.
|
|
//
|
|
// Example of specifying the equation (A and B) or (C and D) for a LUT4:
|
|
//
|
|
// The forllowing parameters are defined to allow for
|
|
// equation-based INIT specification.
|
|
parameter I0 = 16'haaaa;
|
|
parameter I1 = 16'hcccc;
|
|
parameter I2 = 16'hf0f0;
|
|
parameter I3 = 16'hff00;
|
|
|
|
// LUT4: 4-input Look-Up Table with general output
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT4 #(
|
|
.INIT((I0&I1)|(I2&I3)) // Specify LUT Contents
|
|
) LUT4_inst (
|
|
.O(O_LUT), // LUT general output
|
|
.I0(A), // LUT input
|
|
.I1(B), // LUT input
|
|
.I2(C), // LUT input
|
|
.I3(D) // LUT input
|
|
);
|
|
|
|
// End of LUT4_inst instantiation
|
|
|
|
// With the parameters specifying all possible cases for the truth table, a
|
|
// Verilog equation can be written to determine the end INIT value.
|
|
</Template>
|
|
<SubFolder label="INIT Parameters" treetype="folder">
|
|
<Template label="LUT1" treetype="template">
|
|
// The forllowing parameter is defined to allow for
|
|
// equation-based INIT specification for a LUT1.
|
|
parameter I0 = 2'b10;
|
|
</Template>
|
|
<Template label="LUT2" treetype="template">
|
|
// The forllowing parameters are defined to allow for
|
|
// equation-based INIT specification for a LUT2.
|
|
parameter I0 = 4'ha;
|
|
parameter I1 = 4'hc;
|
|
</Template>
|
|
<Template label="LUT3" treetype="template">
|
|
// The forllowing parameters are defined to allow for
|
|
// equation-based INIT specification for a LUT3.
|
|
parameter I0 = 8'haa;
|
|
parameter I1 = 8'hcc;
|
|
parameter I2 = 8'hf0;
|
|
</Template>
|
|
<Template label="LUT4" treetype="template">
|
|
// The forllowing parameters are defined to allow for
|
|
// equation-based INIT specification for a LUT4.
|
|
parameter I0 = 16'haaaa;
|
|
parameter I1 = 16'hcccc;
|
|
parameter I2 = 16'hf0f0;
|
|
parameter I3 = 16'hff00;
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="INIT Truth Tables" treetype="folder">
|
|
<Template label="LUT1" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT1
|
|
// ________
|
|
// | I0 | O |
|
|
// |--------|
|
|
// | 0 | ? |\
|
|
// | 1 | ? |/ = 2'b??
|
|
// ----------
|
|
</Template>
|
|
<Template label="LUT2" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT2
|
|
// ______________
|
|
// | I2 I1 I0 | O |
|
|
// |--------------|
|
|
// | 0 0 0 | ? |\
|
|
// | 0 0 1 | ? | \ = INIT = 4'b???? = 4'h?
|
|
// | 0 1 0 | ? | /
|
|
// | 0 1 1 | ? |/
|
|
// ---------- ---
|
|
</Template>
|
|
<Template label="LUT3" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT3
|
|
// ______________
|
|
// | I2 I1 I0 | O |
|
|
// |--------------|
|
|
// | 0 0 0 | ? |\
|
|
// | 0 0 1 | ? | \ = 4'b???? = 4'h? --------------+
|
|
// | 0 1 0 | ? | / |
|
|
// | 0 1 1 | ? |/ |
|
|
// |----------|---| INIT = 8'h??
|
|
// | 1 0 0 | ? |\ |
|
|
// | 1 0 1 | ? | \ = 4'b???? = 4'h? -------------+
|
|
// | 1 1 0 | ? | /
|
|
// | 1 1 1 | ? |/
|
|
// ----------------
|
|
</Template>
|
|
<Template label="LUT4" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT4
|
|
// _________________
|
|
// | I3 I2 I1 I0 | O |
|
|
// |-----------------|
|
|
// | 0 0 0 0 | ? |\
|
|
// | 0 0 0 1 | ? | \ = 4'b???? = 4'h? ---------------+
|
|
// | 0 0 1 0 | ? | / |
|
|
// | 0 0 1 1 | ? |/ |
|
|
// |-------------|---| |
|
|
// | 0 1 0 0 | ? |\ |
|
|
// | 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 1 0 | ? | / |
|
|
// | 0 1 1 1 | ? |/ |
|
|
// |-------------|---| INIT = 16'h????
|
|
// | 1 0 0 0 | ? |\ |
|
|
// | 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 1 0 | ? | / |
|
|
// | 1 0 1 1 | ? |/ |
|
|
// |-------------|---| |
|
|
// | 1 1 0 0 | ? |\ |
|
|
// | 1 1 0 1 | ? | \ = 4'b???? = 4'h? ------------+
|
|
// | 1 1 1 0 | ? | /
|
|
// | 1 1 1 1 | ? |/
|
|
// -------------------
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<Template label="LUT4" treetype="template">
|
|
// LUT4 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT4_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT4: 4-input Look-Up Table with general output
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT4 #(
|
|
.INIT(16'h0000) // Specify LUT Contents
|
|
) LUT4_inst (
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3) // LUT input
|
|
);
|
|
|
|
// End of LUT4_inst instantiation
|
|
</Template>
|
|
<Template label="LUT4_L" treetype="template">
|
|
// LUT4_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT4_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT4_L: 4-input Look-Up Table with local output
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT4_L #(
|
|
.INIT(16'h0000) // Specify LUT Contents
|
|
) LUT4_L_inst (
|
|
.LO(LO), // LUT local output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3) // LUT input
|
|
);
|
|
|
|
// End of LUT4_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT4_D" treetype="template">
|
|
// LUT4_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT4_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT4_D: 4-input Look-Up Table with general and local outputs
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT4_D #(
|
|
.INIT(16'h0000) // Specify LUT Contents
|
|
) LUT4_D_inst (
|
|
.LO(LO), // LUT local output
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3) // LUT input
|
|
);
|
|
|
|
// End of LUT4_D_inst instantiation
|
|
</Template>
|
|
<Template label="LUT3" treetype="template">
|
|
// LUT3 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT3_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT3: 3-input Look-Up Table with general output
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT3 #(
|
|
.INIT(8'h00) // Specify LUT Contents
|
|
) LUT3_inst (
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2) // LUT input
|
|
);
|
|
|
|
// End of LUT3_inst instantiation
|
|
</Template>
|
|
<Template label="LUT3_L" treetype="template">
|
|
// LUT3_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT3_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT3_L: 3-input Look-Up Table with local output
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT3_L #(
|
|
.INIT(8'h00) // Specify LUT Contents
|
|
) LUT3_L_inst (
|
|
.LO(LO), // LUT local output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2) // LUT input
|
|
);
|
|
|
|
// End of LUT3_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT3_D" treetype="template">
|
|
// LUT3_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT3_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT3_D: 3-input Look-Up Table with general and local outputs
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT3_D #(
|
|
.INIT(8'h00) // Specify LUT Contents
|
|
) LUT3_D_inst (
|
|
.LO(LO), // LUT local output
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2) // LUT input
|
|
);
|
|
|
|
// End of LUT3_D_inst instantiation
|
|
</Template>
|
|
<Template label="LUT2" treetype="template">
|
|
// LUT2 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT2: 2-input Look-Up Table with general output
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT2 #(
|
|
.INIT(4'h0) // Specify LUT Contents
|
|
) LUT2_inst (
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1) // LUT input
|
|
);
|
|
|
|
// End of LUT2_inst instantiation
|
|
</Template>
|
|
<Template label="LUT2_L" treetype="template">
|
|
// LUT2_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT2_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT2_L: 2-input Look-Up Table with local output
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT2_L #(
|
|
.INIT(4'h0) // Specify LUT Contents
|
|
) LUT2_L_inst (
|
|
.LO(LO), // LUT local output
|
|
.I0(I0), // LUT input
|
|
.I1(I1) // LUT input
|
|
);
|
|
|
|
// End of LUT2_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT2_D" treetype="template">
|
|
// LUT2_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT2_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT2_D: 2-input Look-Up Table with general and local outputs
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT2_D #(
|
|
.INIT(4'h0) // Specify LUT Contents
|
|
) LUT2_D_inst (
|
|
.LO(LO), // LUT local output
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1) // LUT input
|
|
);
|
|
|
|
// End of LUT2_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT1" treetype="template">
|
|
// LUT1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT1: 1-input Look-Up Table with general output
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT1 #(
|
|
.INIT(2'b00) // Specify LUT Contents
|
|
) LUT1_inst (
|
|
.O(O), // LUT general output
|
|
.I0(I0) // LUT input
|
|
);
|
|
|
|
// End of LUT1_inst instantiation
|
|
</Template>
|
|
<Template label="LUT1_L" treetype="template">
|
|
// LUT1_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT1_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT1_L: 1-input Look-Up Table with local output
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT1_L #(
|
|
.INIT(2'b00) // Specify LUT Contents
|
|
) LUT1_L_inst (
|
|
.LO(LO), // LUT local output
|
|
.I0(I0) // LUT input
|
|
);
|
|
|
|
// End of LUT1_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT1_D" treetype="template">
|
|
// LUT1_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT1_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT1_D: 1-input Look-Up Table with general and local outputs
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT1_D #(
|
|
.INIT(2'b00) // Specify LUT Contents
|
|
) LUT1_D_inst (
|
|
.LO(LO), // LUT local output
|
|
.O(O), // LUT general output
|
|
.I0(I0) // LUT input
|
|
);
|
|
|
|
// End of LUT1_D_inst instantiation
|
|
</Template>
|
|
<Template label="LUT Local Connect Buffer (BUFCF)" treetype="template">
|
|
// BUFCF : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFCF_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFCF: Fast connect buffer used to connect the outputs of the LUTs
|
|
// and some dedicated logic directly to the input of another LUT.
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFCF BUFCF_inst (
|
|
.O(O), // Connect to the output of a LUT
|
|
.I(I) // Connect to the input of a LUT
|
|
);
|
|
|
|
// End of BUFCF_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Shift Register LUT" treetype="folder">
|
|
<SubFolder label="Non-cascadable" treetype="folder">
|
|
<Template label="16-bit posedge SR (SRL16)" treetype="template">
|
|
// SRL16 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SRL16_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SRL16: 16-bit shift register LUT operating on posedge of clock
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SRL16 #(
|
|
.INIT(16'h0000) // Initial Value of Shift Register
|
|
) SRL16_inst (
|
|
.Q(Q), // SRL data output
|
|
.A0(A0), // Select[0] input
|
|
.A1(A1), // Select[1] input
|
|
.A2(A2), // Select[2] input
|
|
.A3(A3), // Select[3] input
|
|
.CLK(CLK), // Clock input
|
|
.D(D) // SRL data input
|
|
);
|
|
|
|
// End of SRL16_inst instantiation
|
|
</Template>
|
|
<Template label="16-bit negedge SR (SRL16_1)" treetype="template">
|
|
// SRL16_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SRL16_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SRL16_1: 16-bit shift register LUT operating on negedge of clock
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SRL16_1 #(
|
|
.INIT(16'h0000) // Initial Value of Shift Register
|
|
) SRL16_1_inst (
|
|
.Q(Q), // SRL data output
|
|
.A0(A0), // Select[0] input
|
|
.A1(A1), // Select[1] input
|
|
.A2(A2), // Select[2] input
|
|
.A3(A3), // Select[3] input
|
|
.CLK(CLK), // Clock input
|
|
.D(D) // SRL data input
|
|
);
|
|
|
|
// End of SRL16_1_inst instantiation
|
|
</Template>
|
|
<Template label="16-bit w/ CE posedge SR (SRL16E)" treetype="template">
|
|
// SRL16E : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SRL16E_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SRL16E: 16-bit shift register LUT with clock enable operating on posedge of clock
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SRL16E #(
|
|
.INIT(16'h0000) // Initial Value of Shift Register
|
|
) SRL16E_inst (
|
|
.Q(Q), // SRL data output
|
|
.A0(A0), // Select[0] input
|
|
.A1(A1), // Select[1] input
|
|
.A2(A2), // Select[2] input
|
|
.A3(A3), // Select[3] input
|
|
.CE(CE), // Clock enable input
|
|
.CLK(CLK), // Clock input
|
|
.D(D) // SRL data input
|
|
);
|
|
|
|
// End of SRL16E_inst instantiation
|
|
</Template>
|
|
<Template label="16-bit w/ CE negedge SR (SRL16E_1)" treetype="template">
|
|
// SRL16E_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SRL16E_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SRL16E_1: 16-bit shift register LUT with clock enable operating on negedge of clock
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SRL16E_1 #(
|
|
.INIT(16'h0000) // Initial Value of Shift Register
|
|
) SRL16E_1_inst (
|
|
.Q(Q), // SRL data output
|
|
.A0(A0), // Select[0] input
|
|
.A1(A1), // Select[1] input
|
|
.A2(A2), // Select[2] input
|
|
.A3(A3), // Select[3] input
|
|
.CE(CE), // Clock enable input
|
|
.CLK(CLK), // Clock input
|
|
.D(D) // SRL data input
|
|
);
|
|
|
|
// End of SRL16E_1_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Cascable" treetype="folder">
|
|
<Template label="16-bit posedge SR (SRLC16)" treetype="template">
|
|
// SRLC16 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SRLC16_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SRLC16: 16-bit cascadable shift register LUT operating on posedge of clock
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SRLC16 #(
|
|
.INIT(16'h0000) // Initial Value of Shift Register
|
|
) SRLC16_inst (
|
|
.Q(Q), // SRL data output
|
|
.Q15(Q15), // Carry output (connect to next SRL)
|
|
.A0(A0), // Select[0] input
|
|
.A1(A1), // Select[1] input
|
|
.A2(A2), // Select[2] input
|
|
.A3(A3), // Select[3] input
|
|
.CLK(CLK), // Clock input
|
|
.D(D) // SRL data input
|
|
);
|
|
|
|
// End of SRLC16_inst instantiation
|
|
</Template>
|
|
<Template label="16-bit negedge SR (SRLC16_1)" treetype="template">
|
|
// SRLC16_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SRLC16_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SRLC16_1: 16-bit cascadable shift register LUT operating on negedge of clock
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SRLC16_1 #(
|
|
.INIT(16'h0000) // Initial Value of Shift Register
|
|
) SRLC16_1_inst (
|
|
.Q(Q), // SRL data output
|
|
.Q15(Q15), // Carry output (connect to next SRL)
|
|
.A0(A0), // Select[0] input
|
|
.A1(A1), // Select[1] input
|
|
.A2(A2), // Select[2] input
|
|
.A3(A3), // Select[3] input
|
|
.CLK(CLK), // Clock input
|
|
.D(D) // SRL data input
|
|
);
|
|
|
|
// End of SRLC16_1_inst instantiation
|
|
</Template>
|
|
<Template label="16-bit w/ CE posedge SR (SRLC16E)" treetype="template">
|
|
// SRLC16E : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SRL16E_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SRLC16E: 16-bit cascadable shift register LUT with clock enable operating on posedge of clock
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SRLC16E #(
|
|
.INIT(16'h0000) // Initial Value of Shift Register
|
|
) SRLC16E_inst (
|
|
.Q(Q), // SRL data output
|
|
.Q15(Q15), // Carry output (connect to next SRL)
|
|
.A0(A0), // Select[0] input
|
|
.A1(A1), // Select[1] input
|
|
.A2(A2), // Select[2] input
|
|
.A3(A3), // Select[3] input
|
|
.CE(CE), // Clock enable input
|
|
.CLK(CLK), // Clock input
|
|
.D(D) // SRL data input
|
|
);
|
|
|
|
// End of SRLC16E_inst instantiation
|
|
</Template>
|
|
<Template label="16-bit w/ CE negedge SR (SRLC16E_1)" treetype="template">
|
|
// SRLC16E_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SRLC16E_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SRLC16E_1: 16-bit shift register LUT with clock enable operating on negedge of clock
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SRLC16E_1 #(
|
|
.INIT(16'h0000) // Initial Value of Shift Register
|
|
) SRLC16E_1_inst (
|
|
.Q(Q), // SRL data output
|
|
.Q15(Q15), // Carry output (connect to next SRL)
|
|
.A0(A0), // Select[0] input
|
|
.A1(A1), // Select[1] input
|
|
.A2(A2), // Select[2] input
|
|
.A3(A3), // Select[3] input
|
|
.CE(CE), // Clock enable input
|
|
.CLK(CLK), // Clock input
|
|
.D(D) // SRL data input
|
|
);
|
|
|
|
// End of SRLC16E_1_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Clock Components" treetype="folder">
|
|
<SubFolder label="Digital Clock Manager (DCM)" treetype="folder">
|
|
<Template label="Dynamic Phase Shift DCM (DCM_PS)" treetype="template">
|
|
// DCM_PS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (DCM_PS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Unused inputs
|
|
// : and outputs may be removed or commented out.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// DCM_PS: Dynamic Phase Shift Digital Clock Manager Circuit
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
DCM_PS #(
|
|
.CLKDV_DIVIDE(2.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
|
|
// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
|
|
.CLKFX_DIVIDE(1), // Can be any integer from 1 to 32
|
|
.CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32
|
|
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
|
|
.CLKIN_PERIOD(10.0), // Specify period of input clock in ns from 1.25 to 1000.00
|
|
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift mode of NONE, FIXED,
|
|
// VARIABLE_POSITIVE, VARIABLE_CENTER or DIRECT
|
|
.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X
|
|
.DCM_PERFORMANCE_MODE("MAX_SPEED"), // Can be MAX_SPEED or MAX_RANGE
|
|
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
|
|
// an integer from 0 to 15
|
|
.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
|
|
.DLL_FREQUENCY_MODE("LOW"), // LOW, HIGH, or HIGH_SER frequency mode for DLL
|
|
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
|
|
.FACTORY_JF(16'hf0f0), // FACTORY JF value suggested to be set to 16'hf0f0
|
|
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 1023
|
|
.STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
|
|
) DCM_PS_inst (
|
|
.CLK0(CLK0), // 0 degree DCM CLK output
|
|
.CLK180(CLK180), // 180 degree DCM CLK output
|
|
.CLK270(CLK270), // 270 degree DCM CLK output
|
|
.CLK2X(CLK2X), // 2X DCM CLK output
|
|
.CLK2X180(CLK2X180), // 2X, 180 degree DCM CLK out
|
|
.CLK90(CLK90), // 90 degree DCM CLK output
|
|
.CLKDV(CLKDV), // Divided DCM CLK out (CLKDV_DIVIDE)
|
|
.CLKFX(CLKFX), // DCM CLK synthesis out (M/D)
|
|
.CLKFX180(CLKFX180), // 180 degree CLK synthesis out
|
|
.DO(DO), // 16-bit data output for Dynamic Reconfiguration Port (DRP)
|
|
.LOCKED(LOCKED), // DCM LOCK status output
|
|
.PSDONE(PSDONE), // Dynamic phase adjust done output
|
|
.CLKFB(CLKFB), // DCM clock feedback
|
|
.CLKIN(CLKIN), // Clock input (from IBUFG, BUFG or DCM)
|
|
.PSCLK(PSCLK), // Dynamic phase adjust clock input
|
|
.PSEN(PSEN), // Dynamic phase adjust enable input
|
|
.PSINCDEC(PSINCDEC), // Dynamic phase adjust increment/decrement
|
|
.RST(RST) // DCM asynchronous reset input
|
|
);
|
|
|
|
|
|
// End of DCM_PS_inst instantiation
|
|
</Template>
|
|
<Template label="Base DCM (DCM_BASE)" treetype="template">
|
|
// DCM_BASE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (DCM_BASE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Unused inputs
|
|
// : and outputs may be removed or commented out.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// DCM_BASE: Base Digital Clock Manager Circuit
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
DCM_BASE #(
|
|
.CLKDV_DIVIDE(2.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
|
|
// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
|
|
.CLKFX_DIVIDE(1), // Can be any integer from 1 to 32
|
|
.CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32
|
|
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
|
|
.CLKIN_PERIOD(10.0), // Specify period of input clock in ns from 1.25 to 1000.00
|
|
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift mode of NONE or FIXED
|
|
.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X
|
|
.DCM_PERFORMANCE_MODE("MAX_SPEED"), // Can be MAX_SPEED or MAX_RANGE
|
|
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
|
|
// an integer from 0 to 15
|
|
.DFS_FREQUENCY_MODE("LOW"), // LOW or HIGH frequency mode for frequency synthesis
|
|
.DLL_FREQUENCY_MODE("LOW"), // LOW, HIGH, or HIGH_SER frequency mode for DLL
|
|
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
|
|
.FACTORY_JF(16'hf0f0), // FACTORY JF value suggested to be set to 16'hf0f0
|
|
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 1023
|
|
.STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
|
|
) DCM_BASE_inst (
|
|
.CLK0(CLK0), // 0 degree DCM CLK output
|
|
.CLK180(CLK180), // 180 degree DCM CLK output
|
|
.CLK270(CLK270), // 270 degree DCM CLK output
|
|
.CLK2X(CLK2X), // 2X DCM CLK output
|
|
.CLK2X180(CLK2X180), // 2X, 180 degree DCM CLK out
|
|
.CLK90(CLK90), // 90 degree DCM CLK output
|
|
.CLKDV(CLKDV), // Divided DCM CLK out (CLKDV_DIVIDE)
|
|
.CLKFX(CLKFX), // DCM CLK synthesis out (M/D)
|
|
.CLKFX180(CLKFX180), // 180 degree CLK synthesis out
|
|
.LOCKED(LOCKED), // DCM LOCK status output
|
|
.CLKFB(CLKFB), // DCM clock feedback
|
|
.CLKIN(CLKIN), // Clock input (from IBUFG, BUFG or DCM)
|
|
.RST(RST) // DCM asynchronous reset input
|
|
);
|
|
|
|
// End of DCM_BASE_inst instantiation
|
|
</Template>
|
|
<Template label="Advanced DCM (DCM_ADV)" treetype="template">
|
|
// DCM_ADV : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (DCM_ADV_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Unused inputs
|
|
// : and outputs may be removed or commented out.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// DCM_ADV: Digital Clock Manager Circuit
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
DCM_ADV #(
|
|
.CLKDV_DIVIDE(2.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
|
|
// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
|
|
.CLKFX_DIVIDE(1), // Can be any integer from 1 to 32
|
|
.CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32
|
|
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
|
|
.CLKIN_PERIOD(10.0), // Specify period of input clock in ns from 1.25 to 1000.00
|
|
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift mode of NONE, FIXED,
|
|
// VARIABLE_POSITIVE, VARIABLE_CENTER or DIRECT
|
|
.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE, 1X or 2X
|
|
.DCM_PERforMANCE_MODE("MAX_SPEED"), // Can be MAX_SPEED or MAX_RANGE
|
|
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
|
|
// an integer from 0 to 15
|
|
.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
|
|
.DLL_FREQUENCY_MODE("LOW"), // LOW, HIGH, or HIGH_SER frequency mode for DLL
|
|
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, "TRUE"/"FALSE"
|
|
.FACTORY_JF(16'hf0f0), // FACTORY JF value suggested to be set to 16'hf0f0
|
|
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 1023
|
|
.SIM_DEVICE("VIRTEX4"), // Set target device, "VIRTEX4" or "VIRTEX5"
|
|
.STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, "TRUE"/"FALSE"
|
|
) DCM_ADV_inst (
|
|
.CLK0(CLK0), // 0 degree DCM CLK output
|
|
.CLK180(CLK180), // 180 degree DCM CLK output
|
|
.CLK270(CLK270), // 270 degree DCM CLK output
|
|
.CLK2X(CLK2X), // 2X DCM CLK output
|
|
.CLK2X180(CLK2X180), // 2X, 180 degree DCM CLK out
|
|
.CLK90(CLK90), // 90 degree DCM CLK output
|
|
.CLKDV(CLKDV), // Divided DCM CLK out (CLKDV_DIVIDE)
|
|
.CLKFX(CLKFX), // DCM CLK synthesis out (M/D)
|
|
.CLKFX180(CLKFX180), // 180 degree CLK synthesis out
|
|
.DO(DO), // 16-bit data output for Dynamic Reconfiguration Port (DRP)
|
|
.DRDY(DRDY), // Ready output signal from the DRP
|
|
.LOCKED(LOCKED), // DCM LOCK status output
|
|
.PSDONE(PSDONE), // Dynamic phase adjust done output
|
|
.CLKFB(CLKFB), // DCM clock feedback
|
|
.CLKIN(CLKIN), // Clock input (from IBUFG, BUFG or DCM)
|
|
.DADDR(DADDR), // 7-bit address for the DRP
|
|
.DCLK(DCLK), // Clock for the DRP
|
|
.DEN(DEN), // Enable input for the DRP
|
|
.DI(DI), // 16-bit data input for the DRP
|
|
.DWE(DWE), // Active high allows for writing configuration memory
|
|
.PSCLK(PSCLK), // Dynamic phase adjust clock input
|
|
.PSEN(PSEN), // Dynamic phase adjust enable input
|
|
.PSINCDEC(PSINCDEC), // Dynamic phase adjust increment/decrement
|
|
.RST(RST) // DCM asynchronous reset input
|
|
);
|
|
|
|
// End of DCM_ADV_inst instantiation
|
|
</Template>
|
|
<Template label="Phase-Matched Clock Divider for Virtex-4 (PMCD)" treetype="template">
|
|
// PMCD : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (PMCD_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Unused inputs
|
|
// : and outputs may be removed or commented out.
|
|
// :
|
|
// : Note: This component cannot be retargeted to future architectures
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// PMCD: Phase-Matched Clock Divider Circuit
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
PMCD #(
|
|
.EN_REL("FALSE"), // TRUE/FALSE to allow synchronous deassertion of RST
|
|
.RST_DEASSERT_CLK("CLKA") // Reset syncronization to which clock: CLKA, CLKB, CLKC or CLKD
|
|
) PMCD_inst (
|
|
.CLKA1(CLKA1), // Output CLKA divided by 1
|
|
.CLKA1D2(CLKA1D2), // Output CLKA divided by 2
|
|
.CLKA1D4(CLKA1D4), // Output CLKA divided by 4
|
|
.CLKA1D8(CLKA1D8), // Output CLKA divided by 8
|
|
.CLKB1(CLKB1), // Output phase matched CLKB
|
|
.CLKC1(CLKC1), // Output phase matched CLKC
|
|
.CLKD1(CLKD1), // Output phase matched CLKD
|
|
.CLKA(CLKA), // Input CLKA
|
|
.CLKB(CLKB), // Input CLKB
|
|
.CLKC(CLKC), // Input CLKC
|
|
.CLKD(CLKD), // Input CLKD
|
|
.REL(REL), // PCMD release input
|
|
.RST(RST) // Active high reset input
|
|
);
|
|
|
|
// End of PMCD_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Clock Buffers" treetype="folder">
|
|
<Template label="Global Clock Buffer (BUFG)" treetype="template">
|
|
// BUFG : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFG_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFG: Global Clock Buffer (source by an internal signal)
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFG BUFG_inst (
|
|
.O(O), // Clock buffer output
|
|
.I(I) // Clock buffer input
|
|
);
|
|
|
|
// End of BUFG_inst instantiation
|
|
</Template>
|
|
<Template label="Single-ended input Global Clock Buffer (IBUFG)" treetype="template">
|
|
// IBUFG : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFG_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFG: Global Clock Buffer (sourced by an external pin)
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFG #(
|
|
.CAPACITANCE("DONT_CARE"), // "DONT_CARE". "LOW" or "NORMAL" (Virtex-4 only)
|
|
.IOSTANDARD("DEFAULT")
|
|
) IBUFG_inst (
|
|
.O(O), // Clock buffer output
|
|
.I(I) // Clock buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUFG_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Input Global Clock Buffer (IBUFGDS)" treetype="template">
|
|
// IBUFGDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFGDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFGDS: Differential Global Clock Buffer (sourced by an external pin)
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFGDS #(
|
|
.CAPACITANCE("DONT_CARE"), // "DONT_CARE". "LOW" or "NORMAL" (Virtex-4 only)
|
|
.DIFF_TERM("FALSE"), // Differential Termination
|
|
.IOSTANDARD("DEFAULT") // Specifies the I/O standard for this buffer
|
|
) IBUFGDS_inst (
|
|
.O(O), // Clock buffer output
|
|
.I(I), // Diff_p clock buffer input
|
|
.IB(IB) // Diff_n clock buffer input
|
|
);
|
|
|
|
// End of IBUFGDS_inst instantiation
|
|
</Template>
|
|
<Template label="Global Clock Buffer w/ Enable (BUFGCE)" treetype="template">
|
|
// BUFGCE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFGCE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFGCE: Global Clock Buffer with Clock Enable (active high)
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFGCE BUFGCE_inst (
|
|
.O(O), // Clock buffer output
|
|
.CE(CE), // Clock enable input
|
|
.I(I) // Clock buffer input
|
|
);
|
|
|
|
// End of BUFGCE_inst instantiation
|
|
</Template>
|
|
<Template label="Global Clock Buffer w/ Enable (BUFGCE_1)" treetype="template">
|
|
// BUFGCE_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFGCE_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFGCE_1: Global Clock Buffer with Clock Enable (active low)
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFGCE_1 BUFGCE_1_inst (
|
|
.O(O), // Clock buffer output
|
|
.CE(CE), // Clock enable input
|
|
.I(I) // Clock buffer input
|
|
);
|
|
|
|
// End of BUFGCE_1_inst instantiation
|
|
</Template>
|
|
<Template label="Local Clock Buffer (BUFIO)" treetype="template">
|
|
// BUFIO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFIO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFIO: Local Clock Buffer
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFIO BUFIO_inst (
|
|
.O(O), // Clock buffer output
|
|
.I(I) // Clock buffer input
|
|
);
|
|
|
|
// End of BUFIO_inst instantiation
|
|
|
|
// End of BUFGMUX_1_inst instantiation
|
|
</Template>
|
|
<Template label="Regional Clock Buffer (BUFR)" treetype="template">
|
|
// BUFR : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFR_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFR: Regional Clock Buffer w/ Enable, Clear and Division Capabilities
|
|
// Virtex-4/5, Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFR #(
|
|
.BUFR_DIVIDE("BYPASS"), // "BYPASS", "1", "2", "3", "4", "5", "6", "7", "8"
|
|
.SIM_DEVICE("VIRTEX4") // Specify target device, "VIRTEX4", "VIRTEX5", "VIRTEX6"
|
|
) BUFR_inst (
|
|
.O(O), // Clock buffer output
|
|
.CE(CE), // Clock enable input
|
|
.CLR(CLR), // Clock buffer reset input
|
|
.I(I) // Clock buffer input
|
|
);
|
|
|
|
// End of BUFR_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Clock MUX" treetype="folder">
|
|
<Template label="Global Clock Buffer MUX for Virtex-4 (BUFGMUX_VIRTEX4)" treetype="template">
|
|
// BUFGMUX_VIRTEX4 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFGMUX_VIRTEX4_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFGMUX_VIRTEX4: Global Clock Buffer 2-to-1 MUX
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFGMUX_VIRTEX4 BUFGMUX_VIRTEX4_inst (
|
|
.O(O), // Clock MUX output
|
|
.I0(I0), // Clock0 input
|
|
.I1(I1), // Clock1 input
|
|
.S(S) // Clock select input
|
|
);
|
|
|
|
// End of BUFGMUX_VIRTEX4_inst instantiation
|
|
</Template>
|
|
<Template label="Advanced Clock Primitive (BUFGCTRL)" treetype="template">
|
|
// BUFGCTRL : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFGCTRL_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFGCTRL: Advanced Clock MUX Primitive
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFGCTRL #(
|
|
.INIT_OUT(0), // Inital value of 0 or 1 after configuration
|
|
.PRESELECT_I0("FALSE"), // "TRUE" or "FALSE" set the I0 input after configuration
|
|
.PRESELECT_I1("FALSE") // "TRUE" or "FALSE" set the I1 input after configuration
|
|
) BUFGCTRL_inst (
|
|
.O(O), // 1-bit output
|
|
.CE0(CE0), // 1-bit clock enable 0
|
|
.CE1(CE1), // 1-bit clock enable 1
|
|
.I0(I0), // 1-bit clock 0 input
|
|
.I1(I1), // 1-bit clock 1 input
|
|
.IGNORE0(IGNORE0), // 1-bit ignore 0 input
|
|
.IGNORE1(IGNORE1), // 1-bit ignore 1 input
|
|
.S0(S0), // 1-bit select 0 input
|
|
.S1(S1) // 1-bit select 1 input
|
|
);
|
|
|
|
// End of BUFGCTRL_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="RAM/ROM" treetype="folder">
|
|
<SubFolder label="Distributed ROM" treetype="folder">
|
|
<Template label="16 X 1 (ROM16X1)" treetype="template">
|
|
// ROM16X1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ROM16X1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ROM16X1: 16 x 1 Asynchronous Distributed (LUT) ROM
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ROM16X1 #(
|
|
.INIT(16'h0000) // Contents of ROM
|
|
) ROM16X1_inst (
|
|
.O(O), // ROM output
|
|
.A0(A0), // ROM address[0]
|
|
.A1(A1), // ROM address[1]
|
|
.A2(A2), // ROM address[2]
|
|
.A3(A3) // ROM address[3]
|
|
);
|
|
|
|
// End of ROM16X1_inst instantiation
|
|
</Template>
|
|
<Template label="32 X 1 (ROM32X1)" treetype="template">
|
|
// ROM32X1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ROM32X1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ROM32X1: 32 x 1 Asynchronous Distributed (LUT) ROM
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ROM32X1 #(
|
|
.INIT(32'h00000000) // Contents of ROM
|
|
) ROM32X1_inst (
|
|
.O(O), // ROM output
|
|
.A0(A0), // ROM address[0]
|
|
.A1(A1), // ROM address[1]
|
|
.A2(A2), // ROM address[2]
|
|
.A3(A3), // ROM address[3]
|
|
.A4(A4) // ROM address[4]
|
|
);
|
|
|
|
// End of ROM32X1_inst instantiation
|
|
</Template>
|
|
<Template label="64 X 1 (ROM64X1)" treetype="template">
|
|
// ROM64X1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ROM64X1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ROM64X1: 64 x 1 Asynchronous Distributed (LUT) ROM
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ROM64X1 #(
|
|
.INIT(64'h0000000000000000) // Contents of ROM
|
|
) ROM64X1_inst (
|
|
.O(O), // ROM output
|
|
.A0(A0), // ROM address[0]
|
|
.A1(A1), // ROM address[1]
|
|
.A2(A2), // ROM address[2]
|
|
.A3(A3), // ROM address[3]
|
|
.A4(A4), // ROM address[4]
|
|
.A5(A5) // ROM address[5]
|
|
);
|
|
|
|
// End of ROM64X1_inst instantiation
|
|
</Template>
|
|
<Template label="128 X 1 (ROM128X1)" treetype="template">
|
|
// ROM128X1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ROM128X1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ROM128X1: 128 x 1 Asynchronous Distributed (LUT) ROM
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ROM128X1 #(
|
|
.INIT(128'h00000000000000000000000000000000) // Contents of ROM
|
|
) ROM128X1_inst (
|
|
.O(O), // ROM output
|
|
.A0(A0), // ROM address[0]
|
|
.A1(A1), // ROM address[1]
|
|
.A2(A2), // ROM address[2]
|
|
.A3(A3), // ROM address[3]
|
|
.A4(A4), // ROM address[4]
|
|
.A5(A5), // ROM address[5]
|
|
.A6(A6) // ROM address[6]
|
|
);
|
|
|
|
// End of ROM128X1_inst instantiation
|
|
</Template>
|
|
<Template label="256 X 1 (ROM256X1)" treetype="template">
|
|
// ROM256X1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ROM256X1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ROM256X1: 256 x 1 Asynchronous Distributed (LUT) ROM
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ROM256X1 #(
|
|
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000) // Contents of ROM
|
|
) ROM256X1_inst (
|
|
.O(O), // ROM output
|
|
.A0(A0), // ROM address[0]
|
|
.A1(A1), // ROM address[1]
|
|
.A2(A2), // ROM address[2]
|
|
.A3(A3), // ROM address[3]
|
|
.A4(A4), // ROM address[4]
|
|
.A5(A5), // ROM address[5]
|
|
.A6(A6), // ROM address[6]
|
|
.A7(A7) // ROM address[7]
|
|
);
|
|
|
|
// End of ROM256X1_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Distributed RAM" treetype="folder">
|
|
<SubFolder label="Single-Port" treetype="folder">
|
|
<SubFolder label="16 Deep (4-bit address)" treetype="folder">
|
|
<Template label="16 x 1 posedge write (RAM16X1S)" treetype="template">
|
|
// RAM16X1S : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM16X1S_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM16X1S: 16 x 1 posedge write distributed (LUT) RAM
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM16X1S #(
|
|
.INIT(16'h0000) // Initial contents of RAM
|
|
) RAM16X1S_inst (
|
|
.O(O), // RAM output
|
|
.A0(A0), // RAM address[0] input
|
|
.A1(A1), // RAM address[1] input
|
|
.A2(A2), // RAM address[2] input
|
|
.A3(A3), // RAM address[3] input
|
|
.D(D), // RAM data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM16X1S_inst instantiation
|
|
</Template>
|
|
<Template label="16 x 1 negedge write (RAM16X1S_1)" treetype="template">
|
|
// RAM16X1S_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM16X1S_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM16X1S_1: 16 x 1 negedge write distributed (LUT) RAM
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM16X1S_1 #(
|
|
.INIT(16'h0000) // Initial contents of RAM
|
|
) RAM16X1S_1_inst (
|
|
.O(O), // RAM output
|
|
.A0(A0), // RAM address[0] input
|
|
.A1(A1), // RAM address[1] input
|
|
.A2(A2), // RAM address[2] input
|
|
.A3(A3), // RAM address[3] input
|
|
.D(D), // RAM data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM16X1S_1_inst instantiation
|
|
</Template>
|
|
<Template label="16 x 2 posedge write (RAM16X2S)" treetype="template">
|
|
// RAM16X2S : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM16X2S_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM16X2S: 16 x 2 posedge write distributed (LUT) RAM
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM16X2S #(
|
|
.INIT_00(16'h0000), // Initial contents of bit 0 of RAM
|
|
.INIT_01(16'h0000) // Initial contents of bit 1 of RAM
|
|
) RAM16X2S_inst (
|
|
.O0(O0), // RAM data[0] output
|
|
.O1(O1), // RAM data[1] output
|
|
.A0(A0), // RAM address[0] input
|
|
.A1(A1), // RAM address[1] input
|
|
.A2(A2), // RAM address[2] input
|
|
.A3(A3), // RAM address[3] input
|
|
.D0(D0), // RAM data[0] input
|
|
.D1(D1), // RAM data[1] input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM16X2S_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="32 Deep (5-bit address)" treetype="folder">
|
|
<Template label="32 x 1 posedge write (RAM32X1S)" treetype="template">
|
|
// RAM32X1S : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM32X1S_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM32X1S: 32 x 1 posedge write distributed (LUT) RAM
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM32X1S #(
|
|
.INIT(32'h00000000) // Initial contents of RAM
|
|
) RAM32X1S_inst (
|
|
.O(O), // RAM output
|
|
.A0(A0), // RAM address[0] input
|
|
.A1(A1), // RAM address[1] input
|
|
.A2(A2), // RAM address[2] input
|
|
.A3(A3), // RAM address[3] input
|
|
.A4(A4), // RAM address[4] input
|
|
.D(D), // RAM data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM32X1S_inst instantiation
|
|
</Template>
|
|
<Template label="32 x 1 negedge write (RAM32X1S_1)" treetype="template">
|
|
// RAM32X1S_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM32X1S_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM32X1S_1: 32 x 1 negedge write distributed (LUT) RAM
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM32X1S_1 #(
|
|
.INIT(32'h00000000) // Initial contents of RAM
|
|
)RAM32X1S_1_inst (
|
|
.O(O), // RAM output
|
|
.A0(A0), // RAM address[0] input
|
|
.A1(A1), // RAM address[1] input
|
|
.A2(A2), // RAM address[2] input
|
|
.A3(A3), // RAM address[3] input
|
|
.A4(A4), // RAM address[4] input
|
|
.D(D), // RAM data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM32X1S_1_inst instantiation
|
|
</Template>
|
|
<Template label="32 x 2 posedge write (RAM32X2S)" treetype="template">
|
|
// RAM32X2S : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM16X2S_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM32X2S: 32 x 2 posedge write distributed (LUT) RAM
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM32X2S #(
|
|
.INIT_00(32'h00000000), // INIT for bit 0 of RAM
|
|
.INIT_01(32'h00000000) // INIT for bit 1 of RAM
|
|
) RAM32X2S_inst (
|
|
.O0(O0), // RAM data[0] output
|
|
.O1(O1), // RAM data[1] output
|
|
.A0(A0), // RAM address[0] input
|
|
.A1(A1), // RAM address[1] input
|
|
.A2(A2), // RAM address[2] input
|
|
.A3(A3), // RAM address[3] input
|
|
.A4(A4), // RAM address[4] input
|
|
.D0(D0), // RAM data[0] input
|
|
.D1(D1), // RAM data[1] input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM32X2S_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="64 Deep (6-bit address)" treetype="folder">
|
|
<Template label="64 X 1 posedge write (RAM64X1S)" treetype="template">
|
|
// RAM64X1S : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM64X1S_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM64X1S: 64 x 1 positive edge write, asynchronous read single-port distributed RAM
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM64X1S #(
|
|
.INIT(64'h0000000000000000) // Initial contents of RAM
|
|
) RAM64X1S_inst (
|
|
.O(O), // 1-bit data output
|
|
.A0(A0), // Address[0] input bit
|
|
.A1(A1), // Address[1] input bit
|
|
.A2(A2), // Address[2] input bit
|
|
.A3(A3), // Address[3] input bit
|
|
.A4(A4), // Address[4] input bit
|
|
.A5(A5), // Address[5] input bit
|
|
.D(D), // 1-bit data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM64X1S_inst instantiation
|
|
</Template>
|
|
<Template label="64 X 1 negedge write (RAM64X1S_1)" treetype="template">
|
|
// RAM64X1S_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM64X1S_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM64X1S_1: 64 x 1 negative edge write, asynchronous read single-port distributed RAM
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM64X1S_1 #(
|
|
.INIT(64'h0000000000000000) // Initial contents of RAM
|
|
) RAM64X1S_1_inst (
|
|
.O(O), // 1-bit data output
|
|
.A0(A0), // Address[0] input bit
|
|
.A1(A1), // Address[1] input bit
|
|
.A2(A2), // Address[2] input bit
|
|
.A3(A3), // Address[3] input bit
|
|
.A4(A4), // Address[4] input bit
|
|
.A5(A5), // Address[5] input bit
|
|
.D(D), // 1-bit data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM64X1S_1_inst instantiation
|
|
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Dual-Port" treetype="folder">
|
|
<Template label="16 X 1 posedge write (RAM16X1D)" treetype="template">
|
|
// RAM16X1D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM16X1D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM16X1D: 16 x 1 positive edge write, asynchronous read dual-port distributed RAM
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM16X1D #(
|
|
.INIT(16'h0000) // Initial contents of RAM
|
|
) RAM16X1D_inst (
|
|
.DPO(DPO), // Read-only 1-bit data output for DPRA
|
|
.SPO(SPO), // Rw/ 1-bit data output for A0-A3
|
|
.A0(A0), // Rw/ address[0] input bit
|
|
.A1(A1), // Rw/ address[1] input bit
|
|
.A2(A2), // Rw/ address[2] input bit
|
|
.A3(A3), // Rw/ address[3] input bit
|
|
.D(D), // Write 1-bit data input
|
|
.DPRA0(DPRA0), // Read address[0] input bit
|
|
.DPRA1(DPRA1), // Read address[1] input bit
|
|
.DPRA2(DPRA2), // Read address[2] input bit
|
|
.DPRA3(DPRA3), // Read address[3] input bit
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM16X1D_inst instantiation
|
|
</Template>
|
|
<Template label="16 X 1 negedge write (RAM16X1D_1)" treetype="template">
|
|
// RAM16X1D_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM16X1D_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM16X1D_1: 16 x 1 negative edge write, asynchronous read dual-port distributed RAM
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM16X1D_1 #(
|
|
.INIT(16'h0000) // Initial contents of RAM
|
|
) RAM16X1D_1_inst (
|
|
.DPO(DPO), // Read-only 1-bit data output
|
|
.SPO(SPO), // Rw/ 1-bit data output
|
|
.A0(A0), // Rw/ address[0] input bit
|
|
.A1(A1), // Rw/ address[1] input bit
|
|
.A2(A2), // Rw/ address[2] input bit
|
|
.A3(A3), // Rw/ address[3] input bit
|
|
.D(D), // Write 1-bit data input
|
|
.DPRA0(DPRA0), // Read-only address[0] input bit
|
|
.DPRA1(DPRA1), // Read-only address[1] input bit
|
|
.DPRA2(DPRA2), // Read-only address[2] input bit
|
|
.DPRA3(DPRA3), // Read-only address[3] input bit
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM16X1D_1_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Block RAM" treetype="folder">
|
|
<Template label="16k + 2k parity parameterizable BlockRAM (RAMB16)" treetype="template">
|
|
// RAMB16 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB16_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB16: 16k+2k Parity parameterizable BlockRAM
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB16 #(
|
|
.DOA_REG(0), // Optional output registers on A port (0 or 1)
|
|
.DOB_REG(0), // Optional output registers on B port (0 or 1)
|
|
.INIT_A(36'h000000000), // Initial values on A output port
|
|
.INIT_B(36'h000000000), // Initial values on B output port
|
|
.INVERT_CLK_DOA_REG("FALSE"), // Invert clock on A port output registers ("TRUE" or "FALSE")
|
|
.INVERT_CLK_DOB_REG("FALSE"), // Invert clock on A port output registers ("TRUE" or "FALSE")
|
|
.RAM_EXTENSION_A("NONE"), // "UPPER", "LOWER" or "NONE" when cascaded
|
|
.RAM_EXTENSION_B("NONE"), // "UPPER", "LOWER" or "NONE" when cascaded
|
|
.READ_WIDTH_A(0), // Valid values are 1, 2, 4, 9, 18, or 36
|
|
.READ_WIDTH_B(0), // Valid values are 1, 2, 4, 9, 18, or 36
|
|
.SIM_COLLISION_CHECK("ALL"), // Collision check enable "ALL", "WARNING_ONLY",
|
|
// "GENERATE_X_ONLY" or "NONE"
|
|
.SRVAL_A(36'h000000000), // Set/Reset value for A port output
|
|
.SRVAL_B(36'h000000000), // Set/Reset value for B port output
|
|
.WRITE_MODE_A("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
|
|
.WRITE_MODE_B("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
|
|
.WRITE_WIDTH_A(2), // Valid values are 1, 2, 4, 9, 18, or 36
|
|
.WRITE_WIDTH_B(0), // Valid values are 1, 2, 4, 9, 18, or 36
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB16_inst (
|
|
.CASCADEOUTA(CASCADEOUTA), // 1-bit cascade output
|
|
.CASCADEOUTB(CASCADEOUTB), // 1-bit cascade output
|
|
.DOA(DOA), // 32-bit A port data output
|
|
.DOB(DOB), // 32-bit B port data output
|
|
.DOPA(DOPA), // 4-bit A port parity data output
|
|
.DOPB(DOPB), // 4-bit B port parity data output
|
|
.ADDRA(ADDRA), // 15-bit A port address input
|
|
.ADDRB(ADDRB), // 15-bit B port address input
|
|
.CASCADEINA(CASCADEINA), // 1-bit cascade A input
|
|
.CASCADEINB(CASCADEINB), // 1-bit cascade B input
|
|
.CLKA(CLKA), // 1-bit A port clock input
|
|
.CLKB(CLKB), // 1-bit B port clock input
|
|
.DIA(DIA), // 32-bit A port data input
|
|
.DIB(DIB), // 32-bit B port data input
|
|
.DIPA(DIPA), // 4-bit A port parity data input
|
|
.DIPB(DIPB), // 4-bit B port parity data input
|
|
.ENA(ENA), // 1-bit A port enable input
|
|
.ENB(ENB), // 1-bit B port enable input
|
|
.REGCEA(REGCEA), // 1-bit A port register enable input
|
|
.REGCEB(REGCEB), // 1-bit B port register enable input
|
|
.SSRA(SSRA), // 1-bit A port set/reset input
|
|
.SSRB(SSRB), // 1-bit B port set/reset input
|
|
.WEA(WEA), // 4-bit A port write enable input
|
|
.WEB(WEB) // 4-bit B port write enable input
|
|
);
|
|
|
|
// End of RAMB16_inst instantiation
|
|
</Template>
|
|
<SubFolder label="Async FIFO" treetype="folder">
|
|
<Template label="512 x 36 (FIFO16)" treetype="template">
|
|
// FIFO16 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FIFO16_512x36_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FIFO16: BlockRAM Asynchronous FIFO configured for 512 deep x 36 wide
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FIFO16 #(
|
|
.ALMOST_FULL_OFFSET(12'h080), // Sets almost full threshold
|
|
.ALMOST_EMPTY_OFFSET(12'h080), // Sets the almost empty threshold
|
|
.DATA_WIDTH(36), // Sets data width to 4, 9, 18, or 36
|
|
.FIRST_WORD_FALL_THROUGH("FALSE") // Sets the FIFO FWFT to "TRUE" or "FALSE"
|
|
) FIFO16_512x36_inst (
|
|
.ALMOSTEMPTY(ALMOSTEMPTY), // 1-bit almost empty output flag
|
|
.ALMOSTFULL(ALMOSTFULL), // 1-bit almost full output flag
|
|
.DO(DO), // 32-bit data output
|
|
.DOP(DOP), // 4-bit parity data output
|
|
.EMPTY(EMPTY), // 1-bit empty output flag
|
|
.FULL(FULL), // 1-bit full output flag
|
|
.RDCOUNT(RDCOUNT), // 12-bit read count output
|
|
.RDERR(RDERR), // 1-bit read error output
|
|
.WRCOUNT(WRCOUNT), // 12-bit write count output
|
|
.WRERR(WRERR), // 1-bit write error
|
|
.DI(DI), // 32-bit data input
|
|
.DIP(DIP), // 4-bit parity input
|
|
.RDCLK(RDCLK), // 1-bit read clock input
|
|
.RDEN(RDEN), // 1-bit read enable input
|
|
.RST(RST), // 1-bit reset input
|
|
.WRCLK(WRCLK), // 1-bit write clock input
|
|
.WREN(WREN) // 1-bit write enable input
|
|
);
|
|
|
|
// End of FIFO16_512x36_inst instantiation
|
|
</Template>
|
|
<Template label="1k x 18 (FIFO16)" treetype="template">
|
|
// FIFO16 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FIFO16_1kx18_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FIFO16: BlockRAM Asynchronous FIFO configured for 1k deep x 18 wide
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
wire [17:0] unconnected;
|
|
|
|
FIFO16 #(
|
|
.ALMOST_FULL_OFFSET(12'h080), // Sets almost full threshold
|
|
.ALMOST_EMPTY_OFFSET(12'h080), // Sets the almost empty threshold
|
|
.DATA_WIDTH(18), // Sets data width to 4, 9, 18, or 36
|
|
.FIRST_WORD_FALL_THROUGH("FALSE") // Sets the FIFO FWFT to "TRUE" or "FALSE"
|
|
) FIFO16_1kx18_inst (
|
|
.ALMOSTEMPTY(ALMOSTEMPTY), // 1-bit almost empty output flag
|
|
.ALMOSTFULL(ALMOSTFULL), // 1-bit almost full output flag
|
|
.DO({unconnected[15:0], DO}), // 16-bit data output
|
|
.DOP({unconnected[17:16], DOP}), // 2-bit parity data output
|
|
.EMPTY(EMPTY), // 1-bit empty output flag
|
|
.FULL(FULL), // 1-bit full output flag
|
|
.RDCOUNT(RDCOUNT), // 12-bit read count output
|
|
.RDERR(RDERR), // 1-bit read error output
|
|
.WRCOUNT(WRCOUNT), // 12-bit write count output
|
|
.WRERR(WRERR), // 1-bit write error
|
|
.DI({16'h0000, DI}), // 16-bit data input (rest tied to ground)
|
|
.DIP({2'b00, DIP}), // 2-bit parity input (rest tied to ground)
|
|
.RDCLK(RDCLK), // 1-bit read clock input
|
|
.RDEN(RDEN), // 1-bit read enable input
|
|
.RST(RST), // 1-bit reset input
|
|
.WRCLK(WRCLK), // 1-bit write clock input
|
|
.WREN(WREN) // 1-bit write enable input
|
|
);
|
|
|
|
// End of FIFO16_1kx18_inst instantiation
|
|
</Template>
|
|
<Template label="2k x 9 (FIFO16)" treetype="template">
|
|
// FIFO16 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FIFO16_2kx9_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FIFO16: BlockRAM Asynchronous FIFO configured for 2k deep x 9 wide
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
wire [26:0] unconnected;
|
|
|
|
FIFO16 #(
|
|
.ALMOST_FULL_OFFSET(12'h080), // Sets almost full threshold
|
|
.ALMOST_EMPTY_OFFSET(12'h080), // Sets the almost empty threshold
|
|
.DATA_WIDTH(9), // Sets data width to 4, 9, 18, or 36
|
|
.FIRST_WORD_FALL_THROUGH("FALSE") // Sets the FIFO FWFT to "TRUE" or "FALSE"
|
|
) FIFO16_2kx9_inst (
|
|
.ALMOSTEMPTY(ALMOSTEMPTY), // 1-bit almost empty output flag
|
|
.ALMOSTFULL(ALMOSTFULL), // 1-bit almost full output flag
|
|
.DO({unconnected[23:0], DO}), // 8-bit data output
|
|
.DOP({unconnected[26:24], DOP}), // 1-bit parity data output
|
|
.EMPTY(EMPTY), // 1-bit empty output flag
|
|
.FULL(FULL), // 1-bit full output flag
|
|
.RDCOUNT(RDCOUNT), // 12-bit read count output
|
|
.RDERR(RDERR), // 1-bit read error output
|
|
.WRCOUNT(WRCOUNT), // 12-bit write count output
|
|
.WRERR(WRERR), // 1-bit write error
|
|
.DI({24'h000000, DI}), // 8-bit data input (rest tied to ground)
|
|
.DIP({3'b000, DIP}), // 1-bit parity input (rest tied to ground)
|
|
.RDCLK(RDCLK), // 1-bit read clock input
|
|
.RDEN(RDEN), // 1-bit read enable input
|
|
.RST(RST), // 1-bit reset input
|
|
.WRCLK(WRCLK), // 1-bit write clock input
|
|
.WREN(WREN) // 1-bit write enable input
|
|
);
|
|
|
|
// End of FIFO16_2kx9_inst instantiation
|
|
</Template>
|
|
<Template label="4k x 4 (FIFO16)" treetype="template">
|
|
// FIFO16 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FIFO16_4kx4_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FIFO16: BlockRAM Asynchronous FIFO configured for 4k deep x 4 wide
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
wire [27:0] unconnected;
|
|
|
|
FIFO16 #(
|
|
.ALMOST_FULL_OFFSET(12'h080), // Sets almost full threshold
|
|
.ALMOST_EMPTY_OFFSET(12'h080), // Sets the almost empty threshold
|
|
.DATA_WIDTH(4), // Sets data width to 4, 9, 18, or 36
|
|
.FIRST_WORD_FALL_THROUGH("FALSE") // Sets the FIFO FWFT to "TRUE" or "FALSE"
|
|
) FIFO16_4kx4_inst (
|
|
.ALMOSTEMPTY(ALMOSTEMPTY), // 1-bit almost empty output flag
|
|
.ALMOSTFULL(ALMOSTFULL), // 1-bit almost full output flag
|
|
.DO({unconnected[27:0], DO}), // 4-bit data output
|
|
.EMPTY(EMPTY), // 1-bit empty output flag
|
|
.FULL(FULL), // 1-bit full output flag
|
|
.RDCOUNT(RDCOUNT), // 12-bit read count output
|
|
.RDERR(RDERR), // 1-bit read error output
|
|
.WRCOUNT(WRCOUNT), // 12-bit write count output
|
|
.WRERR(WRERR), // 1-bit write error
|
|
.DI({28'h0000000, DI}), // 4-bit data input (rest tied to ground)
|
|
.DIP(4'h0), // Parity bits tied to Ground
|
|
.RDCLK(RDCLK), // 1-bit read clock input
|
|
.RDEN(RDEN), // 1-bit read enable input
|
|
.RST(RST), // 1-bit reset input
|
|
.WRCLK(WRCLK), // 1-bit write clock input
|
|
.WREN(WREN) // 1-bit write enable input
|
|
);
|
|
|
|
// End of FIFO16_4kx4_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<Template label="512 x 64 ECC RAM (RAMB32_S64_ECC)" treetype="template">
|
|
// RAMB32_S64_ECC: In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB32_S64_ECC_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB32_S64_ECC: 512 x 64 Error Correction BlockRAM
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB32_S64_ECC #(
|
|
.DO_REG(0), // Optional output registers (0 or 1)
|
|
.SIM_COLLISION_CHECK("ALL") // Collision check enable "ALL",
|
|
//"WARNING_ONLY", "GENERATE_X_ONLY"
|
|
) RAMB32_S64_ECC_inst (
|
|
.DO(DO), // 64-bit output data
|
|
.STATUS(STATUS), // 2-bit status output
|
|
.DI(DI), // 64-bit data input
|
|
.RDADDR(RDADDR), // 9-bit data address input
|
|
.RDCLK(RDCLK), // 1-bit read clock input
|
|
.RDEN(RDEN), // 1-bit read enable input
|
|
.SSR(1'b0), // Always tie to ground
|
|
.WRADDR(WRADDR), // 9-bit write address input
|
|
.WRCLK(WRCLK), // 1-bit write clock input
|
|
.WREN(WREN) // 1-bit write enable input
|
|
);
|
|
|
|
// End of RAMB32_S64_ECC_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Arithmetic Functions" treetype="folder">
|
|
<Template label="DSP Block (DSP48)" treetype="template">
|
|
// DSP48 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (DSP48_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// DSP48: DSP Function Block
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
DSP48 #(
|
|
.AREG(1), // Number of pipeline registers on the A input, 0, 1 or 2
|
|
.BREG(1), // Number of pipeline registers on the B input, 0, 1 or 2
|
|
.B_INPUT("DIRECT"), // B input DIRECT from fabric or CASCADE from another DSP48
|
|
.CARRYINREG(1), // Number of pipeline registers for the CARRYIN input, 0 or 1
|
|
.CARRYINSELREG(1), // Number of pipeline registers for the CARRYINSEL, 0 or 1
|
|
.CREG(1), // Number of pipeline registers on the C input, 0 or 1
|
|
.LEGACY_MODE("MULT18X18S"), // Backward compatibility, NONE, MULT18X18 or MULT18X18S
|
|
.MREG(1), // Number of multiplier pipeline registers, 0 or 1
|
|
.OPMODEREG(1), // Number of pipeline regsiters on OPMODE input, 0 or 1
|
|
.PREG(1), // Number of pipeline registers on the P output, 0 or 1
|
|
.SUBTRACTREG(1) // Number of pipeline registers on the SUBTRACT input, 0 or 1
|
|
) DSP48_inst (
|
|
.BCOUT(BCOUT), // 18-bit B cascade output
|
|
.P(P), // 48-bit product output
|
|
.PCOUT(PCOUT), // 48-bit cascade output
|
|
.A(A), // 18-bit A data input
|
|
.B(B), // 18-bit B data input
|
|
.BCIN(BCIN), // 18-bit B cascade input
|
|
.C(C), // 48-bit cascade input
|
|
.CARRYIN(CARRYIN), // Carry input signal
|
|
.CARRYINSEL(CARRYINSEL), // 2-bit carry input select
|
|
.CEA(CEA), // A data clock enable input
|
|
.CEB(CEB), // B data clock enable input
|
|
.CEC(CEC), // C data clock enable input
|
|
.CECARRYIN(CECARRYIN), // CARRYIN clock enable input
|
|
.CECINSUB(CECINSUB), // CINSUB clock enable input
|
|
.CECTRL(CECTRL), // Clock Enable input for CTRL regsiters
|
|
.CEM(CEM), // Clock Enable input for multiplier regsiters
|
|
.CEP(CEP), // Clock Enable input for P regsiters
|
|
.CLK(CLK), // Clock input
|
|
.OPMODE(OPMODE), // 7-bit operation mode input
|
|
.PCIN(PCIN), // 48-bit PCIN input
|
|
.RSTA(RSTA), // Reset input for A pipeline registers
|
|
.RSTB(RSTB), // Reset input for B pipeline registers
|
|
.RSTC(RSTC), // Reset input for C pipeline registers
|
|
.RSTCARRYIN(RSTCARRYIN), // Reset input for CARRYIN registers
|
|
.RSTCTRL(RSTCTRL), // Reset input for CTRL registers
|
|
.RSTM(RSTM), // Reset input for multiplier registers
|
|
.RSTP(RSTP), // Reset input for P pipeline registers
|
|
.SUBTRACT(SUBTRACT) // SUBTRACT input
|
|
);
|
|
|
|
// End of DSP48_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Config/BSCAN Components" treetype="folder">
|
|
<Template label="STARTUP (STARTUP_VIRTEX4)" treetype="template">
|
|
// STARTUP_VIRTEX4 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (STARTUP_VIRTEX4_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// STARTUP_VIRTEX4: Startup primitive for GSR, GTS or startup sequence
|
|
// control.
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
STARTUP_VIRTEX4 STARTUP_VIRTEX4_inst (
|
|
.EOS(EOS), // End Of Startup 1-bit output
|
|
.CLK(CLK), // Clock input for start-up sequence
|
|
.GSR(GSR_PORT), // Global Set/Reset input (GSR cannot be used as a port name)
|
|
.GTS(GTS_PORT), // Global 3-state input (GTS cannot be used as a port name)
|
|
.USRCCLKO(USRCCLKO), // USERCLK0 1-bit input
|
|
.USRCCLKTS(USRCCLKTS), // USERCLKTS 1-bit input
|
|
.USRDONEO(USRDONEO), // USRDONE0 1-bit input
|
|
.USRDONETS(USRDONETS) // USRDONETS 1-bit input
|
|
);
|
|
|
|
// End of STARTUP_VIRTEX4_inst instantiation
|
|
</Template>
|
|
<Template label="BSCAN (BSCAN_VIRTEX4)" treetype="template">
|
|
// BSCAN_VIRTEX4 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BSCAN_VIRTEX4_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BSCAN_VIRTEX4: Boundary Scan primitive for connecting internal logic to
|
|
// JTAG interface.
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BSCAN_VIRTEX4 #(
|
|
.JTAG_CHAIN(1) // Possible values: 1, 2, 3, or 4
|
|
) BSCAN_VIRTEX4_inst (
|
|
.CAPTURE(CAPTURE), // CAPTURE output from TAP controller
|
|
.DRCK(DRCK), // Data register output for USER function
|
|
.RESET(RESET), // Reset output from TAP controller
|
|
.SEL(SEL), // USER active output
|
|
.SHIFT(SHIFT), // SHIFT output from TAP controller
|
|
.TDI(TDI), // TDI output from TAP controller
|
|
.UPDATE(UPDATE), // UPDATE output from TAP controller
|
|
.TDO(TDO) // Data input for USER function
|
|
);
|
|
|
|
// End of BSCAN_VIRTEX4_inst instantiation
|
|
</Template>
|
|
<Template label="JTAG Simulation Model (JTAG_SIM_VIRTEX4)" treetype="template">
|
|
// JTAG_SIM_VIRTEX4 : In order to use this simulation model, the
|
|
// Verilog : forllowing instance declaration needs to be placed
|
|
// instance : in the testbench code to simulate the design. This
|
|
// declaration : should not be instantiated into synthesizable design code.
|
|
// code : None of the ports need to be connected to the design
|
|
// : as communication is handled through the glbl.v module.
|
|
// : All ports can be connected to reg/wires in the testbench.
|
|
// : Only one JTAG_SIM_VIRTEX4 should be instantiated per design.
|
|
// : All inputs and outputs should be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// JTAG_SIM_VIRTEX4: JTAG Interface Simulation Model
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
JTAG_SIM_VIRTEX4 #(
|
|
.PART_NAME("LX15") // Specify target V4 device. Possible values are:
|
|
// "LX15", "LX25", "LX40", "LX60", "LX80", "LX100", "LX160",
|
|
// "LX200", "SX25", "SX35", "SX55", "FX12", "FX20"
|
|
) JTAG_SIM_VIRTEX4_inst (
|
|
.TDO(TDO), // JTAG data output (1-bit)
|
|
.TCK(TCK), // Clock input (1-bit)
|
|
.TDI(TDI), // JTAG data input (1-bit)
|
|
.TMS(TMS) // JTAG command input (1-bit)
|
|
);
|
|
|
|
// End of JTAG_SIM_VIRTEX4_inst instantiation
|
|
</Template>
|
|
<Template label="Capture (CAPTURE_VIRTEX4)" treetype="template">
|
|
// CAPTURE_VIRTEX4 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (CAPTURE_VIRTEX4_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// CAPTURE_VIRTEX4: Register State Capture for Bitstream Readback
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
CAPTURE_VIRTEX4 #(
|
|
.ONESHOT("TRUE") // "TRUE" or "FALSE"
|
|
) CAPTURE_VIRTEX4_inst (
|
|
.CAP(CAP), // Capture input
|
|
.CLK(CLK) // Clock input
|
|
);
|
|
|
|
// End of CAPTURE_VIRTEX4_inst instantiation
|
|
</Template>
|
|
<Template label="Internal Config Access Port (ICAP_VIRTEX4)" treetype="template">
|
|
// ICAP_VIRTEX4 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ICAP_VIRTEX4_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ICAP_VIRTEX4: Internal Configuration Access Port
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ICAP_VIRTEX4 #(
|
|
.ICAP_WIDTH("X8") // "X8" or "X32"
|
|
) ICAP_VIRTEX4_inst (
|
|
.BUSY(BUSY), // Busy output
|
|
.O(O), // 32-bit data output
|
|
.CE(CE), // Clock enable input
|
|
.CLK(CLK), // Clock input
|
|
.I(I), // 32-bit data input
|
|
.WRITE(WRITE) // Write input
|
|
);
|
|
|
|
// End of ICAP_VIRTEX4_inst instantiation
|
|
</Template>
|
|
<Template label="Config Frame Error Correction (FRAME_ECC_VIRTEX4)" treetype="template">
|
|
// FRAME_ECC_VIRTEX4 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FRAME_ECC_VIRTEX4_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FRAME_ECC_VIRTEX4: Configuration Frame Error Correction Circuitry
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FRAME_ECC_VIRTEX4 FRAME_ECC_VIRTEX4_inst (
|
|
.ERROR(ERROR), // 1-bit output indicating an error
|
|
.SYNDROME(SYNDROME), // 12-bit output location of erroroneous bit
|
|
.SYNDROMEVALID(SYNDROMEVALID) // 1-bit output indicating 0, 1 or 2 bit errors in frame
|
|
);
|
|
|
|
// End of FRAME_ECC_VIRTEX4_inst instantiation
|
|
</Template>
|
|
<Template label="Config Data Access (USR_ACCESS_VIRTEX4)" treetype="template">
|
|
// USR_ACCESS_VIRTEX4 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (USR_ACCESS_VIRTEX4_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// USR_ACCESS_VIRTEX4: Configuration Data Memory Access Port
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
USR_ACCESS_VIRTEX4 USR_ACCESS_VIRTEX4_inst (
|
|
.DATA(DATA), // 32-bit config data output
|
|
.DATAVALID(DATAVALID) // 1-bit data valid output
|
|
);
|
|
|
|
// End of USR_ACCESS_VIRTEX4_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="I/O Components" treetype="folder">
|
|
<SubFolder label="Input" treetype="folder">
|
|
<Template label="Single-ended Buffer (IBUF)" treetype="template">
|
|
// IBUF : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUF_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUF: Single-ended Input Buffer
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUF #(
|
|
.CAPACITANCE("DONT_CARE"), // "DONT_CARE". "LOW" or "NORMAL" (Virtex-4 only)
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
)IBUF_inst (
|
|
.O(O), // Buffer output
|
|
.I(I) // Buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUF_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer (IBUFDS)" treetype="template">
|
|
// IBUFDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFDS: Differential Input Buffer
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFDS #(
|
|
.CAPACITANCE("DONT_CARE"), // "LOW", "NORMAL", "DONT_CARE" (Virtex-4 only)
|
|
.DIFF_TERM("FALSE"), // Differential Termination
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
) IBUFDS_inst (
|
|
.O(O), // Buffer output
|
|
.I(I), // Diff_p buffer input (connect directly to top-level port)
|
|
.IB(IB) // Diff_n buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUFDS_inst instantiation
|
|
</Template>
|
|
<Template label="Single-ended Global Clock (IBUFG)" treetype="template">
|
|
// IBUFG : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFG_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFG: Single-ended global clock input buffer
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFG #(
|
|
.CAPACITANCE("DONT_CARE"), // "DONT_CARE". "LOW" or "NORMAL" (Virtex-4 only)
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
) IBUFG_inst (
|
|
.O(O), // Clock buffer output
|
|
.I(I) // Clock buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUFG_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Global Clock (IBUFGDS)" treetype="template">
|
|
// IBUFGDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFGDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFGDS: Differential Global Clock Input Buffer
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFGDS #(
|
|
.CAPACITANCE("DONT_CARE"), // "DONT_CARE". "LOW" or "NORMAL" (Virtex-4 only)
|
|
.DIFF_TERM("FALSE"), // Differential Termination
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
) IBUFGDS_inst (
|
|
.O(O), // Clock buffer output
|
|
.I(I), // Diff_p clock buffer input (connect directly to top-level port)
|
|
.IB(IB) // Diff_n clock buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUFGDS_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Output" treetype="folder">
|
|
<Template label="Single-ended Buffer (OBUF)" treetype="template">
|
|
// OBUF : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OBUF_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OBUF: Single-ended Output Buffer
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OBUF #(
|
|
.CAPACITANCE("DONT_CARE"), // "DONT_CARE". "LOW" or "NORMAL" (Virtex-4 only)
|
|
.DRIVE(12), // Specify the output drive strength
|
|
.IOSTANDARD("DEFAULT"), // Specify the output I/O standard
|
|
.SLEW("SLOW") // Specify the output slew rate
|
|
) OBUF_inst (
|
|
.O(O), // Buffer output (connect directly to top-level port)
|
|
.I(I) // Buffer input
|
|
);
|
|
|
|
// End of OBUF_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer (OBUFDS)" treetype="template">
|
|
|
|
// OBUFDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OBUFDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OBUFDS: Differential Output Buffer
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OBUFDS #(
|
|
.CAPACITANCE("DONT_CARE"), // "DONT_CARE". "LOW" or "NORMAL" (Virtex-4 only)
|
|
.IOSTANDARD("DEFAULT") // Specify the output I/O standard
|
|
) OBUFDS_inst (
|
|
.O(O), // Diff_p output (connect directly to top-level port)
|
|
.OB(OB), // Diff_n output (connect directly to top-level port)
|
|
.I(I) // Buffer input
|
|
);
|
|
|
|
// End of OBUFDS_inst instantiation
|
|
</Template>
|
|
<Template label="Single-ended 3-state Buffer (OBUFT)" treetype="template">
|
|
// OBUFT : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OBUFT_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OBUFT: Single-ended 3-state Output Buffer
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OBUFT #(
|
|
.CAPACITANCE("DONT_CARE"), // "DONT_CARE". "LOW" or "NORMAL" (Virtex-4 only)
|
|
.DRIVE(12), // Specify the output drive strength
|
|
.IOSTANDARD("DEFAULT"), // Specify the output I/O standard
|
|
.SLEW("SLOW") // Specify the output slew rate
|
|
) OBUFT_inst (
|
|
.O(O), // Buffer output (connect directly to top-level port)
|
|
.I(I), // Buffer input
|
|
.T(T) // 3-state enable input
|
|
);
|
|
|
|
// End of OBUFT_inst instantiation
|
|
</Template>
|
|
<Template label="Differential 3-state Buffer (OBUFTDS)" treetype="template">
|
|
// OBUFTDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OBUFTDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OBUFTDS: Differential 3-state Output Buffer
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OBUFTDS #(
|
|
.CAPACITANCE("DONT_CARE"), // "DONT_CARE". "LOW" or "NORMAL" (Virtex-4 only)
|
|
.IOSTANDARD("DEFAULT") // Specify the output I/O standard
|
|
) OBUFTDS_inst (
|
|
.O(O), // Diff_p output (connect directly to top-level port)
|
|
.OB(OB), // Diff_n output (connect directly to top-level port)
|
|
.I(I), // Buffer input
|
|
.T(T) // 3-state enable input
|
|
);
|
|
|
|
// End of OBUFTDS_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<Template label="Digital Controlled Impedance Reset (DCIRESET)" treetype="template">
|
|
// DCIRESET : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (DCIRESET_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// DCIRESET: Digital Controlled Impedance (DCI) Reset Component
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
DCIRESET DCIRESET_inst (
|
|
.LOCKED(LOCKED), // 1-bit DCI LOCKED Output
|
|
.RST(RST) // 1-bit DCI Reset Input
|
|
);
|
|
|
|
// End of DCIRESET_inst instantiation
|
|
</Template>
|
|
<SubFolder label="Bi-directional" treetype="folder">
|
|
<Template label="Single-ended Buffer (IOBUF)" treetype="template">
|
|
// IOBUF : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IOBUF_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IOBUF: Single-ended Bi-directional Buffer
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IOBUF #(
|
|
.CAPACITANCE("DONT_CARE"), // "DONT_CARE". "LOW" or "NORMAL" (Virtex-4 only)
|
|
.DRIVE(12), // Specify the output drive strength
|
|
.IOSTANDARD("DEFAULT"), // Specify the I/O standard
|
|
.SLEW("SLOW") // Specify the output slew rate
|
|
) IOBUF_inst (
|
|
.O(O), // Buffer output
|
|
.IO(IO), // Buffer inout port (connect directly to top-level port)
|
|
.I(I), // Buffer input
|
|
.T(T) // 3-state enable input, high=input, low=output
|
|
);
|
|
|
|
// End of IOBUF_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer (IOBUFDS)" treetype="template">
|
|
// IOBUFDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IOBUFDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IOBUFDS: Differential Bi-directional Buffer
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IOBUFDS #(
|
|
.CAPACITANCE("DONT_CARE"), // "DONT_CARE". "LOW" or "NORMAL" (Virtex-4 only)
|
|
.IOSTANDARD("BLVDS_25") // Specify the I/O standard
|
|
) IOBUFDS_inst (
|
|
.O(O), // Buffer output
|
|
.IO(IO), // Diff_p inout (connect directly to top-level port)
|
|
.IOB(IOB), // Diff_n inout (connect directly to top-level port)
|
|
.I(I), // Buffer input
|
|
.T(T) // 3-state enable input, high=input, low=output
|
|
);
|
|
|
|
// End of IOBUFDS_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Weak drivers" treetype="folder">
|
|
<Template label="PULLUP" treetype="template">
|
|
// PULLUP : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (PULLUP_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design.
|
|
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// PULLUP: I/O Buffer Weak Pull-up
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
PULLUP PULLUP_inst (
|
|
.O(O) // Pullup output (connect directly to top-level port)
|
|
);
|
|
|
|
// End of PULLUP_inst instantiation
|
|
</Template>
|
|
<Template label="PULLDOWN" treetype="template">
|
|
// PULLDOWN : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (PULLDOWN_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// PULLDOWN: I/O Buffer Weak Pull-down
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
PULLDOWN PULLDOWN_inst (
|
|
.O(O) // Pulldown output (connect directly to top-level port)
|
|
);
|
|
|
|
// End of PULLDOWN_inst instantiation
|
|
</Template>
|
|
<Template label="KEEPER" treetype="template">
|
|
// KEEPER : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (KEEPER_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// KEEPER: I/O Buffer Weak Keeper
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
KEEPER KEEPER_inst (
|
|
.O(O) // Keeper output (connect directly to top-level port)
|
|
);
|
|
|
|
// End of KEEPER_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="SERDES and Delay Components" treetype="folder">
|
|
<Template label="Input Delay Element (IDELAY)" treetype="template">
|
|
// IDELAY : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IDELAY_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IDELAY: Input Delay Element
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
(* IODELAY_GROUP = "<iodelay_group_name>" *) // Specifies group name for associated IDELAYs and IDELAYCTRL
|
|
IDELAY #(
|
|
.IOBDELAY_TYPE("FIXED"), // "FIXED" or "VARIABLE"
|
|
.IOBDELAY_VALUE(0) // Any value from 0 to 63
|
|
) IDELAY_inst (
|
|
.O(O), // 1-bit output
|
|
.C(C), // 1-bit clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.I(I), // 1-bit data input
|
|
.INC(INC), // 1-bit increment input
|
|
.RST(RST) // 1-bit reset input
|
|
);
|
|
|
|
// End of IDELAY_inst instantiation
|
|
</Template>
|
|
<Template label="Input Delay Control Element (IDELAYCTRL)" treetype="template">
|
|
// IDELAYCTRL : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IDELAYCTRL_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IDELAYCTRL: Input Delay Control Element (Must be used in conjunction with the IDELAY
|
|
// when used in FIXED or VARIABLE tap-delay mode)
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
(* IODELAY_GROUP = "<iodelay_group_name>" *) // Specifies group name for associated IDELAYs and IDELAYCTRL
|
|
IDELAYCTRL IDELAYCTRL_inst (
|
|
.RDY(RDY), // 1-bit ready output
|
|
.REFCLK(REFCLK), // 1-bit reference clock input
|
|
.RST(RST) // 1-bit reset input
|
|
);
|
|
|
|
// End of IDELAYCTRL_inst instantiation
|
|
</Template>
|
|
<Template label="Input SERDES (ISERDES)" treetype="template">
|
|
// ISERDES : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ISERDES_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ISERDES: Source Synchronous Input Deserializer
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ISERDES #(
|
|
.BITSLIP_ENABLE("FALSE"), // "TRUE"/"FALSE" to enable bitslip controller
|
|
// Must be "FALSE" if INTERFACE_TYPE set to "MEMORY"
|
|
.DATA_RATE("DDR"), // Specify data rate of "DDR" or "SDR"
|
|
.DATA_WIDTH(4), // Specify data width - for DDR 4,6,8, or 10
|
|
// for SDR 2,3,4,5,6,7, or 8
|
|
.INTERFACE_TYPE("MEMORY"), // Use model - "MEMORY" or "NETWORKING"
|
|
.IOBDELAY("NONE"), // Specify outputs where delay chain will be applied
|
|
// "NONE", "IBUF", "IFD", or "BOTH"
|
|
.IOBDELAY_TYPE("DEFAULT"), // Set tap delay "DEFAULT", "FIXED", or "VARIABLE"
|
|
.IOBDELAY_VALUE(0), // Set initial tap delay to an integer from 0 to 63
|
|
.NUM_CE(2), // Define number or clock enables to an integer of 1 or 2
|
|
.SERDES_MODE("MASTER") // Set SERDES mode to "MASTER" or "SLAVE"
|
|
) ISERDES_inst (
|
|
.O(O), // 1-bit combinatorial output
|
|
.Q1(Q1), // 1-bit registered output
|
|
.Q2(Q2), // 1-bit registered output
|
|
.Q3(Q3), // 1-bit registered output
|
|
.Q4(Q4), // 1-bit registered output
|
|
.Q5(Q5), // 1-bit registered output
|
|
.Q6(Q6), // 1-bit registered output
|
|
.SHIFTOUT1(SHIFTOUT1), // 1-bit carry output
|
|
.SHIFTOUT2(SHIFTOUT2), // 1-bit carry output
|
|
.BITSLIP(BITSLIP), // 1-bit Bitslip input
|
|
.CE1(CE1), // 1-bit clock enable input
|
|
.CE2(CE2), // 1-bit clock enable input
|
|
.CLK(CLK), // 1-bit clock input
|
|
.CLKDIV(CLKDIV), // 1-bit divided clock input
|
|
.D(D), // 1-bit serial data input
|
|
.DLYCE(DLYCE), // 1-bit delay chain enable input
|
|
.DLYINC(DLYINC), // 1-bit delay increment/decrement input
|
|
.DLYRST(DLYRST), // 1-bit delay chain reset input
|
|
.OCLK(OCLK), // 1-bit high-speed clock input
|
|
.REV(1'b0), // Must be tied to logic zero
|
|
.SHIFTIN1(SHIFTIN1), // 1-bit carry input
|
|
.SHIFTIN2(SHIFTIN2), // 1-bit carry input
|
|
.SR(SR) // 1-bit set/reset input
|
|
);
|
|
|
|
// End of ISERDES_inst instantiation
|
|
</Template>
|
|
<Template label="Output SERDES (OSERDES)" treetype="template">
|
|
// OSERDES : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OSERDES_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OSERDES: Source Synchronous Output Serializer
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OSERDES #(
|
|
.DATA_RATE_OQ("DDR"), // Specify data rate to "DDR" or "SDR"
|
|
.DATA_RATE_TQ("DDR"), // Specify data rate to "DDR", "SDR", or "BUF"
|
|
.DATA_WIDTH(4), // Specify data width - for DDR: 4,6,8, or 10
|
|
// for SDR or BUF: 2,3,4,5,6,7, or 8
|
|
.INIT_OQ(1'b0), // INIT for OQ register - 1'b1 or 1'b0
|
|
.INIT_TQ(1'b0), // INIT for OQ register - 1'b1 or 1'b0
|
|
.SERDES_MODE("MASTER"), // Set SERDES mode to "MASTER" or "SLAVE"
|
|
.SRVAL_OQ(1'b0), // Define OQ output value upon SR assertion - 1'b1 or 1'b0
|
|
.SRVAL_TQ(1'b0), // Define TQ output value upon SR assertion - 1'b1 or 1'b0
|
|
.TRISTATE_WIDTH(4) // Specify parallel to serial converter width
|
|
// When DATA_RATE_TQ = DDR: 2 or 4
|
|
// When DATA_RATE_TQ = SDR or BUF: 1
|
|
) OSERDES_inst (
|
|
.OQ(OQ), // 1-bit data path output
|
|
.SHIFTOUT1(SHIFTOUT1), // 1-bit data expansion output
|
|
.SHIFTOUT2(SHIFTOUT2), // 1-bit data expansion output
|
|
.TQ(TQ), // 1-bit 3-state control output
|
|
.CLK(CLK), // 1-bit clock input
|
|
.CLKDIV(CLKDIV), // 1-bit divided clock input
|
|
.D1(D1), // 1-bit parallel data input
|
|
.D2(D2), // 1-bit parallel data input
|
|
.D3(D3), // 1-bit parallel data input
|
|
.D4(D4), // 1-bit parallel data input
|
|
.D5(D5), // 1-bit parallel data input
|
|
.D6(D6), // 1-bit parallel data input
|
|
.OCE(OCE), // 1-bit clock enable input
|
|
.REV(1'b0), // Must be tied to logic zero
|
|
.SHIFTIN1(SHIFTIN1), // 1-bit data expansion input
|
|
.SHIFTIN2(SHIFTIN2), // 1-bit data expansion input
|
|
.SR(SR), // 1-bit set/reset input
|
|
.T1(T1), // 1-bit parallel 3-state input
|
|
.T2(T2), // 1-bit parallel 3-state input
|
|
.T3(T3), // 1-bit parallel 3-state input
|
|
.T4(T4), // 1-bit parallel 3-state input
|
|
.TCE(TCE) // 1-bit 3-state signal clock enable input
|
|
);
|
|
|
|
// End of OSERDES_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="DDR Registers" treetype="folder">
|
|
<Template label="Input DDR Register (IDDR)" treetype="template">
|
|
// IDDR : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IDDR_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IDDR: Input Double Data Rate Input Register with Set, Reset
|
|
// and Clock Enable.
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IDDR #(
|
|
.DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE", "SAME_EDGE"
|
|
// or "SAME_EDGE_PIPELINED"
|
|
.INIT_Q1(1'b0), // Initial value of Q1: 1'b0 or 1'b1
|
|
.INIT_Q2(1'b0), // Initial value of Q2: 1'b0 or 1'b1
|
|
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
|
|
) IDDR_inst (
|
|
.Q1(Q1), // 1-bit output for positive edge of clock
|
|
.Q2(Q2), // 1-bit output for negative edge of clock
|
|
.C(C), // 1-bit clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.D(D), // 1-bit DDR data input
|
|
.R(R), // 1-bit reset
|
|
.S(S) // 1-bit set
|
|
);
|
|
|
|
// End of IDDR_inst instantiation
|
|
</Template>
|
|
<Template label="Output DDR Register (ODDR)" treetype="template">
|
|
// ODDR : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ODDR_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ODDR: Output Double Data Rate Output Register with Set, Reset
|
|
// and Clock Enable.
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ODDR #(
|
|
.DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE"
|
|
.INIT(1'b0), // Initial value of Q: 1'b0 or 1'b1
|
|
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
|
|
) ODDR_inst (
|
|
.Q(Q), // 1-bit DDR output
|
|
.C(C), // 1-bit clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.D1(D1), // 1-bit data input (positive edge)
|
|
.D2(D2), // 1-bit data input (negative edge)
|
|
.R(R), // 1-bit reset
|
|
.S(S) // 1-bit set
|
|
);
|
|
|
|
// End of ODDR_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Registers & Latches" treetype="folder">
|
|
<SubFolder label="Double Data Rate (DDR)" treetype="folder">
|
|
<Template label="Input DDR Register (IDDR)" treetype="template">
|
|
// IDDR : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IDDR_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IDDR: Input Double Data Rate Input Register with Set, Reset
|
|
// and Clock Enable.
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IDDR #(
|
|
.DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE", "SAME_EDGE"
|
|
// or "SAME_EDGE_PIPELINED"
|
|
.INIT_Q1(1'b0), // Initial value of Q1: 1'b0 or 1'b1
|
|
.INIT_Q2(1'b0), // Initial value of Q2: 1'b0 or 1'b1
|
|
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
|
|
) IDDR_inst (
|
|
.Q1(Q1), // 1-bit output for positive edge of clock
|
|
.Q2(Q2), // 1-bit output for negative edge of clock
|
|
.C(C), // 1-bit clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.D(D), // 1-bit DDR data input
|
|
.R(R), // 1-bit reset
|
|
.S(S) // 1-bit set
|
|
);
|
|
|
|
// End of IDDR_inst instantiation
|
|
</Template>
|
|
<Template label="Output DDR Register (ODDR)" treetype="template">
|
|
// ODDR : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ODDR_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ODDR: Output Double Data Rate Output Register with Set, Reset
|
|
// and Clock Enable.
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ODDR #(
|
|
.DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE"
|
|
.INIT(1'b0), // Initial value of Q: 1'b0 or 1'b1
|
|
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
|
|
) ODDR_inst (
|
|
.Q(Q), // 1-bit DDR output
|
|
.C(C), // 1-bit clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.D1(D1), // 1-bit data input (positive edge)
|
|
.D2(D2), // 1-bit data input (negative edge)
|
|
.R(R), // 1-bit reset
|
|
.S(S) // 1-bit set
|
|
);
|
|
|
|
// End of ODDR_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Single Data Rate" treetype="folder">
|
|
<Template label="Posedge D-FF w/ Async Clear, Set and CE (FDCPE)" treetype="template">
|
|
// FDCPE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FDCPE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FDCPE: Single Data Rate D Flip-Flop with Asynchronous Clear, Set and
|
|
// Clock Enable (posedge clk).
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FDCPE #(
|
|
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
|
|
) FDCPE_inst (
|
|
.Q(Q), // Data output
|
|
.C(C), // Clock input
|
|
.CE(CE), // Clock enable input
|
|
.CLR(CLR), // Asynchronous clear input
|
|
.D(D), // Data input
|
|
.PRE(PRE) // Asynchronous set input
|
|
);
|
|
|
|
// End of FDCPE_inst instantiation
|
|
</Template>
|
|
<Template label="Posedge D-FF w/ Sync Clear, Set and CE (FDRSE)" treetype="template">
|
|
// FDRSE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FDCRS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FDRSE: Single Data Rate D Flip-Flop with Synchronous Clear, Set and
|
|
// Clock Enable (posedge clk).
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FDRSE #(
|
|
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
|
|
) FDRSE_inst (
|
|
.Q(Q), // Data output
|
|
.C(C), // Clock input
|
|
.CE(CE), // Clock enable input
|
|
.D(D), // Data input
|
|
.R(R), // Synchronous reset input
|
|
.S(S) // Synchronous set input
|
|
);
|
|
|
|
// End of FDRSE_inst instantiation
|
|
</Template>
|
|
<Template label="Posedge D-FF w/ Async Clear and CE (FDCE)" treetype="template">
|
|
// FDCE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FDCE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FDCE: Single Data Rate D Flip-Flop with Asynchronous Clear and
|
|
// Clock Enable (posedge clk).
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FDCE #(
|
|
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
|
|
) FDCE_inst (
|
|
.Q(Q), // 1-bit Data output
|
|
.C(C), // 1-bit Clock input
|
|
.CE(CE), // 1-bit Clock enable input
|
|
.CLR(CLR), // 1-bit Asynchronous clear input
|
|
.D(D) // 1-bit Data input
|
|
);
|
|
|
|
// End of FDCE_inst instantiation
|
|
</Template>
|
|
<Template label="Posedge D-FF w/ Async Preset and CE (FDPE)" treetype="template">
|
|
// FDPE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FDPE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FDPE: Single Data Rate D Flip-Flop with Asynchronous Preset and
|
|
// Clock Enable (posedge clk).
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FDPE #(
|
|
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
|
|
) FDPE_inst (
|
|
.Q(Q), // 1-bit Data output
|
|
.C(C), // 1-bit Clock input
|
|
.CE(CE), // 1-bit Clock enable input
|
|
.PRE(PRE), // 1-bit Asynchronous preset input
|
|
.D(D) // 1-bit Data input
|
|
);
|
|
|
|
// End of FDPE_inst instantiation
|
|
</Template>
|
|
<Template label="Posedge D-FF w/ Sync Reset and CE (FDRE)" treetype="template">
|
|
// FDRE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FDRE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FDRE: Single Data Rate D Flip-Flop with Synchronous Reset and
|
|
// Clock Enable (posedge clk).
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FDRE #(
|
|
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
|
|
) FDRE_inst (
|
|
.Q(Q), // 1-bit Data output
|
|
.C(C), // 1-bit Clock input
|
|
.CE(CE), // 1-bit Clock enable input
|
|
.R(R), // 1-bit Synchronous reset input
|
|
.D(D) // 1-bit Data input
|
|
);
|
|
|
|
// End of FDRE_inst instantiation
|
|
</Template>
|
|
<Template label="Posedge D-FF w/ Sync Set and CE (FDSE)" treetype="template">
|
|
// FDSE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FDSE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FDSE: Single Data Rate D Flip-Flop with Synchronous Set and
|
|
// Clock Enable (posedge clk).
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FDSE #(
|
|
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
|
|
) FDSE_inst (
|
|
.Q(Q), // 1-bit Data output
|
|
.C(C), // 1-bit Clock input
|
|
.CE(CE), // 1-bit Clock enable input
|
|
.S(S), // 1-bit Synchronous set input
|
|
.D(D) // 1-bit Data input
|
|
);
|
|
|
|
// End of FDSE_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Transparent Latch" treetype="folder">
|
|
<Template label="Latch with Async Reset, Set and Gate Enable (LDCPE)" treetype="template">
|
|
// LDCPE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LDCPE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LDCPE: Transparent latch with Asynchronous Reset, Preset and
|
|
// Gate Enable.
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LDCPE #(
|
|
.INIT(1'b0) // Initial value of latch (1'b0 or 1'b1)
|
|
) LDCPE_inst (
|
|
.Q(Q), // Data output
|
|
.CLR(CLR), // Asynchronous clear/reset input
|
|
.D(D), // Data input
|
|
.G(G), // Gate input
|
|
.GE(GE), // Gate enable input
|
|
.PRE(PRE) // Asynchronous preset/set input
|
|
);
|
|
|
|
// End of LDCPE_inst instantiation
|
|
</Template>
|
|
<Template label="Latch with Async Reset and Gate Enable (LDCE)" treetype="template">
|
|
// LDCE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LDCE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LDCE: Transparent latch with Asynchronous Reset and Gate Enable.
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LDCE #(
|
|
.INIT(1'b0) // Initial value of latch (1'b0 or 1'b1)
|
|
) LDCE_inst (
|
|
.Q(Q), // Data output
|
|
.CLR(CLR), // Asynchronous clear/reset input
|
|
.D(D), // Data input
|
|
.G(G), // Gate input
|
|
.GE(GE) // Gate enable input
|
|
);
|
|
|
|
// End of LDCE_inst instantiation
|
|
</Template>
|
|
<Template label="Latch with Async Set and Gate Enable (LDPE)" treetype="template">
|
|
// LDPE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LDPE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LDPE: Transparent latch with Asynchronous Preset and Gate Enable.
|
|
// Virtex-4
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LDPE #(
|
|
.INIT(1'b0) // Initial value of latch (1'b0 or 1'b1)
|
|
) LDPE_inst (
|
|
.Q(Q), // Data output
|
|
.PRE(PRE), // Asynchronous preset/set input
|
|
.D(D), // Data input
|
|
.G(G), // Gate input
|
|
.GE(GE) // Gate enable input
|
|
);
|
|
|
|
// End of LDPE_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Virtex-5" treetype="folder">
|
|
<SubFolder label="Slice/CLB Primitives" treetype="folder">
|
|
<SubFolder label="MUXFx" treetype="folder">
|
|
<Template label="MUXF7" treetype="template">
|
|
// MUXF7 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF7_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF7: CLB MUX to tie two LUT6's together with general output
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF7 MUXF7_inst (
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie to MUXF6 LO out or LUT6 O6 pin)
|
|
.I1(I1), // Input (tie to MUXF6 LO out or LUT6 O6 pin)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF7_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF7_L" treetype="template">
|
|
// MUXF7_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF7_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF7_L: CLB MUX to tie two LUT6's together with local output
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF7_L MUXF7_L_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.I0(I0), // Input (tie to MUXF6 LO out or LUT6 O6 pin)
|
|
.I1(I1), // Input (tie to MUXF6 LO out or LUT6 O6 pin)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF7_L_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF7_D" treetype="template">
|
|
// MUXF7_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF7_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF7_D: CLB MUX to tie two LUT6's together with general and local outputs
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF7_D MUXF7_D_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie to MUXF6 LO out or LUT6 O6 pin)
|
|
.I1(I1), // Input (tie to MUXF6 LO out or LUT6 O6 pin)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF7_D_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF8" treetype="template">
|
|
// MUXF8 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF8_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF8: CLB MUX to tie two MUXF7's together with general output
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF8 MUXF8_inst (
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie to MUXF7 LO out)
|
|
.I1(I1), // Input (tie to MUXF7 LO out)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF8_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF8_L" treetype="template">
|
|
// MUXF8_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF8_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF8_L: CLB MUX to tie two MUXF7's together with local output
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF8_L MUXF8_L_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.I0(I0), // Input (tie to MUXF7 LO out)
|
|
.I1(I1), // Input (tie to MUXF7 LO out)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF8_L_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF8_D" treetype="template">
|
|
// MUXF8_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF8_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF8_D: CLB MUX to tie two MUXF7's together with general and local outputs
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF8_D MUXF8_D_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie to MUXF7 LO out)
|
|
.I1(I1), // Input (tie to MUXF7 LO out)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF8_D_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="LUTs" treetype="folder">
|
|
<SubFolder label="Info" treetype="folder">
|
|
<Template label="Info (LUT INIT)" treetype="template">
|
|
// The INIT parameter for the FPGA LUT primitive is what gives the LUT its
|
|
// logical value. By default this value is zero thus driving the output to a
|
|
// zero regardless of the input values (acting as a ground) however in most
|
|
// cases an new INIT value must be determined in order to specify the logic
|
|
// function for the LUT primitive. There are a few methods in which the LUT
|
|
// value can be determined and two of those methods will be discussed here.
|
|
//
|
|
// The Truth Table Method
|
|
// ----------------------
|
|
//
|
|
// A common method to determine the desired INIT value for a LUT is using a
|
|
// truth table. To do so, simply create a binary truth table of all possible
|
|
// inputs, specify the desired logic value of the output and then create the
|
|
// INIT string from those output values. An example is shown below:
|
|
//
|
|
// Example of determining an XOR INIT equation for a LUT4:
|
|
//
|
|
// _________________
|
|
// | I3 I2 I1 I0 | O |
|
|
// |-----------------|
|
|
// | 0 0 0 0 | 0 |\
|
|
// | 0 0 0 1 | 1 | \ = 4'b0110 = 4'h6 ---------------+
|
|
// | 0 0 1 0 | 1 | / |
|
|
// | 0 0 1 1 | 0 |/ |
|
|
// |-------------|---| |
|
|
// | 0 1 0 0 | 1 |\ |
|
|
// | 0 1 0 1 | 0 | \ = 4'b1001 = 4'h9 |
|
|
// | 0 1 1 0 | 0 | / |
|
|
// | 0 1 1 1 | 1 |/ |
|
|
// |-------------|---| INIT = 16'h6996
|
|
// | 1 0 0 0 | 1 |\ |
|
|
// | 1 0 0 1 | 0 | \ = 4'b0110 = 4'h9 |
|
|
// | 1 0 1 0 | 0 | / |
|
|
// | 1 0 1 1 | 1 |/ |
|
|
// |-------------|---| |
|
|
// | 1 1 0 0 | 0 |\ |
|
|
// | 1 1 0 1 | 1 | \ = 4'b1001 = 4'h6 ------------+
|
|
// | 1 1 1 0 | 1 | /
|
|
// | 1 1 1 1 | 0 |/
|
|
// -------------------
|
|
//
|
|
// Example of determining a 3-input AND gate:
|
|
//
|
|
// ______________
|
|
// | I2 I1 I0 | O |
|
|
// |--------------|
|
|
// | 0 0 0 | 0 |\
|
|
// | 0 0 1 | 0 | \ = 4'b0000 = 4'h0 --------------+
|
|
// | 0 1 0 | 0 | / |
|
|
// | 0 1 1 | 0 |/ |
|
|
// |----------|---| INIT = 8'h80
|
|
// | 1 0 0 | 0 |\ |
|
|
// | 1 0 1 | 0 | \ = 4'b1000 = 4'h8 -------------+
|
|
// | 1 1 0 | 0 | /
|
|
// | 1 1 1 | 1 |/
|
|
// ----------------
|
|
//
|
|
// The Equation Method
|
|
// -------------------
|
|
//
|
|
// Another method to determine the LUT value is to define parameters for each
|
|
// input to the LUT that correspond to their listed truth value and use those to
|
|
// build the logic equation you are after. This method is easier to understand
|
|
// once you have grasped the concept and more self-documenting that the above
|
|
// method however does require the code to first specify the appropriate
|
|
// parameters. See the example below.
|
|
//
|
|
// Example of specifying the equation (A and B) or (C and D) for a LUT4:
|
|
//
|
|
// The forllowing parameters are defined to allow for
|
|
// equation-based INIT specification.
|
|
parameter I0 = 16'haaaa;
|
|
parameter I1 = 16'hcccc;
|
|
parameter I2 = 16'hf0f0;
|
|
parameter I3 = 16'hff00;
|
|
|
|
// LUT4: 4-input Look-Up Table with general output
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT4 #(
|
|
.INIT((I0&I1)|(I2&I3)) // Specify LUT Contents
|
|
) LUT4_inst (
|
|
.O(O_LUT), // LUT general output
|
|
.I0(A), // LUT input
|
|
.I1(B), // LUT input
|
|
.I2(C), // LUT input
|
|
.I3(D) // LUT input
|
|
);
|
|
|
|
// End of LUT4_inst instantiation
|
|
|
|
// With the parameters specifying all possible cases for the truth table, a
|
|
// Verilog equation can be written to determine the end INIT value.
|
|
</Template>
|
|
<SubFolder label="INIT Parameters" treetype="folder">
|
|
<Template label="LUT1" treetype="template">
|
|
// The forllowing parameter is defined to allow for
|
|
// equation-based INIT specification for a LUT1.
|
|
parameter I0 = 2'b10;
|
|
</Template>
|
|
<Template label="LUT2" treetype="template">
|
|
// The forllowing parameters are defined to allow for
|
|
// equation-based INIT specification for a LUT2.
|
|
parameter I0 = 4'ha;
|
|
parameter I1 = 4'hc;
|
|
</Template>
|
|
<Template label="LUT3" treetype="template">
|
|
// The forllowing parameters are defined to allow for
|
|
// equation-based INIT specification for a LUT3.
|
|
parameter I0 = 8'haa;
|
|
parameter I1 = 8'hcc;
|
|
parameter I2 = 8'hf0;
|
|
</Template>
|
|
<Template label="LUT4" treetype="template">
|
|
// The forllowing parameters are defined to allow for
|
|
// equation-based INIT specification for a LUT4.
|
|
parameter I0 = 16'haaaa;
|
|
parameter I1 = 16'hcccc;
|
|
parameter I2 = 16'hf0f0;
|
|
parameter I3 = 16'hff00;
|
|
</Template>
|
|
<Template label="LUT5" treetype="template">
|
|
// The forllowing parameters are defined to allow for
|
|
// equation-based INIT specification for a LUT5.
|
|
parameter I0 = 32'haaaaaaaa;
|
|
parameter I1 = 32'hcccccccc;
|
|
parameter I2 = 32'hf0f0f0f0;
|
|
parameter I3 = 32'hff00ff00;
|
|
parameter I4 = 32'hffff0000;
|
|
</Template>
|
|
<Template label="LUT6" treetype="template">
|
|
// The forllowing parameters are defined to allow for
|
|
// equation-based INIT specification for a LUT6.
|
|
parameter I0 = 64'haaaaaaaaaaaaaaaa;
|
|
parameter I1 = 64'hcccccccccccccccc;
|
|
parameter I2 = 64'hf0f0f0f0f0f0f0f0;
|
|
parameter I3 = 64'hff00ff00ff00ff00;
|
|
parameter I4 = 64'hffff0000ffff0000;
|
|
parameter I5 = 64'hffffffff00000000;
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="INIT Truth Tables" treetype="folder">
|
|
<Template label="LUT1" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT1
|
|
// ________
|
|
// | I0 | O |
|
|
// |--------|
|
|
// | 0 | ? |\
|
|
// | 1 | ? |/ = 2'b??
|
|
// ----------
|
|
</Template>
|
|
<Template label="LUT2" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT2
|
|
// ______________
|
|
// | I2 I1 I0 | O |
|
|
// |--------------|
|
|
// | 0 0 0 | ? |\
|
|
// | 0 0 1 | ? | \ = INIT = 4'b???? = 4'h?
|
|
// | 0 1 0 | ? | /
|
|
// | 0 1 1 | ? |/
|
|
// ---------- ---
|
|
</Template>
|
|
<Template label="LUT3" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT3
|
|
// ______________
|
|
// | I2 I1 I0 | O |
|
|
// |--------------|
|
|
// | 0 0 0 | ? |\
|
|
// | 0 0 1 | ? | \ = 4'b???? = 4'h? --------------+
|
|
// | 0 1 0 | ? | / |
|
|
// | 0 1 1 | ? |/ |
|
|
// |----------|---| INIT = 8'h??
|
|
// | 1 0 0 | ? |\ |
|
|
// | 1 0 1 | ? | \ = 4'b???? = 4'h? -------------+
|
|
// | 1 1 0 | ? | /
|
|
// | 1 1 1 | ? |/
|
|
// ----------------
|
|
</Template>
|
|
<Template label="LUT4" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT4
|
|
// _________________
|
|
// | I3 I2 I1 I0 | O |
|
|
// |-----------------|
|
|
// | 0 0 0 0 | ? |\
|
|
// | 0 0 0 1 | ? | \ = 4'b???? = 4'h? ---------------+
|
|
// | 0 0 1 0 | ? | / |
|
|
// | 0 0 1 1 | ? |/ |
|
|
// |-------------|---| |
|
|
// | 0 1 0 0 | ? |\ |
|
|
// | 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 1 0 | ? | / |
|
|
// | 0 1 1 1 | ? |/ |
|
|
// |-------------|---| INIT = 16'h????
|
|
// | 1 0 0 0 | ? |\ |
|
|
// | 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 1 0 | ? | / |
|
|
// | 1 0 1 1 | ? |/ |
|
|
// |-------------|---| |
|
|
// | 1 1 0 0 | ? |\ |
|
|
// | 1 1 0 1 | ? | \ = 4'b???? = 4'h? ------------+
|
|
// | 1 1 1 0 | ? | /
|
|
// | 1 1 1 1 | ? |/
|
|
// -------------------
|
|
</Template>
|
|
<Template label="LUT5" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT5
|
|
// ____________________
|
|
// | I4 I3 I2 I1 I0 | O |
|
|
// |--------------------|
|
|
// | 0 0 0 0 0 | ? |\
|
|
// | 0 0 0 0 1 | ? | \ = 4'b???? = 4'h? -------------------+
|
|
// | 0 0 0 1 0 | ? | / |
|
|
// | 0 0 0 1 1 | ? |/ |
|
|
// |----------------|---| |
|
|
// | 0 0 1 0 0 | ? |\ |
|
|
// | 0 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 0 1 1 0 | ? | / |
|
|
// | 0 0 1 1 1 | ? |/ |
|
|
// |----------------|---| |
|
|
// | 0 1 0 0 0 | ? |\ |
|
|
// | 0 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 0 1 0 | ? | / |
|
|
// | 0 1 0 1 1 | ? |/ |
|
|
// |----------------|---| |
|
|
// | 0 1 1 0 0 | ? |\ |
|
|
// | 0 1 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 1 1 0 | ? | / |
|
|
// | 0 1 1 1 1 | ? |/ |
|
|
// ---------------------- INIT = 32'h????????
|
|
// | 1 0 0 0 0 | ? |\ |
|
|
// | 1 0 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 0 1 0 | ? | / |
|
|
// | 1 0 0 1 1 | ? |/ |
|
|
// |----------------|---| |
|
|
// | 1 0 1 0 0 | ? |\ |
|
|
// | 1 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 1 1 0 | ? | / |
|
|
// | 1 0 1 1 1 | ? |/ |
|
|
// |----------------|---| |
|
|
// | 1 1 0 0 0 | ? |\ |
|
|
// | 1 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 1 0 1 0 | ? | / |
|
|
// | 1 1 0 1 1 | ? |/ |
|
|
// |----------------|---| |
|
|
// | 1 1 1 0 0 | ? |\ |
|
|
// | 1 1 1 0 1 | ? | \ = 4'b???? = 4'h? ------------+
|
|
// | 1 1 1 1 0 | ? | /
|
|
// | 1 1 1 1 1 | ? |/
|
|
// ----------------------
|
|
</Template>
|
|
<Template label="LUT6" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT6
|
|
// _______________________
|
|
// | I5 I4 I3 I2 I1 I0 | O |
|
|
// |-----------------------|
|
|
// | 0 0 0 0 0 0 | ? |\
|
|
// | 0 0 0 0 0 1 | ? | \ = 4'b???? = 4'h? -------------------+
|
|
// | 0 0 0 0 1 0 | ? | / |
|
|
// | 0 0 0 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 0 0 0 1 0 0 | ? |\ |
|
|
// | 0 0 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 0 0 1 1 0 | ? | / |
|
|
// | 0 0 0 1 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 0 0 1 0 0 0 | ? |\ |
|
|
// | 0 0 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 0 1 0 1 0 | ? | / |
|
|
// | 0 0 1 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 0 0 1 1 0 0 | ? |\ |
|
|
// | 0 0 1 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 0 1 1 1 0 | ? | / |
|
|
// | 0 0 1 1 1 1 | ? |/ |
|
|
// ------------------------- |
|
|
// | 0 1 0 0 0 0 | ? |\ |
|
|
// | 0 1 0 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 0 0 1 0 | ? | / |
|
|
// | 0 1 0 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 0 1 0 1 0 0 | ? |\ |
|
|
// | 0 1 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 0 1 1 0 | ? | / |
|
|
// | 0 1 0 1 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 0 1 1 0 0 0 | ? |\ |
|
|
// | 0 1 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 1 0 1 0 | ? | / |
|
|
// | 0 1 1 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 0 1 1 1 0 0 | ? |\ |
|
|
// | 0 1 1 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 1 1 1 0 | ? | / |
|
|
// | 0 1 1 1 1 1 | ? |/ |
|
|
// ------------------------ INIT = 64'h????????????????
|
|
// | 1 0 0 0 0 0 | ? |\ |
|
|
// | 1 0 0 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 0 0 1 0 | ? | / |
|
|
// | 1 0 0 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 0 0 1 0 0 | ? |\ |
|
|
// | 1 0 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 0 1 1 0 | ? | / |
|
|
// | 1 0 0 1 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 0 1 0 0 0 | ? |\ |
|
|
// | 1 0 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 1 0 1 0 | ? | / |
|
|
// | 1 0 1 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 0 1 1 0 0 | ? |\ |
|
|
// | 1 0 1 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 1 1 1 0 | ? | / |
|
|
// | 1 0 1 1 1 1 | ? |/ |
|
|
// ------------------------- |
|
|
// | 1 1 0 0 0 0 | ? |\ |
|
|
// | 1 1 0 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 1 0 0 1 0 | ? | / |
|
|
// | 1 1 0 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 1 0 1 0 0 | ? |\ |
|
|
// | 1 1 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 1 0 1 1 0 | ? | / |
|
|
// | 1 1 0 1 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 1 1 0 0 0 | ? |\ |
|
|
// | 1 1 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 1 1 0 1 0 | ? | / |
|
|
// | 1 1 1 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 1 1 1 0 0 | ? |\ |
|
|
// | 1 1 1 1 0 1 | ? | \ = 4'b???? = 4'h? ----+
|
|
// | 1 1 1 1 1 0 | ? | /
|
|
// | 1 1 1 1 1 1 | ? |/
|
|
// ------------------------
|
|
</Template>
|
|
<Template label="LUT6_2" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT6_2
|
|
// _____________________________
|
|
// | I5 I4 I3 I2 I1 I0 | O6 | O5 |
|
|
// |-----------------------------|
|
|
// | 0 0 0 0 0 0 | ? |\
|
|
// | 0 0 0 0 0 1 | ? | \ = 4'b???? = 4'h? -------------+
|
|
// | 0 0 0 0 1 0 | ? | / |
|
|
// | 0 0 0 0 1 1 | ? |/ |
|
|
// |-------------------|---------| |
|
|
// | 0 0 0 1 0 0 | ? |\ |
|
|
// | 0 0 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 0 0 1 1 0 | ? | / |
|
|
// | 0 0 0 1 1 1 | ? |/ |
|
|
// |-------------------|---------| |
|
|
// | 0 0 1 0 0 0 | ? |\ |
|
|
// | 0 0 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 0 1 0 1 0 | ? | / |
|
|
// | 0 0 1 0 1 1 | ? |/ |
|
|
// |-------------------|---------| |
|
|
// | 0 0 1 1 0 0 | ? |\ |
|
|
// | 0 0 1 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 0 1 1 1 0 | ? | / |
|
|
// | 0 0 1 1 1 1 | ? |/ |
|
|
// ------------------------------- |
|
|
// | 0 1 0 0 0 0 | ? |\ |
|
|
// | 0 1 0 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 0 0 1 0 | ? | / |
|
|
// | 0 1 0 0 1 1 | ? |/ |
|
|
// |-------------------|---------| |
|
|
// | 0 1 0 1 0 0 | ? |\ |
|
|
// | 0 1 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 0 1 1 0 | ? | / |
|
|
// | 0 1 0 1 1 1 | ? |/ |
|
|
// |-------------------|---------| |
|
|
// | 0 1 1 0 0 0 | ? |\ |
|
|
// | 0 1 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 1 0 1 0 | ? | / |
|
|
// | 0 1 1 0 1 1 | ? |/ |
|
|
// |-------------------|---------| |
|
|
// | 0 1 1 1 0 0 | ? |\ |
|
|
// | 0 1 1 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 1 1 1 0 | ? | / |
|
|
// | 0 1 1 1 1 1 | ? |/ |
|
|
// ------------------------------ INIT = 64'h????????????????
|
|
// | 1 0 0 0 0 0 | ? |\ |
|
|
// | 1 0 0 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 0 0 1 0 | ? | / |
|
|
// | 1 0 0 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 0 0 1 0 0 | ? |\ |
|
|
// | 1 0 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 0 1 1 0 | ? | / |
|
|
// | 1 0 0 1 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 0 1 0 0 0 | ? |\ |
|
|
// | 1 0 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 1 0 1 0 | ? | / |
|
|
// | 1 0 1 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 0 1 1 0 0 | ? |\ |
|
|
// | 1 0 1 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 1 1 1 0 | ? | / |
|
|
// | 1 0 1 1 1 1 | ? |/ |
|
|
// ------------------------- |
|
|
// | 1 1 0 0 0 0 | ? |\ |
|
|
// | 1 1 0 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 1 0 0 1 0 | ? | / |
|
|
// | 1 1 0 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 1 0 1 0 0 | ? |\ |
|
|
// | 1 1 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 1 0 1 1 0 | ? | / |
|
|
// | 1 1 0 1 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 1 1 0 0 0 | ? |\ |
|
|
// | 1 1 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 1 1 0 1 0 | ? | / |
|
|
// | 1 1 1 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 1 1 1 0 0 | ? |\ |
|
|
// | 1 1 1 1 0 1 | ? | \ = 4'b???? = 4'h? ----+
|
|
// | 1 1 1 1 1 0 | ? | /
|
|
// | 1 1 1 1 1 1 | ? |/
|
|
// ------------------------
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<Template label="LUT4" treetype="template">
|
|
// LUT4 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT4_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT4: 4-input Look-Up Table with general output
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT4 #(
|
|
.INIT(16'h0000) // Specify LUT Contents
|
|
) LUT4_inst (
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3) // LUT input
|
|
);
|
|
|
|
// End of LUT4_inst instantiation
|
|
</Template>
|
|
<Template label="LUT4_L" treetype="template">
|
|
// LUT4_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT4_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT4_L: 4-input Look-Up Table with local output
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT4_L #(
|
|
.INIT(16'h0000) // Specify LUT Contents
|
|
) LUT4_L_inst (
|
|
.LO(LO), // LUT local output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3) // LUT input
|
|
);
|
|
|
|
// End of LUT4_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT4_D" treetype="template">
|
|
// LUT4_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT4_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT4_D: 4-input Look-Up Table with general and local outputs
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT4_D #(
|
|
.INIT(16'h0000) // Specify LUT Contents
|
|
) LUT4_D_inst (
|
|
.LO(LO), // LUT local output
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3) // LUT input
|
|
);
|
|
|
|
// End of LUT4_D_inst instantiation
|
|
</Template>
|
|
<Template label="LUT3" treetype="template">
|
|
// LUT3 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT3_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT3: 3-input Look-Up Table with general output
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT3 #(
|
|
.INIT(8'h00) // Specify LUT Contents
|
|
) LUT3_inst (
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2) // LUT input
|
|
);
|
|
|
|
// End of LUT3_inst instantiation
|
|
</Template>
|
|
<Template label="LUT3_L" treetype="template">
|
|
// LUT3_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT3_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT3_L: 3-input Look-Up Table with local output
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT3_L #(
|
|
.INIT(8'h00) // Specify LUT Contents
|
|
) LUT3_L_inst (
|
|
.LO(LO), // LUT local output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2) // LUT input
|
|
);
|
|
|
|
// End of LUT3_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT3_D" treetype="template">
|
|
// LUT3_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT3_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT3_D: 3-input Look-Up Table with general and local outputs
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT3_D #(
|
|
.INIT(8'h00) // Specify LUT Contents
|
|
) LUT3_D_inst (
|
|
.LO(LO), // LUT local output
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2) // LUT input
|
|
);
|
|
|
|
// End of LUT3_D_inst instantiation
|
|
</Template>
|
|
<Template label="LUT2" treetype="template">
|
|
// LUT2 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT2: 2-input Look-Up Table with general output
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT2 #(
|
|
.INIT(4'h0) // Specify LUT Contents
|
|
) LUT2_inst (
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1) // LUT input
|
|
);
|
|
|
|
// End of LUT2_inst instantiation
|
|
</Template>
|
|
<Template label="LUT2_L" treetype="template">
|
|
// LUT2_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT2_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT2_L: 2-input Look-Up Table with local output
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT2_L #(
|
|
.INIT(4'h0) // Specify LUT Contents
|
|
) LUT2_L_inst (
|
|
.LO(LO), // LUT local output
|
|
.I0(I0), // LUT input
|
|
.I1(I1) // LUT input
|
|
);
|
|
|
|
// End of LUT2_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT2_D" treetype="template">
|
|
// LUT2_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT2_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT2_D: 2-input Look-Up Table with general and local outputs
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT2_D #(
|
|
.INIT(4'h0) // Specify LUT Contents
|
|
) LUT2_D_inst (
|
|
.LO(LO), // LUT local output
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1) // LUT input
|
|
);
|
|
|
|
// End of LUT2_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT1" treetype="template">
|
|
// LUT1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT1: 1-input Look-Up Table with general output
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT1 #(
|
|
.INIT(2'b00) // Specify LUT Contents
|
|
) LUT1_inst (
|
|
.O(O), // LUT general output
|
|
.I0(I0) // LUT input
|
|
);
|
|
|
|
// End of LUT1_inst instantiation
|
|
</Template>
|
|
<Template label="LUT1_L" treetype="template">
|
|
// LUT1_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT1_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT1_L: 1-input Look-Up Table with local output
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT1_L #(
|
|
.INIT(2'b00) // Specify LUT Contents
|
|
) LUT1_L_inst (
|
|
.LO(LO), // LUT local output
|
|
.I0(I0) // LUT input
|
|
);
|
|
|
|
// End of LUT1_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT1_D" treetype="template">
|
|
// LUT1_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT1_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT1_D: 1-input Look-Up Table with general and local outputs
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT1_D #(
|
|
.INIT(2'b00) // Specify LUT Contents
|
|
) LUT1_D_inst (
|
|
.LO(LO), // LUT local output
|
|
.O(O), // LUT general output
|
|
.I0(I0) // LUT input
|
|
);
|
|
|
|
// End of LUT1_D_inst instantiation
|
|
</Template>
|
|
<Template label="LUT Local Connect Buffer (BUFCF)" treetype="template">
|
|
// BUFCF : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFCF_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFCF: Fast connect buffer used to connect the outputs of the LUTs
|
|
// and some dedicated logic directly to the input of another LUT.
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFCF BUFCF_inst (
|
|
.O(O), // Connect to the output of a LUT
|
|
.I(I) // Connect to the input of a LUT
|
|
);
|
|
|
|
// End of BUFCF_inst instantiation
|
|
</Template>
|
|
<Template label="Reconfigurable LUT (CFGLUT5)" treetype="template">
|
|
// CFGLUT5 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (CFGLUT5_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// CFGLUT5: Reconfigurable 5-input LUT
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
CFGLUT5 #(
|
|
.INIT(32'h00000000) // Specify initial LUT contents
|
|
) CFGLUT5_inst (
|
|
.CDO(CDO), // Reconfiguration cascade output
|
|
.O5(O5), // 4-LUT output
|
|
.O6(O6), // 5-LUT output
|
|
.CDI(CDI), // Reconfiguration data input
|
|
.CE(CE), // Reconfiguration enable input
|
|
.CLK(CLK), // Clock input
|
|
.I0(I0), // Logic data input
|
|
.I1(I1), // Logic data input
|
|
.I2(I2), // Logic data input
|
|
.I3(I3), // Logic data input
|
|
.I4(I4) // Logic data input
|
|
);
|
|
|
|
// End of CFGLUT5_inst instantiation
|
|
</Template>
|
|
<Template label="LUT5" treetype="template">
|
|
// LUT5 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT5_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT5: 5-input Look-Up Table with general output
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT5 #(
|
|
.INIT(32'h00000000) // Specify LUT Contents
|
|
) LUT5_inst (
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3), // LUT input
|
|
.I4(I4) // LUT input
|
|
);
|
|
|
|
// End of LUT5_inst instantiation
|
|
</Template>
|
|
<Template label="LUT5_L" treetype="template">
|
|
// LUT5_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT5_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT5_L: 5-input Look-Up Table with local output
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT5_L #(
|
|
.INIT(32'h0000000) // Specify LUT Contents
|
|
) LUT5_L_inst (
|
|
.LO(LO), // LUT local output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3), // LUT input
|
|
.I4(I4) // LUT input
|
|
);
|
|
|
|
// End of LUT5_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT5_D" treetype="template">
|
|
// LUT5_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT5_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT5_D: 5-input Look-Up Table with general and local outputs
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT5_D #(
|
|
.INIT(32'h0000000) // Specify LUT Contents
|
|
) LUT5_D_inst (
|
|
.LO(LO), // LUT local output
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3), // LUT input
|
|
.I4(I4) // LUT input
|
|
);
|
|
|
|
// End of LUT5_D_inst instantiation
|
|
</Template>
|
|
<Template label="LUT6" treetype="template">
|
|
// LUT6 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT6_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT6: 6-input Look-Up Table with general output
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT6 #(
|
|
.INIT(64'h0000000000000000) // Specify LUT Contents
|
|
) LUT6_inst (
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3), // LUT input
|
|
.I4(I4), // LUT input
|
|
.I5(I5) // LUT input
|
|
);
|
|
|
|
// End of LUT6_inst instantiation
|
|
</Template>
|
|
<Template label="LUT6_L" treetype="template">
|
|
// LUT6_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT6_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT6_L: 6-input Look-Up Table with local output
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT6_L #(
|
|
.INIT(64'h0000000000000000) // Specify LUT Contents
|
|
) LUT6_L_inst (
|
|
.LO(LO), // LUT local output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3), // LUT input
|
|
.I4(I4), // LUT input
|
|
.I5(I5) // LUT input
|
|
);
|
|
|
|
// End of LUT6_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT6_D" treetype="template">
|
|
// LUT6_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT6_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT6_D: 6-input Look-Up Table with general and local outputs
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT6_D #(
|
|
.INIT(64'h0000000000000000) // Specify LUT Contents
|
|
) LUT6_D_inst (
|
|
.LO(LO), // LUT local output
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3), // LUT input
|
|
.I4(I4), // LUT input
|
|
.I5(I5) // LUT input
|
|
);
|
|
|
|
// End of LUT6_D_inst instantiation
|
|
</Template>
|
|
<Template label="LUT6_2" treetype="template">
|
|
// LUT6_2 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT6_2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT6_2: 6-input, 2 output Look-Up Table
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT6_2 #(
|
|
.INIT(64'h0000000000000000) // Specify LUT Contents
|
|
) LUT6_2_inst (
|
|
.O6(O6), // 1-bit LUT6 output
|
|
.O5(O5), // 1-bit lower LUT5 output
|
|
.I0(I0), // 1-bit LUT input
|
|
.I1(I1), // 1-bit LUT input
|
|
.I2(I2), // 1-bit LUT input
|
|
.I3(I3), // 1-bit LUT input
|
|
.I4(I4), // 1-bit LUT input
|
|
.I5(I5) // 1-bit LUT input (fast MUX select only available to O6 output)
|
|
);
|
|
|
|
// End of LUT6_2_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Shift Register LUT" treetype="folder">
|
|
<Template label="16-bit w/ CE posedge SR (SRL16E)" treetype="template">
|
|
// SRL16E : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SRL16E_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SRL16E: 16-bit shift register LUT with clock enable operating on posedge of clock
|
|
// All FPGAs
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SRL16E #(
|
|
.INIT(16'h0000) // Initial Value of Shift Register
|
|
) SRL16E_inst (
|
|
.Q(Q), // SRL data output
|
|
.A0(A0), // Select[0] input
|
|
.A1(A1), // Select[1] input
|
|
.A2(A2), // Select[2] input
|
|
.A3(A3), // Select[3] input
|
|
.CE(CE), // Clock enable input
|
|
.CLK(CLK), // Clock input
|
|
.D(D) // SRL data input
|
|
);
|
|
|
|
// End of SRL16E_inst instantiation
|
|
</Template>
|
|
<Template label="32-bit w/ CE posedge SR (SRLC32E)" treetype="template">
|
|
// SRLC32E : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SRL32E_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SRLC32E: 32-bit variable length cascadable shift register LUT
|
|
// with clock enable
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SRLC32E #(
|
|
.INIT(32'h00000000) // Initial Value of Shift Register
|
|
) SRLC32E_inst (
|
|
.Q(Q), // SRL data output
|
|
.Q31(Q31), // SRL cascade output pin
|
|
.A(A), // 5-bit shift depth select input
|
|
.CE(CE), // Clock enable input
|
|
.CLK(CLK), // Clock input
|
|
.D(D) // SRL data input
|
|
);
|
|
|
|
// End of SRLC32E_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<Template label="Carry (CARRY4)" treetype="template">
|
|
// CARRY4 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (CARRY4_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs and
|
|
// : and outputs of this primitive should be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// CARRY4: Fast Carry Logic Component
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
CARRY4 CARRY4_inst (
|
|
.CO(CO), // 4-bit carry out
|
|
.O(O), // 4-bit carry chain XOR data out
|
|
.CI(CI), // 1-bit carry cascade input
|
|
.CYINIT(CYINIT), // 1-bit carry initialization
|
|
.DI(DI), // 4-bit carry-MUX data in
|
|
.S(S) // 4-bit carry-MUX select input
|
|
);
|
|
|
|
// End of CARRY4_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Clock Components" treetype="folder">
|
|
<SubFolder label="Digital Clock Manager (DCM)" treetype="folder">
|
|
<Template label="Dynamic Phase Shift DCM (DCM_PS)" treetype="template">
|
|
// DCM_PS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (DCM_PS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Unused inputs
|
|
// : and outputs may be removed or commented out.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// DCM_PS: Dynamic Phase Shift Digital Clock Manager Circuit
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
DCM_PS #(
|
|
.CLKDV_DIVIDE(2.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
|
|
// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
|
|
.CLKFX_DIVIDE(1), // Can be any integer from 1 to 32
|
|
.CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32
|
|
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
|
|
.CLKIN_PERIOD(10.0), // Specify period of input clock in ns from 1.25 to 1000.00
|
|
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift mode of NONE, FIXED,
|
|
// VARIABLE_POSITIVE, VARIABLE_CENTER or DIRECT
|
|
.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE or 1X
|
|
.DCM_PERFORMANCE_MODE("MAX_SPEED"), // Can be MAX_SPEED or MAX_RANGE
|
|
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
|
|
// an integer from 0 to 15
|
|
.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
|
|
.DLL_FREQUENCY_MODE("LOW"), // LOW, HIGH, or HIGH_SER frequency mode for DLL
|
|
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
|
|
.FACTORY_JF(16'hf0f0), // FACTORY JF value suggested to be set to 16'hf0f0
|
|
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 1023
|
|
.STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
|
|
) DCM_PS_inst (
|
|
.CLK0(CLK0), // 0 degree DCM CLK output
|
|
.CLK180(CLK180), // 180 degree DCM CLK output
|
|
.CLK270(CLK270), // 270 degree DCM CLK output
|
|
.CLK2X(CLK2X), // 2X DCM CLK output
|
|
.CLK2X180(CLK2X180), // 2X, 180 degree DCM CLK out
|
|
.CLK90(CLK90), // 90 degree DCM CLK output
|
|
.CLKDV(CLKDV), // Divided DCM CLK out (CLKDV_DIVIDE)
|
|
.CLKFX(CLKFX), // DCM CLK synthesis out (M/D)
|
|
.CLKFX180(CLKFX180), // 180 degree CLK synthesis out
|
|
.DO(DO), // 16-bit data output for Dynamic Reconfiguration Port (DRP)
|
|
.LOCKED(LOCKED), // DCM LOCK status output
|
|
.PSDONE(PSDONE), // Dynamic phase adjust done output
|
|
.CLKFB(CLKFB), // DCM clock feedback
|
|
.CLKIN(CLKIN), // Clock input (from IBUFG, BUFG or DCM)
|
|
.PSCLK(PSCLK), // Dynamic phase adjust clock input
|
|
.PSEN(PSEN), // Dynamic phase adjust enable input
|
|
.PSINCDEC(PSINCDEC), // Dynamic phase adjust increment/decrement
|
|
.RST(RST) // DCM asynchronous reset input
|
|
);
|
|
|
|
|
|
// End of DCM_PS_inst instantiation
|
|
</Template>
|
|
<Template label="Base DCM (DCM_BASE)" treetype="template">
|
|
// DCM_BASE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (DCM_BASE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Unused inputs
|
|
// : and outputs may be removed or commented out.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// DCM_BASE: Base Digital Clock Manager Circuit
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
DCM_BASE #(
|
|
.CLKDV_DIVIDE(2.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
|
|
// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
|
|
.CLKFX_DIVIDE(1), // Can be any integer from 1 to 32
|
|
.CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32
|
|
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
|
|
.CLKIN_PERIOD(10.0), // Specify period of input clock in ns from 1.25 to 1000.00
|
|
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift mode of NONE or FIXED
|
|
.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE or 1X
|
|
.DCM_PERFORMANCE_MODE("MAX_SPEED"), // Can be MAX_SPEED or MAX_RANGE
|
|
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
|
|
// an integer from 0 to 15
|
|
.DFS_FREQUENCY_MODE("LOW"), // LOW or HIGH frequency mode for frequency synthesis
|
|
.DLL_FREQUENCY_MODE("LOW"), // LOW, HIGH, or HIGH_SER frequency mode for DLL
|
|
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
|
|
.FACTORY_JF(16'hf0f0), // FACTORY JF value suggested to be set to 16'hf0f0
|
|
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 1023
|
|
.STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
|
|
) DCM_BASE_inst (
|
|
.CLK0(CLK0), // 0 degree DCM CLK output
|
|
.CLK180(CLK180), // 180 degree DCM CLK output
|
|
.CLK270(CLK270), // 270 degree DCM CLK output
|
|
.CLK2X(CLK2X), // 2X DCM CLK output
|
|
.CLK2X180(CLK2X180), // 2X, 180 degree DCM CLK out
|
|
.CLK90(CLK90), // 90 degree DCM CLK output
|
|
.CLKDV(CLKDV), // Divided DCM CLK out (CLKDV_DIVIDE)
|
|
.CLKFX(CLKFX), // DCM CLK synthesis out (M/D)
|
|
.CLKFX180(CLKFX180), // 180 degree CLK synthesis out
|
|
.LOCKED(LOCKED), // DCM LOCK status output
|
|
.CLKFB(CLKFB), // DCM clock feedback
|
|
.CLKIN(CLKIN), // Clock input (from IBUFG, BUFG or DCM)
|
|
.RST(RST) // DCM asynchronous reset input
|
|
);
|
|
|
|
// End of DCM_BASE_inst instantiation
|
|
</Template>
|
|
<Template label="Advanced DCM (DCM_ADV)" treetype="template">
|
|
// DCM_ADV : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (DCM_ADV_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Unused inputs
|
|
// : and outputs may be removed or commented out.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// DCM_ADV: Digital Clock Manager Circuit
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
DCM_ADV #(
|
|
.CLKDV_DIVIDE(2.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
|
|
// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
|
|
.CLKFX_DIVIDE(1), // Can be any integer from 1 to 32
|
|
.CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32
|
|
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
|
|
.CLKIN_PERIOD(10.0), // Specify period of input clock in ns from 1.25 to 1000.00
|
|
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift mode of NONE, FIXED,
|
|
// VARIABLE_POSITIVE, VARIABLE_CENTER or DIRECT
|
|
.CLK_FEEDBACK("1X"), // Specify clock feedback of NONE or 1X
|
|
.DCM_PERFORMANCE_MODE("MAX_SPEED"), // Can be MAX_SPEED or MAX_RANGE
|
|
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
|
|
// an integer from 0 to 15
|
|
.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
|
|
.DLL_FREQUENCY_MODE("LOW"), // LOW, HIGH, or HIGH_SER frequency mode for DLL
|
|
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, "TRUE"/"FALSE"
|
|
.FACTORY_JF(16'hf0f0), // FACTORY JF value suggested to be set to 16'hf0f0
|
|
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 1023
|
|
.SIM_DEVICE("VIRTEX5"), // Set target device, "VIRTEX4" or "VIRTEX5"
|
|
.STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, "TRUE"/"FALSE"
|
|
) DCM_ADV_inst (
|
|
.CLK0(CLK0), // 0 degree DCM CLK output
|
|
.CLK180(CLK180), // 180 degree DCM CLK output
|
|
.CLK270(CLK270), // 270 degree DCM CLK output
|
|
.CLK2X(CLK2X), // 2X DCM CLK output
|
|
.CLK2X180(CLK2X180), // 2X, 180 degree DCM CLK out
|
|
.CLK90(CLK90), // 90 degree DCM CLK output
|
|
.CLKDV(CLKDV), // Divided DCM CLK out (CLKDV_DIVIDE)
|
|
.CLKFX(CLKFX), // DCM CLK synthesis out (M/D)
|
|
.CLKFX180(CLKFX180), // 180 degree CLK synthesis out
|
|
.DO(DO), // 16-bit data output for Dynamic Reconfiguration Port (DRP)
|
|
.DRDY(DRDY), // Ready output signal from the DRP
|
|
.LOCKED(LOCKED), // DCM LOCK status output
|
|
.PSDONE(PSDONE), // Dynamic phase adjust done output
|
|
.CLKFB(CLKFB), // DCM clock feedback
|
|
.CLKIN(CLKIN), // Clock input (from IBUFG, BUFG or DCM)
|
|
.DADDR(DADDR), // 7-bit address for the DRP
|
|
.DCLK(DCLK), // Clock for the DRP
|
|
.DEN(DEN), // Enable input for the DRP
|
|
.DI(DI), // 16-bit data input for the DRP
|
|
.DWE(DWE), // Active high allows for writing configuration memory
|
|
.PSCLK(PSCLK), // Dynamic phase adjust clock input
|
|
.PSEN(PSEN), // Dynamic phase adjust enable input
|
|
.PSINCDEC(PSINCDEC), // Dynamic phase adjust increment/decrement
|
|
.RST(RST) // DCM asynchronous reset input
|
|
);
|
|
|
|
// End of DCM_ADV_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Clock Buffers" treetype="folder">
|
|
<Template label="Global Clock Buffer (BUFG)" treetype="template">
|
|
// BUFG : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFG_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFG: Global Clock Buffer (source by an internal signal)
|
|
// All FPGAs
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFG BUFG_inst (
|
|
.O(O), // Clock buffer output
|
|
.I(I) // Clock buffer input
|
|
);
|
|
|
|
// End of BUFG_inst instantiation
|
|
</Template>
|
|
<Template label="Single-ended input Global Clock Buffer (IBUFG)" treetype="template">
|
|
// IBUFG : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFG_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFG: Global Clock Buffer (sourced by an external pin)
|
|
// All FPGAs
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFG #(
|
|
.IOSTANDARD("DEFAULT")
|
|
) IBUFG_inst (
|
|
.O(O), // Clock buffer output
|
|
.I(I) // Clock buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUFG_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Input Global Clock Buffer (IBUFGDS)" treetype="template">
|
|
// IBUFGDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFGDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFGDS: Differential Global Clock Buffer (sourced by an external pin)
|
|
// Virtex-5, Spartan-3/3E/3A
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFGDS #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination
|
|
.IOSTANDARD("DEFAULT") // Specifies the I/O standard for this buffer
|
|
) IBUFGDS_inst (
|
|
.O(O), // Clock buffer output
|
|
.I(I), // Diff_p clock buffer input
|
|
.IB(IB) // Diff_n clock buffer input
|
|
);
|
|
|
|
// End of IBUFGDS_inst instantiation
|
|
</Template>
|
|
<Template label="Global Clock Buffer w/ Enable (BUFGCE)" treetype="template">
|
|
// BUFGCE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFGCE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFGCE: Global Clock Buffer with Clock Enable (active high)
|
|
// Virtex-5/6, Spartan-3/3E/3A/6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFGCE BUFGCE_inst (
|
|
.O(O), // Clock buffer output
|
|
.CE(CE), // Clock enable input
|
|
.I(I) // Clock buffer input
|
|
);
|
|
|
|
// End of BUFGCE_inst instantiation
|
|
</Template>
|
|
<Template label="Global Clock Buffer w/ Enable (BUFGCE_1)" treetype="template">
|
|
// BUFGCE_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFGCE_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFGCE_1: Global Clock Buffer with Clock Enable (active low)
|
|
// Virtex-5/6, Spartan-3/3E/3A/6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFGCE_1 BUFGCE_1_inst (
|
|
.O(O), // Clock buffer output
|
|
.CE(CE), // Clock enable input
|
|
.I(I) // Clock buffer input
|
|
);
|
|
|
|
// End of BUFGCE_1_inst instantiation
|
|
</Template>
|
|
<Template label="I/O Clock Buffer (BUFIO)" treetype="template">
|
|
// BUFIO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFIO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFIO: Local Clock Buffer
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFIO BUFIO_inst (
|
|
.O(O), // Clock buffer output
|
|
.I(I) // Clock buffer input
|
|
);
|
|
|
|
// End of BUFIO_inst instantiation
|
|
</Template>
|
|
<Template label="Regional Clock Buffer (BUFR)" treetype="template">
|
|
// BUFR : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFR_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFR: Regional Clock Buffer w/ Enable, Clear and Division Capabilities
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFR #(
|
|
.BUFR_DIVIDE("BYPASS"), // "BYPASS", "1", "2", "3", "4", "5", "6", "7", "8"
|
|
.SIM_DEVICE("VIRTEX5") // Specify target device, "VIRTEX4", "VIRTEX5", "VIRTEX6"
|
|
) BUFR_inst (
|
|
.O(O), // Clock buffer output
|
|
.CE(CE), // Clock enable input
|
|
.CLR(CLR), // Clock buffer reset input
|
|
.I(I) // Clock buffer input
|
|
);
|
|
|
|
// End of BUFR_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Clock MUX" treetype="folder">
|
|
<Template label="Advanced Clock Primitive (BUFGCTRL)" treetype="template">
|
|
// BUFGCTRL : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFGCTRL_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFGCTRL: Advanced Clock MUX Primitive
|
|
// Virtex-5/6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFGCTRL #(
|
|
.INIT_OUT(0), // Inital value of 0 or 1 after configuration
|
|
.PRESELECT_I0("FALSE"), // "TRUE" or "FALSE" set the I0 input after configuration
|
|
.PRESELECT_I1("FALSE") // "TRUE" or "FALSE" set the I1 input after configuration
|
|
) BUFGCTRL_inst (
|
|
.O(O), // 1-bit output
|
|
.CE0(CE0), // 1-bit clock enable 0
|
|
.CE1(CE1), // 1-bit clock enable 1
|
|
.I0(I0), // 1-bit clock 0 input
|
|
.I1(I1), // 1-bit clock 1 input
|
|
.IGNORE0(IGNORE0), // 1-bit ignore 0 input
|
|
.IGNORE1(IGNORE1), // 1-bit ignore 1 input
|
|
.S0(S0), // 1-bit select 0 input
|
|
.S1(S1) // 1-bit select 1 input
|
|
);
|
|
|
|
// End of BUFGCTRL_inst instantiation
|
|
</Template>
|
|
<Template label="Global Clock Buffer MUX (BUFGMUX_CTRL)" treetype="template">
|
|
// BUFGMUX_CTRL : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFGMUX_CTRL_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFGMUX_CTRL: Global Clock Buffer 2-to-1 MUX
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFGMUX_CTRL BUFGMUX_CTRL_inst (
|
|
.O(O), // Clock MUX output
|
|
.I0(I0), // Clock0 input
|
|
.I1(I1), // Clock1 input
|
|
.S(S) // Clock select input
|
|
);
|
|
|
|
// End of BUFGMUX_CTRL_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Phase Locked Loop (PLL)" treetype="folder">
|
|
<Template label="Advanced PLL for Virtex-5 (PLL_ADV)" treetype="template">
|
|
// PLL_ADV : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (PLL_ADV_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Unused inputs
|
|
// : and outputs may be removed or commented out.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// PLL_ADV: Phase-Lock Loop Clock Circuit
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
PLL_ADV #(
|
|
.BANDWIDTH("OPTIMIZED"), // "HIGH", "LOW" or "OPTIMIZED"
|
|
.CLKFBOUT_MULT(1), // Multiplication factor for all output clocks
|
|
.CLKFBOUT_PHASE(0.0), // Phase shift (degrees) of all output clocks
|
|
.CLKIN1_PERIOD(0.000), // Clock period (ns) of input clock on CLKIN1
|
|
.CLKIN2_PERIOD(0.000), // Clock period (ns) of input clock on CLKIN2
|
|
.CLKOUT0_DIVIDE(1), // Division factor for CLKOUT0 (1 to 128)
|
|
.CLKOUT0_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0 (0.01 to 0.99)
|
|
.CLKOUT0_PHASE(0.0), // Phase shift (degrees) for CLKOUT0 (0.0 to 360.0)
|
|
.CLKOUT1_DIVIDE(1), // Division factor for CLKOUT1 (1 to 128)
|
|
.CLKOUT1_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT1 (0.01 to 0.99)
|
|
.CLKOUT1_PHASE(0.0), // Phase shift (degrees) for CLKOUT1 (0.0 to 360.0)
|
|
.CLKOUT2_DIVIDE(1), // Division factor for CLKOUT2 (1 to 128)
|
|
.CLKOUT2_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT2 (0.01 to 0.99)
|
|
.CLKOUT2_PHASE(0.0), // Phase shift (degrees) for CLKOUT2 (0.0 to 360.0)
|
|
.CLKOUT3_DIVIDE(1), // Division factor for CLKOUT3 (1 to 128)
|
|
.CLKOUT3_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT3 (0.01 to 0.99)
|
|
.CLKOUT3_PHASE(0.0), // Phase shift (degrees) for CLKOUT3 (0.0 to 360.0)
|
|
.CLKOUT4_DIVIDE(1), // Division factor for CLKOUT4 (1 to 128)
|
|
.CLKOUT4_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT4 (0.01 to 0.99)
|
|
.CLKOUT4_PHASE(0.0), // Phase shift (degrees) for CLKOUT4 (0.0 to 360.0)
|
|
.CLKOUT5_DIVIDE(1), // Division factor for CLKOUT5 (1 to 128)
|
|
.CLKOUT5_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT5 (0.01 to 0.99)
|
|
.CLKOUT5_PHASE(0.0), // Phase shift (degrees) for CLKOUT5 (0.0 to 360.0)
|
|
.COMPENSATION("SYSTEM_SYNCHRONOUS"), // "SYSTEM_SYNCHRONOUS",
|
|
// "SOURCE_SYNCHRONOUS", "INTERNAL", "EXTERNAL",
|
|
// "DCM2PLL", "PLL2DCM"
|
|
.DIVCLK_DIVIDE(1), // Division factor for all clocks (1 to 52)
|
|
.EN_REL("FALSE"), // Enable release (PMCD mode only)
|
|
.PLL_PMCD_MODE("FALSE"), // PMCD Mode, TRUE/FASLE
|
|
.REF_JITTER(0.100), // Input reference jitter (0.000 to 0.999 UI%)
|
|
.RST_DEASSERT_CLK("CLKIN1") // In PMCD mode, clock to synchronize RST release
|
|
) PLL_ADV_inst (
|
|
.CLKFBDCM(CLKFBDCM), // Output feedback signal used when PLL feeds a DCM
|
|
.CLKFBOUT(CLKFBOUT), // General output feedback signal
|
|
.CLKOUT0(CLKOUT0), // One of six general clock output signals
|
|
.CLKOUT1(CLKOUT1), // One of six general clock output signals
|
|
.CLKOUT2(CLKOUT2), // One of six general clock output signals
|
|
.CLKOUT3(CLKOUT3), // One of six general clock output signals
|
|
.CLKOUT4(CLKOUT4), // One of six general clock output signals
|
|
.CLKOUT5(CLKOUT5), // One of six general clock output signals
|
|
.CLKOUTDCM0(CLKOUTDCM0), // One of six clock outputs to connect to the DCM
|
|
.CLKOUTDCM1(CLKOUTDCM1), // One of six clock outputs to connect to the DCM
|
|
.CLKOUTDCM2(CLKOUTDCM2), // One of six clock outputs to connect to the DCM
|
|
.CLKOUTDCM3(CLKOUTDCM3), // One of six clock outputs to connect to the DCM
|
|
.CLKOUTDCM4(CLKOUTDCM4), // One of six clock outputs to connect to the DCM
|
|
.CLKOUTDCM5(CLKOUTDCM5), // One of six clock outputs to connect to the DCM
|
|
.DO(DO), // Dynamic reconfig data output (16-bits)
|
|
.DRDY(DRDY), // Dynamic reconfig ready output
|
|
.LOCKED(LOCKED), // Active high PLL lock signal
|
|
.CLKFBIN(CLKFBIN), // Clock feedback input
|
|
.CLKIN1(CLKIN1), // Primary clock input
|
|
.CLKIN2(CLKIN2), // Secondary clock input
|
|
.CLKINSEL(CLKINSEL), // Selects '1' = CLKIN1, '0' = CLKIN2
|
|
.DADDR(DADDR), // Dynamic reconfig address input (5-bits)
|
|
.DCLK(DCLK), // Dynamic reconfig clock input
|
|
.DEN(DEN), // Dynamic reconfig enable input
|
|
.DI(DI), // Dynamic reconfig data input (16-bits)
|
|
.DWE(DWE), // Dynamic reconfig write enable input
|
|
.REL(REL), // Clock release input (PMCD mode only)
|
|
.RST(RST) // Asynchronous PLL reset
|
|
);
|
|
|
|
// End of PLL_ADV_inst instantiation
|
|
</Template>
|
|
<Template label="Base PLL (PLL_BASE)" treetype="template">
|
|
// PLL_BASE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (PLL_BASE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Unused inputs
|
|
// : and outputs may be removed or commented out.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// PLL_BASE: Phase-Lock Loop Clock Circuit
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
PLL_BASE #(
|
|
.BANDWIDTH("OPTIMIZED"), // "HIGH", "LOW" or "OPTIMIZED"
|
|
.CLKFBOUT_MULT(1), // Multiplication factor for all output clocks
|
|
.CLKFBOUT_PHASE(0.0), // Phase shift (degrees) of all output clocks
|
|
.CLKIN_PERIOD(0.000), // Clock period (ns) of input clock on CLKIN
|
|
.CLKOUT0_DIVIDE(1), // Division factor for CLKOUT0 (1 to 128)
|
|
.CLKOUT0_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0 (0.01 to 0.99)
|
|
.CLKOUT0_PHASE(0.0), // Phase shift (degrees) for CLKOUT0 (0.0 to 360.0)
|
|
.CLKOUT1_DIVIDE(1), // Division factor for CLKOUT1 (1 to 128)
|
|
.CLKOUT1_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT1 (0.01 to 0.99)
|
|
.CLKOUT1_PHASE(0.0), // Phase shift (degrees) for CLKOUT1 (0.0 to 360.0)
|
|
.CLKOUT2_DIVIDE(1), // Division factor for CLKOUT2 (1 to 128)
|
|
.CLKOUT2_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT2 (0.01 to 0.99)
|
|
.CLKOUT2_PHASE(0.0), // Phase shift (degrees) for CLKOUT2 (0.0 to 360.0)
|
|
.CLKOUT3_DIVIDE(1), // Division factor for CLKOUT3 (1 to 128)
|
|
.CLKOUT3_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT3 (0.01 to 0.99)
|
|
.CLKOUT3_PHASE(0.0), // Phase shift (degrees) for CLKOUT3 (0.0 to 360.0)
|
|
.CLKOUT4_DIVIDE(1), // Division factor for CLKOUT4 (1 to 128)
|
|
.CLKOUT4_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT4 (0.01 to 0.99)
|
|
.CLKOUT4_PHASE(0.0), // Phase shift (degrees) for CLKOUT4 (0.0 to 360.0)
|
|
.CLKOUT5_DIVIDE(1), // Division factor for CLKOUT5 (1 to 128)
|
|
.CLKOUT5_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT5 (0.01 to 0.99)
|
|
.CLKOUT5_PHASE(0.0), // Phase shift (degrees) for CLKOUT5 (0.0 to 360.0)
|
|
.COMPENSATION("SYSTEM_SYNCHRONOUS"), // "SYSTEM_SYNCHRONOUS",
|
|
// "SOURCE_SYNCHRONOUS", "INTERNAL", "EXTERNAL",
|
|
// "DCM2PLL", "PLL2DCM"
|
|
.DIVCLK_DIVIDE(1), // Division factor for all clocks (1 to 52)
|
|
.REF_JITTER(0.100) // Input reference jitter (0.000 to 0.999 UI%)
|
|
) PLL_BASE_inst (
|
|
.CLKFBOUT(CLKFBOUT), // General output feedback signal
|
|
.CLKOUT0(CLKOUT0), // One of six general clock output signals
|
|
.CLKOUT1(CLKOUT1), // One of six general clock output signals
|
|
.CLKOUT2(CLKOUT2), // One of six general clock output signals
|
|
.CLKOUT3(CLKOUT3), // One of six general clock output signals
|
|
.CLKOUT4(CLKOUT4), // One of six general clock output signals
|
|
.CLKOUT5(CLKOUT5), // One of six general clock output signals
|
|
.LOCKED(LOCKED), // Active high PLL lock signal
|
|
.CLKFBIN(CLKFBIN), // Clock feedback input
|
|
.CLKIN(CLKIN), // Clock input
|
|
.RST(RST) // Asynchronous PLL reset
|
|
);
|
|
|
|
// End of PLL_BASE_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="RAM/ROM" treetype="folder">
|
|
<SubFolder label="Distributed ROM" treetype="folder">
|
|
<Template label="32 X 1 (ROM32X1)" treetype="template">
|
|
// ROM32X1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ROM32X1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ROM32X1: 32 x 1 Asynchronous Distributed (LUT) ROM
|
|
// All FPGAs
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ROM32X1 #(
|
|
.INIT(32'h00000000) // Contents of ROM
|
|
) ROM32X1_inst (
|
|
.O(O), // ROM output
|
|
.A0(A0), // ROM address[0]
|
|
.A1(A1), // ROM address[1]
|
|
.A2(A2), // ROM address[2]
|
|
.A3(A3), // ROM address[3]
|
|
.A4(A4) // ROM address[4]
|
|
);
|
|
|
|
// End of ROM32X1_inst instantiation
|
|
</Template>
|
|
<Template label="64 X 1 (ROM64X1)" treetype="template">
|
|
// ROM64X1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ROM64X1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ROM64X1: 64 x 1 Asynchronous Distributed (LUT) ROM
|
|
// Virtex-5/6, Spartan-3/3E/3A/6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ROM64X1 #(
|
|
.INIT(64'h0000000000000000) // Contents of ROM
|
|
) ROM64X1_inst (
|
|
.O(O), // ROM output
|
|
.A0(A0), // ROM address[0]
|
|
.A1(A1), // ROM address[1]
|
|
.A2(A2), // ROM address[2]
|
|
.A3(A3), // ROM address[3]
|
|
.A4(A4), // ROM address[4]
|
|
.A5(A5) // ROM address[5]
|
|
);
|
|
|
|
// End of ROM64X1_inst instantiation
|
|
</Template>
|
|
<Template label="128 X 1 (ROM128X1)" treetype="template">
|
|
// ROM128X1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ROM128X1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ROM128X1: 128 x 1 Asynchronous Distributed (LUT) ROM
|
|
// Virtex-5/6, Spartan-3/3E/3A/6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ROM128X1 #(
|
|
.INIT(128'h00000000000000000000000000000000) // Contents of ROM
|
|
) ROM128X1_inst (
|
|
.O(O), // ROM output
|
|
.A0(A0), // ROM address[0]
|
|
.A1(A1), // ROM address[1]
|
|
.A2(A2), // ROM address[2]
|
|
.A3(A3), // ROM address[3]
|
|
.A4(A4), // ROM address[4]
|
|
.A5(A5), // ROM address[5]
|
|
.A6(A6) // ROM address[6]
|
|
);
|
|
|
|
// End of ROM128X1_inst instantiation
|
|
</Template>
|
|
<Template label="256 X 1 (ROM256X1)" treetype="template">
|
|
// ROM256X1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ROM256X1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ROM256X1: 256 x 1 Asynchronous Distributed (LUT) ROM
|
|
// Virtex-5/6, Spartan-3/3E/3A/6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ROM256X1 #(
|
|
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000) // Contents of ROM
|
|
) ROM256X1_inst (
|
|
.O(O), // ROM output
|
|
.A0(A0), // ROM address[0]
|
|
.A1(A1), // ROM address[1]
|
|
.A2(A2), // ROM address[2]
|
|
.A3(A3), // ROM address[3]
|
|
.A4(A4), // ROM address[4]
|
|
.A5(A5), // ROM address[5]
|
|
.A6(A6), // ROM address[6]
|
|
.A7(A7) // ROM address[7]
|
|
);
|
|
|
|
// End of ROM256X1_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Distributed RAM" treetype="folder">
|
|
<SubFolder label="Single-Port" treetype="folder">
|
|
<SubFolder label="32 Deep (5-bit address)" treetype="folder">
|
|
<Template label="32 x 1 posedge write (RAM32X1S)" treetype="template">
|
|
// RAM32X1S : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM32X1S_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM32X1S: 32 x 1 posedge write distributed (LUT) RAM
|
|
// All FPGA
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM32X1S #(
|
|
.INIT(32'h00000000) // Initial contents of RAM
|
|
) RAM32X1S_inst (
|
|
.O(O), // RAM output
|
|
.A0(A0), // RAM address[0] input
|
|
.A1(A1), // RAM address[1] input
|
|
.A2(A2), // RAM address[2] input
|
|
.A3(A3), // RAM address[3] input
|
|
.A4(A4), // RAM address[4] input
|
|
.D(D), // RAM data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM32X1S_inst instantiation
|
|
</Template>
|
|
<Template label="32 x 1 negedge write (RAM32X1S_1)" treetype="template">
|
|
// RAM32X1S_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM32X1S_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM32X1S_1: 32 x 1 negedge write distributed (LUT) RAM
|
|
// All FPGA
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM32X1S_1 #(
|
|
.INIT(32'h00000000) // Initial contents of RAM
|
|
)RAM32X1S_1_inst (
|
|
.O(O), // RAM output
|
|
.A0(A0), // RAM address[0] input
|
|
.A1(A1), // RAM address[1] input
|
|
.A2(A2), // RAM address[2] input
|
|
.A3(A3), // RAM address[3] input
|
|
.A4(A4), // RAM address[4] input
|
|
.D(D), // RAM data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM32X1S_1_inst instantiation
|
|
</Template>
|
|
<Template label="32 x 2 posedge write (RAM32X2S)" treetype="template">
|
|
// RAM32X2S : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM16X2S_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM32X2S: 32 x 2 posedge write distributed (LUT) RAM
|
|
// All FPGA
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM32X2S #(
|
|
.INIT_00(32'h00000000), // INIT for bit 0 of RAM
|
|
.INIT_01(32'h00000000) // INIT for bit 1 of RAM
|
|
) RAM32X2S_inst (
|
|
.O0(O0), // RAM data[0] output
|
|
.O1(O1), // RAM data[1] output
|
|
.A0(A0), // RAM address[0] input
|
|
.A1(A1), // RAM address[1] input
|
|
.A2(A2), // RAM address[2] input
|
|
.A3(A3), // RAM address[3] input
|
|
.A4(A4), // RAM address[4] input
|
|
.D0(D0), // RAM data[0] input
|
|
.D1(D1), // RAM data[1] input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM32X2S_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="64 Deep (6-bit address)" treetype="folder">
|
|
<Template label="64 X 1 posedge write (RAM64X1S)" treetype="template">
|
|
// RAM64X1S : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM64X1S_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM64X1S: 64 x 1 positive edge write, asynchronous read single-port distributed RAM
|
|
// All FPGA
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM64X1S #(
|
|
.INIT(64'h0000000000000000) // Initial contents of RAM
|
|
) RAM64X1S_inst (
|
|
.O(O), // 1-bit data output
|
|
.A0(A0), // Address[0] input bit
|
|
.A1(A1), // Address[1] input bit
|
|
.A2(A2), // Address[2] input bit
|
|
.A3(A3), // Address[3] input bit
|
|
.A4(A4), // Address[4] input bit
|
|
.A5(A5), // Address[5] input bit
|
|
.D(D), // 1-bit data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM64X1S_inst instantiation
|
|
</Template>
|
|
<Template label="64 X 1 negedge write (RAM64X1S_1)" treetype="template">
|
|
// RAM64X1S_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM64X1S_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM64X1S_1: 64 x 1 negative edge write, asynchronous read single-port distributed RAM
|
|
// All FPGA
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM64X1S_1 #(
|
|
.INIT(64'h0000000000000000) // Initial contents of RAM
|
|
) RAM64X1S_1_inst (
|
|
.O(O), // 1-bit data output
|
|
.A0(A0), // Address[0] input bit
|
|
.A1(A1), // Address[1] input bit
|
|
.A2(A2), // Address[2] input bit
|
|
.A3(A3), // Address[3] input bit
|
|
.A4(A4), // Address[4] input bit
|
|
.A5(A5), // Address[5] input bit
|
|
.D(D), // 1-bit data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM64X1S_1_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="128 Deep (7-bit address)" treetype="folder">
|
|
<Template label="128 X 1 posedge write (RAM128X1S)" treetype="template">
|
|
// RAM128X1S : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM128X1S_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM128X1S: 128 x 1 positive edge write, asynchronous read single-port distributed RAM
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM128X1S #(
|
|
.INIT(128'h00000000000000000000000000000000) // Initial contents of RAM
|
|
) RAM128X1S_inst (
|
|
.O(O), // 1-bit data output
|
|
.A0(A0), // Address[0] input bit
|
|
.A1(A1), // Address[1] input bit
|
|
.A2(A2), // Address[2] input bit
|
|
.A3(A3), // Address[3] input bit
|
|
.A4(A4), // Address[4] input bit
|
|
.A5(A5), // Address[5] input bit
|
|
.A6(A6), // Address[6] input bit
|
|
.D(D), // 1-bit data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM128X1S_inst instantiation
|
|
</Template>
|
|
<Template label="128 X 1 negedge write (RAM128X1S_1)" treetype="template">
|
|
// RAM128X1S_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM128X1S_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM128X1S_1: 128 x 1 negative edge write, asynchronous read single-port distributed RAM
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM128X1S_1 #(
|
|
.INIT(128'h00000000000000000000000000000000) // Initial contents of RAM
|
|
) RAM128X1S_1_inst (
|
|
.O(O), // 1-bit data output
|
|
.A0(A0), // Address[0] input bit
|
|
.A1(A1), // Address[1] input bit
|
|
.A2(A2), // Address[2] input bit
|
|
.A3(A3), // Address[3] input bit
|
|
.A4(A4), // Address[4] input bit
|
|
.A5(A5), // Address[5] input bit
|
|
.A6(A6), // Address[6] input bit
|
|
.D(D), // 1-bit data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM128X1S_1_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="256 Deep (8-bit address)" treetype="folder">
|
|
<Template label="256 X 1 posedge write (RAM256X1S)" treetype="template">
|
|
// RAM256X1S : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM256X1S_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM256X1S: 256-deep by 1-wide positive edge write, asynchronous read
|
|
// single-port distributed LUT RAM
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM256X1S #(
|
|
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAM256X1S_inst (
|
|
.O(O), // Read/write port 1-bit output
|
|
.A(A), // Read/write port 8-bit address input
|
|
.WE(WE), // Write enable input
|
|
.WCLK(WCLK), // Write clock input
|
|
.D(D) // RAM data input
|
|
);
|
|
|
|
// End of RAM256X1S_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Dual-Port" treetype="folder">
|
|
<Template label="32 X 1 posedge write (RAM32X1D)" treetype="template">
|
|
// RAM32X1D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM32X1D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM32X1D: 32 x 1 positive edge write, asynchronous read dual-port distributed RAM
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM32X1D #(
|
|
.INIT(32'h00000000) // Initial contents of RAM
|
|
) RAM32X1D_inst (
|
|
.DPO(DPO), // Read-only 1-bit data output
|
|
.SPO(SPO), // Rw/ 1-bit data output
|
|
.A0(A0), // Rw/ address[0] input bit
|
|
.A1(A1), // Rw/ address[1] input bit
|
|
.A2(A2), // Rw/ address[2] input bit
|
|
.A3(A3), // Rw/ address[3] input bit
|
|
.A4(A4), // Rw/ address[4] input bit
|
|
.D(D), // Write 1-bit data input
|
|
.DPRA0(DPRA0), // Read-only address[0] input bit
|
|
.DPRA1(DPRA1), // Read-only address[1] input bit
|
|
.DPRA2(DPRA2), // Read-only address[2] input bit
|
|
.DPRA3(DPRA3), // Read-only address[3] input bit
|
|
.DPRA4(DPRA4), // Read-only address[4] input bit
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM32X1D_inst instantiation
|
|
</Template>
|
|
<Template label="32 X 1 negedge write (RAM32X1D_1)" treetype="template">
|
|
// RAM32X1D_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM32X1D_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM32X1D_1: 32 x 1 negative edge write, asynchronous read dual-port distributed RAM
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM32X1D_1 #(
|
|
.INIT(32'h00000000) // Initial contents of RAM
|
|
) RAM32X1D_1_inst (
|
|
.DPO(DPO), // Read-only 1-bit data output
|
|
.SPO(SPO), // Rw/ 1-bit data output
|
|
.A0(A0), // Rw/ address[0] input bit
|
|
.A1(A1), // Rw/ address[1] input bit
|
|
.A2(A2), // Rw/ address[2] input bit
|
|
.A3(A3), // Rw/ address[3] input bit
|
|
.A4(A4), // Rw/ address[4] input bit
|
|
.D(D), // Write 1-bit data input
|
|
.DPRA0(DPRA0), // Read-only address[0] input bit
|
|
.DPRA1(DPRA1), // Read-only address[1] input bit
|
|
.DPRA2(DPRA2), // Read-only address[2] input bit
|
|
.DPRA3(DPRA3), // Read-only address[3] input bit
|
|
.DPRA4(DPRA4), // Read-only address[4] input bit
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM32X1D_1_inst instantiation
|
|
</Template>
|
|
<Template label="64 X 1 posedge write (RAM64X1D)" treetype="template">
|
|
// RAM64X1D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM64X1D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM64X1D: 64 x 1 positive edge write, asynchronous read dual-port distributed RAM
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM64X1D #(
|
|
.INIT(64'h0000000000000000) // Initial contents of RAM
|
|
) RAM64X1D_inst (
|
|
.DPO(DPO), // Read-only 1-bit data output
|
|
.SPO(SPO), // Rw/ 1-bit data output
|
|
.A0(A0), // Rw/ address[0] input bit
|
|
.A1(A1), // Rw/ address[1] input bit
|
|
.A2(A2), // Rw/ address[2] input bit
|
|
.A3(A3), // Rw/ address[3] input bit
|
|
.A4(A4), // Rw/ address[4] input bit
|
|
.A5(A5), // Rw/ address[5] input bit
|
|
.D(D), // Write 1-bit data input
|
|
.DPRA0(DPRA0), // Read-only address[0] input bit
|
|
.DPRA1(DPRA1), // Read-only address[1] input bit
|
|
.DPRA2(DPRA2), // Read-only address[2] input bit
|
|
.DPRA3(DPRA3), // Read-only address[3] input bit
|
|
.DPRA4(DPRA4), // Read-only address[4] input bit
|
|
.DPRA5(DPRA5), // Read-only address[5] input bit
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM64X1D_inst instantiation
|
|
</Template>
|
|
<Template label="128 X 1 posedge write (RAM128X1D)" treetype="template">
|
|
// RAM128X1D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM128X1D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM128X1D: 128-deep by 1-wide positive edge write, asynchronous read
|
|
// dual-port distributed LUT RAM
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM128X1D #(
|
|
.INIT(128'h00000000000000000000000000000000)
|
|
) RAM128X1D_inst (
|
|
.DPO(DPO), // Read port 1-bit output
|
|
.SPO(SPO), // Read/write port 1-bit output
|
|
.A(A), // Read/write port 7-bit address input
|
|
.D(D), // RAM data input
|
|
.DPRA(DPRA), // Read port 7-bit address input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM128X1D_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Multi-Port" treetype="folder">
|
|
<Template label="32 X 8 (RAM32M)" treetype="template">
|
|
// RAM32M : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM32M_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM32M: 32-deep by 8-wide Multi Port LUT RAM
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM32M #(
|
|
.INIT_A(64'h0000000000000000), // Initial contents of A Port
|
|
.INIT_B(64'h0000000000000000), // Initial contents of B Port
|
|
.INIT_C(64'h0000000000000000), // Initial contents of C Port
|
|
.INIT_D(64'h0000000000000000) // Initial contents of D Port
|
|
) RAM32M_inst (
|
|
.DOA(DOA), // Read port A 2-bit output
|
|
.DOB(DOB), // Read port B 2-bit output
|
|
.DOC(DOC), // Read port C 2-bit output
|
|
.DOD(DOD), // Read/write port D 2-bit output
|
|
.ADDRA(ADDRA), // Read port A 5-bit address input
|
|
.ADDRB(ADDRB), // Read port B 5-bit address input
|
|
.ADDRC(ADDRC), // Read port C 5-bit address input
|
|
.ADDRD(ADDRD), // Read/write port D 5-bit address input
|
|
.DIA(DIA), // RAM 2-bit data write input addressed by ADDRD,
|
|
// read addressed by ADDRA
|
|
.DIB(DIB), // RAM 2-bit data write input addressed by ADDRD,
|
|
// read addressed by ADDRB
|
|
.DIC(DIC), // RAM 2-bit data write input addressed by ADDRD,
|
|
// read addressed by ADDRC
|
|
.DID(DID), // RAM 2-bit data write input addressed by ADDRD,
|
|
// read addressed by ADDRD
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM32M_inst instantiation
|
|
</Template>
|
|
<Template label="64 X 4 (RAM64M)" treetype="template">
|
|
// RAM64M : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM64M_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM64M: 64-deep by 4-wide Multi Port LUT RAM
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM64M #(
|
|
.INIT_A(64'h0000000000000000), // Initial contents of A Port
|
|
.INIT_B(64'h0000000000000000), // Initial contents of B Port
|
|
.INIT_C(64'h0000000000000000), // Initial contents of C Port
|
|
.INIT_D(64'h0000000000000000) // Initial contents of D Port
|
|
) RAM64M_inst (
|
|
.DOA(DOA), // Read port A 1-bit output
|
|
.DOB(DOB), // Read port B 1-bit output
|
|
.DOC(DOC), // Read port C 1-bit output
|
|
.DOD(DOD), // Read/write port D 1-bit output
|
|
.DIA(DIA), // RAM 1-bit data write input addressed by ADDRD,
|
|
// read addressed by ADDRA
|
|
.DIB(DIB), // RAM 1-bit data write input addressed by ADDRD,
|
|
// read addressed by ADDRB
|
|
.DIC(DIC), // RAM 1-bit data write input addressed by ADDRD,
|
|
// read addressed by ADDRC
|
|
.DID(DID), // RAM 1-bit data write input addressed by ADDRD,
|
|
// read addressed by ADDRD
|
|
.ADDRA(ADDRA), // Read port A 6-bit address input
|
|
.ADDRB(ADDRB), // Read port B 6-bit address input
|
|
.ADDRC(ADDRC), // Read port C 6-bit address input
|
|
.ADDRD(ADDRD), // Read/write port D 6-bit address input
|
|
.WE(WE), // Write enable input
|
|
.WCLK(WCLK) // Write clock input
|
|
);
|
|
|
|
// End of RAM64M_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Block RAM" treetype="folder">
|
|
<Template label="72x36k Simple Dual-Port BlockRAM w/ ECC (RAMB36SDP)" treetype="template">
|
|
// RAMB36SDP : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB36SDP_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB36SDP: 72x512 Simple Dual-Port BlockRAM w/ ECC
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB36SDP #(
|
|
.SIM_MODE("SAFE"), // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details
|
|
.DO_REG(0), // Optional output register (0 or 1)
|
|
.EN_ECC_READ("FALSE"), // Enable ECC decoder, "TRUE" or "FALSE"
|
|
.EN_ECC_WRITE("FALSE"), // Enable ECC encoder, "TRUE" or "FALSE"
|
|
.INIT(72'h000000000000000000), // Initial values on output port
|
|
.SIM_COLLISION_CHECK("ALL"), // Collision check enable "ALL", "WARNING_ONLY",
|
|
// "GENERATE_X_ONLY" or "NONE"
|
|
.SRVAL(72'h000000000000000000), // Set/Reset value for port output
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
.INIT_00(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_01(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_02(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_03(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_04(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_05(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_06(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_07(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_08(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_09(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_0A(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_0B(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_0C(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_0D(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_0E(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_0F(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_10(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_11(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_12(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_13(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_14(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_15(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_16(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_17(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_18(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_19(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_1A(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_1B(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_1C(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_1D(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_1E(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_1F(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_20(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_21(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_22(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_23(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_24(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_25(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_26(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_27(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_28(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_29(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_2A(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_2B(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_2C(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_2D(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_2E(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_2F(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_30(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_31(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_32(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_33(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_34(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_35(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_36(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_37(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_38(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_39(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_3A(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_3B(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_3C(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_3D(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_3E(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_3F(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_40(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_41(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_42(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_43(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_44(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_45(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_46(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_47(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_48(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_49(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_4A(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_4B(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_4C(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_4D(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_4E(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_4F(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_50(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_51(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_52(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_53(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_54(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_55(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_56(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_57(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_58(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_59(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_5A(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_5B(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_5C(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_5D(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_5E(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_5F(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_60(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_61(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_62(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_63(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_64(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_65(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_66(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_67(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_68(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_69(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_6A(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_6B(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_6C(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_6D(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_6E(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_6F(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_70(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_71(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_72(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_73(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_74(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_75(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_76(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_77(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_78(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_79(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_7A(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_7B(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_7C(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_7D(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_7E(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
.INIT_7F(256'h0000000000000000_0000000000000000_0000000000000000_0000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
.INITP_00(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INITP_01(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INITP_02(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INITP_03(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INITP_04(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INITP_05(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INITP_06(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INITP_07(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INITP_08(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INITP_09(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INITP_0A(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INITP_0B(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INITP_0C(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INITP_0D(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INITP_0E(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00),
|
|
.INITP_0F(256'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00)
|
|
) RAMB36SDP_inst (
|
|
.DBITERR(DBITERR), // 1-bit double bit error status output
|
|
.SBITERR(SBITERR), // 1-bit single bit error status output
|
|
.DO(DO), // 64-bit data output
|
|
.DOP(DOP), // 8-bit parity data output
|
|
.ECCPARITY(ECCPARITY), // 8-bit generated error correction parity
|
|
.RDCLK(RDCLK), // 1-bit read port clock
|
|
.RDEN(RDEN), // 1-bit read port enable
|
|
.REGCE(REGCE), // 1-bit register enable input
|
|
.SSR(SSR), // 1-bit synchronous output set/reset input
|
|
.WRCLK(WRCLK), // 1-bit write port clock
|
|
.WREN(WREN), // 1-bit write port enable
|
|
.WRADDR(WRADDR), // 9-bit write port address input
|
|
.RDADDR(RDADDR), // 9-bit read port address input
|
|
.DI(DI), // 64-bit data input
|
|
.DIP(DIP), // 8-bit parity data input
|
|
.WE(WE) // 8-bit write enable input
|
|
);
|
|
|
|
// End of RAMB36SDP_inst instantiation
|
|
</Template>
|
|
<Template label="32k + 4k Parity parameterizable True Dual-Port BlockRAM (RAMB36)" treetype="template">
|
|
// RAMB36 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB36_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB36: 32k+4k Parity parameterizable True Dual-Port BlockRAM
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB36 #(
|
|
.SIM_MODE("SAFE"), // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details
|
|
.DOA_REG(0), // Optional output registers on A port (0 or 1)
|
|
.DOB_REG(0), // Optional output registers on B port (0 or 1)
|
|
.INIT_A(36'h000000000), // Initial values on A output port
|
|
.INIT_B(36'h000000000), // Initial values on B output port
|
|
.RAM_EXTENSION_A("NONE"), // "UPPER", "LOWER" or "NONE" when cascaded
|
|
.RAM_EXTENSION_B("NONE"), // "UPPER", "LOWER" or "NONE" when cascaded
|
|
.READ_WIDTH_A(0), // Valid values are 1, 2, 4, 9, 18, or 36
|
|
.READ_WIDTH_B(0), // Valid values are 1, 2, 4, 9, 18, or 36
|
|
.SIM_COLLISION_CHECK("ALL"), // Collision check enable "ALL", "WARNING_ONLY",
|
|
// "GENERATE_X_ONLY" or "NONE"
|
|
.SRVAL_A(36'h000000000), // Set/Reset value for A port output
|
|
.SRVAL_B(36'h000000000), // Set/Reset value for B port output
|
|
.WRITE_MODE_A("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
|
|
.WRITE_MODE_B("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
|
|
.WRITE_WIDTH_A(0), // Valid values are 1, 2, 4, 9, 18, or 36
|
|
.WRITE_WIDTH_B(0), // Valid values are 1, 2, 4, 9, 18, or 36
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB36_inst (
|
|
.CASCADEOUTLATA(CASCADEOUTLATA), // 1-bit cascade A latch output
|
|
.CASCADEOUTLATB(CASCADEOUTLATB), // 1-bit cascade B latch output
|
|
.CASCADEOUTREGA(CASCADEOUTREGA), // 1-bit cascade A register output
|
|
.CASCADEOUTREGB(CASCADEOUTREGB), // 1-bit cascade B register output
|
|
.DOA(DOA), // 32-bit A port data output
|
|
.DOB(DOB), // 32-bit B port data output
|
|
.DOPA(DOPA), // 4-bit A port parity data output
|
|
.DOPB(DOPB), // 4-bit B port parity data output
|
|
.ADDRA(ADDRA), // 16-bit A port address input
|
|
.ADDRB(ADDRB), // 16-bit B port address input
|
|
.CASCADEINLATA(CASCADEINLATA), // 1-bit cascade A latch input
|
|
.CASCADEINLATB(CASCADEINLATB), // 1-bit cascade B latch input
|
|
.CASCADEINREGA(CASCADEINREGA), // 1-bit cascade A register input
|
|
.CASCADEINREGB(CASCADEINREGB), // 1-bit cascade B register input
|
|
.CLKA(CLKA), // 1-bit A port clock input
|
|
.CLKB(CLKB), // 1-bit B port clock input
|
|
.DIA(DIA), // 32-bit A port data input
|
|
.DIB(DIB), // 32-bit B port data input
|
|
.DIPA(DIPA), // 4-bit A port parity data input
|
|
.DIPB(DIPB), // 4-bit B port parity data input
|
|
.ENA(ENA), // 1-bit A port enable input
|
|
.ENB(ENB), // 1-bit B port enable input
|
|
.REGCEA(REGCEA), // 1-bit A port register enable input
|
|
.REGCEB(REGCEB), // 1-bit B port register enable input
|
|
.SSRA(SSRA), // 1-bit A port set/reset input
|
|
.SSRB(SSRB), // 1-bit B port set/reset input
|
|
.WEA(WEA), // 4-bit A port write enable input
|
|
.WEB(WEB) // 4-bit B port write enable input
|
|
);
|
|
|
|
// End of RAMB36_inst instantiation
|
|
</Template>
|
|
<Template label="16k + 2k Parity parameterizable True Dual-Port BlockRAM (RAMB18)" treetype="template">
|
|
// RAMB18 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB18_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB18: 16k+2k Parity parameterizable True Dual-Port BlockRAM
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB18 #(
|
|
.SIM_MODE("SAFE"), // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details
|
|
.DOA_REG(0), // Optional output registers on A port (0 or 1)
|
|
.DOB_REG(0), // Optional output registers on B port (0 or 1)
|
|
.INIT_A(18'h00000), // Initial values on A output port
|
|
.INIT_B(18'h00000), // Initial values on B output port
|
|
.READ_WIDTH_A(0), // Valid values are 1, 2, 4, 9 or 18
|
|
.READ_WIDTH_B(0), // Valid values are 1, 2, 4, 9 or 18
|
|
.SIM_COLLISION_CHECK("ALL"), // Collision check enable "ALL", "WARNING_ONLY",
|
|
// "GENERATE_X_ONLY" or "NONE"
|
|
.SRVAL_A(18'h00000), // Set/Reset value for A port output
|
|
.SRVAL_B(18'h00000), // Set/Reset value for B port output
|
|
.WRITE_MODE_A("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
|
|
.WRITE_MODE_B("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
|
|
.WRITE_WIDTH_A(0), // Valid values are 1, 2, 4, 9 or 18
|
|
.WRITE_WIDTH_B(0), // Valid values are 1, 2, 4, 9 or 18
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB18_inst (
|
|
.DOA(DOA), // 16-bit A port data output
|
|
.DOB(DOB), // 16-bit B port data output
|
|
.DOPA(DOPA), // 2-bit A port parity data output
|
|
.DOPB(DOPB), // 2-bit B port parity data output
|
|
.ADDRA(ADDRA), // 14-bit A port address input
|
|
.ADDRB(ADDRB), // 14-bit B port address input
|
|
.CLKA(CLKA), // 1-bit A port clock input
|
|
.CLKB(CLKB), // 1-bit B port clock input
|
|
.DIA(DIA), // 16-bit A port data input
|
|
.DIB(DIB), // 16-bit B port data input
|
|
.DIPA(DIPA), // 2-bit A port parity data input
|
|
.DIPB(DIPB), // 2-bit B port parity data input
|
|
.ENA(ENA), // 1-bit A port enable input
|
|
.ENB(ENB), // 1-bit B port enable input
|
|
.REGCEA(REGCEA), // 1-bit A port register enable input
|
|
.REGCEB(REGCEB), // 1-bit B port register enable input
|
|
.SSRA(SSRA), // 1-bit A port set/reset input
|
|
.SSRB(SSRB), // 1-bit B port set/reset input
|
|
.WEA(WEA), // 2-bit A port write enable input
|
|
.WEB(WEB) // 2-bit B port write enable input
|
|
);
|
|
|
|
// End of RAMB18_inst instantiation
|
|
</Template>
|
|
<Template label="36x18k Simple Dual-Port BlockRAM (RAMB18SDP)" treetype="template">
|
|
// RAMB18SDP : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB18SDP_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB18SDP: 36x512 Simple Dual-Port BlockRAM
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB18SDP #(
|
|
.SIM_MODE("SAFE"), // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details
|
|
.DO_REG(0), // Optional output register (0 or 1)
|
|
.INIT(36'h000000000), // Initial values on output port
|
|
.SIM_COLLISION_CHECK("ALL"), // Collision check enable "ALL", "WARNING_ONLY",
|
|
// "GENERATE_X_ONLY" or "NONE"
|
|
.SRVAL(36'h000000000), // Set/Reset value for port output
|
|
|
|
// The forllowing INIT_xx declarations specify the initial contents of the RAM
|
|
.INIT_00(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_01(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_02(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_03(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_04(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_05(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_06(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_07(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_08(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_09(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_0A(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_0B(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_0C(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_0D(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_0E(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_0F(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_10(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_11(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_12(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_13(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_14(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_15(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_16(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_17(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_18(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_19(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_1A(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_1B(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_1C(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_1D(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_1E(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_1F(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_20(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_21(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_22(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_23(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_24(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_25(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_26(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_27(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_28(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_29(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_2A(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_2B(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_2C(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_2D(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_2E(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_2F(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_30(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_31(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_32(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_33(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_34(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_35(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_36(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_37(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_38(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_39(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_3A(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_3B(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_3C(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_3D(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_3E(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
.INIT_3F(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAMB18SDP_inst (
|
|
.DO(DO), // 32-bit data output
|
|
.DOP(DOP), // 4-bit parity data output
|
|
.RDCLK(RDCLK), // 1-bit read port clock
|
|
.RDEN(RDEN), // 1-bit read port enable
|
|
.REGCE(REGCE), // 1-bit register enable input
|
|
.SSR(SSR), // 1-bit synchronous output set/reset input
|
|
.WRCLK(WRCLK), // 1-bit write port clock
|
|
.WREN(WREN), // 1-bit write port enable
|
|
.WRADDR(WRADDR), // 9-bit write port address input
|
|
.RDADDR(RDADDR), // 9-bit read port address input
|
|
.DI(DI), // 32-bit data input
|
|
.DIP(DIP), // 4-bit parity data input
|
|
.WE(WE) // 4-bit write enable input
|
|
);
|
|
|
|
// End of RAMB18SDP_inst instantiation
|
|
</Template>
|
|
<SubFolder label="FIFO" treetype="folder">
|
|
<Template label="16k+2k Parity FIFO (FIFO18)" treetype="template">
|
|
// FIFO18 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FIFO18_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FIFO18: 16k+2k Parity Synchronous/Asynchronous BlockRAM FIFO
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FIFO18 #(
|
|
.SIM_MODE("SAFE"), // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details
|
|
.ALMOST_FULL_OFFSET(12'h080), // Sets almost full threshold
|
|
.ALMOST_EMPTY_OFFSET(12'h080), // Sets the almost empty threshold
|
|
.DATA_WIDTH(4), // Sets data width to 4, 9 or 18
|
|
.DO_REG(1), // Enable output register (0 or 1)
|
|
// Must be 1 if EN_SYN = "FALSE"
|
|
.EN_SYN("FALSE"), // Specifies FIFO as Asynchronous ("FALSE")
|
|
// or Synchronous ("TRUE")
|
|
.FIRST_WORD_FALL_THROUGH("FALSE") // Sets the FIFO FWFT to "TRUE" or "FALSE"
|
|
) FIFO18_inst (
|
|
.ALMOSTEMPTY(ALMOSTEMPTY), // 1-bit almost empty output flag
|
|
.ALMOSTFULL(ALMOSTFULL), // 1-bit almost full output flag
|
|
.DO(DO), // 16-bit data output
|
|
.DOP(DOP), // 2-bit parity data output
|
|
.EMPTY(EMPTY), // 1-bit empty output flag
|
|
.FULL(FULL), // 1-bit full output flag
|
|
.RDCOUNT(RDCOUNT), // 12-bit read count output
|
|
.RDERR(RDERR), // 1-bit read error output
|
|
.WRCOUNT(WRCOUNT), // 12-bit write count output
|
|
.WRERR(WRERR), // 1-bit write error
|
|
.DI(DI), // 16-bit data input
|
|
.DIP(DIP), // 2-bit parity input
|
|
.RDCLK(RDCLK), // 1-bit read clock input
|
|
.RDEN(RDEN), // 1-bit read enable input
|
|
.RST(RST), // 1-bit reset input
|
|
.WRCLK(WRCLK), // 1-bit write clock input
|
|
.WREN(WREN) // 1-bit write enable input
|
|
);
|
|
|
|
// End of FIFO18_inst instantiation
|
|
</Template>
|
|
<Template label="36x18k FIFO (FIFO18_36)" treetype="template">
|
|
// FIFO18_36 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FIFO18_36_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FIFO18_36: 36x18k Synchronous/Asynchronous BlockRAM FIFO
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FIFO18_36 #(
|
|
.SIM_MODE("SAFE"), // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details
|
|
.ALMOST_FULL_OFFSET(9'h080), // Sets almost full threshold
|
|
.ALMOST_EMPTY_OFFSET(9'h080), // Sets the almost empty threshold
|
|
.DO_REG(1), // Enable output register (0 or 1)
|
|
// Must be 1 if EN_SYN = "FALSE"
|
|
.EN_SYN("FALSE"), // Specifies FIFO as Asynchronous ("FALSE")
|
|
// or Synchronous ("TRUE")
|
|
.FIRST_WORD_FALL_THROUGH("FALSE") // Sets the FIFO FWFT to "TRUE" or "FALSE"
|
|
) FIFO18_36_inst (
|
|
.ALMOSTEMPTY(ALMOSTEMPTY), // 1-bit almost empty output flag
|
|
.ALMOSTFULL(ALMOSTFULL), // 1-bit almost full output flag
|
|
.DO(DO), // 32-bit data output
|
|
.DOP(DOP), // 4-bit parity data output
|
|
.EMPTY(EMPTY), // 1-bit empty output flag
|
|
.FULL(FULL), // 1-bit full output flag
|
|
.RDCOUNT(RDCOUNT), // 9-bit read count output
|
|
.RDERR(RDERR), // 1-bit read error output
|
|
.WRCOUNT(WRCOUNT), // 9-bit write count output
|
|
.WRERR(WRERR), // 1-bit write error
|
|
.DI(DI), // 32-bit data input
|
|
.DIP(DIP), // 4-bit parity input
|
|
.RDCLK(RDCLK), // 1-bit read clock input
|
|
.RDEN(RDEN), // 1-bit read enable input
|
|
.RST(RST), // 1-bit reset input
|
|
.WRCLK(WRCLK), // 1-bit write clock input
|
|
.WREN(WREN) // 1-bit write enable input
|
|
);
|
|
|
|
// End of FIFO18_36_inst instantiation
|
|
</Template>
|
|
<Template label="32k+4k Parity FIFO (FIFO36)" treetype="template">
|
|
// FIFO36 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FIFO36_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FIFO36: 32k+4k Parity Synchronous/Asynchronous BlockRAM FIFO
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FIFO36 #(
|
|
.SIM_MODE("SAFE"), // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details
|
|
.ALMOST_FULL_OFFSET(13'h0080), // Sets almost full threshold
|
|
.ALMOST_EMPTY_OFFSET(13'h0080), // Sets the almost empty threshold
|
|
.DATA_WIDTH(4), // Sets data width to 4, 9, 18 or 36
|
|
.DO_REG(1), // Enable output register (0 or 1)
|
|
// Must be 1 if EN_SYN = "FALSE"
|
|
.EN_SYN("FALSE"), // Specifies FIFO as Asynchronous ("FALSE")
|
|
// or Synchronous ("TRUE")
|
|
.FIRST_WORD_FALL_THROUGH("FALSE") // Sets the FIFO FWFT to "TRUE" or "FALSE"
|
|
) FIFO36_inst (
|
|
.ALMOSTEMPTY(ALMOSTEMPTY), // 1-bit almost empty output flag
|
|
.ALMOSTFULL(ALMOSTFULL), // 1-bit almost full output flag
|
|
.DO(DO), // 32-bit data output
|
|
.DOP(DOP), // 4-bit parity data output
|
|
.EMPTY(EMPTY), // 1-bit empty output flag
|
|
.FULL(FULL), // 1-bit full output flag
|
|
.RDCOUNT(RDCOUNT), // 13-bit read count output
|
|
.RDERR(RDERR), // 1-bit read error output
|
|
.WRCOUNT(WRCOUNT), // 13-bit write count output
|
|
.WRERR(WRERR), // 1-bit write error
|
|
.DI(DI), // 32-bit data input
|
|
.DIP(DIP), // 4-bit parity input
|
|
.RDCLK(RDCLK), // 1-bit read clock input
|
|
.RDEN(RDEN), // 1-bit read enable input
|
|
.RST(RST), // 1-bit reset input
|
|
.WRCLK(WRCLK), // 1-bit write clock input
|
|
.WREN(WREN) // 1-bit write enable input
|
|
);
|
|
|
|
// End of FIFO36_inst instantiation
|
|
</Template>
|
|
<Template label="72x36k FIFO w/ ECC (FIFO36_72)" treetype="template">
|
|
// FIFO36_72 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FIFO36_72_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FIFO36_72: 72x36k Synchronous/Asynchronous BlockRAM FIFO w/ ECC
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FIFO36_72 #(
|
|
.SIM_MODE("SAFE"), // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details
|
|
.ALMOST_FULL_OFFSET(9'h080), // Sets almost full threshold
|
|
.ALMOST_EMPTY_OFFSET(9'h080), // Sets the almost empty threshold
|
|
.DO_REG(1), // Enable output register (0 or 1)
|
|
// Must be 1 if EN_SYN = "FALSE"
|
|
.EN_ECC_READ("FALSE"), // Enable ECC decoder, "TRUE" or "FALSE"
|
|
.EN_ECC_WRITE("FALSE"), // Enable ECC encoder, "TRUE" or "FALSE"
|
|
.EN_SYN("FALSE"), // Specifies FIFO as Asynchronous ("FALSE")
|
|
// or Synchronous ("TRUE")
|
|
.FIRST_WORD_FALL_THROUGH("FALSE") // Sets the FIFO FWFT to "TRUE" or "FALSE"
|
|
) FIFO36_72_inst (
|
|
.ALMOSTEMPTY(ALMOSTEMPTY), // 1-bit almost empty output flag
|
|
.ALMOSTFULL(ALMOSTFULL), // 1-bit almost full output flag
|
|
.DBITERR(DBITERR), // 1-bit double bit error status output
|
|
.DO(DO), // 64-bit data output
|
|
.DOP(DOP), // 4-bit parity data output
|
|
.ECCPARITY(ECCPARITY), // 8-bit generated error correction parity
|
|
.EMPTY(EMPTY), // 1-bit empty output flag
|
|
.FULL(FULL), // 1-bit full output flag
|
|
.RDCOUNT(RDCOUNT), // 9-bit read count output
|
|
.RDERR(RDERR), // 1-bit read error output
|
|
.SBITERR(SBITERR), // 1-bit single bit error status output
|
|
.WRCOUNT(WRCOUNT), // 9-bit write count output
|
|
.WRERR(WRERR), // 1-bit write error
|
|
.DI(DI), // 64-bit data input
|
|
.DIP(DIP), // 4-bit parity input
|
|
.RDCLK(RDCLK), // 1-bit read clock input
|
|
.RDEN(RDEN), // 1-bit read enable input
|
|
.RST(RST), // 1-bit reset input
|
|
.WRCLK(WRCLK), // 1-bit write clock input
|
|
.WREN(WREN) // 1-bit write enable input
|
|
);
|
|
|
|
// End of FIFO36_72_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="I/O Components" treetype="folder">
|
|
<SubFolder label="Input" treetype="folder">
|
|
<Template label="Single-ended Buffer (IBUF)" treetype="template">
|
|
// IBUF : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUF_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUF: Single-ended Input Buffer
|
|
// All devices
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUF #(
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
)IBUF_inst (
|
|
.O(O), // Buffer output
|
|
.I(I) // Buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUF_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer (IBUFDS)" treetype="template">
|
|
// IBUFDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFDS: Differential Input Buffer
|
|
// Virtex-5, Spartan-3/3E/3A
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFDS #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination (Virtex-5, Spartan-3E/3A)
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
) IBUFDS_inst (
|
|
.O(O), // Buffer output
|
|
.I(I), // Diff_p buffer input (connect directly to top-level port)
|
|
.IB(IB) // Diff_n buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUFDS_inst instantiation
|
|
</Template>
|
|
<Template label="Single-ended Global Clock (IBUFG)" treetype="template">
|
|
// IBUFG : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFG_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFG: Single-ended global clock input buffer
|
|
// All FPGA
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFG #(
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
) IBUFG_inst (
|
|
.O(O), // Clock buffer output
|
|
.I(I) // Clock buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUFG_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Global Clock (IBUFGDS)" treetype="template">
|
|
// IBUFGDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFGDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFGDS: Differential Global Clock Input Buffer
|
|
// Virtex-5, Spartan-3/3E/3A
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFGDS #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
) IBUFGDS_inst (
|
|
.O(O), // Clock buffer output
|
|
.I(I), // Diff_p clock buffer input (connect directly to top-level port)
|
|
.IB(IB) // Diff_n clock buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUFGDS_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Output" treetype="folder">
|
|
<Template label="Single-ended Buffer (OBUF)" treetype="template">
|
|
// OBUF : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OBUF_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OBUF: Single-ended Output Buffer
|
|
// All devices
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OBUF #(
|
|
.DRIVE(12), // Specify the output drive strength
|
|
.IOSTANDARD("DEFAULT"), // Specify the output I/O standard
|
|
.SLEW("SLOW") // Specify the output slew rate
|
|
) OBUF_inst (
|
|
.O(O), // Buffer output (connect directly to top-level port)
|
|
.I(I) // Buffer input
|
|
);
|
|
|
|
// End of OBUF_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer (OBUFDS)" treetype="template">
|
|
|
|
// OBUFDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OBUFDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OBUFDS: Differential Output Buffer
|
|
// Virtex-5, Spartan-3/3E/3A
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OBUFDS #(
|
|
.IOSTANDARD("DEFAULT") // Specify the output I/O standard
|
|
) OBUFDS_inst (
|
|
.O(O), // Diff_p output (connect directly to top-level port)
|
|
.OB(OB), // Diff_n output (connect directly to top-level port)
|
|
.I(I) // Buffer input
|
|
);
|
|
|
|
// End of OBUFDS_inst instantiation
|
|
</Template>
|
|
<Template label="Single-ended 3-state Buffer (OBUFT)" treetype="template">
|
|
// OBUFT : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OBUFT_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OBUFT: Single-ended 3-state Output Buffer
|
|
// All devices
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OBUFT #(
|
|
.DRIVE(12), // Specify the output drive strength
|
|
.IOSTANDARD("DEFAULT"), // Specify the output I/O standard
|
|
.SLEW("SLOW") // Specify the output slew rate
|
|
) OBUFT_inst (
|
|
.O(O), // Buffer output (connect directly to top-level port)
|
|
.I(I), // Buffer input
|
|
.T(T) // 3-state enable input
|
|
);
|
|
|
|
// End of OBUFT_inst instantiation
|
|
</Template>
|
|
<Template label="Differential 3-state Buffer (OBUFTDS)" treetype="template">
|
|
// OBUFTDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OBUFTDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OBUFTDS: Differential 3-state Output Buffer
|
|
// Virtex-5, Spartan-3/3E/3A
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OBUFTDS #(
|
|
.IOSTANDARD("DEFAULT") // Specify the output I/O standard
|
|
) OBUFTDS_inst (
|
|
.O(O), // Diff_p output (connect directly to top-level port)
|
|
.OB(OB), // Diff_n output (connect directly to top-level port)
|
|
.I(I), // Buffer input
|
|
.T(T) // 3-state enable input
|
|
);
|
|
|
|
// End of OBUFTDS_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<Template label="Digital Controlled Impedance Reset (DCIRESET)" treetype="template">
|
|
// DCIRESET : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (DCIRESET_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// DCIRESET: Digital Controlled Impedance (DCI) Reset Component
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
DCIRESET DCIRESET_inst (
|
|
.LOCKED(LOCKED), // 1-bit DCI LOCKED Output
|
|
.RST(RST) // 1-bit DCI Reset Input
|
|
);
|
|
|
|
// End of DCIRESET_inst instantiation
|
|
</Template>
|
|
<SubFolder label="Bi-directional" treetype="folder">
|
|
<Template label="Single-ended Buffer (IOBUF)" treetype="template">
|
|
// IOBUF : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IOBUF_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IOBUF: Single-ended Bi-directional Buffer
|
|
// All devices
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IOBUF #(
|
|
.DRIVE(12), // Specify the output drive strength
|
|
.IOSTANDARD("DEFAULT"), // Specify the I/O standard
|
|
.SLEW("SLOW") // Specify the output slew rate
|
|
) IOBUF_inst (
|
|
.O(O), // Buffer output
|
|
.IO(IO), // Buffer inout port (connect directly to top-level port)
|
|
.I(I), // Buffer input
|
|
.T(T) // 3-state enable input, high=input, low=output
|
|
);
|
|
|
|
// End of IOBUF_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer (IOBUFDS)" treetype="template">
|
|
// IOBUFDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IOBUFDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IOBUFDS: Differential Bi-directional Buffer
|
|
// Virtex-5, Spartan-3/3E/3A
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IOBUFDS #(
|
|
.IOSTANDARD("BLVDS_25") // Specify the I/O standard
|
|
) IOBUFDS_inst (
|
|
.O(O), // Buffer output
|
|
.IO(IO), // Diff_p inout (connect directly to top-level port)
|
|
.IOB(IOB), // Diff_n inout (connect directly to top-level port)
|
|
.I(I), // Buffer input
|
|
.T(T) // 3-state enable input, high=input, low=output
|
|
);
|
|
|
|
// End of IOBUFDS_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Weak drivers" treetype="folder">
|
|
<Template label="PULLUP" treetype="template">
|
|
// PULLUP : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (PULLUP_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design.
|
|
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// PULLUP: I/O Buffer Weak Pull-up
|
|
// All FPGA, CoolRunner-II
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
PULLUP PULLUP_inst (
|
|
.O(O) // Pullup output (connect directly to top-level port)
|
|
);
|
|
|
|
// End of PULLUP_inst instantiation
|
|
</Template>
|
|
<Template label="PULLDOWN" treetype="template">
|
|
// PULLDOWN : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (PULLDOWN_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// PULLDOWN: I/O Buffer Weak Pull-down
|
|
// All FPGA
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
PULLDOWN PULLDOWN_inst (
|
|
.O(O) // Pulldown output (connect directly to top-level port)
|
|
);
|
|
|
|
// End of PULLDOWN_inst instantiation
|
|
</Template>
|
|
<Template label="KEEPER" treetype="template">
|
|
// KEEPER : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (KEEPER_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// KEEPER: I/O Buffer Weak Keeper
|
|
// All FPGA, CoolRunner-II
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
KEEPER KEEPER_inst (
|
|
.O(O) // Keeper output (connect directly to top-level port)
|
|
);
|
|
|
|
// End of KEEPER_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="SERDES and Delay Components" treetype="folder">
|
|
<Template label="Input Delay Control Element (IDELAYCTRL)" treetype="template">
|
|
// IDELAYCTRL : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IDELAYCTRL_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IDELAYCTRL: Input Delay Control Element (Must be used in conjunction with the IDELAY
|
|
// when used in FIXED or VARIABLE tap-delay mode)
|
|
// Virtex-5/6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
(* IODELAY_GROUP = "<iodelay_group_name>" *) // Specifies group name for associated IODELAYs and IDELAYCTRL
|
|
IDELAYCTRL IDELAYCTRL_inst (
|
|
.RDY(RDY), // 1-bit ready output
|
|
.REFCLK(REFCLK), // 1-bit reference clock input
|
|
.RST(RST) // 1-bit reset input
|
|
);
|
|
|
|
// End of IDELAYCTRL_inst instantiation
|
|
</Template>
|
|
<Template label="Input SERDES (ISERDES)" treetype="template">
|
|
// ISERDES : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ISERDES_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ISERDES: Source Synchronous Input Deserializer
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ISERDES #(
|
|
.BITSLIP_ENABLE("FALSE"), // "TRUE"/"FALSE" to enable bitslip controller
|
|
// Must be "FALSE" if INTERFACE_TYPE set to "MEMORY"
|
|
.DATA_RATE("DDR"), // Specify data rate of "DDR" or "SDR"
|
|
.DATA_WIDTH(4), // Specify data width - for DDR 4,6,8, or 10
|
|
// for SDR 2,3,4,5,6,7, or 8
|
|
.INTERFACE_TYPE("MEMORY"), // Use model - "MEMORY" or "NETWORKING"
|
|
.IOBDELAY("NONE"), // Specify outputs where delay chain will be applied
|
|
// "NONE", "IBUF", "IFD", or "BOTH"
|
|
.IOBDELAY_TYPE("DEFAULT"), // Set tap delay "DEFAULT", "FIXED", or "VARIABLE"
|
|
.IOBDELAY_VALUE(0), // Set initial tap delay to an integer from 0 to 63
|
|
.NUM_CE(2), // Define number or clock enables to an integer of 1 or 2
|
|
.SERDES_MODE("MASTER") // Set SERDES mode to "MASTER" or "SLAVE"
|
|
) ISERDES_inst (
|
|
.O(O), // 1-bit combinatorial output
|
|
.Q1(Q1), // 1-bit registered output
|
|
.Q2(Q2), // 1-bit registered output
|
|
.Q3(Q3), // 1-bit registered output
|
|
.Q4(Q4), // 1-bit registered output
|
|
.Q5(Q5), // 1-bit registered output
|
|
.Q6(Q6), // 1-bit registered output
|
|
.SHIFTOUT1(SHIFTOUT1), // 1-bit carry output
|
|
.SHIFTOUT2(SHIFTOUT2), // 1-bit carry output
|
|
.BITSLIP(BITSLIP), // 1-bit Bitslip input
|
|
.CE1(CE1), // 1-bit clock enable input
|
|
.CE2(CE2), // 1-bit clock enable input
|
|
.CLK(CLK), // 1-bit clock input
|
|
.CLKDIV(CLKDIV), // 1-bit divided clock input
|
|
.D(D), // 1-bit serial data input
|
|
.DLYCE(DLYCE), // 1-bit delay chain enable input
|
|
.DLYINC(DLYINC), // 1-bit delay increment/decrement input
|
|
.DLYRST(DLYRST), // 1-bit delay chain reset input
|
|
.OCLK(OCLK), // 1-bit high-speed clock input
|
|
.REV(1'b0), // Must be tied to logic zero
|
|
.SHIFTIN1(SHIFTIN1), // 1-bit carry input
|
|
.SHIFTIN2(SHIFTIN2), // 1-bit carry input
|
|
.SR(SR) // 1-bit set/reset input
|
|
);
|
|
|
|
// End of ISERDES_inst instantiation
|
|
</Template>
|
|
<Template label="Output SERDES (OSERDES)" treetype="template">
|
|
// OSERDES : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OSERDES_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OSERDES: Source Synchronous Output Serializer
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OSERDES #(
|
|
.DATA_RATE_OQ("DDR"), // Specify data rate to "DDR" or "SDR"
|
|
.DATA_RATE_TQ("DDR"), // Specify data rate to "DDR", "SDR", or "BUF"
|
|
.DATA_WIDTH(4), // Specify data width - for DDR: 4,6,8, or 10
|
|
// for SDR or BUF: 2,3,4,5,6,7, or 8
|
|
.INIT_OQ(1'b0), // INIT for OQ register - 1'b1 or 1'b0
|
|
.INIT_TQ(1'b0), // INIT for OQ register - 1'b1 or 1'b0
|
|
.SERDES_MODE("MASTER"), // Set SERDES mode to "MASTER" or "SLAVE"
|
|
.SRVAL_OQ(1'b0), // Define OQ output value upon SR assertion - 1'b1 or 1'b0
|
|
.SRVAL_TQ(1'b0), // Define TQ output value upon SR assertion - 1'b1 or 1'b0
|
|
.TRISTATE_WIDTH(4) // Specify parallel to serial converter width
|
|
// When DATA_RATE_TQ = DDR: 2 or 4
|
|
// When DATA_RATE_TQ = SDR or BUF: 1
|
|
) OSERDES_inst (
|
|
.OQ(OQ), // 1-bit data path output
|
|
.SHIFTOUT1(SHIFTOUT1), // 1-bit data expansion output
|
|
.SHIFTOUT2(SHIFTOUT2), // 1-bit data expansion output
|
|
.TQ(TQ), // 1-bit 3-state control output
|
|
.CLK(CLK), // 1-bit clock input
|
|
.CLKDIV(CLKDIV), // 1-bit divided clock input
|
|
.D1(D1), // 1-bit parallel data input
|
|
.D2(D2), // 1-bit parallel data input
|
|
.D3(D3), // 1-bit parallel data input
|
|
.D4(D4), // 1-bit parallel data input
|
|
.D5(D5), // 1-bit parallel data input
|
|
.D6(D6), // 1-bit parallel data input
|
|
.OCE(OCE), // 1-bit clock enable input
|
|
.REV(1'b0), // Must be tied to logic zero
|
|
.SHIFTIN1(SHIFTIN1), // 1-bit data expansion input
|
|
.SHIFTIN2(SHIFTIN2), // 1-bit data expansion input
|
|
.SR(SR), // 1-bit set/reset input
|
|
.T1(T1), // 1-bit parallel 3-state input
|
|
.T2(T2), // 1-bit parallel 3-state input
|
|
.T3(T3), // 1-bit parallel 3-state input
|
|
.T4(T4), // 1-bit parallel 3-state input
|
|
.TCE(TCE) // 1-bit 3-state signal clock enable input
|
|
);
|
|
|
|
// End of OSERDES_inst instantiation
|
|
</Template>
|
|
<Template label="Input/Output Delay Element (IODELAY)" treetype="template">
|
|
// IODELAY : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IODELAY_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IODELAY: Input and/or Output Fixed/variable Delay Element
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
(* IODELAY_GROUP = "<iodelay_group_name>" *) // Specifies group name for associated IODELAYs and IDELAYCTRL
|
|
IODELAY # (
|
|
.DELAY_SRC("I"), // Specify which input port to be used, "I"=IDATAIN,
|
|
// "O"=ODATAIN, "DATAIN"=DATAIN, "IO"=Bi-directional
|
|
.HIGH_PERFORMANCE_MODE("TRUE"), // "TRUE" specifies lower jitter
|
|
// at expense of more power
|
|
.IDELAY_TYPE("FIXED"), // "FIXED" or "VARIABLE"
|
|
.IDELAY_VALUE(0), // 0 to 63 tap values
|
|
.ODELAY_VALUE(0), // 0 to 63 tap values
|
|
.REFCLK_FREQUENCY(200.0), // Frequency used for IDELAYCTRL
|
|
// 175.0 to 225.0
|
|
.SIGNAL_PATTERN("DATA") // Input signal type, "CLOCK" or "DATA"
|
|
) IODELAY_INST (
|
|
.DATAOUT(DATAOUT), // 1-bit delayed data output
|
|
.C(C), // 1-bit clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.DATAIN(DATAIN), // 1-bit internal data input
|
|
.IDATAIN(IDATAIN), // 1-bit input data input (connect to port)
|
|
.INC(INC), // 1-bit increment/decrement input
|
|
.ODATAIN(ODATAIN), // 1-bit output data input
|
|
.RST(RST), // 1-bit active high, synch reset input
|
|
.T(T) // 1-bit 3-state control input
|
|
);
|
|
|
|
// End of IODELAY_inst instantiation
|
|
</Template>
|
|
<Template label="Input SERDES (ISERDES_NODELAY)" treetype="template">
|
|
// ISERDES_NODELAY : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ISERDES_NODELAY_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ISERDES_NODELAY: Input SERial / DESerilizer
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ISERDES_NODELAY #(
|
|
.BITSLIP_ENABLE("FALSE"), // "TRUE"/"FALSE" to enable bitslip controller
|
|
// Must be "FALSE" if INTERFACE_TYPE set to "MEMORY"
|
|
.DATA_RATE("DDR"), // Specify data rate of "DDR" or "SDR"
|
|
.DATA_WIDTH(4), // Specify data width -
|
|
// NETWORKING SDR: 2, 3, 4, 5, 6, 7, 8 : DDR 4, 6, 8, 10
|
|
// MEMORY SDR N/A : DDR 4
|
|
.INTERFACE_TYPE("MEMORY"), // Use model - "MEMORY" or "NETWORKING"
|
|
.NUM_CE(2), // Number of clock enables used, 1 or 2
|
|
.SERDES_MODE("MASTER") // Set SERDES mode to "MASTER" or "SLAVE"
|
|
) ISERDES_NODELAY_inst (
|
|
.Q1(Q1), // 1-bit registered SERDES output
|
|
.Q2(Q2), // 1-bit registered SERDES output
|
|
.Q3(Q3), // 1-bit registered SERDES output
|
|
.Q4(Q4), // 1-bit registered SERDES output
|
|
.Q5(Q5), // 1-bit registered SERDES output
|
|
.Q6(Q6), // 1-bit registered SERDES output
|
|
.SHIFTOUT1(SHIFTOUT1), // 1-bit cascade Master/Slave output
|
|
.SHIFTOUT2(SHIFTOUT2), // 1-bit cascade Master/Slave output
|
|
.BITSLIP(BITSLIP), // 1-bit Bitslip enable input
|
|
.CE1(CE1), // 1-bit clock enable input
|
|
.CE2(CE2), // 1-bit clock enable input
|
|
.CLK(CLK), // 1-bit master clock input
|
|
.CLKB(CLKB), // 1-bit secondary clock input for DATA_RATE=DDR
|
|
.CLKDIV(CLKDIV), // 1-bit divided clock input
|
|
.D(D), // 1-bit data input, connects to IODELAY or input buffer
|
|
.OCLK(OCLK), // 1-bit fast output clock input
|
|
.RST(RST), // 1-bit asynchronous reset input
|
|
.SHIFTIN1(SHIFTIN1), // 1-bit cascade Master/Slave input
|
|
.SHIFTIN2(SHIFTIN2) // 1-bit cascade Master/Slave input
|
|
);
|
|
|
|
// End of ISERDES_NODELAY_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="DDR Registers" treetype="folder">
|
|
<Template label="Input DDR Register (IDDR)" treetype="template">
|
|
// IDDR : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IDDR_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IDDR: Input Double Data Rate Input Register with Set, Reset
|
|
// and Clock Enable.
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IDDR #(
|
|
.DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE", "SAME_EDGE"
|
|
// or "SAME_EDGE_PIPELINED"
|
|
.INIT_Q1(1'b0), // Initial value of Q1: 1'b0 or 1'b1
|
|
.INIT_Q2(1'b0), // Initial value of Q2: 1'b0 or 1'b1
|
|
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
|
|
) IDDR_inst (
|
|
.Q1(Q1), // 1-bit output for positive edge of clock
|
|
.Q2(Q2), // 1-bit output for negative edge of clock
|
|
.C(C), // 1-bit clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.D(D), // 1-bit DDR data input
|
|
.R(R), // 1-bit reset
|
|
.S(S) // 1-bit set
|
|
);
|
|
|
|
// End of IDDR_inst instantiation
|
|
</Template>
|
|
<Template label="Output DDR Register (ODDR)" treetype="template">
|
|
// ODDR : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ODDR_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ODDR: Output Double Data Rate Output Register with Set, Reset
|
|
// and Clock Enable.
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ODDR #(
|
|
.DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE"
|
|
.INIT(1'b0), // Initial value of Q: 1'b0 or 1'b1
|
|
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
|
|
) ODDR_inst (
|
|
.Q(Q), // 1-bit DDR output
|
|
.C(C), // 1-bit clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.D1(D1), // 1-bit data input (positive edge)
|
|
.D2(D2), // 1-bit data input (negative edge)
|
|
.R(R), // 1-bit reset
|
|
.S(S) // 1-bit set
|
|
);
|
|
|
|
// End of ODDR_inst instantiation
|
|
</Template>
|
|
<Template label="Dual-Clock, Input DDR Register (IDDR_2CLK)" treetype="template">
|
|
// IDDR_2CLK : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IDDR_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IDDR_2CLK: Dual-Clock, Input Double Data Rate Input Register with
|
|
// Set, Reset and Clock Enable.
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IDDR_2CLK #(
|
|
.DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE", "SAME_EDGE"
|
|
// or "SAME_EDGE_PIPELINED"
|
|
.INIT_Q1(1'b0), // Initial value of Q1: 1'b0 or 1'b1
|
|
.INIT_Q2(1'b0), // Initial value of Q2: 1'b0 or 1'b1
|
|
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
|
|
) IDDR_2CLK_inst (
|
|
.Q1(Q1), // 1-bit output for positive edge of clock
|
|
.Q2(Q2), // 1-bit output for negative edge of clock
|
|
.C(C), // 1-bit primary clock input
|
|
.CB(CB), // 1-bit secondary clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.D(D), // 1-bit DDR data input
|
|
.R(R), // 1-bit reset
|
|
.S(S) // 1-bit set
|
|
);
|
|
|
|
// End of IDDR_2CLK_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Registers & Latches" treetype="folder">
|
|
<SubFolder label="Double Data Rate" treetype="folder">
|
|
<Template label="Input DDR Register (IDDR)" treetype="template">
|
|
// IDDR : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IDDR_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IDDR: Input Double Data Rate Input Register with Set, Reset
|
|
// and Clock Enable.
|
|
// Virtex-5/6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IDDR #(
|
|
.DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE", "SAME_EDGE"
|
|
// or "SAME_EDGE_PIPELINED"
|
|
.INIT_Q1(1'b0), // Initial value of Q1: 1'b0 or 1'b1
|
|
.INIT_Q2(1'b0), // Initial value of Q2: 1'b0 or 1'b1
|
|
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
|
|
) IDDR_inst (
|
|
.Q1(Q1), // 1-bit output for positive edge of clock
|
|
.Q2(Q2), // 1-bit output for negative edge of clock
|
|
.C(C), // 1-bit clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.D(D), // 1-bit DDR data input
|
|
.R(R), // 1-bit reset
|
|
.S(S) // 1-bit set
|
|
);
|
|
|
|
// End of IDDR_inst instantiation
|
|
</Template>
|
|
<Template label="Output DDR Register (ODDR)" treetype="template">
|
|
// ODDR : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ODDR_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ODDR: Output Double Data Rate Output Register with Set, Reset
|
|
// and Clock Enable.
|
|
// Virtex-5/6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ODDR #(
|
|
.DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE"
|
|
.INIT(1'b0), // Initial value of Q: 1'b0 or 1'b1
|
|
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
|
|
) ODDR_inst (
|
|
.Q(Q), // 1-bit DDR output
|
|
.C(C), // 1-bit clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.D1(D1), // 1-bit data input (positive edge)
|
|
.D2(D2), // 1-bit data input (negative edge)
|
|
.R(R), // 1-bit reset
|
|
.S(S) // 1-bit set
|
|
);
|
|
|
|
// End of ODDR_inst instantiation
|
|
</Template>
|
|
<Template label="Dual-Clock, Input DDR Register (IDDR_2CLK)" treetype="template">
|
|
// IDDR_2CLK : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IDDR_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IDDR_2CLK: Dual-Clock, Input Double Data Rate Input Register with
|
|
// Set, Reset and Clock Enable.
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IDDR_2CLK #(
|
|
.DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE", "SAME_EDGE"
|
|
// or "SAME_EDGE_PIPELINED"
|
|
.INIT_Q1(1'b0), // Initial value of Q1: 1'b0 or 1'b1
|
|
.INIT_Q2(1'b0), // Initial value of Q2: 1'b0 or 1'b1
|
|
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
|
|
) IDDR_2CLK_inst (
|
|
.Q1(Q1), // 1-bit output for positive edge of clock
|
|
.Q2(Q2), // 1-bit output for negative edge of clock
|
|
.C(C), // 1-bit primary clock input
|
|
.CB(CB), // 1-bit secondary clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.D(D), // 1-bit DDR data input
|
|
.R(R), // 1-bit reset
|
|
.S(S) // 1-bit set
|
|
);
|
|
|
|
// End of IDDR_2CLK_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Single Data Rate" treetype="folder">
|
|
<Template label="Posedge D-FF w/ Async Clear, Set and CE (FDCPE)" treetype="template">
|
|
// FDCPE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FDCPE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FDCPE: Single Data Rate D Flip-Flop with Asynchronous Clear, Set and
|
|
// Clock Enable (posedge clk).
|
|
// Virtex-5, Spartan-3/3E/3A/3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FDCPE #(
|
|
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
|
|
) FDCPE_inst (
|
|
.Q(Q), // Data output
|
|
.C(C), // Clock input
|
|
.CE(CE), // Clock enable input
|
|
.CLR(CLR), // Asynchronous clear input
|
|
.D(D), // Data input
|
|
.PRE(PRE) // Asynchronous set input
|
|
);
|
|
|
|
// End of FDCPE_inst instantiation
|
|
</Template>
|
|
<Template label="Posedge D-FF w/ Sync Clear, Set and CE (FDRSE)" treetype="template">
|
|
// FDRSE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FDCRS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FDRSE: Single Data Rate D Flip-Flop with Synchronous Clear, Set and
|
|
// Clock Enable (posedge clk).
|
|
// Virtex-5, Spartan-3/3E/3A/3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FDRSE #(
|
|
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
|
|
) FDRSE_inst (
|
|
.Q(Q), // Data output
|
|
.C(C), // Clock input
|
|
.CE(CE), // Clock enable input
|
|
.D(D), // Data input
|
|
.R(R), // Synchronous reset input
|
|
.S(S) // Synchronous set input
|
|
);
|
|
|
|
// End of FDRSE_inst instantiation
|
|
</Template>
|
|
<Template label="Posedge D-FF w/ Async Clear and CE (FDCE)" treetype="template">
|
|
// FDCE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FDCE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FDCE: Single Data Rate D Flip-Flop with Asynchronous Clear and
|
|
// Clock Enable (posedge clk).
|
|
// All families.
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FDCE #(
|
|
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
|
|
) FDCE_inst (
|
|
.Q(Q), // 1-bit Data output
|
|
.C(C), // 1-bit Clock input
|
|
.CE(CE), // 1-bit Clock enable input
|
|
.CLR(CLR), // 1-bit Asynchronous clear input
|
|
.D(D) // 1-bit Data input
|
|
);
|
|
|
|
// End of FDCE_inst instantiation
|
|
</Template>
|
|
<Template label="Posedge D-FF w/ Async Preset and CE (FDPE)" treetype="template">
|
|
// FDPE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FDPE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FDPE: Single Data Rate D Flip-Flop with Asynchronous Preset and
|
|
// Clock Enable (posedge clk).
|
|
// All families.
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FDPE #(
|
|
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
|
|
) FDPE_inst (
|
|
.Q(Q), // 1-bit Data output
|
|
.C(C), // 1-bit Clock input
|
|
.CE(CE), // 1-bit Clock enable input
|
|
.PRE(PRE), // 1-bit Asynchronous preset input
|
|
.D(D) // 1-bit Data input
|
|
);
|
|
|
|
// End of FDPE_inst instantiation
|
|
</Template>
|
|
<Template label="Posedge D-FF w/ Sync Reset and CE (FDRE)" treetype="template">
|
|
// FDRE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FDRE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FDRE: Single Data Rate D Flip-Flop with Synchronous Reset and
|
|
// Clock Enable (posedge clk).
|
|
// All families.
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FDRE #(
|
|
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
|
|
) FDRE_inst (
|
|
.Q(Q), // 1-bit Data output
|
|
.C(C), // 1-bit Clock input
|
|
.CE(CE), // 1-bit Clock enable input
|
|
.R(R), // 1-bit Synchronous reset input
|
|
.D(D) // 1-bit Data input
|
|
);
|
|
|
|
// End of FDRE_inst instantiation
|
|
</Template>
|
|
<Template label="Posedge D-FF w/ Sync Set and CE (FDSE)" treetype="template">
|
|
// FDSE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FDSE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FDSE: Single Data Rate D Flip-Flop with Synchronous Set and
|
|
// Clock Enable (posedge clk).
|
|
// All families.
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FDSE #(
|
|
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
|
|
) FDSE_inst (
|
|
.Q(Q), // 1-bit Data output
|
|
.C(C), // 1-bit Clock input
|
|
.CE(CE), // 1-bit Clock enable input
|
|
.S(S), // 1-bit Synchronous set input
|
|
.D(D) // 1-bit Data input
|
|
);
|
|
|
|
// End of FDSE_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Transparent Latch" treetype="folder">
|
|
<Template label="Latch with Async Reset, Set and Gate Enable (LDCPE)" treetype="template">
|
|
// LDCPE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LDCPE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LDCPE: Transparent latch with Asynchronous Reset, Preset and
|
|
// Gate Enable.
|
|
// Virtex-5, Spartan-3/3E/3A/3A DSP
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LDCPE #(
|
|
.INIT(1'b0) // Initial value of latch (1'b0 or 1'b1)
|
|
) LDCPE_inst (
|
|
.Q(Q), // Data output
|
|
.CLR(CLR), // Asynchronous clear/reset input
|
|
.D(D), // Data input
|
|
.G(G), // Gate input
|
|
.GE(GE), // Gate enable input
|
|
.PRE(PRE) // Asynchronous preset/set input
|
|
);
|
|
|
|
// End of LDCPE_inst instantiation
|
|
</Template>
|
|
<Template label="Latch with Async Reset and Gate Enable (LDCE)" treetype="template">
|
|
// LDCE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LDCE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LDCE: Transparent latch with Asynchronous Reset and Gate Enable.
|
|
// All FPGAs
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LDCE #(
|
|
.INIT(1'b0) // Initial value of latch (1'b0 or 1'b1)
|
|
) LDCE_inst (
|
|
.Q(Q), // Data output
|
|
.CLR(CLR), // Asynchronous clear/reset input
|
|
.D(D), // Data input
|
|
.G(G), // Gate input
|
|
.GE(GE) // Gate enable input
|
|
);
|
|
|
|
// End of LDCE_inst instantiation
|
|
</Template>
|
|
<Template label="Latch with Async Set and Gate Enable (LDPE)" treetype="template">
|
|
// LDPE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LDPE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LDPE: Transparent latch with Asynchronous Preset and Gate Enable.
|
|
// All FPGAs
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LDPE #(
|
|
.INIT(1'b0) // Initial value of latch (1'b0 or 1'b1)
|
|
) LDPE_inst (
|
|
.Q(Q), // Data output
|
|
.PRE(PRE), // Asynchronous preset/set input
|
|
.D(D), // Data input
|
|
.G(G), // Gate input
|
|
.GE(GE) // Gate enable input
|
|
);
|
|
|
|
// End of LDPE_inst instantiation
|
|
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Arithmetic Functions" treetype="folder">
|
|
<Template label="DSP Block (DSP48E)" treetype="template">
|
|
// DSP48E : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (DSP48E_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// DSP48E: DSP Function Block
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
DSP48E #(
|
|
.SIM_MODE("SAFE"), // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details
|
|
.ACASCREG(1), // Number of pipeline registers between A/ACIN input and ACOUT output, 0, 1, or 2
|
|
.ALUMODEREG(1), // Number of pipeline registers on ALUMODE input, 0 or 1
|
|
.AREG(1), // Number of pipeline registers on the A input, 0, 1 or 2
|
|
.AUTORESET_PATTERN_DETECT("FALSE"), // Auto-reset upon pattern detect, "TRUE" or "FALSE"
|
|
.AUTORESET_PATTERN_DETECT_OPTINV("MATCH"), // Reset if "MATCH" or "NOMATCH"
|
|
.A_INPUT("DIRECT"), // Selects A input used, "DIRECT" (A port) or "CASCADE" (ACIN port)
|
|
.BCASCREG(1), // Number of pipeline registers between B/BCIN input and BCOUT output, 0, 1, or 2
|
|
.BREG(1), // Number of pipeline registers on the B input, 0, 1 or 2
|
|
.B_INPUT("DIRECT"), // Selects B input used, "DIRECT" (B port) or "CASCADE" (BCIN port)
|
|
.CARRYINREG(1), // Number of pipeline registers for the CARRYIN input, 0 or 1
|
|
.CARRYINSELREG(1), // Number of pipeline registers for the CARRYINSEL input, 0 or 1
|
|
.CREG(1), // Number of pipeline registers on the C input, 0 or 1
|
|
.MASK(48'h3fffffffffff), // 48-bit Mask value for pattern detect
|
|
.MREG(1), // Number of multiplier pipeline registers, 0 or 1
|
|
.MULTCARRYINREG(1), // Number of pipeline registers for multiplier carry in bit, 0 or 1
|
|
.OPMODEREG(1), // Number of pipeline registers on OPMODE input, 0 or 1
|
|
.PATTERN(48'h000000000000), // 48-bit Pattern match for pattern detect
|
|
.PREG(1), // Number of pipeline registers on the P output, 0 or 1
|
|
.SEL_MASK("MASK"), // Select mask value between the "MASK" value or the value on the "C" port
|
|
.SEL_PATTERN("PATTERN"), // Select pattern value between the "PATTERN" value or the value on the "C" port
|
|
.SEL_ROUNDING_MASK("SEL_MASK"), // "SEL_MASK", "MODE1", "MODE2"
|
|
.USE_MULT("MULT_S"), // Select multiplier usage, "MULT" (MREG => 0), "MULT_S" (MREG => 1), "NONE" (no multiplier)
|
|
.USE_PATTERN_DETECT("NO_PATDET"), // Enable pattern detect, "PATDET", "NO_PATDET"
|
|
.USE_SIMD("ONE48") // SIMD selection, "ONE48", "TWO24", "FOUR12"
|
|
) DSP48E_inst (
|
|
.ACOUT(ACOUT), // 30-bit A port cascade output
|
|
.BCOUT(BCOUT), // 18-bit B port cascade output
|
|
.CARRYCASCOUT(CARRYCASCOUT), // 1-bit cascade carry output
|
|
.CARRYOUT(CARRYOUT), // 4-bit carry output
|
|
.MULTSIGNOUT(MULTSIGNOUT), // 1-bit multiplier sign cascade output
|
|
.OVERFLOW(OVERFLOW), // 1-bit overflow in add/acc output
|
|
.P(P), // 48-bit output
|
|
.PATTERNBDETECT(PATTERNBDETECT), // 1-bit active high pattern bar detect output
|
|
.PATTERNDETECT(PATTERNDETECT), // 1-bit active high pattern detect output
|
|
.PCOUT(PCOUT), // 48-bit cascade output
|
|
.UNDERFLOW(UNDERFLOW), // 1-bit active high underflow in add/acc output
|
|
.A(A), // 30-bit A data input
|
|
.ACIN(ACIN), // 30-bit A cascade data input
|
|
.ALUMODE(ALUMODE), // 4-bit ALU control input
|
|
.B(B), // 18-bit B data input
|
|
.BCIN(BCIN), // 18-bit B cascade input
|
|
.C(C), // 48-bit C data input
|
|
.CARRYCASCIN(CARRYCASCIN), // 1-bit cascade carry input
|
|
.CARRYIN(CARRYIN), // 1-bit carry input signal
|
|
.CARRYINSEL(CARRYINSEL), // 3-bit carry select input
|
|
.CEA1(CEA1), // 1-bit active high clock enable input for 1st stage A registers
|
|
.CEA2(CEA2), // 1-bit active high clock enable input for 2nd stage A registers
|
|
.CEALUMODE(CEALUMODE), // 1-bit active high clock enable input for ALUMODE registers
|
|
.CEB1(CEB1), // 1-bit active high clock enable input for 1st stage B registers
|
|
.CEB2(CEB2), // 1-bit active high clock enable input for 2nd stage B registers
|
|
.CEC(CEC), // 1-bit active high clock enable input for C registers
|
|
.CECARRYIN(CECARRYIN), // 1-bit active high clock enable input for CARRYIN register
|
|
.CECTRL(CECTRL), // 1-bit active high clock enable input for OPMODE and carry registers
|
|
.CEM(CEM), // 1-bit active high clock enable input for multiplier registers
|
|
.CEMULTCARRYIN(CEMULTCARRYIN), // 1-bit active high clock enable for multiplier carry in register
|
|
.CEP(CEP), // 1-bit active high clock enable input for P registers
|
|
.CLK(CLK), // Clock input
|
|
.MULTSIGNIN(MULTSIGNIN), // 1-bit multiplier sign input
|
|
.OPMODE(OPMODE), // 7-bit operation mode input
|
|
.PCIN(PCIN), // 48-bit P cascade input
|
|
.RSTA(RSTA), // 1-bit reset input for A pipeline registers
|
|
.RSTALLCARRYIN(RSTALLCARRYIN), // 1-bit reset input for carry pipeline registers
|
|
.RSTALUMODE(RSTALUMODE), // 1-bit reset input for ALUMODE pipeline registers
|
|
.RSTB(RSTB), // 1-bit reset input for B pipeline registers
|
|
.RSTC(RSTC), // 1-bit reset input for C pipeline registers
|
|
.RSTCTRL(RSTCTRL), // 1-bit reset input for OPMODE pipeline registers
|
|
.RSTM(RSTM), // 1-bit reset input for multiplier registers
|
|
.RSTP(RSTP) // 1-bit reset input for P pipeline registers
|
|
);
|
|
|
|
// End of DSP48E_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Config/BSCAN Components" treetype="folder">
|
|
<Template label="Boundary Scan (BSCAN_VIRTEX5)" treetype="template">
|
|
// BSCAN_VIRTEX5 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BSCAN_VIRTEX5_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BSCAN_VIRTEX5: Boundary Scan primitive for connecting internal
|
|
// logic to JTAG interface.
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BSCAN_VIRTEX5 #(
|
|
.JTAG_CHAIN(1) // Value for USER command. Possible values: (1,2,3 or 4)
|
|
) BSCAN_VIRTEX5_inst (
|
|
.CAPTURE(CAPTURE), // CAPTURE output from TAP controller
|
|
.DRCK(DRCK), // Data register output for USER function
|
|
.RESET(RESET), // Reset output from TAP controller
|
|
.SEL(SEL), // USER active output
|
|
.SHIFT(SHIFT), // SHIFT output from TAP controller
|
|
.TDI(TDI), // TDI output from TAP controller
|
|
.UPDATE(UPDATE), // UPDATE output from TAP controller
|
|
.TDO(TDO) // Data input for USER function
|
|
);
|
|
|
|
// End of BSCAN_VIRTEX5_inst instantiation
|
|
</Template>
|
|
<Template label="Register Capture (CAPTURE_VIRTEX5)" treetype="template">
|
|
// CAPTURE_VIRTEX5 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (CAPTURE_VIRTEX5_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// CAPTURE_VIRTEX5: Register State Capture for Bitstream Readback
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
CAPTURE_VIRTEX5 #(
|
|
.ONESHOT("TRUE") // "TRUE" or "FALSE"
|
|
) CAPTURE_VIRTEX5_inst (
|
|
.CAP(CAP), // Capture input
|
|
.CLK(CLK) // Clock input
|
|
);
|
|
|
|
// End of CAPTURE_VIRTEX5_inst instantiation
|
|
</Template>
|
|
<Template label="Config Frame Error Correction (FRAME_ECC_VIRTEX5)" treetype="template">
|
|
// FRAME_ECC_VIRTEX5 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FRAME_ECC_VIRTEX5_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FRAME_ECC_VIRTEX5: Configuration Frame Error Correction Circuitry
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FRAME_ECC_VIRTEX5 FRAME_ECC_VIRTEX5_inst (
|
|
.CRCERROR(CRCERROR), // 1-bit output indicating a CRC error
|
|
.ECCERROR(ECCERROR), // 1-bit output indicating an ECC error
|
|
.SYNDROME(SYNDROME), // 12-bit output location of erroneous bit
|
|
.SYNDROMEVALID(SYNDROMEVALID) // 1-bit output indicating the
|
|
// SYNDROME output is valid
|
|
);
|
|
|
|
// End of FRAME_ECC_VIRTEX5_inst instantiation
|
|
</Template>
|
|
<Template label="Internal Config Access Port (ICAP_VIRTEX5)" treetype="template">
|
|
// ICAP_VIRTEX5 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ICAP_VIRTEX5_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ICAP_VIRTEX5: Internal Configuration Access Port
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ICAP_VIRTEX5 #(
|
|
.ICAP_WIDTH("X8") // "X8", "X16" or "X32"
|
|
) ICAP_VIRTEX5_inst (
|
|
.BUSY(BUSY), // Busy output
|
|
.O(O), // 32-bit data output
|
|
.CE(CE), // Clock enable input
|
|
.CLK(CLK), // Clock input
|
|
.I(I), // 32-bit data input
|
|
.WRITE(WRITE) // Write input
|
|
);
|
|
|
|
// End of ICAP_VIRTEX5_inst instantiation
|
|
</Template>
|
|
<Template label="JTAG Simulation Model (JTAG_SIM_VIRTEX5)" treetype="template">
|
|
// JTAG_SIM_VIRTEX5 : In order to use this simulation model, the
|
|
// Verilog : forllowing instance declaration needs to be placed
|
|
// instance : in the testbench code to simulate the design. This
|
|
// declaration : should not be instnatiated into synthesizable design code.
|
|
// code : None of the ports need to be connected to the design
|
|
// : as communication is handled through the glbl.v module.
|
|
// : All ports can be connected to reg/wires in the testbench.
|
|
// : Only one JTAG_SIM_VIRTEX5 should be instantiated per design.
|
|
// : All inputs and outputs should be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// JTAG_SIM_VIRTEX5: JTAG Interface Simulation Model
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
JTAG_SIM_VIRTEX5 #(
|
|
.PART_NAME("LX30") // Specify target V5 device. Possible values are:
|
|
// "LX30", "LX50", "LX85", "LX110", "LX220", "LX330"
|
|
) JTAG_SIM_VIRTEX5_inst (
|
|
.TDO(TDO), // JTAG data output (1-bit)
|
|
.TCK(TCK), // Clock input (1-bit)
|
|
.TDI(TDI), // JTAG data input (1-bit)
|
|
.TMS(TMS) // JTAG command input (1-bit)
|
|
);
|
|
|
|
// End of JTAG_SIM_VIRTEX5_inst instantiation
|
|
</Template>
|
|
<Template label="Startup Block (STARTUP_VIRTEX5)" treetype="template">
|
|
// STARTUP_VIRTEX5 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (STARTUP_VIRTEX5_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// STARTUP_VIRTEX5: Startup primitive for accessing GSR, GTS, startup sequence
|
|
// control, SPI PROM pins, configuration clock and start-up status
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
STARTUP_VIRTEX5 STARTUP_VIRTEX5_inst (
|
|
.CFGCLK(CFGCLK), // Config logic clock 1-bit output
|
|
.CFGMCLK(CFGMCLK), // Config internal osc clock 1-bit output
|
|
.DINSPI(DINSPI), // DIN SPI PROM access 1-bit output
|
|
.EOS(EOS), // End Of Startup 1-bit output
|
|
.TCKSPI(TCKSPI), // TCK SPI PROM access 1-bit output
|
|
.CLK(CLK), // Clock input for start-up sequence
|
|
.GSR(GSR_PORT), // Global Set/Reset input (GSR cannot be used as a port name)
|
|
.GTS(GTS_PORT), // Global 3-state input (GTS cannot be used as a port name)
|
|
.USRCCLKO(USRCCLKO), // User CCLK 1-bit input
|
|
.USRCCLKTS(USRCCLKTS), // User CCLK 3-state 1-bit input
|
|
.USRDONEO(USRDONEO), // User Done 1-bit input
|
|
.USRDONETS(USRDONETS) // User Done 3-state 1-bit input
|
|
);
|
|
|
|
// End of STARTUP_VIRTEX5_inst instantiation
|
|
</Template>
|
|
<Template label="Config Data Access (USR_ACCESS_VIRTEX5)" treetype="template">
|
|
// USR_ACCESS_VIRTEX5 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (USR_ACCESS_VIRTEX5_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// USR_ACCESS_VIRTEX5: Configuration Data Memory Access Port
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
USR_ACCESS_VIRTEX5 USR_ACCESS_VIRTEX5_inst (
|
|
.CFGCLK(CFGCLK), // 1-bit configuration clock output
|
|
.DATA(DATA), // 32-bit config data output
|
|
.DATAVALID(DATAVALID) // 1-bit data valid output
|
|
);
|
|
|
|
// End of USR_ACCESS_VIRTEX5_inst instantiation
|
|
</Template>
|
|
<Template label="Clear Encryption Key Value (KEY_CLEAR)" treetype="template">
|
|
// KEY_CLEAR : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (KEY_CLEAR_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// KEY_CLEAR: Startup primitive for GSR, GTS or startup sequence control
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
KEY_CLEAR KEY_CLEAR_inst (
|
|
.KEYCLEARB(KEYCLEARB) // Active low key reset 1-bit input
|
|
);
|
|
|
|
// End of KEY_CLEAR_inst instantiation
|
|
</Template>
|
|
<Template label="Configuration Simulation Model (SIM_CONFIG_V5)" treetype="template">
|
|
// SIM_CONFIG_V5 : In order to incorporate this function into the testbench (not the design),
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SIM_CONFIG_V5_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SIM_CONFIG_V5: Behavioral Simulation-only Model of FPGA SelectMap Configuration
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SIM_CONFIG_V5 #(
|
|
.DEVICE_ID(32'h00000000)
|
|
) SIM_CONFIG_V5_inst (
|
|
.BUSY(BUSY), // 1-bit output Busy pin
|
|
.CSOB(CSOB), // 1-bit output chip select pin
|
|
.DONE(DONE), // 1-bit bi-directional Done pin
|
|
.CCLK(CCLK), // 1-bit input configuration clock
|
|
.CSB(CSB), // 1-bit input chip select
|
|
.D(D), // 32-bit bi-directional configuration data
|
|
.DCMLOCK(DCMLOCK), // 1-bit input DCM Lock
|
|
.INITB(INITB), // 1-bit bi-directional INIT status pin
|
|
.M(M), // 3-bit input Mode pins
|
|
.PROGB(PROGB), // 1-bit input Program pin
|
|
.RDWRB(RDWRB) // 1-bit input Read/write pin
|
|
);
|
|
|
|
// End of SIM_CONFIG_V5_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="System Monitor" treetype="folder">
|
|
<Template label="System Monitor (SYSMON)" treetype="template">
|
|
// SYSMON : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SYSMON_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SYSMON: System Monitor
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SYSMON #(
|
|
.INIT_40(16'h0), // Configuration register 0
|
|
.INIT_41(16'h0), // Configuration register 1
|
|
.INIT_42(16'h0), // Configuration register 2
|
|
.INIT_43(16'h0), // Test register 0
|
|
.INIT_44(16'h0), // Test register 1
|
|
.INIT_45(16'h0), // Test register 2
|
|
.INIT_46(16'h0), // Test register 3
|
|
.INIT_47(16'h0), // Test register 4
|
|
.INIT_48(16'h0), // Sequence register 0
|
|
.INIT_49(16'h0), // Sequence register 1
|
|
.INIT_4A(16'h0), // Sequence register 2
|
|
.INIT_4B(16'h0), // Sequence register 3
|
|
.INIT_4C(16'h0), // Sequence register 4
|
|
.INIT_4D(16'h0), // Sequence register 5
|
|
.INIT_4E(16'h0), // Sequence register 6
|
|
.INIT_4F(16'h0), // Sequence register 7
|
|
.INIT_50(16'h0), // Alarm limit register 0
|
|
.INIT_51(16'h0), // Alarm limit register 1
|
|
.INIT_52(16'h0), // Alarm limit register 2
|
|
.INIT_53(16'h0), // Alarm limit register 3
|
|
.INIT_54(16'h0), // Alarm limit register 4
|
|
.INIT_55(16'h0), // Alarm limit register 5
|
|
.INIT_56(16'h0), // Alarm limit register 6
|
|
.INIT_57(16'h0), // Alarm limit register 7
|
|
.SIM_MONITOR_FILE("design.txt") // Simulation analog entry file
|
|
) SYSMON_inst (
|
|
.ALM(ALM), // 3-bit output for temp, Vccint and Vccaux
|
|
.BUSY(BUSY), // 1-bit output ADC busy signal
|
|
.CHANNEL(CHANNEL), // 5-bit output channel selection
|
|
.DO(DO), // 16-bit output data bus for dynamic reconfig
|
|
.DRDY(DRDY), // 1-bit output data ready for dynamic reconfig
|
|
.EOC(EOC), // 1-bit output end of conversion
|
|
.EOS(EOS), // 1-bit output end of sequence
|
|
.JTAGBUSY(JTAGBUSY), // 1-bit output JTAG DRP busy
|
|
.JTAGLOCKED(JTAGLOCKED), // 1-bit output DRP port lock
|
|
.JTAGMODIFIED(JTAGMODIFIED), // 1-bit output JTAG write to DRP
|
|
.OT(OT), // 1-bit output over temperature alarm
|
|
.CONVST(CONVST), // 1-bit input convert start
|
|
.CONVSTCLK(CONVSTCLK), // 1-bit input convert start clock
|
|
.DADDR(DADDR), // 7-bit input address bus for dynamic reconfig
|
|
.DCLK(DCLK), // 1-bit input clock for dynamic reconfig
|
|
.DEN(DEN), // 1-bit input enable for dynamic reconfig
|
|
.DI(DI), // 16-bit input data bus for dynamic reconfig
|
|
.DWE(DWE), // 1-bit input write enable for dynamic reconfig
|
|
.RESET(RESET), // 1-bit input active high reset
|
|
.VAUXN(VAUXN), // 16-bit input N-side auxiliary analog input
|
|
.VAUXP(VAUXP), // 16-bit input P-side auxiliary analog input
|
|
.VN(VN), // 1-bit input N-side analog input
|
|
.VP(VP) // 1-bit input P-side analog input
|
|
);
|
|
|
|
// End of SYSMON_inst instantiation
|
|
</Template>
|
|
<Template label="System Monitor Simulation File" treetype="template">
|
|
// Must use valid headers on all columns
|
|
// Comments can be added to the stimulus file using '//'
|
|
|
|
TIME TEMP VCCAUX VCCINT VP VN VAUXP[0] VAUXN[0]
|
|
00000 45 2.5 1.0 0.5 0.0 0.7 0.0
|
|
05000 85 2.45 1.1 0.3 0.0 0.2 0.0
|
|
|
|
// Time stamp data is in nano seconds (ns)
|
|
// Temperature is recorded in C (degrees centigrade)
|
|
// All other channels are recorded as V (Volts)
|
|
// Valid column headers are:
|
|
// TIME, TEMP, VCCAUX, VCCINT, VP, VN,
|
|
// VAUXP[0], VAUXN[0],...............VAUXP[15], VAUXN[15]
|
|
// External analog inputs are differential so VP = 0.5 and VN = 0.0 the
|
|
// input on channel VP/VN in 0.5 - 0.0 = 0.5V
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Virtex-6" treetype="folder">
|
|
<SubFolder label="Config/BSCAN Components" treetype="folder">
|
|
<Template label="Boundary Scan (BSCAN_VIRTEX6)" treetype="template">
|
|
// BSCAN_VIRTEX6 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BSCAN_VIRTEX6_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BSCAN_VIRTEX6: Boundary Scan
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BSCAN_VIRTEX6 #(
|
|
.DISABLE_JTAG("FALSE"), // This attribute is unsupported. Please leave it at default.
|
|
.JTAG_CHAIN(1) // Value for USER command. Possible values: (1,2,3 or 4).
|
|
)
|
|
BSCAN_VIRTEX6_inst (
|
|
.CAPTURE(CAPTURE), // 1-bit output: CAPTURE output from TAP controller
|
|
.DRCK(DRCK), // 1-bit output: Data register output for USER functions
|
|
.RESET(RESET), // 1-bit output: Reset output for TAP controller
|
|
.RUNTEST(RUNTEST), // 1-bit output: State output asserted when TAP controller is in Run Test Idle state.
|
|
.SEL(SEL), // 1-bit output: USER active output
|
|
.SHIFT(SHIFT), // 1-bit output: SHIFT output from TAP controller
|
|
.TCK(TCK), // 1-bit output: Scan Clock output. Fabric connection to TAP Clock pin.
|
|
.TDI(TDI), // 1-bit output: TDI output from TAP controller
|
|
.TMS(TMS), // 1-bit output: Test Mode Select input. Fabric connection to TAP.
|
|
.UPDATE(UPDATE), // 1-bit output: UPDATE output from TAP controller
|
|
.TDO(TDO) // 1-bit input: Data input for USER function
|
|
);
|
|
|
|
// End of BSCAN_VIRTEX6_inst instantiation
|
|
</Template>
|
|
<Template label="Register Capture (CAPTURE_VIRTEX6)" treetype="template">
|
|
// CAPTURE_VIRTEX6 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (CAPTURE_VIRTEX6_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// CAPTURE_VIRTEX6: Register Capture
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
CAPTURE_VIRTEX6 #(
|
|
.ONESHOT("TRUE") // Specifies the procedure for performing single readback per CAP trigger.
|
|
)
|
|
CAPTURE_VIRTEX6_inst (
|
|
.CAP(CAP), // 1-bit input: Capture Input
|
|
.CLK(CLK) // 1-bit input: Clock Input
|
|
);
|
|
|
|
// End of CAPTURE_VIRTEX6_inst instantiation
|
|
</Template>
|
|
<Template label="Device DNA Access Port (DNA_PORT)" treetype="template">
|
|
// DNA_PORT : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (DNA_PORT_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// DNA_PORT: Device DNA Access Port
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
DNA_PORT #(
|
|
.SIM_DNA_VALUE(57'h000000000000000) // Specifies the Pre-programmed factory ID value
|
|
)
|
|
DNA_PORT_inst (
|
|
.DOUT(DOUT), // 1-bit output: DNA output data
|
|
.CLK(CLK), // 1-bit input: Clock input
|
|
.DIN(DIN), // 1-bit input: User data input pin
|
|
.READ(READ), // 1-bit input: Active high load DNA, active low read input
|
|
.SHIFT(SHIFT) // 1-bit input: Active high shift enable input
|
|
);
|
|
|
|
// End of DNA_PORT_inst instantiation
|
|
</Template>
|
|
<Template label="32-bit non-volatile design ID (EFUSE_USR)" treetype="template">
|
|
// EFUSE_USR : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (EFUSE_USR_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// EFUSE_USR: 32-bit non-volatile design ID
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
EFUSE_USR #(
|
|
.SIM_EFUSE_VALUE(32'h00000000) // Value of the 32-bit non-volatile design ID used in simulation
|
|
)
|
|
EFUSE_USR_inst (
|
|
.EFUSEUSR(EFUSEUSR) // 32-bit output: User E-Fuse register value output
|
|
);
|
|
|
|
// End of EFUSE_USR_inst instantiation
|
|
</Template>
|
|
<Template label="Configuration Frame Error Correction (FRAME_ECC_VIRTEX6)" treetype="template">
|
|
// FRAME_ECC_VIRTEX6 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FRAME_ECC_VIRTEX6_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FRAME_ECC_VIRTEX6: Configuration Frame Error Correction
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FRAME_ECC_VIRTEX6 #(
|
|
.FARSRC("EFAR"), // Determines if the output of FAR[23:0] configuration register points to
|
|
// the FAR or EFAR. Sets configuration option register bit CTL0[7].
|
|
.FRAME_RBT_IN_FILENAME("NONE") // This file is output by the ICAP_VIRTEX6 model and it contains Frame
|
|
// Data information for the Raw Bitstream (RBT) file. The FRAME_ECC model
|
|
// will parse this file, calculate ECC and output any error conditions.
|
|
)
|
|
FRAME_ECC_VIRTEX6_inst (
|
|
.CRCERROR(CRCERROR), // 1-bit output: Output indicating a CRC error
|
|
.ECCERROR(ECCERROR), // 1-bit output: Output indicating an ECC error
|
|
.ECCERRORSINGLE(ECCERRORSINGLE), // 1-bit output: Output Indicating single-bit Frame ECC error detected.
|
|
.FAR(FAR), // 24-bit output: Frame Address Register Value output
|
|
.SYNBIT(SYNBIT), // 5-bit output: Output bit address of error
|
|
.SYNDROME(SYNDROME), // 13-bit output: Output location of erroneous bit
|
|
.SYNDROMEVALID(SYNDROMEVALID), // 1-bit output: Frame ECC output indicating the SYNDROME output is
|
|
// valid.
|
|
|
|
.SYNWORD(SYNWORD) // 7-bit output: Word output in the frame where an ECC error has been
|
|
// detected
|
|
|
|
);
|
|
|
|
// End of FRAME_ECC_VIRTEX6_inst instantiation
|
|
</Template>
|
|
<Template label="Internal Configuration Access Port (ICAP_VIRTEX6)" treetype="template">
|
|
// ICAP_VIRTEX6 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ICAP_VIRTEX6_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ICAP_VIRTEX6: Internal Configuration Access Port
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ICAP_VIRTEX6 #(
|
|
.DEVICE_ID(0'h4244093), // Specifies the pre-programmed Device ID value
|
|
.ICAP_WIDTH("X8"), // Specifies the input and output data width to be used with the
|
|
// ICAP_VIRTEX6.
|
|
.SIM_CFG_FILE_NAME("NONE") // Specifies the Raw Bitstream (RBT) file to be parsed by the simulation
|
|
// model
|
|
)
|
|
ICAP_VIRTEX6_inst (
|
|
.BUSY(BUSY), // 1-bit output: Busy/Ready output
|
|
.O(O), // 32-bit output: Configuration data output bus
|
|
.CLK(CLK), // 1-bit input: Clock Input
|
|
.CSB(CSB), // 1-bit input: Active-Low ICAP input Enable
|
|
.I(I), // 32-bit input: Configuration data input bus
|
|
.RDWRB(RDWRB) // 1-bit input: Read/Write Select input
|
|
);
|
|
|
|
// End of ICAP_VIRTEX6_inst instantiation
|
|
</Template>
|
|
<Template label="STARTUP Block (STARTUP_VIRTEX6)" treetype="template">
|
|
// STARTUP_VIRTEX6 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (STARTUP_VIRTEX6_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// STARTUP_VIRTEX6: STARTUP Block
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
STARTUP_VIRTEX6 #(
|
|
.PROG_USR("FALSE") // Activate program event security feature. Requires encrypted bitstreams.
|
|
)
|
|
STARTUP_VIRTEX6_inst (
|
|
.CFGCLK(CFGCLK), // 1-bit output: Configuration main clock output
|
|
.CFGMCLK(CFGMCLK), // 1-bit output: Configuration internal oscillator clock output
|
|
.DINSPI(DINSPI), // 1-bit output: DIN SPI PROM access output
|
|
.EOS(EOS), // 1-bit output: Active high output signal indicating the End Of Configuration.
|
|
.PREQ(PREQ), // 1-bit output: PROGRAM request to fabric output
|
|
.TCKSPI(TCKSPI), // 1-bit output: TCK configuration pin access output
|
|
.CLK(CLK), // 1-bit input: User start-up clock input
|
|
.GSR(GSR), // 1-bit input: Global Set/Reset input (GSR cannot be used for the port name)
|
|
.GTS(GTS), // 1-bit input: Global 3-state input (GTS cannot be used for the port name)
|
|
.KEYCLEARB(KEYCLEARB), // 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM)
|
|
.PACK(PACK), // 1-bit input: PROGRAM acknowledge input
|
|
.USRCCLKO(USRCCLKO), // 1-bit input: User CCLK input
|
|
.USRCCLKTS(USRCCLKTS), // 1-bit input: User CCLK 3-state enable input
|
|
.USRDONEO(USRDONEO), // 1-bit input: User DONE pin output control
|
|
.USRDONETS(USRDONETS) // 1-bit input: User DONE 3-state enable output
|
|
);
|
|
|
|
// End of STARTUP_VIRTEX6_inst instantiation
|
|
</Template>
|
|
<Template label="Configuration Data Access (USR_ACCESS_VIRTEX6)" treetype="template">
|
|
// USR_ACCESS_VIRTEX6 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (USR_ACCESS_VIRTEX6_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// USR_ACCESS_VIRTEX6: Configuration Data Access
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
USR_ACCESS_VIRTEX6 USR_ACCESS_VIRTEX6_inst (
|
|
.CFGCLK(CFGCLK), // 1-bit output: Configuration Clock output
|
|
.DATA(DATA), // 32-bit output: Configuration Data output
|
|
.DATAVALID(DATAVALID) // 1-bit output: Active high data valid output
|
|
);
|
|
|
|
// End of USR_ACCESS_VIRTEX6_inst instantiation
|
|
</Template>
|
|
<Template label="SelectMap Configuration Simulation Model (SIM_CONFIG_V6)" treetype="template">
|
|
// SIM_CONFIG_V6 : In order to incorporate this function into the testbench (not the design),
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SIM_CONFIG_V6_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SIM_CONFIG_V6: Behavioral Simulation-only Model of FPGA SelectMap Configuration
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SIM_CONFIG_V6 #(
|
|
.DEVICE_ID(32'h00000000), // Specify DEVICE_ID
|
|
.ICAP_SUPPORT("FALSE"), // Using ICAP, "TRUE" or "FALSE"
|
|
.ICAP_WIDTH("X8") // ICAP width, "X8", "X16", "X32"
|
|
// Do not need to change/specify if ICAP_SUPPORT="FALSE"
|
|
) SIM_CONFIG_V6_inst (
|
|
.BUSY(BUSY), // 1-bit output Busy pin
|
|
.CSOB(CSOB), // 1-bit output chip select pin
|
|
.DONE(DONE), // 1-bit bi-directional Done pin
|
|
.CCLK(CCLK), // 1-bit input configuration clock
|
|
.CSB(CSB), // 1-bit input chip select
|
|
.D(D), // 32-bit bi-directional configuration data
|
|
.INITB(INITB), // 1-bit bi-directional INIT status pin
|
|
.M(M), // 3-bit input Mode pins
|
|
.PROGB(PROGB), // 1-bit input Program pin
|
|
.RDWRB(RDWRB) // 1-bit input Read/write pin
|
|
);
|
|
|
|
// End of SIM_CONFIG_V6_inst instantiation
|
|
</Template>
|
|
<Template label="Serial Configuration Simulation Model (SIM_CONFIG_V6_SERIAL)" treetype="template">
|
|
// SIM_CONFIG_V6_SERIAL : In order to incorporate this function into the testbench (not the design),
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SIM_CONFIG_V6_SERIAL_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SIM_CONFIG_V6_SERIAL: Behavioral Simulation-only Model of FPGA Serial Configuration
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SIM_CONFIG_V6_SERIAL #(
|
|
.DEVICE_ID(32'h00000000) // Specify DEVICE_ID
|
|
) SIM_CONFIG_V6_SERIAL_inst (
|
|
.DONE(DONE), // 1-bit bi-directional Done pin
|
|
.DOUT(DOUT), // 1-bit data output pin
|
|
.CCLK(CCLK), // 1-bit input configuration clock
|
|
.DIN(DIN), // 1-bit input configuration data
|
|
.INITB(INITB), // 1-bit bi-directional INIT status pin
|
|
.M(M), // 3-bit input Mode pins
|
|
.PROGB(PROGB) // 1-bit input Program pin
|
|
);
|
|
|
|
// End of SIM_CONFIG_V6_SERIAL_inst instantiation
|
|
</Template>
|
|
<Template label="JTAG Simulation Model (JTAG_SIM_VIRTEX6)" treetype="template">
|
|
// JTAG_SIM_VIRTEX6 : In order to use this simulation model, the
|
|
// Verilog : forllowing instance declaration needs to be placed
|
|
// instance : in the testbench code to simulate the design. This
|
|
// declaration : should not be instnatiated into synthesizable design code.
|
|
// code : None of the ports need to be connected to the design
|
|
// : as communication is handled through the glbl.v module.
|
|
// : All ports can be connected to reg/wires in the testbench.
|
|
// : Only one JTAG_SIM_VIRTEX6 should be instantiated per design.
|
|
// : All inputs and outputs should be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// JTAG_SIM_VIRTEX6: JTAG Interface Simulation Model
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
JTAG_SIM_VIRTEX6 #(
|
|
.PART_NAME("LX75T") // Specify target V6 device. Possible values are:
|
|
// "CX130T","CX195T","CX240T","CX75T","HX250T","HX255T","HX380T","HX45T","HX565T",
|
|
// "LX115T","LX130T","LX130TL","LX195T","LX195TL","LX240T","LX240TL","LX365T","LX365TL",
|
|
// "LX40T","LX550T","LX550TL","LX75T","LX760","SX315T","SX475T"
|
|
) JTAG_SIM_VIRTEX6_inst (
|
|
.TDO(TDO), // 1-bit JTAG data output
|
|
.TCK(TCK), // 1-bit Clock input
|
|
.TDI(TDI), // 1-bit JTAG data input
|
|
.TMS(TMS) // 1-bit JTAG command input
|
|
);
|
|
|
|
// End of JTAG_SIM_VIRTEX6_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Clock Components" treetype="folder">
|
|
<Template label="Global Clock Buffer with Clock Enable and Output State 1 (BUFGCE_1)" treetype="template">
|
|
// BUFGCE_1 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFGCE_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFGCE_1: Global Clock Buffer with Clock Enable and Output State 1
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFGCE_1 BUFGCE_1_inst (
|
|
.O(O), // 1-bit output: Clock buffer output
|
|
.CE(CE), // 1-bit input: Clock enable input for I0 input
|
|
.I(I) // 1-bit input: Primary clock input
|
|
);
|
|
|
|
// End of BUFGCE_1_inst instantiation
|
|
</Template>
|
|
<Template label="Global Clock Buffer with Clock Enable (BUFGCE)" treetype="template">
|
|
// BUFGCE : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFGCE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFGCE: Global Clock Buffer with Clock Enable
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFGCE BUFGCE_inst (
|
|
.O(O), // 1-bit output: Clock buffer output
|
|
.CE(CE), // 1-bit input: Clock enable input for I0 input
|
|
.I(I) // 1-bit input: Primary clock input
|
|
);
|
|
|
|
// End of BUFGCE_inst instantiation
|
|
</Template>
|
|
<Template label="Global Clock MUX Buffer (BUFGCTRL)" treetype="template">
|
|
// BUFGCTRL : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFGCTRL_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFGCTRL: Global Clock MUX Buffer
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFGCTRL #(
|
|
.INIT_OUT(0), // Initial value of BUFGCTRL output (0/1)
|
|
.PRESELECT_I0("FALSE"), // BUFGCTRL output uses I0 input (TRUE/FALSE)
|
|
.PRESELECT_I1("FALSE") // BUFGCTRL output uses I1 input (TRUE/FALSE)
|
|
)
|
|
BUFGCTRL_inst (
|
|
.O(O), // 1-bit output: Clock Output pin
|
|
.CE0(CE0), // 1-bit input: Clock enable input for I0 input
|
|
.CE1(CE1), // 1-bit input: Clock enable input for I1 input
|
|
.I0(I0), // 1-bit input: Primary clock input
|
|
.I1(I1), // 1-bit input: Secondary clock input
|
|
.IGNORE0(IGNORE0), // 1-bit input: Clock ignore input for I0
|
|
.IGNORE1(IGNORE1), // 1-bit input: Clock ignore input for I1
|
|
.S0(S0), // 1-bit input: Clock select input for I0
|
|
.S1(S1) // 1-bit input: Clock select input for I1
|
|
);
|
|
|
|
// End of BUFGCTRL_inst instantiation
|
|
</Template>
|
|
<Template label="Global Clock Mux Buffer with Output State 1 (BUFGMUX_1)" treetype="template">
|
|
// BUFGMUX_1 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFGMUX_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFGMUX_1: Global Clock Mux Buffer with Output State 1
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFGMUX_1 BUFGMUX_1_inst (
|
|
.O(O), // 1-bit output: Clock buffer output
|
|
.I0(I0), // 1-bit input: Clock buffer input (S=0)
|
|
.I1(I1), // 1-bit input: Clock buffer input (S=1)
|
|
.S(S) // 1-bit input: Clock buffer select
|
|
);
|
|
|
|
// End of BUFGMUX_1_inst instantiation
|
|
</Template>
|
|
<Template label="2-to-1 Global Clock MUX Buffer (BUFGMUX_CTRL)" treetype="template">
|
|
// BUFGMUX_CTRL : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFGMUX_CTRL_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFGMUX_CTRL: 2-to-1 Global Clock MUX Buffer
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFGMUX_CTRL BUFGMUX_CTRL_inst (
|
|
.O(O), // 1-bit output: Clock buffer output
|
|
.I0(I0), // 1-bit input: Clock buffer input (S=0)
|
|
.I1(I1), // 1-bit input: Clock buffer input (S=1)
|
|
.S(S) // 1-bit input: Clock buffer select
|
|
);
|
|
|
|
// End of BUFGMUX_CTRL_inst instantiation
|
|
</Template>
|
|
<Template label="Global Clock Mux Buffer (BUFGMUX)" treetype="template">
|
|
// BUFGMUX : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFGMUX_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFGMUX: Global Clock Mux Buffer
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFGMUX BUFGMUX_inst (
|
|
.O(O), // 1-bit output: Clock buffer output
|
|
.I0(I0), // 1-bit input: Clock buffer input (S=0)
|
|
.I1(I1), // 1-bit input: Clock buffer input (S=1)
|
|
.S(S) // 1-bit input: Clock buffer select
|
|
);
|
|
|
|
// End of BUFGMUX_inst instantiation
|
|
</Template>
|
|
<Template label="Global Clock Buffer (BUFG)" treetype="template">
|
|
// BUFG : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFG_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFG: Global Clock Buffer
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFG BUFG_inst (
|
|
.O(O), // 1-bit output: Clock buffer output
|
|
.I(I) // 1-bit input: Clock buffer input
|
|
);
|
|
|
|
// End of BUFG_inst instantiation
|
|
</Template>
|
|
<Template label="HROW Clock Buffer for a Single Clocking Region with Clock Enable (BUFHCE)" treetype="template">
|
|
// BUFHCE : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFHCE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFHCE: HROW Clock Buffer for a Single Clocking Region with Clock Enable
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFHCE #(
|
|
.INIT_OUT(0) // Initial output value
|
|
)
|
|
BUFHCE_inst (
|
|
.O(O), // 1-bit output: Clock output
|
|
.CE(CE), // 1-bit input: Active high enable input
|
|
.I(I) // 1-bit input: Clock input
|
|
);
|
|
|
|
// End of BUFHCE_inst instantiation
|
|
</Template>
|
|
<Template label="HROW Clock Buffer for a Single Clocking Region (BUFH)" treetype="template">
|
|
// BUFH : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFH_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFH: HROW Clock Buffer for a Single Clocking Region
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFH BUFH_inst (
|
|
.O(O), // 1-bit output: Clock output
|
|
.I(I) // 1-bit input: Clock input
|
|
);
|
|
|
|
// End of BUFH_inst instantiation
|
|
</Template>
|
|
<Template label="Local Clock Buffer for I/O (BUFIO)" treetype="template">
|
|
// BUFIO : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFIO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFIO: Local Clock Buffer for I/O
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFIO BUFIO_inst (
|
|
.O(O), // 1-bit output: Clock output port (connect to I/O clock loads)
|
|
.I(I) // 1-bit input: Clock input port (connect to IBUFG)
|
|
);
|
|
|
|
// End of BUFIO_inst instantiation
|
|
</Template>
|
|
<Template label="Advanced Mixed Mode Clock Manager (MMCM_ADV)" treetype="template">
|
|
// MMCM_ADV : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MMCM_ADV_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MMCM_ADV: Advanced Mixed Mode Clock Manager
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MMCM_ADV #(
|
|
.BANDWIDTH("OPTIMIZED"), // Jitter programming ("HIGH","LOW","OPTIMIZED")
|
|
.CLKFBOUT_MULT_F(5.0), // Multiply value for all CLKOUT (5.0-64.0).
|
|
.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB (0.00-360.00).
|
|
// CLKIN_PERIOD: Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
|
|
.CLKIN1_PERIOD(0.0),
|
|
.CLKIN2_PERIOD(0.0),
|
|
.CLKOUT0_DIVIDE_F(1.0), // Divide amount for CLKOUT0 (1.000-128.000).
|
|
// CLKOUT0_DUTY_CYCLE - CLKOUT6_DUTY_CYCLE: Duty cycle for CLKOUT outputs (0.01-0.99).
|
|
.CLKOUT0_DUTY_CYCLE(0.5),
|
|
.CLKOUT1_DUTY_CYCLE(0.5),
|
|
.CLKOUT2_DUTY_CYCLE(0.5),
|
|
.CLKOUT3_DUTY_CYCLE(0.5),
|
|
.CLKOUT4_DUTY_CYCLE(0.5),
|
|
.CLKOUT5_DUTY_CYCLE(0.5),
|
|
.CLKOUT6_DUTY_CYCLE(0.5),
|
|
// CLKOUT0_PHASE - CLKOUT6_PHASE: Phase offset for CLKOUT outputs (-360.000-360.000).
|
|
.CLKOUT0_PHASE(0.0),
|
|
.CLKOUT1_PHASE(0.0),
|
|
.CLKOUT2_PHASE(0.0),
|
|
.CLKOUT3_PHASE(0.0),
|
|
.CLKOUT4_PHASE(0.0),
|
|
.CLKOUT5_PHASE(0.0),
|
|
.CLKOUT6_PHASE(0.0),
|
|
// CLKOUT1_DIVIDE - CLKOUT6_DIVIDE: Divide amount for CLKOUT (1-128)
|
|
.CLKOUT1_DIVIDE(1),
|
|
.CLKOUT2_DIVIDE(1),
|
|
.CLKOUT3_DIVIDE(1),
|
|
.CLKOUT4_DIVIDE(1),
|
|
.CLKOUT5_DIVIDE(1),
|
|
.CLKOUT6_DIVIDE(1),
|
|
.CLKOUT4_CASCADE("FALSE"), // Cascase CLKOUT4 counter with CLKOUT6 (TRUE/FALSE)
|
|
.CLOCK_HOLD("FALSE"), // Hold VCO Frequency (TRUE/FALSE)
|
|
.COMPENSATION("ZHOLD"), // "ZHOLD", "INTERNAL", "EXTERNAL", "CASCADE" or "BUF_IN"
|
|
.DIVCLK_DIVIDE(1), // Master division value (1-80)
|
|
// REF_JITTER: Reference input jitter in UI (0.000-0.999).
|
|
.REF_JITTER1(0.0),
|
|
.REF_JITTER2(0.0),
|
|
.STARTUP_WAIT("FALSE"), // Not supported. Must be set to FALSE.
|
|
// USE_FINE_PS: Fine phase shift enable (TRUE/FALSE)
|
|
.CLKFBOUT_USE_FINE_PS("FALSE"),
|
|
.CLKOUT0_USE_FINE_PS("FALSE"),
|
|
.CLKOUT1_USE_FINE_PS("FALSE"),
|
|
.CLKOUT2_USE_FINE_PS("FALSE"),
|
|
.CLKOUT3_USE_FINE_PS("FALSE"),
|
|
.CLKOUT4_USE_FINE_PS("FALSE"),
|
|
.CLKOUT5_USE_FINE_PS("FALSE"),
|
|
.CLKOUT6_USE_FINE_PS("FALSE")
|
|
)
|
|
MMCM_ADV_inst (
|
|
// Clock Outputs: 1-bit (each) output: User configurable clock outputs
|
|
.CLKOUT0(CLKOUT0), // 1-bit output: CLKOUT0 output
|
|
.CLKOUT0B(CLKOUT0B), // 1-bit output: Inverted CLKOUT0 output
|
|
.CLKOUT1(CLKOUT1), // 1-bit output: CLKOUT1 output
|
|
.CLKOUT1B(CLKOUT1B), // 1-bit output: Inverted CLKOUT1 output
|
|
.CLKOUT2(CLKOUT2), // 1-bit output: CLKOUT2 output
|
|
.CLKOUT2B(CLKOUT2B), // 1-bit output: Inverted CLKOUT2 output
|
|
.CLKOUT3(CLKOUT3), // 1-bit output: CLKOUT3 output
|
|
.CLKOUT3B(CLKOUT3B), // 1-bit output: Inverted CLKOUT3 output
|
|
.CLKOUT4(CLKOUT4), // 1-bit output: CLKOUT4 output
|
|
.CLKOUT5(CLKOUT5), // 1-bit output: CLKOUT5 output
|
|
.CLKOUT6(CLKOUT6), // 1-bit output: CLKOUT6 output
|
|
// DRP Ports: 16-bit (each) output: Dynamic reconfigration ports
|
|
.DO(DO), // 16-bit output: DRP data output
|
|
.DRDY(DRDY), // 1-bit output: DRP ready output
|
|
// Dynamic Phase Shift Ports: 1-bit (each) output: Ports used for dynamic phase shifting of the outputs
|
|
.PSDONE(PSDONE), // 1-bit output: Phase shift done output
|
|
// Feedback Clocks: 1-bit (each) output: Clock feedback ports
|
|
.CLKFBOUT(CLKFBOUT), // 1-bit output: Feedback clock output
|
|
.CLKFBOUTB(CLKFBOUTB), // 1-bit output: Inverted CLKFBOUT
|
|
// Status Ports: 1-bit (each) output: MMCM status ports
|
|
.CLKFBSTOPPED(CLKFBSTOPPED), // 1-bit output: Feedback clock stopped output
|
|
.CLKINSTOPPED(CLKINSTOPPED), // 1-bit output: Input clock stopped output
|
|
.LOCKED(LOCKED), // 1-bit output: LOCK output
|
|
// Clock Inputs: 1-bit (each) input: Clock inputs
|
|
.CLKIN1(CLKIN1), // 1-bit input: Primary clock input
|
|
.CLKIN2(CLKIN2), // 1-bit input: Secondary clock input
|
|
// Control Ports: 1-bit (each) input: MMCM control ports
|
|
.CLKINSEL(CLKINSEL), // 1-bit input: Clock select input
|
|
.PWRDWN(PWRDWN), // 1-bit input: Power-down input
|
|
.RST(RST), // 1-bit input: Reset input
|
|
// DRP Ports: 7-bit (each) input: Dynamic reconfigration ports
|
|
.DADDR(DADDR), // 7-bit input: DRP adrress input
|
|
.DCLK(DCLK), // 1-bit input: DRP clock input
|
|
.DEN(DEN), // 1-bit input: DRP enable input
|
|
.DI(DI), // 16-bit input: DRP data input
|
|
.DWE(DWE), // 1-bit input: DRP write enable input
|
|
// Dynamic Phase Shift Ports: 1-bit (each) input: Ports used for dynamic phase shifting of the outputs
|
|
.PSCLK(PSCLK), // 1-bit input: Phase shift clock input
|
|
.PSEN(PSEN), // 1-bit input: Phase shift enable input
|
|
.PSINCDEC(PSINCDEC), // 1-bit input: Phase shift increment/decrement input
|
|
// Feedback Clocks: 1-bit (each) input: Clock feedback ports
|
|
.CLKFBIN(CLKFBIN) // 1-bit input: Feedback clock input
|
|
);
|
|
|
|
// End of MMCM_ADV_inst instantiation
|
|
</Template>
|
|
<Template label="Base Mixed Mode Clock Manager (MMCM_BASE)" treetype="template">
|
|
// MMCM_BASE : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MMCM_BASE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MMCM_BASE: Base Mixed Mode Clock Manager
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MMCM_BASE #(
|
|
.BANDWIDTH("OPTIMIZED"), // Jitter programming ("HIGH","LOW","OPTIMIZED")
|
|
.CLKFBOUT_MULT_F(5.0), // Multiply value for all CLKOUT (5.0-64.0).
|
|
.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB (0.00-360.00).
|
|
.CLKIN1_PERIOD(0.0), // Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
|
|
.CLKOUT0_DIVIDE_F(1.0), // Divide amount for CLKOUT0 (1.000-128.000).
|
|
// CLKOUT0_DUTY_CYCLE - CLKOUT6_DUTY_CYCLE: Duty cycle for each CLKOUT (0.01-0.99).
|
|
.CLKOUT0_DUTY_CYCLE(0.5),
|
|
.CLKOUT1_DUTY_CYCLE(0.5),
|
|
.CLKOUT2_DUTY_CYCLE(0.5),
|
|
.CLKOUT3_DUTY_CYCLE(0.5),
|
|
.CLKOUT4_DUTY_CYCLE(0.5),
|
|
.CLKOUT5_DUTY_CYCLE(0.5),
|
|
.CLKOUT6_DUTY_CYCLE(0.5),
|
|
// CLKOUT0_PHASE - CLKOUT6_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
|
|
.CLKOUT0_PHASE(0.0),
|
|
.CLKOUT1_PHASE(0.0),
|
|
.CLKOUT2_PHASE(0.0),
|
|
.CLKOUT3_PHASE(0.0),
|
|
.CLKOUT4_PHASE(0.0),
|
|
.CLKOUT5_PHASE(0.0),
|
|
.CLKOUT6_PHASE(0.0),
|
|
// CLKOUT1_DIVIDE - CLKOUT6_DIVIDE: Divide amount for each CLKOUT (1-128)
|
|
.CLKOUT1_DIVIDE(1),
|
|
.CLKOUT2_DIVIDE(1),
|
|
.CLKOUT3_DIVIDE(1),
|
|
.CLKOUT4_DIVIDE(1),
|
|
.CLKOUT5_DIVIDE(1),
|
|
.CLKOUT6_DIVIDE(1),
|
|
.CLKOUT4_CASCADE("FALSE"), // Cascase CLKOUT4 counter with CLKOUT6 (TRUE/FALSE)
|
|
.CLOCK_HOLD("FALSE"), // Hold VCO Frequency (TRUE/FALSE)
|
|
.DIVCLK_DIVIDE(1), // Master division value (1-80)
|
|
.REF_JITTER1(0.0), // Reference input jitter in UI (0.000-0.999).
|
|
.STARTUP_WAIT("FALSE") // Not supported. Must be set to FALSE.
|
|
)
|
|
MMCM_BASE_inst (
|
|
// Clock Outputs: 1-bit (each) output: User configurable clock outputs
|
|
.CLKOUT0(CLKOUT0), // 1-bit output: CLKOUT0 output
|
|
.CLKOUT0B(CLKOUT0B), // 1-bit output: Inverted CLKOUT0 output
|
|
.CLKOUT1(CLKOUT1), // 1-bit output: CLKOUT1 output
|
|
.CLKOUT1B(CLKOUT1B), // 1-bit output: Inverted CLKOUT1 output
|
|
.CLKOUT2(CLKOUT2), // 1-bit output: CLKOUT2 output
|
|
.CLKOUT2B(CLKOUT2B), // 1-bit output: Inverted CLKOUT2 output
|
|
.CLKOUT3(CLKOUT3), // 1-bit output: CLKOUT3 output
|
|
.CLKOUT3B(CLKOUT3B), // 1-bit output: Inverted CLKOUT3 output
|
|
.CLKOUT4(CLKOUT4), // 1-bit output: CLKOUT4 output
|
|
.CLKOUT5(CLKOUT5), // 1-bit output: CLKOUT5 output
|
|
.CLKOUT6(CLKOUT6), // 1-bit output: CLKOUT6 output
|
|
// Feedback Clocks: 1-bit (each) output: Clock feedback ports
|
|
.CLKFBOUT(CLKFBOUT), // 1-bit output: Feedback clock output
|
|
.CLKFBOUTB(CLKFBOUTB), // 1-bit output: Inverted CLKFBOUT output
|
|
// Status Port: 1-bit (each) output: MMCM status ports
|
|
.LOCKED(LOCKED), // 1-bit output: LOCK output
|
|
// Clock Input: 1-bit (each) input: Clock input
|
|
.CLKIN1(CLKIN1),
|
|
// Control Ports: 1-bit (each) input: MMCM control ports
|
|
.PWRDWN(PWRDWN), // 1-bit input: Power-down input
|
|
.RST(RST), // 1-bit input: Reset input
|
|
// Feedback Clocks: 1-bit (each) input: Clock feedback ports
|
|
.CLKFBIN(CLKFBIN) // 1-bit input: Feedback clock input
|
|
);
|
|
|
|
// End of MMCM_BASE_inst instantiation
|
|
</Template>
|
|
<Template label="Single-ended Input Global Clock Buffer (IBUFG)" treetype="template">
|
|
// IBUFG : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFG_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFG: Global Clock Buffer (sourced by an external pin)
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFG #(
|
|
.IBUF_LOW_PWR("TRUE"), // Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
) IBUFG_inst (
|
|
.O(O), // Clock buffer output
|
|
.I(I) // Clock buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUFG_inst instantiation
|
|
</Template>
|
|
<Template label="I/O Clock Buffer (BUFIO)" treetype="template">
|
|
// BUFIO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFIO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFIO: Local Clock Buffer
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFIO BUFIO_inst (
|
|
.O(O), // Clock buffer output
|
|
.I(I) // Clock buffer input
|
|
);
|
|
|
|
// End of BUFIO_inst instantiation
|
|
</Template>
|
|
<Template label="Regional Clock Buffer (BUFR)" treetype="template">
|
|
// BUFR : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFR_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFR: Regional Clock Buffer for I/O and Logic Resources within a Clock Region
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFR #(
|
|
.BUFR_DIVIDE("BYPASS"), // Values: "BYPASS, 1, 2, 3, 4, 5, 6, 7, 8"
|
|
.SIM_DEVICE("VIRTEX6") // Must be set to "VIRTEX6"
|
|
)
|
|
BUFR_inst (
|
|
.O(O), // 1-bit output: Clock output port
|
|
.CE(CE), // 1-bit input: Active high, clock enable (Divided modes only)
|
|
.CLR(CLR), // 1-bit input: Active high, asynchronous clear (Divided modes only)
|
|
.I(I) // 1-bit input: Clock buffer input driven by an IBUFG, MMCM or local interconnect
|
|
);
|
|
|
|
// End of BUFR_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Input Global Clock Buffer (IBUFGDS)" treetype="template">
|
|
// IBUFGDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFGDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFGDS: Differential Global Clock Buffer (sourced by an external pin)
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFGDS #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination
|
|
.IOSTANDARD("DEFAULT") // Specifies the I/O standard for this buffer
|
|
) IBUFGDS_inst (
|
|
.O(O), // Clock buffer output
|
|
.I(I), // Diff_p clock buffer input
|
|
.IB(IB) // Diff_n clock buffer input
|
|
);
|
|
|
|
// End of IBUFGDS_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Global Clock Buffer with Differential Output (IBUFGDS_DIFF_OUT)" treetype="template">
|
|
// IBUFGDS_DIFF_OUT : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFGDS_DIFF_OUT_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFGDS_DIFF_OUT: Differential Global Clock Buffer with Differential Output
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFGDS_DIFF_OUT #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination, "TRUE"/"FALSE"
|
|
.IBUF_LOW_PWR("TRUE"), // Low power="TRUE", Highest performance="FALSE"
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
) IBUFGDS_DIFF_OUT_inst (
|
|
.O(O), // Buffer diff_p output
|
|
.OB(OB), // Buffer diff_n output
|
|
.I(I), // Diff_p buffer input (connect directly to top-level port)
|
|
.IB(IB) // Diff_n buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUFGDS_DIFF_OUT_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="I/O Components" treetype="folder">
|
|
<Template label="Digitally Controlled Impedance Reset Component (DCIRESET)" treetype="template">
|
|
// DCIRESET : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (DCIRESET_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// DCIRESET: Digitally Controlled Impedance Reset Component
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
DCIRESET DCIRESET_inst (
|
|
.LOCKED(LOCKED), // 1-bit output: LOCK status output
|
|
.RST(RST) // 1-bit input: Active-high asynchronous reset input
|
|
);
|
|
|
|
// End of DCIRESET_inst instantiation
|
|
</Template>
|
|
<Template label="Input SERial/DESerializer (ISERDESE1)" treetype="template">
|
|
// ISERDESE1 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ISERDESE1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ISERDESE1: Input SERial/DESerializer
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ISERDESE1 #(
|
|
.DATA_RATE("DDR"), // "SDR" or "DDR"
|
|
.DATA_WIDTH(4), // Parallel data width (2-8, 10)
|
|
.DYN_CLKDIV_INV_EN("FALSE"), // Enable DYNCLKDIVINVSEL inversion (TRUE/FALSE)
|
|
.DYN_CLK_INV_EN("FALSE"), // Enable DYNCLKINVSEL inversion (TRUE/FALSE)
|
|
// INIT_Q1 - INIT_Q4: Initial value on the Q outputs (0/1)
|
|
.INIT_Q1(1'b0),
|
|
.INIT_Q2(1'b0),
|
|
.INIT_Q3(1'b0),
|
|
.INIT_Q4(1'b0),
|
|
.INTERFACE_TYPE("MEMORY"), // "MEMORY", "MEMORY_DDR3", "MEMORY_QDR", "NETWORKING", or "OVERSAMPLE"
|
|
.IOBDELAY("NONE"), // "NONE", "IBUF", "IFD", "BOTH"
|
|
.NUM_CE(2), // Number of clock enables (1 or 2)
|
|
.OFB_USED("FALSE"), // Select OFB path (TRUE/FALSE)
|
|
.SERDES_MODE("MASTER"), // "MASTER" or "SLAVE"
|
|
// SRVAL_Q1 - SRVAL_Q4: Q output values when SR is used (0/1)
|
|
.SRVAL_Q1(1'b0),
|
|
.SRVAL_Q2(1'b0),
|
|
.SRVAL_Q3(1'b0),
|
|
.SRVAL_Q4(1'b0)
|
|
)
|
|
ISERDESE1_inst (
|
|
.O(O), // 1-bit output: Combinatorial output
|
|
// Q1 - Q6: 1-bit (each) output: Registered data outputs
|
|
.Q1(Q1),
|
|
.Q2(Q2),
|
|
.Q3(Q3),
|
|
.Q4(Q4),
|
|
.Q5(Q5),
|
|
.Q6(Q6),
|
|
// SHIFTOUT1-SHIFTOUT2: 1-bit (each) output: Data width expansion output ports
|
|
.SHIFTOUT1(SHIFTOUT1),
|
|
.SHIFTOUT2(SHIFTOUT2),
|
|
.BITSLIP(BITSLIP), // 1-bit input: Bitslip enable input
|
|
// CE1, CE2: 1-bit (each) input: Data register clock enable inputs
|
|
.CE1(CE1),
|
|
.CE2(CE2),
|
|
// Clocks: 1-bit (each) input: ISERDESE1 clock input ports
|
|
.CLK(CLK), // 1-bit input: High-speed clock input
|
|
.CLKB(CLKB), // 1-bit input: High-speed secondary clock input
|
|
.CLKDIV(CLKDIV), // 1-bit input: Divided clock input
|
|
.OCLK(OCLK), // 1-bit input: High speed output clock input used when
|
|
// INTERFACE_TYPE="MEMORY"
|
|
|
|
// Dynamic Clock Inversions: 1-bit (each) input: Dynamic clock inversion pins to switch clock polarity
|
|
.DYNCLKDIVSEL(DYNCLKDIVSEL), // 1-bit input: Dynamic CLKDIV inversion input
|
|
.DYNCLKSEL(DYNCLKSEL), // 1-bit input: Dynamic CLK/CLKB inversion input
|
|
// Input Data: 1-bit (each) input: ISERDESE1 data input ports
|
|
.D(D), // 1-bit input: Data input
|
|
.DDLY(DDLY), // 1-bit input: Serial input data from IODELAYE1
|
|
.OFB(OFB), // 1-bit input: Data feedback input from OSERDESE1
|
|
.RST(RST), // 1-bit input: Active high asynchronous reset input
|
|
// SHIFTIN1-SHIFTIN2: 1-bit (each) input: Data width expansion input ports
|
|
.SHIFTIN1(SHIFTIN1),
|
|
.SHIFTIN2(SHIFTIN2)
|
|
);
|
|
|
|
// End of ISERDESE1_inst instantiation
|
|
</Template>
|
|
<Template label="Output SERial/DESerializer (OSERDESE1)" treetype="template">
|
|
// OSERDESE1 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OSERDESE1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OSERDESE1: Output SERial/DESerializer
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OSERDESE1 #(
|
|
.DATA_RATE_OQ("DDR"), // "SDR" or "DDR"
|
|
.DATA_RATE_TQ("DDR"), // "BUF", "SDR" or "DDR"
|
|
.DATA_WIDTH(4), // Parallel data width (1-8,10)
|
|
.DDR3_DATA(1), // Must leave at 1 (MIG-only parameter)
|
|
.INIT_OQ(1'b0), // Initial value of OQ output (0/1)
|
|
.INIT_TQ(1'b0), // Initial value of TQ output (0/1)
|
|
.INTERFACE_TYPE("DEFAULT"), // Must leave at "DEFAULT" (MIG-only parameter)
|
|
.ODELAY_USED(0), // Must leave at 0 (MIG-only parameter)
|
|
.SERDES_MODE("MASTER"), // "MASTER" or "SLAVE"
|
|
.SRVAL_OQ(1'b0), // OQ output value when SR is used (0/1)
|
|
.SRVAL_TQ(1'b0), // TQ output value when SR is used (0/1)
|
|
.TRISTATE_WIDTH(4) // Parallel to serial 3-state converter width (1 or 4)
|
|
)
|
|
OSERDESE1_inst (
|
|
// MIG-only Signals: 1-bit (each) output: Do not use unless generated by MIG
|
|
.OCBEXTEND(OCBEXTEND), // 1-bit output: Leave unconnected (MIG-only connected signal)
|
|
// Outputs: 1-bit (each) output: Serial output ports
|
|
.OFB(OFB), // 1-bit output: Data feedback output to ISERDESE1
|
|
.OQ(OQ), // 1-bit output: Data output (connect to I/O port)
|
|
.TFB(TFB), // 1-bit output: 3-state control output
|
|
.TQ(TQ), // 1-bit output: 3-state path output
|
|
// SHIFTOUT1-SHIFTOUT2: 1-bit (each) output: Data width expansion output ports
|
|
.SHIFTOUT1(SHIFTOUT1), // 1-bit output: Connect to SHIFTIN1 of slave or unconnected
|
|
.SHIFTOUT2(SHIFTOUT2), // 1-bit output: Connect to SHIFTIN2 of slave or unconnected
|
|
// Clocks: 1-bit (each) input: OSERDESE1 clock input ports
|
|
.CLK(CLK), // 1-bit input: High-speed clock input
|
|
.CLKDIV(CLKDIV), // 1-bit input: Divided clock input
|
|
// Control Signals: 1-bit (each) input: Clock enable and reset input ports
|
|
.OCE(OCE), // 1-bit input: Active high clock data path enable input
|
|
.RST(RST), // 1-bit input: Active high reset input
|
|
.TCE(TCE), // 1-bit input: Active high clock enable input for 3-state
|
|
// D1 - D6: 1-bit (each) input: Parallel data inputs
|
|
.D1(D1),
|
|
.D2(D2),
|
|
.D3(D3),
|
|
.D4(D4),
|
|
.D5(D5),
|
|
.D6(D6),
|
|
// MIG-only Signals: 1-bit (each) input: Do not use unless generated by MIG
|
|
.CLKPERF(CLKPERF), // 1-bit input: Ground input (MIG-only connected signal)
|
|
.CLKPERFDELAY(CLKPERFDELAY), // 1-bit input: Ground input (MIG-only connected signal)
|
|
.ODV(ODV), // 1-bit input: Ground input (MIG-only connected signal)
|
|
.WC(WC), // 1-bit input: Ground input (MIG-only connected signal)
|
|
// SHIFTIN1-SHIFTIN2: 1-bit (each) input: Data width expansion input ports
|
|
.SHIFTIN1(SHIFTIN1), // 1-bit input: Connect to SHIFTOUT1 of master or GND
|
|
.SHIFTIN2(SHIFTIN2), // 1-bit input: Connect to SHIFTOUT2 of master or GND
|
|
// T1 - T4: 1-bit (each) input: Parallel 3-state inputs
|
|
.T1(T1),
|
|
.T2(T2),
|
|
.T3(T3),
|
|
.T4(T4)
|
|
);
|
|
|
|
// End of OSERDESE1_inst instantiation
|
|
</Template>
|
|
<SubFolder label="Input Buffers" treetype="folder">
|
|
<Template label="Single-ended Buffer (IBUF)" treetype="template">
|
|
// IBUF : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUF_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUF: Single-ended Input Buffer
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUF #(
|
|
.IBUF_LOW_PWR("TRUE"), // Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
)IBUF_inst (
|
|
.O(O), // Buffer output
|
|
.I(I) // Buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUF_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer (IBUFDS)" treetype="template">
|
|
// IBUFDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFDS: Differential Input Buffer
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFDS #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
) IBUFDS_inst (
|
|
.O(O), // Buffer output
|
|
.I(I), // Diff_p buffer input (connect directly to top-level port)
|
|
.IB(IB) // Diff_n buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUFDS_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer with Differential Output (IBUFDS_DIFF_OUT)" treetype="template">
|
|
// IBUFDS_DIFF_OUT : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFDS_DIFF_OUT_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFDS_DIFF_OUT: Differential Input Buffer with Differential Output
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFDS_DIFF_OUT #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination, "TRUE"/"FALSE"
|
|
.IBUF_LOW_PWR("TRUE"), // Low power="TRUE", Highest performance="FALSE"
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
) IBUFDS_DIFF_OUT_inst (
|
|
.O(O), // Buffer diff_p output
|
|
.OB(OB), // Buffer diff_n output
|
|
.I(I), // Diff_p buffer input (connect directly to top-level port)
|
|
.IB(IB) // Diff_n buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUFDS_DIFF_OUT_inst instantiation
|
|
</Template>
|
|
<Template label="Single-ended Global Clock Buffer (IBUFG)" treetype="template">
|
|
// IBUFG : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFG_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFG: Single-ended global clock input buffer
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFG #(
|
|
.IBUF_LOW_PWR("TRUE"), // Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
) IBUFG_inst (
|
|
.O(O), // Clock buffer output
|
|
.I(I) // Clock buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUFG_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Global Clock (IBUFGDS)" treetype="template">
|
|
// IBUFGDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFGDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFGDS: Differential Global Clock Input Buffer
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFGDS #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
) IBUFGDS_inst (
|
|
.O(O), // Clock buffer output
|
|
.I(I), // Diff_p clock buffer input (connect directly to top-level port)
|
|
.IB(IB) // Diff_n clock buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUFGDS_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Global Clock Buffer with Differential Output (IBUFGDS_DIFF_OUT)" treetype="template">
|
|
// IBUFGDS_DIFF_OUT : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFGDS_DIFF_OUT_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFGDS_DIFF_OUT: Differential Global Clock Buffer with Differential Output
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFGDS_DIFF_OUT #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination, "TRUE"/"FALSE"
|
|
.IBUF_LOW_PWR("TRUE"), // Low power="TRUE", Highest performance="FALSE"
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
) IBUFGDS_DIFF_OUT_inst (
|
|
.O(O), // Buffer diff_p output
|
|
.OB(OB), // Buffer diff_n output
|
|
.I(I), // Diff_p buffer input (connect directly to top-level port)
|
|
.IB(IB) // Diff_n buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUFGDS_DIFF_OUT_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Output Buffers" treetype="folder">
|
|
<Template label="Single-ended Buffer (OBUF)" treetype="template">
|
|
// OBUF : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OBUF_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OBUF: Single-ended Output Buffer
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OBUF #(
|
|
.DRIVE(12), // Specify the output drive strength
|
|
.IOSTANDARD("DEFAULT"), // Specify the output I/O standard
|
|
.SLEW("SLOW") // Specify the output slew rate
|
|
) OBUF_inst (
|
|
.O(O), // Buffer output (connect directly to top-level port)
|
|
.I(I) // Buffer input
|
|
);
|
|
|
|
// End of OBUF_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer (OBUFDS)" treetype="template">
|
|
|
|
// OBUFDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OBUFDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OBUFDS: Differential Output Buffer
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OBUFDS #(
|
|
.IOSTANDARD("DEFAULT") // Specify the output I/O standard
|
|
) OBUFDS_inst (
|
|
.O(O), // Diff_p output (connect directly to top-level port)
|
|
.OB(OB), // Diff_n output (connect directly to top-level port)
|
|
.I(I) // Buffer input
|
|
);
|
|
|
|
// End of OBUFDS_inst instantiation
|
|
</Template>
|
|
<Template label="Single-ended 3-state Buffer (OBUFT)" treetype="template">
|
|
// OBUFT : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OBUFT_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OBUFT: Single-ended 3-state Output Buffer
|
|
// All devices
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OBUFT #(
|
|
.DRIVE(12), // Specify the output drive strength
|
|
.IOSTANDARD("DEFAULT"), // Specify the output I/O standard
|
|
.SLEW("SLOW") // Specify the output slew rate
|
|
) OBUFT_inst (
|
|
.O(O), // Buffer output (connect directly to top-level port)
|
|
.I(I), // Buffer input
|
|
.T(T) // 3-state enable input
|
|
);
|
|
|
|
// End of OBUFT_inst instantiation
|
|
</Template>
|
|
<Template label="Differential 3-state Buffer (OBUFTDS)" treetype="template">
|
|
// OBUFTDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OBUFTDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OBUFTDS: Differential 3-state Output Buffer
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OBUFTDS #(
|
|
.IOSTANDARD("DEFAULT") // Specify the output I/O standard
|
|
) OBUFTDS_inst (
|
|
.O(O), // Diff_p output (connect directly to top-level port)
|
|
.OB(OB), // Diff_n output (connect directly to top-level port)
|
|
.I(I), // Buffer input
|
|
.T(T) // 3-state enable input
|
|
);
|
|
|
|
// End of OBUFTDS_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Bi-directional Buffers" treetype="folder">
|
|
<Template label="Single-ended Buffer (IOBUF)" treetype="template">
|
|
// IOBUF : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IOBUF_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IOBUF: Single-ended Bi-directional Buffer
|
|
// All devices
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IOBUF #(
|
|
.DRIVE(12), // Specify the output drive strength
|
|
.IOSTANDARD("DEFAULT"), // Specify the I/O standard
|
|
.SLEW("SLOW") // Specify the output slew rate
|
|
) IOBUF_inst (
|
|
.O(O), // Buffer output
|
|
.IO(IO), // Buffer inout port (connect directly to top-level port)
|
|
.I(I), // Buffer input
|
|
.T(T) // 3-state enable input, high=input, low=output
|
|
);
|
|
|
|
// End of IOBUF_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer (IOBUFDS)" treetype="template">
|
|
// IOBUFDS : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IOBUFDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IOBUFDS: Differential Bi-directional Buffer
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IOBUFDS #(
|
|
.IOSTANDARD("BLVDS_25") // Specify the I/O standard
|
|
) IOBUFDS_inst (
|
|
.O(O), // Buffer output
|
|
.IO(IO), // Diff_p inout (connect directly to top-level port)
|
|
.IOB(IOB), // Diff_n inout (connect directly to top-level port)
|
|
.I(I), // Buffer input
|
|
.T(T) // 3-state enable input, high=input, low=output
|
|
);
|
|
|
|
// End of IOBUFDS_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Weak drivers" treetype="folder">
|
|
<Template label="PULLUP" treetype="template">
|
|
// PULLUP : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (PULLUP_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design.
|
|
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// PULLUP: I/O Buffer Weak Pull-up
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
PULLUP PULLUP_inst (
|
|
.O(O) // Pullup output (connect directly to top-level port)
|
|
);
|
|
|
|
// End of PULLUP_inst instantiation
|
|
</Template>
|
|
<Template label="PULLDOWN" treetype="template">
|
|
// PULLDOWN : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (PULLDOWN_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// PULLDOWN: I/O Buffer Weak Pull-down
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
PULLDOWN PULLDOWN_inst (
|
|
.O(O) // Pulldown output (connect directly to top-level port)
|
|
);
|
|
|
|
// End of PULLDOWN_inst instantiation
|
|
</Template>
|
|
<Template label="KEEPER" treetype="template">
|
|
// KEEPER : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (KEEPER_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// KEEPER: I/O Buffer Weak Keeper
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
KEEPER KEEPER_inst (
|
|
.O(O) // Keeper output (connect directly to top-level port)
|
|
);
|
|
|
|
// End of KEEPER_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="DDR Registers" treetype="folder">
|
|
<Template label="Dual-Clock, Input DDR Register (IDDR_2CLK)" treetype="template">
|
|
// IDDR_2CLK : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IDDR_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IDDR_2CLK: Dual-Clock, Input Double Data Rate Input Register with
|
|
// Set, Reset and Clock Enable.
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IDDR_2CLK #(
|
|
.DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE", "SAME_EDGE"
|
|
// or "SAME_EDGE_PIPELINED"
|
|
.INIT_Q1(1'b0), // Initial value of Q1: 1'b0 or 1'b1
|
|
.INIT_Q2(1'b0), // Initial value of Q2: 1'b0 or 1'b1
|
|
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
|
|
) IDDR_2CLK_inst (
|
|
.Q1(Q1), // 1-bit output for positive edge of clock
|
|
.Q2(Q2), // 1-bit output for negative edge of clock
|
|
.C(C), // 1-bit primary clock input
|
|
.CB(CB), // 1-bit secondary clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.D(D), // 1-bit DDR data input
|
|
.R(R), // 1-bit reset
|
|
.S(S) // 1-bit set
|
|
);
|
|
|
|
// End of IDDR_2CLK_inst instantiation
|
|
</Template>
|
|
<Template label="Input DDR Register (IDDR)" treetype="template">
|
|
// IDDR : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IDDR_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IDDR: Input Double Data Rate Input Register with Set, Reset
|
|
// and Clock Enable.
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IDDR #(
|
|
.DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE", "SAME_EDGE"
|
|
// or "SAME_EDGE_PIPELINED"
|
|
.INIT_Q1(1'b0), // Initial value of Q1: 1'b0 or 1'b1
|
|
.INIT_Q2(1'b0), // Initial value of Q2: 1'b0 or 1'b1
|
|
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
|
|
) IDDR_inst (
|
|
.Q1(Q1), // 1-bit output for positive edge of clock
|
|
.Q2(Q2), // 1-bit output for negative edge of clock
|
|
.C(C), // 1-bit clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.D(D), // 1-bit DDR data input
|
|
.R(R), // 1-bit reset
|
|
.S(S) // 1-bit set
|
|
);
|
|
|
|
// End of IDDR_inst instantiation
|
|
</Template>
|
|
<Template label="Output DDR Register (ODDR)" treetype="template">
|
|
// ODDR : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ODDR_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ODDR: Output Double Data Rate Output Register with Set, Reset
|
|
// and Clock Enable.
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ODDR #(
|
|
.DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE"
|
|
.INIT(1'b0), // Initial value of Q: 1'b0 or 1'b1
|
|
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
|
|
) ODDR_inst (
|
|
.Q(Q), // 1-bit DDR output
|
|
.C(C), // 1-bit clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.D1(D1), // 1-bit data input (positive edge)
|
|
.D2(D2), // 1-bit data input (negative edge)
|
|
.R(R), // 1-bit reset
|
|
.S(S) // 1-bit set
|
|
);
|
|
|
|
// End of ODDR_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<Template label="IDELAY Tap Delay Value Control (IDELAYCTRL)" treetype="template">
|
|
// IDELAYCTRL : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IDELAYCTRL_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IDELAYCTRL: IDELAY Tap Delay Value Control
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
(* IODELAY_GROUP = "<iodelay_group_name>" *) // Specifies group name for associated IODELAYs and IDELAYCTRL
|
|
IDELAYCTRL IDELAYCTRL_inst (
|
|
.RDY(RDY), // 1-bit Ready output
|
|
.REFCLK(REFCLK), // 1-bit Reference clock input
|
|
.RST(RST) // 1-bit Reset input
|
|
);
|
|
|
|
// End of IDELAYCTRL_inst instantiation
|
|
</Template>
|
|
<Template label="Input and Output Fixed or Variable Delay Element (IODELAYE1)" treetype="template">
|
|
// IODELAYE1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IODELAYE1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IODELAYE1: Input / Output Fixed or Variable Delay Element
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
(* IODELAY_GROUP = "<iodelay_group_name>" *) // Specifies group name for associated IODELAYs and IDELAYCTRL
|
|
IODELAYE1 #(
|
|
.CINVCTRL_SEL("FALSE"), // Enable dynamic clock inversion ("TRUE"/"FALSE")
|
|
.DELAY_SRC("I"), // Delay input ("I", "CLKIN", "DATAIN", "IO", "O")
|
|
.HIGH_PERFORMANCE_MODE("FALSE"), // Reduced jitter ("TRUE"), Reduced power ("FALSE")
|
|
.IDELAY_TYPE("DEFAULT"), // "DEFAULT", "FIXED", "VARIABLE", or "VAR_LOADABLE"
|
|
.IDELAY_VALUE(0), // Input delay tap setting (0-32)
|
|
.ODELAY_TYPE("FIXED"), // "FIXED", "VARIABLE", or "VAR_LOADABLE"
|
|
.ODELAY_VALUE(0), // Output delay tap setting (0-32)
|
|
.REFCLK_FREQUENCY(200.0), // IDELAYCTRL clock input frequency in MHz
|
|
.SIGNAL_PATTERN("DATA") // "DATA" or "CLOCK" input signal
|
|
)
|
|
IODELAYE1_inst (
|
|
.CNTVALUEOUT(CNTVALUEOUT), // 5-bit output - Counter value for monitoring purpose
|
|
.DATAOUT(DATAOUT), // 1-bit output - Delayed data output
|
|
.C(C), // 1-bit input - Clock input
|
|
.CE(CE), // 1-bit input - Active high enable increment/decrement function
|
|
.CINVCTRL(CINVCTRL), // 1-bit input - Dynamically inverts the Clock (C) polarity
|
|
.CLKIN(CLKIN), // 1-bit input - Clock Access into the IODELAY
|
|
.CNTVALUEIN(CNTVALUEIN), // 5-bit input - Counter value for loadable counter application
|
|
.DATAIN(DATAIN), // 1-bit input - Internal delay data
|
|
.IDATAIN(IDATAIN), // 1-bit input - Delay data input
|
|
.INC(INC), // 1-bit input - Increment / Decrement tap delay
|
|
.ODATAIN(ODATAIN), // 1-bit input - Data input for the output datapath from the device
|
|
.RST(RST), // 1-bit input - Active high, synchronous reset, resets delay chain to IDELAY_VALUE/
|
|
// ODELAY_VALUE tap. If no value is specified, the default is 0.
|
|
.T(T) // 1-bit input - 3-state input control. Tie high for input-only or internal delay or
|
|
// tie low for output only.
|
|
|
|
);
|
|
|
|
// End of IODELAYE1_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Arithmetic Functions" treetype="folder">
|
|
<Template label="48-bit Multi-Functional Arithmetic Block (DSP48E1)" treetype="template">
|
|
// DSP48E1 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (DSP48E1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// DSP48E1: 48-bit Multi-Functional Arithmetic Block
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
DSP48E1 #(
|
|
// Feature Control Attributes: Data Path Selection
|
|
.A_INPUT("DIRECT"), // Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
|
|
.B_INPUT("DIRECT"), // Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
|
|
.USE_DPORT("FALSE"), // Select D port usage (TRUE or FALSE)
|
|
.USE_MULT("MULTIPLY"), // Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE")
|
|
// Pattern Detector Attributes: Pattern Detection Configuration
|
|
.AUTORESET_PATDET("NO_RESET"), // "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH"
|
|
.MASK(48'h3fffffffffff), // 48-bit mask value for pattern detect (1=ignore)
|
|
.PATTERN(48'h000000000000), // 48-bit pattern match for pattern detect
|
|
.SEL_MASK("MASK"), // "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2"
|
|
.SEL_PATTERN("PATTERN"), // Select pattern value ("PATTERN" or "C")
|
|
.USE_PATTERN_DETECT("NO_PATDET"), // Enable pattern detect ("PATDET" or "NO_PATDET")
|
|
// Register Control Attributes: Pipeline Register Configuration
|
|
.ACASCREG(1), // Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2)
|
|
.ADREG(1), // Number of pipeline stages for pre-adder (0 or 1)
|
|
.ALUMODEREG(1), // Number of pipeline stages for ALUMODE (0 or 1)
|
|
.AREG(1), // Number of pipeline stages for A (0, 1 or 2)
|
|
.BCASCREG(1), // Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2)
|
|
.BREG(1), // Number of pipeline stages for B (0, 1 or 2)
|
|
.CARRYINREG(1), // Number of pipeline stages for CARRYIN (0 or 1)
|
|
.CARRYINSELREG(1), // Number of pipeline stages for CARRYINSEL (0 or 1)
|
|
.CREG(1), // Number of pipeline stages for C (0 or 1)
|
|
.DREG(1), // Number of pipeline stages for D (0 or 1)
|
|
.INMODEREG(1), // Number of pipeline stages for INMODE (0 or 1)
|
|
.MREG(1), // Number of multiplier pipeline stages (0 or 1)
|
|
.OPMODEREG(1), // Number of pipeline stages for OPMODE (0 or 1)
|
|
.PREG(1), // Number of pipeline stages for P (0 or 1)
|
|
.USE_SIMD("ONE48") // SIMD selection ("ONE48", "TWO24", "FOUR12")
|
|
)
|
|
DSP48E1_inst (
|
|
// Cascade: 30-bit (each) output: Cascade Ports
|
|
.ACOUT(ACOUT), // 30-bit output: A port cascade output
|
|
.BCOUT(BCOUT), // 18-bit output: B port cascade output
|
|
.CARRYCASCOUT(CARRYCASCOUT), // 1-bit output: Cascade carry output
|
|
.MULTSIGNOUT(MULTSIGNOUT), // 1-bit output: Multiplier sign cascade output
|
|
.PCOUT(PCOUT), // 48-bit output: Cascade output
|
|
// Control: 1-bit (each) output: Control Inputs/Status Bits
|
|
.OVERFLOW(OVERFLOW), // 1-bit output: Overflow in add/acc output
|
|
.PATTERNBDETECT(PATTERNBDETECT), // 1-bit output: Pattern bar detect output
|
|
.PATTERNDETECT(PATTERNDETECT), // 1-bit output: Pattern detect output
|
|
.UNDERFLOW(UNDERFLOW), // 1-bit output: Underflow in add/acc output
|
|
// Data: 4-bit (each) output: Data Ports
|
|
.CARRYOUT(CARRYOUT), // 4-bit output: Carry output
|
|
.P(P), // 48-bit output: Primary data output
|
|
// Cascade: 30-bit (each) input: Cascade Ports
|
|
.ACIN(ACIN), // 30-bit input: A cascade data input
|
|
.BCIN(BCIN), // 18-bit input: B cascade input
|
|
.CARRYCASCIN(CARRYCASCIN), // 1-bit input: Cascade carry input
|
|
.MULTSIGNIN(MULTSIGNIN), // 1-bit input: Multiplier sign input
|
|
.PCIN(PCIN), // 48-bit input: P cascade input
|
|
// Control: 4-bit (each) input: Control Inputs/Status Bits
|
|
.ALUMODE(ALUMODE), // 4-bit input: ALU control input
|
|
.CARRYINSEL(CARRYINSEL), // 3-bit input: Carry select input
|
|
.CEINMODE(CEINMODE), // 1-bit input: Clock enable input for INMODEREG
|
|
.CLK(CLK), // 1-bit input: Clock input
|
|
.INMODE(INMODE), // 5-bit input: INMODE control input
|
|
.OPMODE(OPMODE), // 7-bit input: Operation mode input
|
|
.RSTINMODE(RSTINMODE), // 1-bit input: Reset input for INMODEREG
|
|
// Data: 30-bit (each) input: Data Ports
|
|
.A(A), // 30-bit input: A data input
|
|
.B(B), // 18-bit input: B data input
|
|
.C(C), // 48-bit input: C data input
|
|
.CARRYIN(CARRYIN), // 1-bit input: Carry input signal
|
|
.D(D), // 25-bit input: D data input
|
|
// Reset/Clock Enable: 1-bit (each) input: Reset/Clock Enable Inputs
|
|
.CEA1(CEA1), // 1-bit input: Clock enable input for 1st stage AREG
|
|
.CEA2(CEA2), // 1-bit input: Clock enable input for 2nd stage AREG
|
|
.CEAD(CEAD), // 1-bit input: Clock enable input for ADREG
|
|
.CEALUMODE(CEALUMODE), // 1-bit input: Clock enable input for ALUMODERE
|
|
.CEB1(CEB1), // 1-bit input: Clock enable input for 1st stage BREG
|
|
.CEB2(CEB2), // 1-bit input: Clock enable input for 2nd stage BREG
|
|
.CEC(CEC), // 1-bit input: Clock enable input for CREG
|
|
.CECARRYIN(CECARRYIN), // 1-bit input: Clock enable input for CARRYINREG
|
|
.CECTRL(CECTRL), // 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
|
|
.CED(CED), // 1-bit input: Clock enable input for DREG
|
|
.CEM(CEM), // 1-bit input: Clock enable input for MREG
|
|
.CEP(CEP), // 1-bit input: Clock enable input for PREG
|
|
.RSTA(RSTA), // 1-bit input: Reset input for AREG
|
|
.RSTALLCARRYIN(RSTALLCARRYIN), // 1-bit input: Reset input for CARRYINREG
|
|
.RSTALUMODE(RSTALUMODE), // 1-bit input: Reset input for ALUMODEREG
|
|
.RSTB(RSTB), // 1-bit input: Reset input for BREG
|
|
.RSTC(RSTC), // 1-bit input: Reset input for CREG
|
|
.RSTCTRL(RSTCTRL), // 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
|
|
.RSTD(RSTD), // 1-bit input: Reset input for DREG and ADREG
|
|
.RSTM(RSTM), // 1-bit input: Reset input for MREG
|
|
.RSTP(RSTP) // 1-bit input: Reset input for PREG
|
|
);
|
|
|
|
// End of DSP48E1_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="RAM/ROM" treetype="folder">
|
|
<Template label="18KB FIFO (First In, First Out) Block RAM Memory (FIFO18E1)" treetype="template">
|
|
// FIFO18E1 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FIFO18E1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FIFO18E1: 18KB FIFO (First In, First Out) Block RAM Memory
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FIFO18E1 #(
|
|
.ALMOST_EMPTY_OFFSET(13'h0080), // Sets the almost empty threshold
|
|
.ALMOST_FULL_OFFSET(13'h0080), // Sets almost full threshold
|
|
.DATA_WIDTH(4), // Sets data width to 4, 9, 18, or 36
|
|
.DO_REG(1), // Enable output register (0 or 1) Must be 1 if EN_SYN = FALSE
|
|
.EN_SYN("FALSE"), // Specifies FIFO as dual-clock (FALSE) or Synchronous (TRUE)
|
|
.FIFO_MODE("FIFO18"), // Sets mode to FIFO18 or FIFO18_36
|
|
.FIRST_WORD_FALL_THROUGH("FALSE"), // Sets the FIFO FWFT to TRUE or FALSE
|
|
.INIT(36'h000000000), // Initial values on output port
|
|
.SRVAL(36'h000000000) // Set/Reset value for output port
|
|
)
|
|
FIFO18E1_inst (
|
|
// Read Data: 32-bit (each) output: Read output data
|
|
.DO(DO), // 32-bit output: data output
|
|
.DOP(DOP), // 4-bit output: parity data output
|
|
// Status: 1-bit (each) output: Flags and other FIFO status outputs
|
|
.ALMOSTEMPTY(ALMOSTEMPTY), // 1-bit output: almost empty output flag
|
|
.ALMOSTFULL(ALMOSTFULL), // 1-bit output: almost full output flag
|
|
.EMPTY(EMPTY), // 1-bit output: empty output flag
|
|
.FULL(FULL), // 1-bit output: full output flag
|
|
.RDCOUNT(RDCOUNT), // 12-bit output: read count output
|
|
.RDERR(RDERR), // 1-bit output: read error output
|
|
.WRCOUNT(WRCOUNT), // 12-bit output: write count output
|
|
.WRERR(WRERR), // 1-bit output: write error
|
|
// Read Control Signals: 1-bit (each) input: Read clock, enable and reset input signals
|
|
.RDCLK(RDCLK), // 1-bit input: read clock input
|
|
.RDEN(RDEN), // 1-bit input: read enable input
|
|
.REGCE(REGCE), // 1-bit input: clock enable input
|
|
.RST(RST), // 1-bit input: reset input
|
|
.RSTREG(RSTREG), // 1-bit input: output register set/reset
|
|
// Write Control Signals: 1-bit (each) input: Write clock and enable input signals
|
|
.WRCLK(WRCLK), // 1-bit input: write clock input
|
|
.WREN(WREN), // 1-bit input: write enable input
|
|
// Write Data: 32-bit (each) input: Write input data
|
|
.DI(DI), // 32-bit input: data input
|
|
.DIP(DIP) // 4-bit input: parity input
|
|
);
|
|
|
|
// End of FIFO18E1_inst instantiation
|
|
</Template>
|
|
<Template label="36KB FIFO (First In, First Out) Block RAM Memory (FIFO36E1)" treetype="template">
|
|
// FIFO36E1 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FIFO36E1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FIFO36E1: 36KB FIFO (First In, First Out) Block RAM Memory
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FIFO36E1 #(
|
|
.ALMOST_EMPTY_OFFSET(13'h0080), // Sets the almost empty threshold
|
|
.ALMOST_FULL_OFFSET(13'h0080), // Sets almost full threshold
|
|
.DATA_WIDTH(4), // Sets data width to 4, 9, 18, 36, or 72
|
|
.DO_REG(1), // Enable output register (0 or 1) Must be 1 if EN_SYN = FALSE
|
|
.EN_ECC_READ("FALSE"), // Enable ECC decoder, TRUE or FALSE
|
|
.EN_ECC_WRITE("FALSE"), // Enable ECC encoder, TRUE or FALSE
|
|
.EN_SYN("FALSE"), // Specifies FIFO as Asynchronous (FALSE) or Synchronous (TRUE)
|
|
.FIFO_MODE("FIFO36"), // Sets mode to FIFO36 or FIFO36_72
|
|
.FIRST_WORD_FALL_THROUGH("FALSE"), // Sets the FIFO FWFT to TRUE or FALSE
|
|
.INIT(72'h000000000000000000), // Initial values on output port
|
|
.SRVAL(72'h000000000000000000) // Set/Reset value for output port
|
|
)
|
|
FIFO36E1_inst (
|
|
// ECC Signals: 1-bit (each) output: Error Correction Circuitry ports
|
|
.DBITERR(DBITERR), // 1-bit output: double bit error status output
|
|
.ECCPARITY(ECCPARITY), // 8-bit output: generated error correction parity
|
|
.SBITERR(SBITERR), // 1-bit output: single bit error status output
|
|
// Read Data: 64-bit (each) output: Read output data
|
|
.DO(DO), // 64-bit output: data output
|
|
.DOP(DOP), // 8-bit output: parity data output
|
|
// Status: 1-bit (each) output: Flags and other FIFO status outputs
|
|
.ALMOSTEMPTY(ALMOSTEMPTY), // 1-bit output: almost empty output flag
|
|
.ALMOSTFULL(ALMOSTFULL), // 1-bit output: almost full output flag
|
|
.EMPTY(EMPTY), // 1-bit output: empty output flag
|
|
.FULL(FULL), // 1-bit output: full output flag
|
|
.RDCOUNT(RDCOUNT), // 13-bit output: read count output
|
|
.RDERR(RDERR), // 1-bit output: read error output
|
|
.WRCOUNT(WRCOUNT), // 13-bit output: write count output
|
|
.WRERR(WRERR), // 1-bit output: write error
|
|
// ECC Signals: 1-bit (each) input: Error Correction Circuitry ports
|
|
.INJECTDBITERR(INJECTDBITERR), // 1-bit input: Inject a double bit error
|
|
.INJECTSBITERR(INJECTSBITERR),
|
|
// Read Control Signals: 1-bit (each) input: Read clock, enable and reset input signals
|
|
.RDCLK(RDCLK), // 1-bit input: read clock input
|
|
.RDEN(RDEN), // 1-bit input: read enable input
|
|
.REGCE(REGCE), // 1-bit input: clock enable input
|
|
.RST(RST), // 1-bit input: reset input
|
|
.RSTREG(RSTREG), // 1-bit input: output register set/reset
|
|
// Write Control Signals: 1-bit (each) input: Write clock and enable input signals
|
|
.WRCLK(WRCLK), // 1-bit input: write clock input
|
|
.WREN(WREN), // 1-bit input: write enable input
|
|
// Write Data: 64-bit (each) input: Write input data
|
|
.DI(DI), // 64-bit input: data input
|
|
.DIP(DIP) // 8-bit input: parity input
|
|
);
|
|
|
|
// End of FIFO36E1_inst instantiation
|
|
</Template>
|
|
<Template label="18K-bit Configurable Synchronous Block RAM (RAMB18E1)" treetype="template">
|
|
// RAMB18E1 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB18E1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB18E1: 18K-bit Configurable Synchronous Block RAM
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB18E1 #(
|
|
// Colision check: Values ("ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE")
|
|
.SIM_COLLISION_CHECK("ALL"),
|
|
// DOA_REG, DOB_REG: Optional output register (0 or 1)
|
|
.DOA_REG(0),
|
|
.DOB_REG(0),
|
|
// INITP_00 to INITP_07: Initial contents of parity memory array
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// INIT_00 to INIT_3F: Initial contents of data memory array
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// INIT_A, INIT_B: Initial values on output ports
|
|
.INIT_A(18'h00000),
|
|
.INIT_B(18'h00000),
|
|
.INIT_FILE("NONE"), // RAM init file
|
|
.RAM_MODE("TDP"), // "SDP" or "TDP"
|
|
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), // "PERFORMANCE" or
|
|
// "DELAYED_WRITE"
|
|
// READ_WIDTH_A/B, WRITE_WIDTH_A/B: Read/write width per port
|
|
.READ_WIDTH_A(0), // 0,1,2,4,9,18,36
|
|
.READ_WIDTH_B(0), // 0,1,2,4,9,18
|
|
.WRITE_WIDTH_A(0), // 0,1,2,4,9,18
|
|
.WRITE_WIDTH_B(0), // 0,1,2,4,9,18,36
|
|
// RSTREG_PRIORITY_A, RSTREG_PRIORITY_B: Reset or enable priority ("RSTREG" or "REGCE")
|
|
.RSTREG_PRIORITY_A("RSTREG"),
|
|
.RSTREG_PRIORITY_B("RSTREG"),
|
|
// SRVAL_A, SRVAL_B: Set/reset value for output
|
|
.SRVAL_A(18'h00000),
|
|
.SRVAL_B(18'h00000),
|
|
// WriteMode: Value on output upon a write ("WRITE_FIRST", "READ_FIRST", or "NO_CHANGE")
|
|
.WRITE_MODE_A("WRITE_FIRST"),
|
|
.WRITE_MODE_B("WRITE_FIRST")
|
|
)
|
|
RAMB18E1_inst (
|
|
// Port A Data: 16-bit (each) output: Port A data
|
|
.DOADO(DOADO), // 16-bit output: A port data/LSB data output
|
|
.DOPADOP(DOPADOP), // 2-bit output: A port parity/LSB parity output
|
|
// Port B Data: 16-bit (each) output: Port B data
|
|
.DOBDO(DOBDO), // 16-bit output: B port data/MSB data output
|
|
.DOPBDOP(DOPBDOP), // 2-bit output: B port parity/MSB parity output
|
|
// Port A Address/Control Signals: 14-bit (each) input: Port A address and control signals (read port
|
|
// when RAM_MODE="SDP")
|
|
.ADDRARDADDR(ADDRARDADDR), // 14-bit input: A port address/Read address input
|
|
.CLKARDCLK(CLKARDCLK), // 1-bit input: A port clock/Read clock input
|
|
.ENARDEN(ENARDEN), // 1-bit input: A port enable/Read enable input
|
|
.REGCEAREGCE(REGCEAREGCE), // 1-bit input: A port register enable/Register enable input
|
|
.RSTRAMARSTRAM(RSTRAMARSTRAM), // 1-bit input: A port set/reset input
|
|
.RSTREGARSTREG(RSTREGARSTREG), // 1-bit input: A port register set/reset input
|
|
.WEA(WEA), // 2-bit input: A port write enable input
|
|
// Port A Data: 16-bit (each) input: Port A data
|
|
.DIADI(DIADI), // 16-bit input: A port data/LSB data input
|
|
.DIPADIP(DIPADIP), // 2-bit input: A port parity/LSB parity input
|
|
// Port B Address/Control Signals: 14-bit (each) input: Port B address and control signals (write port
|
|
// when RAM_MODE="SDP")
|
|
.ADDRBWRADDR(ADDRBWRADDR), // 14-bit input: B port address/Write address input
|
|
.CLKBWRCLK(CLKBWRCLK), // 1-bit input: B port clock/Write clock input
|
|
.ENBWREN(ENBWREN), // 1-bit input: B port enable/Write enable input
|
|
.REGCEB(REGCEB), // 1-bit input: B port register enable input
|
|
.RSTRAMB(RSTRAMB), // 1-bit input: B port set/reset input
|
|
.RSTREGB(RSTREGB), // 1-bit input: B port register set/reset input
|
|
.WEBWE(WEBWE), // 4-bit input: B port write enable/Write enable input
|
|
// Port B Data: 16-bit (each) input: Port B data
|
|
.DIBDI(DIBDI), // 16-bit input: B port data/MSB data input
|
|
.DIPBDIP(DIPBDIP) // 2-bit input: B port parity/MSB parity input
|
|
);
|
|
|
|
// End of RAMB18E1_inst instantiation
|
|
</Template>
|
|
<Template label="36K-bit Configurable Synchronous Block RAM (RAMB36E1)" treetype="template">
|
|
// RAMB36E1 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAMB36E1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAMB36E1: 36K-bit Configurable Synchronous Block RAM
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAMB36E1 #(
|
|
// Colision check: Values ("ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE")
|
|
.SIM_COLLISION_CHECK("ALL"),
|
|
// DOA_REG, DOB_REG: Optional output register (0 or 1)
|
|
.DOA_REG(0),
|
|
.DOB_REG(0),
|
|
// Error Correction Circuitry (ECC): Encoder/decoder enable (TRUE/FALSE)
|
|
.EN_ECC_READ("FALSE"),
|
|
.EN_ECC_WRITE("FALSE"),
|
|
// INITP_00 to INITP_0F: Initial contents of the parity memory array
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// INIT_00 to INIT_7F: Initial contents of the data memory array
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
// INIT_A, INIT_B: Initial values on output ports
|
|
.INIT_A(36'h000000000),
|
|
.INIT_B(36'h000000000),
|
|
.INIT_FILE("NONE"), // RAM initialization
|
|
// file
|
|
// RAM_EXTENSION_A, RAM_EXTENSION_B: Selects cascade mode ("UPPER", "LOWER", or "NONE")
|
|
.RAM_EXTENSION_A("NONE"),
|
|
.RAM_EXTENSION_B("NONE"),
|
|
.RAM_MODE("TDP"), // "SDP" or "TDP"
|
|
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"), // "PERFORMANCE" or
|
|
// "DELAYED_WRITE"
|
|
// READ_WIDTH_A/B, WRITE_WIDTH_A/B: Read/write width per port
|
|
.READ_WIDTH_A(0), // 0, 1, 2, 4, 9, 18,
|
|
// 36, or 72
|
|
.READ_WIDTH_B(0), // 0, 1, 2, 4, 9, 18,
|
|
// or 36
|
|
.WRITE_WIDTH_A(0), // 0, 1, 2, 4, 9, 18,
|
|
// or 36
|
|
.WRITE_WIDTH_B(0), // 0, 1, 2, 4, 9, 18,
|
|
// 36, or 72
|
|
// RSTREG_PRIORITY_A, RSTREG_PRIORITY_B: Reset or enable priority ("RSTREG" or "REGCE")
|
|
.RSTREG_PRIORITY_A("RSTREG"),
|
|
.RSTREG_PRIORITY_B("RSTREG"),
|
|
// SRVAL_A, SRVAL_B: Set/reset value for output
|
|
.SRVAL_A(36'h000000000),
|
|
.SRVAL_B(36'h000000000),
|
|
// WriteMode: Value on output upon a write ("WRITE_FIRST", "READ_FIRST", or "NO_CHANGE")
|
|
.WRITE_MODE_A("WRITE_FIRST"),
|
|
.WRITE_MODE_B("WRITE_FIRST")
|
|
)
|
|
RAMB36E1_inst (
|
|
// Cascade Signals: 1-bit (each) output: BRAM cascade ports (to create 64kx1)
|
|
.CASCADEOUTA(CASCADEOUTA), // 1-bit output: A port cascade output
|
|
.CASCADEOUTB(CASCADEOUTB), // 1-bit output: B port cascade output
|
|
// ECC Signals: 1-bit (each) output: Error Correction Circuitry ports
|
|
.DBITERR(DBITERR), // 1-bit output: double bit error status output
|
|
.ECCPARITY(ECCPARITY), // 8-bit output: generated error correction parity
|
|
.RDADDRECC(RDADDRECC), // 9-bit output: ECC read address
|
|
.SBITERR(SBITERR), // 1-bit output: Single bit error status output
|
|
// Port A Data: 32-bit (each) output: Port A data
|
|
.DOADO(DOADO), // 32-bit output: A port data/LSB data output
|
|
.DOPADOP(DOPADOP), // 4-bit output: A port parity/LSB parity output
|
|
// Port B Data: 32-bit (each) output: Port B data
|
|
.DOBDO(DOBDO), // 32-bit output: B port data/MSB data output
|
|
.DOPBDOP(DOPBDOP), // 4-bit output: B port parity/MSB parity output
|
|
// Cascade Signals: 1-bit (each) input: BRAM cascade ports (to create 64kx1)
|
|
.CASCADEINA(CASCADEINA), // 1-bit input: A port cascade input
|
|
.CASCADEINB(CASCADEINB), // 1-bit input: B port cascade input
|
|
// ECC Signals: 1-bit (each) input: Error Correction Circuitry ports
|
|
.INJECTDBITERR(INJECTDBITERR), // 1-bit input: Inject a double bit error
|
|
.INJECTSBITERR(INJECTSBITERR), // 1-bit input: Inject a single bit error
|
|
// Port A Address/Control Signals: 16-bit (each) input: Port A address and control signals (read port
|
|
// when RAM_MODE="SDP")
|
|
.ADDRARDADDR(ADDRARDADDR), // 16-bit input: A port address/Read address input
|
|
.CLKARDCLK(CLKARDCLK), // 1-bit input: A port clock/Read clock input
|
|
.ENARDEN(ENARDEN), // 1-bit input: A port enable/Read enable input
|
|
.REGCEAREGCE(REGCEAREGCE), // 1-bit input: A port register enable/Register enable input
|
|
.RSTRAMARSTRAM(RSTRAMARSTRAM), // 1-bit input: A port set/reset input
|
|
.RSTREGARSTREG(RSTREGARSTREG), // 1-bit input: A port register set/reset input
|
|
.WEA(WEA), // 4-bit input: A port write enable input
|
|
// Port A Data: 32-bit (each) input: Port A data
|
|
.DIADI(DIADI), // 32-bit input: A port data/LSB data input
|
|
.DIPADIP(DIPADIP), // 4-bit input: A port parity/LSB parity input
|
|
// Port B Address/Control Signals: 16-bit (each) input: Port B address and control signals (write port
|
|
// when RAM_MODE="SDP")
|
|
.ADDRBWRADDR(ADDRBWRADDR), // 16-bit input: B port address/Write address input
|
|
.CLKBWRCLK(CLKBWRCLK), // 1-bit input: B port clock/Write clock input
|
|
.ENBWREN(ENBWREN), // 1-bit input: B port enable/Write enable input
|
|
.REGCEB(REGCEB), // 1-bit input: B port register enable input
|
|
.RSTRAMB(RSTRAMB), // 1-bit input: B port set/reset input
|
|
.RSTREGB(RSTREGB), // 1-bit input: B port register set/reset input
|
|
.WEBWE(WEBWE), // 8-bit input: B port write enable/Write enable input
|
|
// Port B Data: 32-bit (each) input: Port B data
|
|
.DIBDI(DIBDI), // 32-bit input: B port data/MSB data input
|
|
.DIPBDIP(DIPBDIP) // 4-bit input: B port parity/MSB parity input
|
|
);
|
|
|
|
// End of RAMB36E1_inst instantiation
|
|
</Template>
|
|
<SubFolder label="Distributed ROM" treetype="folder">
|
|
<Template label="32 X 1 (ROM32X1)" treetype="template">
|
|
// ROM32X1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ROM32X1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ROM32X1: 32 x 1 Asynchronous Distributed (LUT) ROM
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ROM32X1 #(
|
|
.INIT(32'h00000000) // Contents of ROM
|
|
) ROM32X1_inst (
|
|
.O(O), // ROM output
|
|
.A0(A0), // ROM address[0]
|
|
.A1(A1), // ROM address[1]
|
|
.A2(A2), // ROM address[2]
|
|
.A3(A3), // ROM address[3]
|
|
.A4(A4) // ROM address[4]
|
|
);
|
|
|
|
// End of ROM32X1_inst instantiation
|
|
</Template>
|
|
<Template label="64 X 1 (ROM64X1)" treetype="template">
|
|
// ROM64X1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ROM64X1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ROM64X1: 64 x 1 Asynchronous Distributed (LUT) ROM
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ROM64X1 #(
|
|
.INIT(64'h0000000000000000) // Contents of ROM
|
|
) ROM64X1_inst (
|
|
.O(O), // ROM output
|
|
.A0(A0), // ROM address[0]
|
|
.A1(A1), // ROM address[1]
|
|
.A2(A2), // ROM address[2]
|
|
.A3(A3), // ROM address[3]
|
|
.A4(A4), // ROM address[4]
|
|
.A5(A5) // ROM address[5]
|
|
);
|
|
|
|
// End of ROM64X1_inst instantiation
|
|
</Template>
|
|
<Template label="128 X 1 (ROM128X1)" treetype="template">
|
|
// ROM128X1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ROM128X1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ROM128X1: 128 x 1 Asynchronous Distributed (LUT) ROM
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ROM128X1 #(
|
|
.INIT(128'h00000000000000000000000000000000) // Contents of ROM
|
|
) ROM128X1_inst (
|
|
.O(O), // ROM output
|
|
.A0(A0), // ROM address[0]
|
|
.A1(A1), // ROM address[1]
|
|
.A2(A2), // ROM address[2]
|
|
.A3(A3), // ROM address[3]
|
|
.A4(A4), // ROM address[4]
|
|
.A5(A5), // ROM address[5]
|
|
.A6(A6) // ROM address[6]
|
|
);
|
|
|
|
// End of ROM128X1_inst instantiation
|
|
</Template>
|
|
<Template label="256 X 1 (ROM256X1)" treetype="template">
|
|
// ROM256X1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ROM256X1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ROM256X1: 256 x 1 Asynchronous Distributed (LUT) ROM
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ROM256X1 #(
|
|
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000) // Contents of ROM
|
|
) ROM256X1_inst (
|
|
.O(O), // ROM output
|
|
.A0(A0), // ROM address[0]
|
|
.A1(A1), // ROM address[1]
|
|
.A2(A2), // ROM address[2]
|
|
.A3(A3), // ROM address[3]
|
|
.A4(A4), // ROM address[4]
|
|
.A5(A5), // ROM address[5]
|
|
.A6(A6), // ROM address[6]
|
|
.A7(A7) // ROM address[7]
|
|
);
|
|
|
|
// End of ROM256X1_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Distributed RAM" treetype="folder">
|
|
<SubFolder label="Single-Port" treetype="folder">
|
|
<SubFolder label="32 Deep (5-bit address)" treetype="folder">
|
|
<Template label="32 x 1 posedge write (RAM32X1S)" treetype="template">
|
|
// RAM32X1S : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM32X1S_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM32X1S: 32 x 1 posedge write distributed (LUT) RAM
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM32X1S #(
|
|
.INIT(32'h00000000) // Initial contents of RAM
|
|
) RAM32X1S_inst (
|
|
.O(O), // RAM output
|
|
.A0(A0), // RAM address[0] input
|
|
.A1(A1), // RAM address[1] input
|
|
.A2(A2), // RAM address[2] input
|
|
.A3(A3), // RAM address[3] input
|
|
.A4(A4), // RAM address[4] input
|
|
.D(D), // RAM data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM32X1S_inst instantiation
|
|
</Template>
|
|
<Template label="32 x 1 negedge write (RAM32X1S_1)" treetype="template">
|
|
// RAM32X1S_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM32X1S_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM32X1S_1: 32 x 1 negedge write distributed (LUT) RAM
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM32X1S_1 #(
|
|
.INIT(32'h00000000) // Initial contents of RAM
|
|
)RAM32X1S_1_inst (
|
|
.O(O), // RAM output
|
|
.A0(A0), // RAM address[0] input
|
|
.A1(A1), // RAM address[1] input
|
|
.A2(A2), // RAM address[2] input
|
|
.A3(A3), // RAM address[3] input
|
|
.A4(A4), // RAM address[4] input
|
|
.D(D), // RAM data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM32X1S_1_inst instantiation
|
|
</Template>
|
|
<Template label="32 x 2 posedge write (RAM32X2S)" treetype="template">
|
|
// RAM32X2S : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM16X2S_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM32X2S: 32 x 2 posedge write distributed (LUT) RAM
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM32X2S #(
|
|
.INIT_00(32'h00000000), // INIT for bit 0 of RAM
|
|
.INIT_01(32'h00000000) // INIT for bit 1 of RAM
|
|
) RAM32X2S_inst (
|
|
.O0(O0), // RAM data[0] output
|
|
.O1(O1), // RAM data[1] output
|
|
.A0(A0), // RAM address[0] input
|
|
.A1(A1), // RAM address[1] input
|
|
.A2(A2), // RAM address[2] input
|
|
.A3(A3), // RAM address[3] input
|
|
.A4(A4), // RAM address[4] input
|
|
.D0(D0), // RAM data[0] input
|
|
.D1(D1), // RAM data[1] input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM32X2S_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="64 Deep (6-bit address)" treetype="folder">
|
|
<Template label="64 X 1 posedge write (RAM64X1S)" treetype="template">
|
|
// RAM64X1S : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM64X1S_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM64X1S: 64 x 1 positive edge write, asynchronous read single-port distributed RAM
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM64X1S #(
|
|
.INIT(64'h0000000000000000) // Initial contents of RAM
|
|
) RAM64X1S_inst (
|
|
.O(O), // 1-bit data output
|
|
.A0(A0), // Address[0] input bit
|
|
.A1(A1), // Address[1] input bit
|
|
.A2(A2), // Address[2] input bit
|
|
.A3(A3), // Address[3] input bit
|
|
.A4(A4), // Address[4] input bit
|
|
.A5(A5), // Address[5] input bit
|
|
.D(D), // 1-bit data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM64X1S_inst instantiation
|
|
</Template>
|
|
<Template label="64 X 1 negedge write (RAM64X1S_1)" treetype="template">
|
|
// RAM64X1S_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM64X1S_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM64X1S_1: 64 x 1 negative edge write, asynchronous read single-port distributed RAM
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM64X1S_1 #(
|
|
.INIT(64'h0000000000000000) // Initial contents of RAM
|
|
) RAM64X1S_1_inst (
|
|
.O(O), // 1-bit data output
|
|
.A0(A0), // Address[0] input bit
|
|
.A1(A1), // Address[1] input bit
|
|
.A2(A2), // Address[2] input bit
|
|
.A3(A3), // Address[3] input bit
|
|
.A4(A4), // Address[4] input bit
|
|
.A5(A5), // Address[5] input bit
|
|
.D(D), // 1-bit data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM64X1S_1_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="128 Deep (7-bit address)" treetype="folder">
|
|
<Template label="128 X 1 posedge write (RAM128X1S)" treetype="template">
|
|
// RAM128X1S : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM128X1S_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM128X1S: 128 x 1 positive edge write, asynchronous read single-port distributed RAM
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM128X1S #(
|
|
.INIT(128'h00000000000000000000000000000000) // Initial contents of RAM
|
|
) RAM128X1S_inst (
|
|
.O(O), // 1-bit data output
|
|
.A0(A0), // Address[0] input bit
|
|
.A1(A1), // Address[1] input bit
|
|
.A2(A2), // Address[2] input bit
|
|
.A3(A3), // Address[3] input bit
|
|
.A4(A4), // Address[4] input bit
|
|
.A5(A5), // Address[5] input bit
|
|
.A6(A6), // Address[6] input bit
|
|
.D(D), // 1-bit data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM128X1S_inst instantiation
|
|
</Template>
|
|
<Template label="128 X 1 negedge write (RAM128X1S_1)" treetype="template">
|
|
// RAM128X1S_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM128X1S_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM128X1S_1: 128 x 1 negative edge write, asynchronous read single-port distributed RAM
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM128X1S_1 #(
|
|
.INIT(128'h00000000000000000000000000000000) // Initial contents of RAM
|
|
) RAM128X1S_1_inst (
|
|
.O(O), // 1-bit data output
|
|
.A0(A0), // Address[0] input bit
|
|
.A1(A1), // Address[1] input bit
|
|
.A2(A2), // Address[2] input bit
|
|
.A3(A3), // Address[3] input bit
|
|
.A4(A4), // Address[4] input bit
|
|
.A5(A5), // Address[5] input bit
|
|
.A6(A6), // Address[6] input bit
|
|
.D(D), // 1-bit data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM128X1S_1_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="256 Deep (8-bit address)" treetype="folder">
|
|
<Template label="256 X 1 posedge write (RAM256X1S)" treetype="template">
|
|
// RAM256X1S : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM256X1S_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM256X1S: 256-deep by 1-wide positive edge write, asynchronous read
|
|
// single-port distributed LUT RAM
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM256X1S #(
|
|
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAM256X1S_inst (
|
|
.O(O), // Read/write port 1-bit output
|
|
.A(A), // Read/write port 8-bit address input
|
|
.WE(WE), // Write enable input
|
|
.WCLK(WCLK), // Write clock input
|
|
.D(D) // RAM data input
|
|
);
|
|
|
|
// End of RAM256X1S_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Dual-Port" treetype="folder">
|
|
<Template label="32 X 1 posedge write (RAM32X1D)" treetype="template">
|
|
// RAM32X1D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM32X1D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM32X1D: 32 x 1 positive edge write, asynchronous read dual-port distributed RAM
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM32X1D #(
|
|
.INIT(32'h00000000) // Initial contents of RAM
|
|
) RAM32X1D_inst (
|
|
.DPO(DPO), // Read-only 1-bit data output
|
|
.SPO(SPO), // Rw/ 1-bit data output
|
|
.A0(A0), // Rw/ address[0] input bit
|
|
.A1(A1), // Rw/ address[1] input bit
|
|
.A2(A2), // Rw/ address[2] input bit
|
|
.A3(A3), // Rw/ address[3] input bit
|
|
.A4(A4), // Rw/ address[4] input bit
|
|
.D(D), // Write 1-bit data input
|
|
.DPRA0(DPRA0), // Read-only address[0] input bit
|
|
.DPRA1(DPRA1), // Read-only address[1] input bit
|
|
.DPRA2(DPRA2), // Read-only address[2] input bit
|
|
.DPRA3(DPRA3), // Read-only address[3] input bit
|
|
.DPRA4(DPRA4), // Read-only address[4] input bit
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM32X1D_inst instantiation
|
|
</Template>
|
|
<Template label="32 X 1 negedge write (RAM32X1D_1)" treetype="template">
|
|
// RAM32X1D_1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM32X1D_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM32X1D_1: 32 x 1 negative edge write, asynchronous read dual-port distributed RAM
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM32X1D_1 #(
|
|
.INIT(32'h00000000) // Initial contents of RAM
|
|
) RAM32X1D_1_inst (
|
|
.DPO(DPO), // Read-only 1-bit data output
|
|
.SPO(SPO), // Rw/ 1-bit data output
|
|
.A0(A0), // Rw/ address[0] input bit
|
|
.A1(A1), // Rw/ address[1] input bit
|
|
.A2(A2), // Rw/ address[2] input bit
|
|
.A3(A3), // Rw/ address[3] input bit
|
|
.A4(A4), // Rw/ address[4] input bit
|
|
.D(D), // Write 1-bit data input
|
|
.DPRA0(DPRA0), // Read-only address[0] input bit
|
|
.DPRA1(DPRA1), // Read-only address[1] input bit
|
|
.DPRA2(DPRA2), // Read-only address[2] input bit
|
|
.DPRA3(DPRA3), // Read-only address[3] input bit
|
|
.DPRA4(DPRA4), // Read-only address[4] input bit
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM32X1D_1_inst instantiation
|
|
</Template>
|
|
<Template label="64 X 1 posedge write (RAM64X1D)" treetype="template">
|
|
// RAM64X1D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM64X1D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM64X1D: 64 x 1 positive edge write, asynchronous read dual-port distributed RAM
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM64X1D #(
|
|
.INIT(64'h0000000000000000) // Initial contents of RAM
|
|
) RAM64X1D_inst (
|
|
.DPO(DPO), // Read-only 1-bit data output
|
|
.SPO(SPO), // Rw/ 1-bit data output
|
|
.A0(A0), // Rw/ address[0] input bit
|
|
.A1(A1), // Rw/ address[1] input bit
|
|
.A2(A2), // Rw/ address[2] input bit
|
|
.A3(A3), // Rw/ address[3] input bit
|
|
.A4(A4), // Rw/ address[4] input bit
|
|
.A5(A5), // Rw/ address[5] input bit
|
|
.D(D), // Write 1-bit data input
|
|
.DPRA0(DPRA0), // Read-only address[0] input bit
|
|
.DPRA1(DPRA1), // Read-only address[1] input bit
|
|
.DPRA2(DPRA2), // Read-only address[2] input bit
|
|
.DPRA3(DPRA3), // Read-only address[3] input bit
|
|
.DPRA4(DPRA4), // Read-only address[4] input bit
|
|
.DPRA5(DPRA5), // Read-only address[5] input bit
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM64X1D_inst instantiation
|
|
</Template>
|
|
<Template label="128 X 1 posedge write (RAM128X1D)" treetype="template">
|
|
// RAM128X1D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM128X1D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM128X1D: 128-deep by 1-wide positive edge write, asynchronous read
|
|
// dual-port distributed LUT RAM
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM128X1D #(
|
|
.INIT(128'h00000000000000000000000000000000)
|
|
) RAM128X1D_inst (
|
|
.DPO(DPO), // Read port 1-bit output
|
|
.SPO(SPO), // Read/write port 1-bit output
|
|
.A(A), // Read/write port 7-bit address input
|
|
.D(D), // RAM data input
|
|
.DPRA(DPRA), // Read port 7-bit address input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM128X1D_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Multi-Port" treetype="folder">
|
|
<Template label="32 X 8 (RAM32M)" treetype="template">
|
|
// RAM32M : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM32M_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM32M: 32-deep by 8-wide Multi Port LUT RAM
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM32M #(
|
|
.INIT_A(64'h0000000000000000), // Initial contents of A Port
|
|
.INIT_B(64'h0000000000000000), // Initial contents of B Port
|
|
.INIT_C(64'h0000000000000000), // Initial contents of C Port
|
|
.INIT_D(64'h0000000000000000) // Initial contents of D Port
|
|
) RAM32M_inst (
|
|
.DOA(DOA), // Read port A 2-bit output
|
|
.DOB(DOB), // Read port B 2-bit output
|
|
.DOC(DOC), // Read port C 2-bit output
|
|
.DOD(DOD), // Read/write port D 2-bit output
|
|
.ADDRA(ADDRA), // Read port A 5-bit address input
|
|
.ADDRB(ADDRB), // Read port B 5-bit address input
|
|
.ADDRC(ADDRC), // Read port C 5-bit address input
|
|
.ADDRD(ADDRD), // Read/write port D 5-bit address input
|
|
.DIA(DIA), // RAM 2-bit data write input addressed by ADDRD,
|
|
// read addressed by ADDRA
|
|
.DIB(DIB), // RAM 2-bit data write input addressed by ADDRD,
|
|
// read addressed by ADDRB
|
|
.DIC(DIC), // RAM 2-bit data write input addressed by ADDRD,
|
|
// read addressed by ADDRC
|
|
.DID(DID), // RAM 2-bit data write input addressed by ADDRD,
|
|
// read addressed by ADDRD
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM32M_inst instantiation
|
|
</Template>
|
|
<Template label="64 X 4 (RAM64M)" treetype="template">
|
|
// RAM64M : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM64M_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM64M: 64-deep by 4-wide Multi Port LUT RAM
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM64M #(
|
|
.INIT_A(64'h0000000000000000), // Initial contents of A Port
|
|
.INIT_B(64'h0000000000000000), // Initial contents of B Port
|
|
.INIT_C(64'h0000000000000000), // Initial contents of C Port
|
|
.INIT_D(64'h0000000000000000) // Initial contents of D Port
|
|
) RAM64M_inst (
|
|
.DOA(DOA), // Read port A 1-bit output
|
|
.DOB(DOB), // Read port B 1-bit output
|
|
.DOC(DOC), // Read port C 1-bit output
|
|
.DOD(DOD), // Read/write port D 1-bit output
|
|
.DIA(DIA), // RAM 1-bit data write input addressed by ADDRD,
|
|
// read addressed by ADDRA
|
|
.DIB(DIB), // RAM 1-bit data write input addressed by ADDRD,
|
|
// read addressed by ADDRB
|
|
.DIC(DIC), // RAM 1-bit data write input addressed by ADDRD,
|
|
// read addressed by ADDRC
|
|
.DID(DID), // RAM 1-bit data write input addressed by ADDRD,
|
|
// read addressed by ADDRD
|
|
.ADDRA(ADDRA), // Read port A 6-bit address input
|
|
.ADDRB(ADDRB), // Read port B 6-bit address input
|
|
.ADDRC(ADDRC), // Read port C 6-bit address input
|
|
.ADDRD(ADDRD), // Read/write port D 6-bit address input
|
|
.WE(WE), // Write enable input
|
|
.WCLK(WCLK) // Write clock input
|
|
);
|
|
|
|
// End of RAM64M_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Advanced" treetype="folder">
|
|
<Template label="System Monitor (SYSMON)" treetype="template">
|
|
// SYSMON : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SYSMON_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SYSMON: System Monitor
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SYSMON #(
|
|
// INIT_40 - INIT_42: System Monitor configuration registers
|
|
.INIT_40(16'h0000),
|
|
.INIT_41(16'h0000),
|
|
.INIT_42(16'h0800),
|
|
// INIT_43 - INIT_47: System Monitor Test registers (do not edit)
|
|
.INIT_43(16'h0000),
|
|
.INIT_44(16'h0000),
|
|
.INIT_45(16'h0000),
|
|
.INIT_46(16'h0000),
|
|
.INIT_47(16'h0000),
|
|
// INIT_48 - INIT_4F: Sequence registers for the Channel Sequencer
|
|
.INIT_48(16'h0000),
|
|
.INIT_49(16'h0000),
|
|
.INIT_4A(16'h0000),
|
|
.INIT_4B(16'h0000),
|
|
.INIT_4C(16'h0000),
|
|
.INIT_4D(16'h0000),
|
|
.INIT_4E(16'h0000),
|
|
.INIT_4F(16'h0000),
|
|
// INIT_50 - INIT_57: Alarm threshold registers
|
|
.INIT_50(16'h0000),
|
|
.INIT_51(16'h0000),
|
|
.INIT_52(16'h0000),
|
|
.INIT_53(16'h0000),
|
|
.INIT_54(16'h0000),
|
|
.INIT_55(16'h0000),
|
|
.INIT_56(16'h0000),
|
|
.INIT_57(16'h0000),
|
|
// Simulation attributes: Set for proper simulation behavior
|
|
.SIM_DEVICE("VIRTEX5"), // Must be set to VIRTEX6
|
|
.SIM_MONITOR_FILE("design.txt") // Analog simulation data file name
|
|
)
|
|
SYSMON_inst (
|
|
// Alarm Ports: 3-bit (each) output: ALM, OT
|
|
.ALM(ALM), // 3-bit output: output alarm for temp, Vccint and Vccaux
|
|
.OT(OT), // 1-bit output: Over-Temperature alarm output
|
|
// DRP Ports: 16-bit (each) output: Dynamic Reconfiguration Ports
|
|
.DO(DO), // 16-bit output: DRP output data bus
|
|
.DRDY(DRDY), // 1-bit output: DRP data ready output signal
|
|
// Status Ports: 1-bit (each) output: SYSMON status ports
|
|
.BUSY(BUSY), // 1-bit output: ADC busy output
|
|
.CHANNEL(CHANNEL), // 5-bit output: Channel selection outputs
|
|
.EOC(EOC), // 1-bit output: End of Conversion output
|
|
.EOS(EOS), // 1-bit output: End of Sequence output
|
|
.JTAGBUSY(JTAGBUSY), // 1-bit output: JTAG DRP transaction in progress output
|
|
.JTAGLOCKED(JTAGLOCKED), // 1-bit output: JTAG requested DRP port lock output
|
|
.JTAGMODIFIED(JTAGMODIFIED), // 1-bit output: JTAG Write to the DRP has occurred output
|
|
// Auxiliary Analog-Input Pairs: 16-bit (each) input: VAUXP[15:0], VAUXN[15:0]
|
|
.VAUXN(VAUXN), // 16-bit input: N-side auxiliary analog input
|
|
.VAUXP(VAUXP), // 16-bit input: P-side auxiliary analog input
|
|
// Control and Clock Ports: 1-bit (each) input: Reset and Converstion Start
|
|
.CONVST(CONVST), // 1-bit input: Convert start input
|
|
.CONVSTCLK(CONVSTCLK), // 1-bit input: Convert start input
|
|
.RESET(RESET), // 1-bit input: Active-high reset input
|
|
// DRP Ports: 7-bit (each) input: Dynamic Reconfiguration Ports
|
|
.DADDR(DADDR), // 7-bit input: DRP input address bus
|
|
.DCLK(DCLK), // 1-bit input: DRP clock input
|
|
.DEN(DEN), // 1-bit input: DRP input enable signal
|
|
.DI(DI), // 16-bit input: DRP input data bus
|
|
.DWE(DWE), // 1-bit input: DRP write enable input
|
|
// Dedicated Analog Input Pair: 1-bit (each) input: VP/VN
|
|
.VN(VN), // 1-bit input: N-side analog input
|
|
.VP(VP) // 1-bit input: P-side analog input
|
|
);
|
|
|
|
// End of SYSMON_inst instantiation
|
|
</Template>
|
|
<Template label="System Monitor Simulation File" treetype="template">
|
|
// Must use valid headers on all columns
|
|
// Comments can be added to the stimulus file using '//'
|
|
|
|
TIME TEMP VCCAUX VCCINT VP VN VAUXP[0] VAUXN[0]
|
|
00000 45 2.5 1.0 0.5 0.0 0.7 0.0
|
|
05000 85 2.45 1.1 0.3 0.0 0.2 0.0
|
|
|
|
// Time stamp data is in nano seconds (ns)
|
|
// Temperature is recorded in C (degrees centigrade)
|
|
// All other channels are recorded as V (Volts)
|
|
// Valid column headers are:
|
|
// TIME, TEMP, VCCAUX, VCCINT, VP, VN,
|
|
// VAUXP[0], VAUXN[0],...............VAUXP[15], VAUXN[15]
|
|
// External analog inputs are differential so VP = 0.5 and VN = 0.0 the
|
|
// input on channel VP/VN in 0.5 - 0.0 = 0.5V
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Slice/CLB Primitives" treetype="folder">
|
|
<SubFolder label="MUXFx" treetype="folder">
|
|
<Template label="MUXF7" treetype="template">
|
|
// MUXF7 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF7_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF7: CLB MUX to tie two LUT6's together with general output
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF7 MUXF7_inst (
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie to LUT6 O6 pin)
|
|
.I1(I1), // Input (tie to LUT6 O6 pin)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF7_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF7_L" treetype="template">
|
|
// MUXF7_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF7_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF7_L: CLB MUX to tie two LUT6's together with local output
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF7_L MUXF7_L_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.I0(I0), // Input (tie to LUT6 O6 pin)
|
|
.I1(I1), // Input (tie to LUT6 O6 pin)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF7_L_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF7_D" treetype="template">
|
|
// MUXF7_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF7_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF7_D: CLB MUX to tie two LUT6's together with general and local outputs
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF7_D MUXF7_D_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie to LUT6 O6 pin)
|
|
.I1(I1), // Input (tie to LUT6 O6 pin)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF7_D_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF8" treetype="template">
|
|
// MUXF8 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF8_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF8: CLB MUX to tie two MUXF7's together with general output
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF8 MUXF8_inst (
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie to MUXF7 LO out)
|
|
.I1(I1), // Input (tie to MUXF7 LO out)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF8_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF8_L" treetype="template">
|
|
// MUXF8_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF8_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF8_L: CLB MUX to tie two MUXF7's together with local output
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF8_L MUXF8_L_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.I0(I0), // Input (tie to MUXF7 LO out)
|
|
.I1(I1), // Input (tie to MUXF7 LO out)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF8_L_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF8_D" treetype="template">
|
|
// MUXF8_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF8_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF8_D: CLB MUX to tie two MUXF7's together with general and local outputs
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF8_D MUXF8_D_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie to MUXF7 LO out)
|
|
.I1(I1), // Input (tie to MUXF7 LO out)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF8_D_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="LUTs" treetype="folder">
|
|
<SubFolder label="Info" treetype="folder">
|
|
<Template label="Info (LUT INIT)" treetype="template">
|
|
// The INIT parameter for the FPGA LUT primitive is what gives the LUT its
|
|
// logical value. By default this value is zero thus driving the output to a
|
|
// zero regardless of the input values (acting as a ground) however in most
|
|
// cases an new INIT value must be determined in order to specify the logic
|
|
// function for the LUT primitive. There are a few methods in which the LUT
|
|
// value can be determined and two of those methods will be discussed here.
|
|
//
|
|
// The Truth Table Method
|
|
// ----------------------
|
|
//
|
|
// A common method to determine the desired INIT value for a LUT is using a
|
|
// truth table. To do so, simply create a binary truth table of all possible
|
|
// inputs, specify the desired logic value of the output and then create the
|
|
// INIT string from those output values. An example is shown below:
|
|
//
|
|
// Example of determining an XOR INIT equation for a LUT4:
|
|
//
|
|
// _________________
|
|
// | I3 I2 I1 I0 | O |
|
|
// |-----------------|
|
|
// | 0 0 0 0 | 0 |\
|
|
// | 0 0 0 1 | 1 | \ = 4'b0110 = 4'h6 ---------------+
|
|
// | 0 0 1 0 | 1 | / |
|
|
// | 0 0 1 1 | 0 |/ |
|
|
// |-------------|---| |
|
|
// | 0 1 0 0 | 1 |\ |
|
|
// | 0 1 0 1 | 0 | \ = 4'b1001 = 4'h9 |
|
|
// | 0 1 1 0 | 0 | / |
|
|
// | 0 1 1 1 | 1 |/ |
|
|
// |-------------|---| INIT = 16'h6996
|
|
// | 1 0 0 0 | 1 |\ |
|
|
// | 1 0 0 1 | 0 | \ = 4'b0110 = 4'h9 |
|
|
// | 1 0 1 0 | 0 | / |
|
|
// | 1 0 1 1 | 1 |/ |
|
|
// |-------------|---| |
|
|
// | 1 1 0 0 | 0 |\ |
|
|
// | 1 1 0 1 | 1 | \ = 4'b1001 = 4'h6 ------------+
|
|
// | 1 1 1 0 | 1 | /
|
|
// | 1 1 1 1 | 0 |/
|
|
// -------------------
|
|
//
|
|
// Example of determining a 3-input AND gate:
|
|
//
|
|
// ______________
|
|
// | I2 I1 I0 | O |
|
|
// |--------------|
|
|
// | 0 0 0 | 0 |\
|
|
// | 0 0 1 | 0 | \ = 4'b0000 = 4'h0 --------------+
|
|
// | 0 1 0 | 0 | / |
|
|
// | 0 1 1 | 0 |/ |
|
|
// |----------|---| INIT = 8'h80
|
|
// | 1 0 0 | 0 |\ |
|
|
// | 1 0 1 | 0 | \ = 4'b1000 = 4'h8 -------------+
|
|
// | 1 1 0 | 0 | /
|
|
// | 1 1 1 | 1 |/
|
|
// ----------------
|
|
//
|
|
// The Equation Method
|
|
// -------------------
|
|
//
|
|
// Another method to determine the LUT value is to define parameters for each
|
|
// input to the LUT that correspond to their listed truth value and use those to
|
|
// build the logic equation you are after. This method is easier to understand
|
|
// once you have grasped the concept and more self-documenting that the above
|
|
// method however does require the code to first specify the appropriate
|
|
// parameters. See the example below.
|
|
//
|
|
// Example of specifying the equation (A and B) or (C and D) for a LUT4:
|
|
//
|
|
// The forllowing parameters are defined to allow for
|
|
// equation-based INIT specification.
|
|
parameter I0 = 16'haaaa;
|
|
parameter I1 = 16'hcccc;
|
|
parameter I2 = 16'hf0f0;
|
|
parameter I3 = 16'hff00;
|
|
|
|
// LUT4: 4-input Look-Up Table with general output
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT4 #(
|
|
.INIT((I0&I1)|(I2&I3)) // Specify LUT Contents
|
|
) LUT4_inst (
|
|
.O(O_LUT), // LUT general output
|
|
.I0(A), // LUT input
|
|
.I1(B), // LUT input
|
|
.I2(C), // LUT input
|
|
.I3(D) // LUT input
|
|
);
|
|
|
|
// End of LUT4_inst instantiation
|
|
|
|
// With the parameters specifying all possible cases for the truth table, a
|
|
// Verilog equation can be written to determine the end INIT value.
|
|
</Template>
|
|
<SubFolder label="INIT Parameters" treetype="folder">
|
|
<Template label="LUT1" treetype="template">
|
|
// The forllowing parameter is defined to allow for
|
|
// equation-based INIT specification for a LUT1.
|
|
parameter I0 = 2'b10;
|
|
</Template>
|
|
<Template label="LUT2" treetype="template">
|
|
// The forllowing parameters are defined to allow for
|
|
// equation-based INIT specification for a LUT2.
|
|
parameter I0 = 4'ha;
|
|
parameter I1 = 4'hc;
|
|
</Template>
|
|
<Template label="LUT3" treetype="template">
|
|
// The forllowing parameters are defined to allow for
|
|
// equation-based INIT specification for a LUT3.
|
|
parameter I0 = 8'haa;
|
|
parameter I1 = 8'hcc;
|
|
parameter I2 = 8'hf0;
|
|
</Template>
|
|
<Template label="LUT4" treetype="template">
|
|
// The forllowing parameters are defined to allow for
|
|
// equation-based INIT specification for a LUT4.
|
|
parameter I0 = 16'haaaa;
|
|
parameter I1 = 16'hcccc;
|
|
parameter I2 = 16'hf0f0;
|
|
parameter I3 = 16'hff00;
|
|
</Template>
|
|
<Template label="LUT5" treetype="template">
|
|
// The forllowing parameters are defined to allow for
|
|
// equation-based INIT specification for a LUT5.
|
|
parameter I0 = 32'haaaaaaaa;
|
|
parameter I1 = 32'hcccccccc;
|
|
parameter I2 = 32'hf0f0f0f0;
|
|
parameter I3 = 32'hff00ff00;
|
|
parameter I4 = 32'hffff0000;
|
|
</Template>
|
|
<Template label="LUT6" treetype="template">
|
|
// The forllowing parameters are defined to allow for
|
|
// equation-based INIT specification for a LUT6.
|
|
parameter I0 = 64'haaaaaaaaaaaaaaaa;
|
|
parameter I1 = 64'hcccccccccccccccc;
|
|
parameter I2 = 64'hf0f0f0f0f0f0f0f0;
|
|
parameter I3 = 64'hff00ff00ff00ff00;
|
|
parameter I4 = 64'hffff0000ffff0000;
|
|
parameter I5 = 64'hffffffff00000000;
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="INIT Truth Tables" treetype="folder">
|
|
<Template label="LUT1" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT1
|
|
// ________
|
|
// | I0 | O |
|
|
// |--------|
|
|
// | 0 | ? |\
|
|
// | 1 | ? |/ = 2'b??
|
|
// ----------
|
|
</Template>
|
|
<Template label="LUT2" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT2
|
|
// ______________
|
|
// | I2 I1 I0 | O |
|
|
// |--------------|
|
|
// | 0 0 0 | ? |\
|
|
// | 0 0 1 | ? | \ = INIT = 4'b???? = 4'h?
|
|
// | 0 1 0 | ? | /
|
|
// | 0 1 1 | ? |/
|
|
// ---------- ---
|
|
</Template>
|
|
<Template label="LUT3" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT3
|
|
// ______________
|
|
// | I2 I1 I0 | O |
|
|
// |--------------|
|
|
// | 0 0 0 | ? |\
|
|
// | 0 0 1 | ? | \ = 4'b???? = 4'h? --------------+
|
|
// | 0 1 0 | ? | / |
|
|
// | 0 1 1 | ? |/ |
|
|
// |----------|---| INIT = 8'h??
|
|
// | 1 0 0 | ? |\ |
|
|
// | 1 0 1 | ? | \ = 4'b???? = 4'h? -------------+
|
|
// | 1 1 0 | ? | /
|
|
// | 1 1 1 | ? |/
|
|
// ----------------
|
|
</Template>
|
|
<Template label="LUT4" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT4
|
|
// _________________
|
|
// | I3 I2 I1 I0 | O |
|
|
// |-----------------|
|
|
// | 0 0 0 0 | ? |\
|
|
// | 0 0 0 1 | ? | \ = 4'b???? = 4'h? ---------------+
|
|
// | 0 0 1 0 | ? | / |
|
|
// | 0 0 1 1 | ? |/ |
|
|
// |-------------|---| |
|
|
// | 0 1 0 0 | ? |\ |
|
|
// | 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 1 0 | ? | / |
|
|
// | 0 1 1 1 | ? |/ |
|
|
// |-------------|---| INIT = 16'h????
|
|
// | 1 0 0 0 | ? |\ |
|
|
// | 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 1 0 | ? | / |
|
|
// | 1 0 1 1 | ? |/ |
|
|
// |-------------|---| |
|
|
// | 1 1 0 0 | ? |\ |
|
|
// | 1 1 0 1 | ? | \ = 4'b???? = 4'h? ------------+
|
|
// | 1 1 1 0 | ? | /
|
|
// | 1 1 1 1 | ? |/
|
|
// -------------------
|
|
</Template>
|
|
<Template label="LUT5" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT5
|
|
// ____________________
|
|
// | I4 I3 I2 I1 I0 | O |
|
|
// |--------------------|
|
|
// | 0 0 0 0 0 | ? |\
|
|
// | 0 0 0 0 1 | ? | \ = 4'b???? = 4'h? -------------------+
|
|
// | 0 0 0 1 0 | ? | / |
|
|
// | 0 0 0 1 1 | ? |/ |
|
|
// |----------------|---| |
|
|
// | 0 0 1 0 0 | ? |\ |
|
|
// | 0 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 0 1 1 0 | ? | / |
|
|
// | 0 0 1 1 1 | ? |/ |
|
|
// |----------------|---| |
|
|
// | 0 1 0 0 0 | ? |\ |
|
|
// | 0 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 0 1 0 | ? | / |
|
|
// | 0 1 0 1 1 | ? |/ |
|
|
// |----------------|---| |
|
|
// | 0 1 1 0 0 | ? |\ |
|
|
// | 0 1 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 1 1 0 | ? | / |
|
|
// | 0 1 1 1 1 | ? |/ |
|
|
// ---------------------- INIT = 32'h????????
|
|
// | 1 0 0 0 0 | ? |\ |
|
|
// | 1 0 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 0 1 0 | ? | / |
|
|
// | 1 0 0 1 1 | ? |/ |
|
|
// |----------------|---| |
|
|
// | 1 0 1 0 0 | ? |\ |
|
|
// | 1 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 1 1 0 | ? | / |
|
|
// | 1 0 1 1 1 | ? |/ |
|
|
// |----------------|---| |
|
|
// | 1 1 0 0 0 | ? |\ |
|
|
// | 1 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 1 0 1 0 | ? | / |
|
|
// | 1 1 0 1 1 | ? |/ |
|
|
// |----------------|---| |
|
|
// | 1 1 1 0 0 | ? |\ |
|
|
// | 1 1 1 0 1 | ? | \ = 4'b???? = 4'h? ------------+
|
|
// | 1 1 1 1 0 | ? | /
|
|
// | 1 1 1 1 1 | ? |/
|
|
// ----------------------
|
|
</Template>
|
|
<Template label="LUT6" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT6
|
|
// _______________________
|
|
// | I5 I4 I3 I2 I1 I0 | O |
|
|
// |-----------------------|
|
|
// | 0 0 0 0 0 0 | ? |\
|
|
// | 0 0 0 0 0 1 | ? | \ = 4'b???? = 4'h? -------------------+
|
|
// | 0 0 0 0 1 0 | ? | / |
|
|
// | 0 0 0 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 0 0 0 1 0 0 | ? |\ |
|
|
// | 0 0 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 0 0 1 1 0 | ? | / |
|
|
// | 0 0 0 1 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 0 0 1 0 0 0 | ? |\ |
|
|
// | 0 0 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 0 1 0 1 0 | ? | / |
|
|
// | 0 0 1 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 0 0 1 1 0 0 | ? |\ |
|
|
// | 0 0 1 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 0 1 1 1 0 | ? | / |
|
|
// | 0 0 1 1 1 1 | ? |/ |
|
|
// ------------------------- |
|
|
// | 0 1 0 0 0 0 | ? |\ |
|
|
// | 0 1 0 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 0 0 1 0 | ? | / |
|
|
// | 0 1 0 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 0 1 0 1 0 0 | ? |\ |
|
|
// | 0 1 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 0 1 1 0 | ? | / |
|
|
// | 0 1 0 1 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 0 1 1 0 0 0 | ? |\ |
|
|
// | 0 1 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 1 0 1 0 | ? | / |
|
|
// | 0 1 1 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 0 1 1 1 0 0 | ? |\ |
|
|
// | 0 1 1 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 1 1 1 0 | ? | / |
|
|
// | 0 1 1 1 1 1 | ? |/ |
|
|
// ------------------------ INIT = 64'h????????????????
|
|
// | 1 0 0 0 0 0 | ? |\ |
|
|
// | 1 0 0 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 0 0 1 0 | ? | / |
|
|
// | 1 0 0 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 0 0 1 0 0 | ? |\ |
|
|
// | 1 0 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 0 1 1 0 | ? | / |
|
|
// | 1 0 0 1 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 0 1 0 0 0 | ? |\ |
|
|
// | 1 0 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 1 0 1 0 | ? | / |
|
|
// | 1 0 1 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 0 1 1 0 0 | ? |\ |
|
|
// | 1 0 1 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 1 1 1 0 | ? | / |
|
|
// | 1 0 1 1 1 1 | ? |/ |
|
|
// ------------------------- |
|
|
// | 1 1 0 0 0 0 | ? |\ |
|
|
// | 1 1 0 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 1 0 0 1 0 | ? | / |
|
|
// | 1 1 0 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 1 0 1 0 0 | ? |\ |
|
|
// | 1 1 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 1 0 1 1 0 | ? | / |
|
|
// | 1 1 0 1 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 1 1 0 0 0 | ? |\ |
|
|
// | 1 1 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 1 1 0 1 0 | ? | / |
|
|
// | 1 1 1 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 1 1 1 0 0 | ? |\ |
|
|
// | 1 1 1 1 0 1 | ? | \ = 4'b???? = 4'h? ----+
|
|
// | 1 1 1 1 1 0 | ? | /
|
|
// | 1 1 1 1 1 1 | ? |/
|
|
// ------------------------
|
|
</Template>
|
|
<Template label="LUT6_2" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT6_2
|
|
// _____________________________
|
|
// | I5 I4 I3 I2 I1 I0 | O6 | O5 |
|
|
// |-----------------------------|
|
|
// | 0 0 0 0 0 0 | ? |\
|
|
// | 0 0 0 0 0 1 | ? | \ = 4'b???? = 4'h? -------------+
|
|
// | 0 0 0 0 1 0 | ? | / |
|
|
// | 0 0 0 0 1 1 | ? |/ |
|
|
// |-------------------|---------| |
|
|
// | 0 0 0 1 0 0 | ? |\ |
|
|
// | 0 0 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 0 0 1 1 0 | ? | / |
|
|
// | 0 0 0 1 1 1 | ? |/ |
|
|
// |-------------------|---------| |
|
|
// | 0 0 1 0 0 0 | ? |\ |
|
|
// | 0 0 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 0 1 0 1 0 | ? | / |
|
|
// | 0 0 1 0 1 1 | ? |/ |
|
|
// |-------------------|---------| |
|
|
// | 0 0 1 1 0 0 | ? |\ |
|
|
// | 0 0 1 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 0 1 1 1 0 | ? | / |
|
|
// | 0 0 1 1 1 1 | ? |/ |
|
|
// ------------------------------- |
|
|
// | 0 1 0 0 0 0 | ? |\ |
|
|
// | 0 1 0 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 0 0 1 0 | ? | / |
|
|
// | 0 1 0 0 1 1 | ? |/ |
|
|
// |-------------------|---------| |
|
|
// | 0 1 0 1 0 0 | ? |\ |
|
|
// | 0 1 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 0 1 1 0 | ? | / |
|
|
// | 0 1 0 1 1 1 | ? |/ |
|
|
// |-------------------|---------| |
|
|
// | 0 1 1 0 0 0 | ? |\ |
|
|
// | 0 1 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 1 0 1 0 | ? | / |
|
|
// | 0 1 1 0 1 1 | ? |/ |
|
|
// |-------------------|---------| |
|
|
// | 0 1 1 1 0 0 | ? |\ |
|
|
// | 0 1 1 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 1 1 1 0 | ? | / |
|
|
// | 0 1 1 1 1 1 | ? |/ |
|
|
// ------------------------------ INIT = 64'h????????????????
|
|
// | 1 0 0 0 0 0 | ? |\ |
|
|
// | 1 0 0 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 0 0 1 0 | ? | / |
|
|
// | 1 0 0 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 0 0 1 0 0 | ? |\ |
|
|
// | 1 0 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 0 1 1 0 | ? | / |
|
|
// | 1 0 0 1 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 0 1 0 0 0 | ? |\ |
|
|
// | 1 0 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 1 0 1 0 | ? | / |
|
|
// | 1 0 1 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 0 1 1 0 0 | ? |\ |
|
|
// | 1 0 1 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 1 1 1 0 | ? | / |
|
|
// | 1 0 1 1 1 1 | ? |/ |
|
|
// ------------------------- |
|
|
// | 1 1 0 0 0 0 | ? |\ |
|
|
// | 1 1 0 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 1 0 0 1 0 | ? | / |
|
|
// | 1 1 0 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 1 0 1 0 0 | ? |\ |
|
|
// | 1 1 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 1 0 1 1 0 | ? | / |
|
|
// | 1 1 0 1 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 1 1 0 0 0 | ? |\ |
|
|
// | 1 1 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 1 1 0 1 0 | ? | / |
|
|
// | 1 1 1 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 1 1 1 0 0 | ? |\ |
|
|
// | 1 1 1 1 0 1 | ? | \ = 4'b???? = 4'h? ----+
|
|
// | 1 1 1 1 1 0 | ? | /
|
|
// | 1 1 1 1 1 1 | ? |/
|
|
// ------------------------
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<Template label="LUT4" treetype="template">
|
|
// LUT4 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT4_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT4: 4-input Look-Up Table with general output
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT4 #(
|
|
.INIT(16'h0000) // Specify LUT Contents
|
|
) LUT4_inst (
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3) // LUT input
|
|
);
|
|
|
|
// End of LUT4_inst instantiation
|
|
</Template>
|
|
<Template label="LUT4_L" treetype="template">
|
|
// LUT4_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT4_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT4_L: 4-input Look-Up Table with local output
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT4_L #(
|
|
.INIT(16'h0000) // Specify LUT Contents
|
|
) LUT4_L_inst (
|
|
.LO(LO), // LUT local output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3) // LUT input
|
|
);
|
|
|
|
// End of LUT4_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT4_D" treetype="template">
|
|
// LUT4_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT4_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT4_D: 4-input Look-Up Table with general and local outputs
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT4_D #(
|
|
.INIT(16'h0000) // Specify LUT Contents
|
|
) LUT4_D_inst (
|
|
.LO(LO), // LUT local output
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3) // LUT input
|
|
);
|
|
|
|
// End of LUT4_D_inst instantiation
|
|
</Template>
|
|
<Template label="LUT3" treetype="template">
|
|
// LUT3 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT3_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT3: 3-input Look-Up Table with general output
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT3 #(
|
|
.INIT(8'h00) // Specify LUT Contents
|
|
) LUT3_inst (
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2) // LUT input
|
|
);
|
|
|
|
// End of LUT3_inst instantiation
|
|
</Template>
|
|
<Template label="LUT3_L" treetype="template">
|
|
// LUT3_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT3_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT3_L: 3-input Look-Up Table with local output
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT3_L #(
|
|
.INIT(8'h00) // Specify LUT Contents
|
|
) LUT3_L_inst (
|
|
.LO(LO), // LUT local output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2) // LUT input
|
|
);
|
|
|
|
// End of LUT3_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT3_D" treetype="template">
|
|
// LUT3_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT3_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT3_D: 3-input Look-Up Table with general and local outputs
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT3_D #(
|
|
.INIT(8'h00) // Specify LUT Contents
|
|
) LUT3_D_inst (
|
|
.LO(LO), // LUT local output
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2) // LUT input
|
|
);
|
|
|
|
// End of LUT3_D_inst instantiation
|
|
</Template>
|
|
<Template label="LUT2" treetype="template">
|
|
// LUT2 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT2: 2-input Look-Up Table with general output
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT2 #(
|
|
.INIT(4'h0) // Specify LUT Contents
|
|
) LUT2_inst (
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1) // LUT input
|
|
);
|
|
|
|
// End of LUT2_inst instantiation
|
|
</Template>
|
|
<Template label="LUT2_L" treetype="template">
|
|
// LUT2_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT2_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT2_L: 2-input Look-Up Table with local output
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT2_L #(
|
|
.INIT(4'h0) // Specify LUT Contents
|
|
) LUT2_L_inst (
|
|
.LO(LO), // LUT local output
|
|
.I0(I0), // LUT input
|
|
.I1(I1) // LUT input
|
|
);
|
|
|
|
// End of LUT2_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT2_D" treetype="template">
|
|
// LUT2_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT2_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT2_D: 2-input Look-Up Table with general and local outputs
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT2_D #(
|
|
.INIT(4'h0) // Specify LUT Contents
|
|
) LUT2_D_inst (
|
|
.LO(LO), // LUT local output
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1) // LUT input
|
|
);
|
|
|
|
// End of LUT2_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT1" treetype="template">
|
|
// LUT1 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT1: 1-input Look-Up Table with general output
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT1 #(
|
|
.INIT(2'b00) // Specify LUT Contents
|
|
) LUT1_inst (
|
|
.O(O), // LUT general output
|
|
.I0(I0) // LUT input
|
|
);
|
|
|
|
// End of LUT1_inst instantiation
|
|
</Template>
|
|
<Template label="LUT1_L" treetype="template">
|
|
// LUT1_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT1_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT1_L: 1-input Look-Up Table with local output
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT1_L #(
|
|
.INIT(2'b00) // Specify LUT Contents
|
|
) LUT1_L_inst (
|
|
.LO(LO), // LUT local output
|
|
.I0(I0) // LUT input
|
|
);
|
|
|
|
// End of LUT1_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT1_D" treetype="template">
|
|
// LUT1_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT1_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT1_D: 1-input Look-Up Table with general and local outputs
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT1_D #(
|
|
.INIT(2'b00) // Specify LUT Contents
|
|
) LUT1_D_inst (
|
|
.LO(LO), // LUT local output
|
|
.O(O), // LUT general output
|
|
.I0(I0) // LUT input
|
|
);
|
|
|
|
// End of LUT1_D_inst instantiation
|
|
</Template>
|
|
<Template label="Reconfigurable LUT (CFGLUT5)" treetype="template">
|
|
// CFGLUT5 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (CFGLUT5_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// CFGLUT5: Reconfigurable 5-input LUT
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
CFGLUT5 #(
|
|
.INIT(32'h00000000) // Specify initial LUT contents
|
|
) CFGLUT5_inst (
|
|
.CDO(CDO), // Reconfiguration cascade output
|
|
.O5(O5), // 4-LUT output
|
|
.O6(O6), // 5-LUT output
|
|
.CDI(CDI), // Reconfiguration data input
|
|
.CE(CE), // Reconfiguration enable input
|
|
.CLK(CLK), // Clock input
|
|
.I0(I0), // Logic data input
|
|
.I1(I1), // Logic data input
|
|
.I2(I2), // Logic data input
|
|
.I3(I3), // Logic data input
|
|
.I4(I4) // Logic data input
|
|
);
|
|
|
|
// End of CFGLUT5_inst instantiation
|
|
</Template>
|
|
<Template label="LUT5" treetype="template">
|
|
// LUT5 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT5_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT5: 5-input Look-Up Table with general output
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT5 #(
|
|
.INIT(32'h00000000) // Specify LUT Contents
|
|
) LUT5_inst (
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3), // LUT input
|
|
.I4(I4) // LUT input
|
|
);
|
|
|
|
// End of LUT5_inst instantiation
|
|
</Template>
|
|
<Template label="LUT5_L" treetype="template">
|
|
// LUT5_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT5_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT5_L: 5-input Look-Up Table with local output
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT5_L #(
|
|
.INIT(32'h0000000) // Specify LUT Contents
|
|
) LUT5_L_inst (
|
|
.LO(LO), // LUT local output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3), // LUT input
|
|
.I4(I4) // LUT input
|
|
);
|
|
|
|
// End of LUT5_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT5_D" treetype="template">
|
|
// LUT5_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT5_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT5_D: 5-input Look-Up Table with general and local outputs
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT5_D #(
|
|
.INIT(32'h0000000) // Specify LUT Contents
|
|
) LUT5_D_inst (
|
|
.LO(LO), // LUT local output
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3), // LUT input
|
|
.I4(I4) // LUT input
|
|
);
|
|
|
|
// End of LUT5_D_inst instantiation
|
|
</Template>
|
|
<Template label="LUT6" treetype="template">
|
|
// LUT6 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT6_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT6: 6-input Look-Up Table with general output
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT6 #(
|
|
.INIT(64'h0000000000000000) // Specify LUT Contents
|
|
) LUT6_inst (
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3), // LUT input
|
|
.I4(I4), // LUT input
|
|
.I5(I5) // LUT input
|
|
);
|
|
|
|
// End of LUT6_inst instantiation
|
|
</Template>
|
|
<Template label="LUT6_L" treetype="template">
|
|
// LUT6_L : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT6_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT6_L: 6-input Look-Up Table with local output
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT6_L #(
|
|
.INIT(64'h0000000000000000) // Specify LUT Contents
|
|
) LUT6_L_inst (
|
|
.LO(LO), // LUT local output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3), // LUT input
|
|
.I4(I4), // LUT input
|
|
.I5(I5) // LUT input
|
|
);
|
|
|
|
// End of LUT6_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT6_D" treetype="template">
|
|
// LUT6_D : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT6_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT6_D: 6-input Look-Up Table with general and local outputs
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT6_D #(
|
|
.INIT(64'h0000000000000000) // Specify LUT Contents
|
|
) LUT6_D_inst (
|
|
.LO(LO), // LUT local output
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3), // LUT input
|
|
.I4(I4), // LUT input
|
|
.I5(I5) // LUT input
|
|
);
|
|
|
|
// End of LUT6_D_inst instantiation
|
|
</Template>
|
|
<Template label="LUT6_2" treetype="template">
|
|
// LUT6_2 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT6_2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT6_2: 6-input, 2 output Look-Up Table
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT6_2 #(
|
|
.INIT(64'h0000000000000000) // Specify LUT Contents
|
|
) LUT6_2_inst (
|
|
.O6(O6), // 1-bit LUT6 output
|
|
.O5(O5), // 1-bit lower LUT5 output
|
|
.I0(I0), // 1-bit LUT input
|
|
.I1(I1), // 1-bit LUT input
|
|
.I2(I2), // 1-bit LUT input
|
|
.I3(I3), // 1-bit LUT input
|
|
.I4(I4), // 1-bit LUT input
|
|
.I5(I5) // 1-bit LUT input (fast MUX select only available to O6 output)
|
|
);
|
|
|
|
// End of LUT6_2_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Shift Register LUT" treetype="folder">
|
|
<Template label="16-bit w/ CE posedge SR (SRL16E)" treetype="template">
|
|
// SRL16E : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SRL16E_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SRL16E: 16-bit shift register LUT with clock enable operating on posedge of clock
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SRL16E #(
|
|
.INIT(16'h0000) // Initial Value of Shift Register
|
|
) SRL16E_inst (
|
|
.Q(Q), // SRL data output
|
|
.A0(A0), // Select[0] input
|
|
.A1(A1), // Select[1] input
|
|
.A2(A2), // Select[2] input
|
|
.A3(A3), // Select[3] input
|
|
.CE(CE), // Clock enable input
|
|
.CLK(CLK), // Clock input
|
|
.D(D) // SRL data input
|
|
);
|
|
|
|
// End of SRL16E_inst instantiation
|
|
</Template>
|
|
<Template label="32-bit w/ CE posedge SR (SRLC32E)" treetype="template">
|
|
// SRLC32E : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SRL32E_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SRLC32E: 32-bit variable length cascadable shift register LUT
|
|
// with clock enable
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SRLC32E #(
|
|
.INIT(32'h00000000) // Initial Value of Shift Register
|
|
) SRLC32E_inst (
|
|
.Q(Q), // SRL data output
|
|
.Q31(Q31), // SRL cascade output pin
|
|
.A(A), // 5-bit shift depth select input
|
|
.CE(CE), // Clock enable input
|
|
.CLK(CLK), // Clock input
|
|
.D(D) // SRL data input
|
|
);
|
|
|
|
// End of SRLC32E_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<Template label="Carry (CARRY4)" treetype="template">
|
|
// CARRY4 : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (CARRY4_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs and
|
|
// : and outputs of this primitive should be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// CARRY4: Fast Carry Logic Component
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
CARRY4 CARRY4_inst (
|
|
.CO(CO), // 4-bit carry out
|
|
.O(O), // 4-bit carry chain XOR data out
|
|
.CI(CI), // 1-bit carry cascade input
|
|
.CYINIT(CYINIT), // 1-bit carry initialization
|
|
.DI(DI), // 4-bit carry-MUX data in
|
|
.S(S) // 4-bit carry-MUX select input
|
|
);
|
|
|
|
// End of CARRY4_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Registers & Latches" treetype="folder">
|
|
<SubFolder label="Single Data Rate" treetype="folder">
|
|
<Template label="Posedge D-FF w/ Async Clear and CE (FDCE)" treetype="template">
|
|
// FDCE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FDCE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FDCE: Single Data Rate D Flip-Flop with Asynchronous Clear and
|
|
// Clock Enable (posedge clk).
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FDCE #(
|
|
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
|
|
) FDCE_inst (
|
|
.Q(Q), // 1-bit Data output
|
|
.C(C), // 1-bit Clock input
|
|
.CE(CE), // 1-bit Clock enable input
|
|
.CLR(CLR), // 1-bit Asynchronous clear input
|
|
.D(D) // 1-bit Data input
|
|
);
|
|
|
|
// End of FDCE_inst instantiation
|
|
</Template>
|
|
<Template label="Posedge D-FF w/ Async Preset and CE (FDPE)" treetype="template">
|
|
// FDPE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FDPE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FDPE: Single Data Rate D Flip-Flop with Asynchronous Preset and
|
|
// Clock Enable (posedge clk).
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FDPE #(
|
|
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
|
|
) FDPE_inst (
|
|
.Q(Q), // 1-bit Data output
|
|
.C(C), // 1-bit Clock input
|
|
.CE(CE), // 1-bit Clock enable input
|
|
.PRE(PRE), // 1-bit Asynchronous preset input
|
|
.D(D) // 1-bit Data input
|
|
);
|
|
|
|
// End of FDPE_inst instantiation
|
|
</Template>
|
|
<Template label="Posedge D-FF w/ Sync Reset and CE (FDRE)" treetype="template">
|
|
// FDRE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FDRE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FDRE: Single Data Rate D Flip-Flop with Synchronous Reset and
|
|
// Clock Enable (posedge clk).
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FDRE #(
|
|
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
|
|
) FDRE_inst (
|
|
.Q(Q), // 1-bit Data output
|
|
.C(C), // 1-bit Clock input
|
|
.CE(CE), // 1-bit Clock enable input
|
|
.R(R), // 1-bit Synchronous reset input
|
|
.D(D) // 1-bit Data input
|
|
);
|
|
|
|
// End of FDRE_inst instantiation
|
|
</Template>
|
|
<Template label="Posedge D-FF w/ Sync Set and CE (FDSE)" treetype="template">
|
|
// FDSE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FDSE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FDSE: Single Data Rate D Flip-Flop with Synchronous Set and
|
|
// Clock Enable (posedge clk).
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FDSE #(
|
|
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
|
|
) FDSE_inst (
|
|
.Q(Q), // 1-bit Data output
|
|
.C(C), // 1-bit Clock input
|
|
.CE(CE), // 1-bit Clock enable input
|
|
.S(S), // 1-bit Synchronous set input
|
|
.D(D) // 1-bit Data input
|
|
);
|
|
|
|
// End of FDSE_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Transparent Latch" treetype="folder">
|
|
<Template label="Latch with Async Reset and Gate Enable (LDCE)" treetype="template">
|
|
// LDCE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LDCE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LDCE: Transparent latch with Asynchronous Reset and Gate Enable.
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LDCE #(
|
|
.INIT(1'b0) // Initial value of latch (1'b0 or 1'b1)
|
|
) LDCE_inst (
|
|
.Q(Q), // Data output
|
|
.CLR(CLR), // Asynchronous clear/reset input
|
|
.D(D), // Data input
|
|
.G(G), // Gate input
|
|
.GE(GE) // Gate enable input
|
|
);
|
|
|
|
// End of LDCE_inst instantiation
|
|
</Template>
|
|
<Template label="Latch with Async Set and Gate Enable (LDPE)" treetype="template">
|
|
// LDPE : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LDPE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LDPE: Transparent latch with Asynchronous Preset and Gate Enable.
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LDPE #(
|
|
.INIT(1'b1) // Initial value of latch (1'b0 or 1'b1)
|
|
) LDPE_inst (
|
|
.Q(Q), // Data output
|
|
.PRE(PRE), // Asynchronous preset/set input
|
|
.D(D), // Data input
|
|
.G(G), // Gate input
|
|
.GE(GE) // Gate enable input
|
|
);
|
|
|
|
// End of LDPE_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Double Data Rate" treetype="folder">
|
|
<Template label="Dual-Clock, Input DDR Register (IDDR_2CLK)" treetype="template">
|
|
// IDDR_2CLK : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IDDR_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IDDR_2CLK: Dual-Clock, Input Double Data Rate Input Register with
|
|
// Set, Reset and Clock Enable.
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IDDR_2CLK #(
|
|
.DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE", "SAME_EDGE"
|
|
// or "SAME_EDGE_PIPELINED"
|
|
.INIT_Q1(1'b0), // Initial value of Q1: 1'b0 or 1'b1
|
|
.INIT_Q2(1'b0), // Initial value of Q2: 1'b0 or 1'b1
|
|
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
|
|
) IDDR_2CLK_inst (
|
|
.Q1(Q1), // 1-bit output for positive edge of clock
|
|
.Q2(Q2), // 1-bit output for negative edge of clock
|
|
.C(C), // 1-bit primary clock input
|
|
.CB(CB), // 1-bit secondary clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.D(D), // 1-bit DDR data input
|
|
.R(R), // 1-bit reset
|
|
.S(S) // 1-bit set
|
|
);
|
|
|
|
// End of IDDR_2CLK_inst instantiation
|
|
</Template>
|
|
<Template label="Input DDR Register (IDDR)" treetype="template">
|
|
// IDDR : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IDDR_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IDDR: Input Double Data Rate Input Register with Set, Reset
|
|
// and Clock Enable.
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IDDR #(
|
|
.DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE", "SAME_EDGE"
|
|
// or "SAME_EDGE_PIPELINED"
|
|
.INIT_Q1(1'b0), // Initial value of Q1: 1'b0 or 1'b1
|
|
.INIT_Q2(1'b0), // Initial value of Q2: 1'b0 or 1'b1
|
|
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
|
|
) IDDR_inst (
|
|
.Q1(Q1), // 1-bit output for positive edge of clock
|
|
.Q2(Q2), // 1-bit output for negative edge of clock
|
|
.C(C), // 1-bit clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.D(D), // 1-bit DDR data input
|
|
.R(R), // 1-bit reset
|
|
.S(S) // 1-bit set
|
|
);
|
|
|
|
// End of IDDR_inst instantiation
|
|
</Template>
|
|
<Template label="Output DDR Register (ODDR)" treetype="template">
|
|
// ODDR : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ODDR_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ODDR: Output Double Data Rate Output Register with Set, Reset
|
|
// and Clock Enable.
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ODDR #(
|
|
.DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE"
|
|
.INIT(1'b0), // Initial value of Q: 1'b0 or 1'b1
|
|
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
|
|
) ODDR_inst (
|
|
.Q(Q), // 1-bit DDR output
|
|
.C(C), // 1-bit clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.D1(D1), // 1-bit data input (positive edge)
|
|
.D2(D2), // 1-bit data input (negative edge)
|
|
.R(R), // 1-bit reset
|
|
.S(S) // 1-bit set
|
|
);
|
|
|
|
// End of ODDR_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Virtex-7" treetype="folder">
|
|
<SubFolder label="Config/BSCAN Components" treetype="folder">
|
|
<Template label="Boundary-Scan User Instruction (BSCANE2)" treetype="template">
|
|
// BSCANE2 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BSCANE2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BSCANE2: Boundary-Scan User Instruction
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BSCANE2 #(
|
|
.JTAG_CHAIN(1) // Value for USER command.
|
|
)
|
|
BSCANE2_inst (
|
|
.CAPTURE(CAPTURE), // 1-bit output: CAPTURE output from TAP controller.
|
|
.DRCK(DRCK), // 1-bit output: Gated TCK output. When SEL is asserted, DRCK toggles when CAPTURE or
|
|
// SHIFT are asserted.
|
|
|
|
.RESET(RESET), // 1-bit output: Reset output for TAP controller.
|
|
.RUNTEST(RUNTEST), // 1-bit output: Output asserted when TAP controller is in Run Test/Idle state.
|
|
.SEL(SEL), // 1-bit output: USER instruction active output.
|
|
.SHIFT(SHIFT), // 1-bit output: SHIFT output from TAP controller.
|
|
.TCK(TCK), // 1-bit output: Test Clock output. Fabric connection to TAP Clock pin.
|
|
.TDI(TDI), // 1-bit output: Test Data Input (TDI) output from TAP controller.
|
|
.TMS(TMS), // 1-bit output: Test Mode Select output. Fabric connection to TAP.
|
|
.UPDATE(UPDATE), // 1-bit output: UPDATE output from TAP controller
|
|
.TDO(TDO) // 1-bit input: Test Data Output (TDO) input for USER function.
|
|
);
|
|
|
|
// End of BSCANE2_inst instantiation
|
|
</Template>
|
|
<Template label="Register Capture (CAPTUREE2)" treetype="template">
|
|
// CAPTUREE2 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (CAPTUREE2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// CAPTUREE2: Register Capture
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
CAPTUREE2 #(
|
|
.ONESHOT("TRUE") // Specifies the procedure for performing single readback per CAP trigger.
|
|
)
|
|
CAPTUREE2_inst (
|
|
.CAP(CAP), // 1-bit input: Capture Input
|
|
.CLK(CLK) // 1-bit input: Clock Input
|
|
);
|
|
|
|
// End of CAPTUREE2_inst instantiation
|
|
</Template>
|
|
<Template label="Device DNA Access Port (DNA_PORT)" treetype="template">
|
|
// DNA_PORT : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (DNA_PORT_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// DNA_PORT: Device DNA Access Port
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
DNA_PORT #(
|
|
.SIM_DNA_VALUE(57'h000000000000000) // Specifies a sample 57-bit DNA value for simulation
|
|
)
|
|
DNA_PORT_inst (
|
|
.DOUT(DOUT), // 1-bit output: DNA output data.
|
|
.CLK(CLK), // 1-bit input: Clock input.
|
|
.DIN(DIN), // 1-bit input: User data input pin.
|
|
.READ(READ), // 1-bit input: Active high load DNA, active low read input.
|
|
.SHIFT(SHIFT) // 1-bit input: Active high shift enable input.
|
|
);
|
|
|
|
// End of DNA_PORT_inst instantiation
|
|
</Template>
|
|
<Template label="32-bit non-volatile design ID (EFUSE_USR)" treetype="template">
|
|
// EFUSE_USR : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (EFUSE_USR_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// EFUSE_USR: 32-bit non-volatile design ID
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
EFUSE_USR #(
|
|
.SIM_EFUSE_VALUE(32'h00000000) // Value of the 32-bit non-volatile value used in simulation
|
|
)
|
|
EFUSE_USR_inst (
|
|
.EFUSEUSR(EFUSEUSR) // 32-bit output: User eFUSE register value output
|
|
);
|
|
|
|
// End of EFUSE_USR_inst instantiation
|
|
</Template>
|
|
<Template label="Configuration Frame Error Correction (FRAME_ECCE2)" treetype="template">
|
|
// FRAME_ECCE2 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FRAME_ECCE2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FRAME_ECCE2: Configuration Frame Error Correction
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FRAME_ECCE2 #(
|
|
.FARSRC("EFAR"), // Determines if the output of FAR[25:0] configuration register points to
|
|
// the FAR or EFAR. Sets configuration option register bit CTL0[7].
|
|
.FRAME_RBT_IN_FILENAME("None") // This file is output by the ICAP_E2 model and it contains Frame Data
|
|
// information for the Raw Bitstream (RBT) file. The FRAME_ECCE2 model
|
|
// will parse this file, calculate ECC and output any error conditions.
|
|
)
|
|
FRAME_ECCE2_inst (
|
|
.CRCERROR(CRCERROR), // 1-bit output: Output indicating a CRC error.
|
|
.ECCERROR(ECCERROR), // 1-bit output: Output indicating an ECC error.
|
|
.ECCERRORSINGLE(ECCERRORSINGLE), // 1-bit output: Output Indicating single-bit Frame ECC error detected.
|
|
.FAR(FAR), // 26-bit output: Frame Address Register Value output.
|
|
.SYNBIT(SYNBIT), // 5-bit output: Output bit address of error.
|
|
.SYNDROME(SYNDROME), // 13-bit output: Output location of erroneous bit.
|
|
.SYNDROMEVALID(SYNDROMEVALID), // 1-bit output: Frame ECC output indicating the SYNDROME output is
|
|
// valid.
|
|
|
|
.SYNWORD(SYNWORD) // 7-bit output: Word output in the frame where an ECC error has been
|
|
// detected.
|
|
|
|
);
|
|
|
|
// End of FRAME_ECCE2_inst instantiation
|
|
</Template>
|
|
<Template label="Internal Configuration Access Port (ICAPE2)" treetype="template">
|
|
// ICAPE2 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ICAPE2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ICAPE2: Internal Configuration Access Port
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ICAPE2 #(
|
|
.DEVICE_ID(0'h3651093), // Specifies the pre-programmed Device ID value to be used for simulation
|
|
// purposes.
|
|
.ICAP_WIDTH("X32"), // Specifies the input and output data width.
|
|
.SIM_CFG_FILE_NAME("None") // Specifies the Raw Bitstream (RBT) file to be parsed by the simulation
|
|
// model.
|
|
)
|
|
ICAPE2_inst (
|
|
.O(O), // 32-bit output: Configuration data output bus
|
|
.CLK(CLK), // 1-bit input: Clock Input
|
|
.CSIB(CSIB), // 1-bit input: Active-Low ICAP Enable
|
|
.I(I), // 32-bit input: Configuration data input bus
|
|
.RDWRB(RDWRB) // 1-bit input: Read/Write Select input
|
|
);
|
|
|
|
// End of ICAPE2_inst instantiation
|
|
</Template>
|
|
<Template label="STARTUP Block (STARTUPE2)" treetype="template">
|
|
// STARTUPE2 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (STARTUPE2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// STARTUPE2: STARTUP Block
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
STARTUPE2 #(
|
|
.PROG_USR("FALSE"), // Activate program event security feature. Requires encrypted bitstreams.
|
|
.SIM_CCLK_FREQ(0.0) // Set the Configuration Clock Frequency(ns) for simulation.
|
|
)
|
|
STARTUPE2_inst (
|
|
.CFGCLK(CFGCLK), // 1-bit output: Configuration main clock output
|
|
.CFGMCLK(CFGMCLK), // 1-bit output: Configuration internal oscillator clock output
|
|
.EOS(EOS), // 1-bit output: Active high output signal indicating the End Of Startup.
|
|
.PREQ(PREQ), // 1-bit output: PROGRAM request to fabric output
|
|
.CLK(CLK), // 1-bit input: User start-up clock input
|
|
.GSR(GSR), // 1-bit input: Global Set/Reset input (GSR cannot be used for the port name)
|
|
.GTS(GTS), // 1-bit input: Global 3-state input (GTS cannot be used for the port name)
|
|
.KEYCLEARB(KEYCLEARB), // 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM)
|
|
.PACK(PACK), // 1-bit input: PROGRAM acknowledge input
|
|
.USRCCLKO(USRCCLKO), // 1-bit input: User CCLK input
|
|
.USRCCLKTS(USRCCLKTS), // 1-bit input: User CCLK 3-state enable input
|
|
.USRDONEO(USRDONEO), // 1-bit input: User DONE pin output control
|
|
.USRDONETS(USRDONETS) // 1-bit input: User DONE 3-state enable output
|
|
);
|
|
|
|
// End of STARTUPE2_inst instantiation
|
|
</Template>
|
|
<Template label="Configuration Data Access (USR_ACCESSE2)" treetype="template">
|
|
// USR_ACCESSE2 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (USR_ACCESSE2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// USR_ACCESSE2: Configuration Data Access
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
USR_ACCESSE2 USR_ACCESSE2_inst (
|
|
.CFGCLK(CFGCLK), // 1-bit output: Configuration Clock output
|
|
.DATA(DATA), // 32-bit output: Configuration Data output
|
|
.DATAVALID(DATAVALID) // 1-bit output: Active high data valid output
|
|
);
|
|
|
|
// End of USR_ACCESSE2_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Clock Components" treetype="folder">
|
|
<SubFolder label="Clock Buffers" treetype="folder">
|
|
<Template label="Global Clock Buffer with Clock Enable and Output State 1 (BUFGCE_1)" treetype="template">
|
|
// BUFGCE_1 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFGCE_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFGCE_1: Global Clock Buffer with Clock Enable and Output State 1
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFGCE_1 BUFGCE_1_inst (
|
|
.O(O), // 1-bit output: Clock output
|
|
.CE(CE), // 1-bit input: Clock enable input for I0
|
|
.I(I) // 1-bit input: Primary clock
|
|
);
|
|
|
|
// End of BUFGCE_1_inst instantiation
|
|
</Template>
|
|
<Template label="Global Clock Buffer with Clock Enable (BUFGCE)" treetype="template">
|
|
// BUFGCE : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFGCE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFGCE: Global Clock Buffer with Clock Enable
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFGCE BUFGCE_inst (
|
|
.O(O), // 1-bit output: Clock output
|
|
.CE(CE), // 1-bit input: Clock enable input for I0
|
|
.I(I) // 1-bit input: Primary clock
|
|
);
|
|
|
|
// End of BUFGCE_inst instantiation
|
|
</Template>
|
|
<Template label="Global Clock Simple Buffer (BUFG)" treetype="template">
|
|
// BUFG : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFG_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFG: Global Clock Simple Buffer
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFG BUFG_inst (
|
|
.O(O), // 1-bit output: Clock output
|
|
.I(I) // 1-bit input: Clock input
|
|
);
|
|
|
|
// End of BUFG_inst instantiation
|
|
</Template>
|
|
<Template label="HROW Clock Buffer with Clock Enable (BUFHCE)" treetype="template">
|
|
// BUFHCE : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFHCE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFHCE: HROW Clock Buffer for a Single Clocking Region with Clock Enable
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFHCE #(
|
|
.CE_TYPE("SYNC"), // "SYNC" (glitchless switching) or "ASYNC" (immediate switch)
|
|
.INIT_OUT(0) // Initial output value (0-1)
|
|
)
|
|
BUFHCE_inst (
|
|
.O(O), // 1-bit output: Clock output
|
|
.CE(CE), // 1-bit input: Active high enable
|
|
.I(I) // 1-bit input: Clock input
|
|
);
|
|
|
|
// End of BUFHCE_inst instantiation
|
|
</Template>
|
|
<Template label="HROW Clock Buffer (BUFH)" treetype="template">
|
|
// BUFH : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFH_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFH: HROW Clock Buffer for a Single Clocking Region
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFH BUFH_inst (
|
|
.O(O), // 1-bit output: Clock output
|
|
.I(I) // 1-bit input: Clock input
|
|
);
|
|
|
|
// End of BUFH_inst instantiation
|
|
</Template>
|
|
<Template label="I/O Clock Buffer (BUFIO)" treetype="template">
|
|
// BUFIO : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFIO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFIO: Local Clock Buffer for I/O
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFIO BUFIO_inst (
|
|
.O(O), // 1-bit output: Clock output (connect to I/O clock loads).
|
|
.I(I) // 1-bit input: Clock input (connect to an IBUF or BUFMR).
|
|
);
|
|
|
|
// End of BUFIO_inst instantiation
|
|
</Template>
|
|
<Template label="Multi-Region Clock Buffer with Clock Enable (BUFMRCE)" treetype="template">
|
|
// BUFMRCE : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFMRCE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFMRCE: Multi-Region Clock Buffer with Clock Enable
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFMRCE #(
|
|
.CE_TYPE("SYNC"), // SYNC, ASYNC
|
|
.INIT_OUT(0) // Initial output and stopped polarity, (0-1)
|
|
)
|
|
BUFMRCE_inst (
|
|
.O(O), // 1-bit output: Clock output (connect to BUFIOs/BUFRs)
|
|
.CE(CE), // 1-bit input: Active high buffer enable
|
|
.I(I) // 1-bit input: Clock input (Connect to IBUF)
|
|
);
|
|
|
|
// End of BUFMRCE_inst instantiation
|
|
</Template>
|
|
<Template label="Multi-Region Clock Buffer (BUFMR)" treetype="template">
|
|
// BUFMR : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFMR_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFMR: Multi-Region Clock Buffer
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFMR BUFMR_inst (
|
|
.O(O), // 1-bit output: Clock output (connect to BUFIOs/BUFRs)
|
|
.I(I) // 1-bit input: Clock input (Connect to IBUF)
|
|
);
|
|
|
|
// End of BUFMR_inst instantiation
|
|
</Template>
|
|
<Template label="Regional Clock Buffer (BUFR)" treetype="template">
|
|
// BUFR : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFR_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFR: Regional Clock Buffer for I/O and Logic Resources within a Clock Region
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFR #(
|
|
.BUFR_DIVIDE("BYPASS"), // Values: "BYPASS, 1, 2, 3, 4, 5, 6, 7, 8"
|
|
.SIM_DEVICE(""7SERIES"") // Must be set to "7SERIES"
|
|
)
|
|
BUFR_inst (
|
|
.O(O), // 1-bit output: Clock output port
|
|
.CE(CE), // 1-bit input: Active high, clock enable (Divided modes only)
|
|
.CLR(CLR), // 1-bit input: Active high, asynchronous clear (Divided modes only)
|
|
.I(I) // 1-bit input: Clock buffer input driven by an IBUF, MMCM or local interconnect
|
|
);
|
|
|
|
// End of BUFR_inst instantiation
|
|
</Template>
|
|
<Template label="Single-ended Input Global Clock Buffer (IBUFG)" treetype="template">
|
|
// IBUFG : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFG_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFG: Global Clock Buffer (sourced by an external pin)
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFG #(
|
|
.IBUF_LOW_PWR("TRUE"), // Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
) IBUFG_inst (
|
|
.O(O), // Clock buffer output
|
|
.I(I) // Clock buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUFG_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Input Global Clock Buffer (IBUFGDS)" treetype="template">
|
|
// IBUFGDS : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFGDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFGDS: Differential Global Clock Buffer (sourced by an external pin)
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFGDS #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination
|
|
.IBUF_LOW_PWR("TRUE"), // Low power="TRUE", Highest performance="FALSE"
|
|
.IOSTANDARD("DEFAULT") // Specifies the I/O standard for this buffer
|
|
) IBUFGDS_inst (
|
|
.O(O), // Clock buffer output
|
|
.I(I), // Diff_p clock buffer input
|
|
.IB(IB) // Diff_n clock buffer input
|
|
);
|
|
|
|
// End of IBUFGDS_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Global Clock Buffer with Differential Output (IBUFGDS_DIFF_OUT)" treetype="template">
|
|
// IBUFGDS_DIFF_OUT : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFGDS_DIFF_OUT_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFGDS_DIFF_OUT: Differential Global Clock Buffer with Differential Output
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFGDS_DIFF_OUT #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination, "TRUE"/"FALSE"
|
|
.IBUF_LOW_PWR("TRUE"), // Low power="TRUE", Highest performance="FALSE"
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
) IBUFGDS_DIFF_OUT_inst (
|
|
.O(O), // Buffer diff_p output
|
|
.OB(OB), // Buffer diff_n output
|
|
.I(I), // Diff_p buffer input (connect directly to top-level port)
|
|
.IB(IB) // Diff_n buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUFGDS_DIFF_OUT_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Clock MUXes" treetype="folder">
|
|
<Template label="Global Clock Control Buffer (BUFGCTRL)" treetype="template">
|
|
// BUFGCTRL : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFGCTRL_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFGCTRL: Global Clock Control Buffer
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFGCTRL #(
|
|
.INIT_OUT(0), // Initial value of BUFGCTRL output ($VALUES;)
|
|
.PRESELECT_I0("FALSE"), // BUFGCTRL output uses I0 input ($VALUES;)
|
|
.PRESELECT_I1("FALSE") // BUFGCTRL output uses I1 input ($VALUES;)
|
|
)
|
|
BUFGCTRL_inst (
|
|
.O(O), // 1-bit output: Clock output
|
|
.CE0(CE0), // 1-bit input: Clock enable input for I0
|
|
.CE1(CE1), // 1-bit input: Clock enable input for I1
|
|
.I0(I0), // 1-bit input: Primary clock
|
|
.I1(I1), // 1-bit input: Secondary clock
|
|
.IGNORE0(IGNORE0), // 1-bit input: Clock ignore input for I0
|
|
.IGNORE1(IGNORE1), // 1-bit input: Clock ignore input for I1
|
|
.S0(S0), // 1-bit input: Clock select for I0
|
|
.S1(S1) // 1-bit input: Clock select for I1
|
|
);
|
|
|
|
// End of BUFGCTRL_inst instantiation
|
|
</Template>
|
|
<Template label="Global Clock Mux Buffer with Output State 1 (BUFGMUX_1)" treetype="template">
|
|
// BUFGMUX_1 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFGMUX_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFGMUX_1: Global Clock Mux Buffer with Output State 1
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFGMUX_1 #(
|
|
)
|
|
BUFGMUX_1_inst (
|
|
.O(O), // 1-bit output: Clock output
|
|
.I0(I0), // 1-bit input: Clock input (S=0)
|
|
.I1(I1), // 1-bit input: Clock input (S=1)
|
|
.S(S) // 1-bit input: Clock select
|
|
);
|
|
|
|
// End of BUFGMUX_1_inst instantiation
|
|
</Template>
|
|
<Template label="2-to-1 Global Clock MUX Buffer (BUFGMUX_CTRL)" treetype="template">
|
|
// BUFGMUX_CTRL : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFGMUX_CTRL_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFGMUX_CTRL: 2-to-1 Global Clock MUX Buffer
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFGMUX_CTRL BUFGMUX_CTRL_inst (
|
|
.O(O), // 1-bit output: Clock output
|
|
.I0(I0), // 1-bit input: Clock input (S=0)
|
|
.I1(I1), // 1-bit input: Clock input (S=1)
|
|
.S(S) // 1-bit input: Clock select
|
|
);
|
|
|
|
// End of BUFGMUX_CTRL_inst instantiation
|
|
</Template>
|
|
<Template label="Global Clock Mux Buffer (BUFGMUX)" treetype="template">
|
|
// BUFGMUX : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BUFGMUX_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BUFGMUX: Global Clock Mux Buffer
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
BUFGMUX #(
|
|
)
|
|
BUFGMUX_inst (
|
|
.O(O), // 1-bit output: Clock output
|
|
.I0(I0), // 1-bit input: Clock input (S=0)
|
|
.I1(I1), // 1-bit input: Clock input (S=1)
|
|
.S(S) // 1-bit input: Clock select
|
|
);
|
|
|
|
// End of BUFGMUX_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="MMCM / PLL" treetype="folder">
|
|
<Template label="Advanced Mixed Mode Clock Manager (MMCME2_ADV)" treetype="template">
|
|
// MMCME2_ADV : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MMCME2_ADV_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MMCME2_ADV: Advanced Mixed Mode Clock Manager
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MMCME2_ADV #(
|
|
.BANDWIDTH("OPTIMIZED"), // Jitter programming (OPTIMIZED, HIGH, LOW)
|
|
.CLKFBOUT_MULT_F(5.0), // Multiply value for all CLKOUT (2.000-64.000).
|
|
.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB (-360.000-360.000).
|
|
// CLKIN_PERIOD: Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
|
|
.CLKIN1_PERIOD(0.0),
|
|
.CLKIN2_PERIOD(0.0),
|
|
// CLKOUT0_DIVIDE - CLKOUT6_DIVIDE: Divide amount for CLKOUT (1-128)
|
|
.CLKOUT1_DIVIDE(1),
|
|
.CLKOUT2_DIVIDE(1),
|
|
.CLKOUT3_DIVIDE(1),
|
|
.CLKOUT4_DIVIDE(1),
|
|
.CLKOUT5_DIVIDE(1),
|
|
.CLKOUT6_DIVIDE(1),
|
|
.CLKOUT0_DIVIDE_F(1.0), // Divide amount for CLKOUT0 (1.000-128.000).
|
|
// CLKOUT0_DUTY_CYCLE - CLKOUT6_DUTY_CYCLE: Duty cycle for CLKOUT outputs (0.01-0.99).
|
|
.CLKOUT0_DUTY_CYCLE(0.5),
|
|
.CLKOUT1_DUTY_CYCLE(0.5),
|
|
.CLKOUT2_DUTY_CYCLE(0.5),
|
|
.CLKOUT3_DUTY_CYCLE(0.5),
|
|
.CLKOUT4_DUTY_CYCLE(0.5),
|
|
.CLKOUT5_DUTY_CYCLE(0.5),
|
|
.CLKOUT6_DUTY_CYCLE(0.5),
|
|
// CLKOUT0_PHASE - CLKOUT6_PHASE: Phase offset for CLKOUT outputs (-360.000-360.000).
|
|
.CLKOUT0_PHASE(0.0),
|
|
.CLKOUT1_PHASE(0.0),
|
|
.CLKOUT2_PHASE(0.0),
|
|
.CLKOUT3_PHASE(0.0),
|
|
.CLKOUT4_PHASE(0.0),
|
|
.CLKOUT5_PHASE(0.0),
|
|
.CLKOUT6_PHASE(0.0),
|
|
.CLKOUT4_CASCADE("FALSE"), // Cascade CLKOUT4 counter with CLKOUT6 (FALSE, TRUE)
|
|
.COMPENSATION("ZHOLD"), // ZHOLD, BUF_IN, EXTERNAL, INTERNAL
|
|
.DIVCLK_DIVIDE(1), // Master division value (1-106)
|
|
// REF_JITTER: Reference input jitter in UI (0.000-0.999).
|
|
.REF_JITTER1(0.0),
|
|
.REF_JITTER2(0.0),
|
|
.STARTUP_WAIT("FALSE"), // Delays DONE until MMCM is locked (FALSE, TRUE)
|
|
// Spread Spectrum: Spread Spectrum Attributes
|
|
.SS_EN("FALSE"), // Enables spread spectrum (FALSE, TRUE)
|
|
.SS_MODE("CENTER_HIGH"), // CENTER_HIGH, CENTER_LOW, DOWN_HIGH, DOWN_LOW
|
|
.SS_MOD_PERIOD(10000), // Spread spectrum modulation period (ns) (VALUES)
|
|
// USE_FINE_PS: Fine phase shift enable (TRUE/FALSE)
|
|
.CLKFBOUT_USE_FINE_PS("FALSE"),
|
|
.CLKOUT0_USE_FINE_PS("FALSE"),
|
|
.CLKOUT1_USE_FINE_PS("FALSE"),
|
|
.CLKOUT2_USE_FINE_PS("FALSE"),
|
|
.CLKOUT3_USE_FINE_PS("FALSE"),
|
|
.CLKOUT4_USE_FINE_PS("FALSE"),
|
|
.CLKOUT5_USE_FINE_PS("FALSE"),
|
|
.CLKOUT6_USE_FINE_PS("FALSE")
|
|
)
|
|
MMCME2_ADV_inst (
|
|
// Clock Outputs: 1-bit (each) output: User configurable clock outputs
|
|
.CLKOUT0(CLKOUT0), // 1-bit output: CLKOUT0
|
|
.CLKOUT0B(CLKOUT0B), // 1-bit output: Inverted CLKOUT0
|
|
.CLKOUT1(CLKOUT1), // 1-bit output: CLKOUT1
|
|
.CLKOUT1B(CLKOUT1B), // 1-bit output: Inverted CLKOUT1
|
|
.CLKOUT2(CLKOUT2), // 1-bit output: CLKOUT2
|
|
.CLKOUT2B(CLKOUT2B), // 1-bit output: Inverted CLKOUT2
|
|
.CLKOUT3(CLKOUT3), // 1-bit output: CLKOUT3
|
|
.CLKOUT3B(CLKOUT3B), // 1-bit output: Inverted CLKOUT3
|
|
.CLKOUT4(CLKOUT4), // 1-bit output: CLKOUT4
|
|
.CLKOUT5(CLKOUT5), // 1-bit output: CLKOUT5
|
|
.CLKOUT6(CLKOUT6), // 1-bit output: CLKOUT6
|
|
// DRP Ports: 16-bit (each) output: Dynamic reconfiguration ports
|
|
.DO(DO), // 16-bit output: DRP data
|
|
.DRDY(DRDY), // 1-bit output: DRP ready
|
|
// Dynamic Phase Shift Ports: 1-bit (each) output: Ports used for dynamic phase shifting of the outputs
|
|
.PSDONE(PSDONE), // 1-bit output: Phase shift done
|
|
// Feedback Clocks: 1-bit (each) output: Clock feedback ports
|
|
.CLKFBOUT(CLKFBOUT), // 1-bit output: Feedback clock
|
|
.CLKFBOUTB(CLKFBOUTB), // 1-bit output: Inverted CLKFBOUT
|
|
// Status Ports: 1-bit (each) output: MMCM status ports
|
|
.CLKFBSTOPPED(CLKFBSTOPPED), // 1-bit output: Feedback clock stopped
|
|
.CLKINSTOPPED(CLKINSTOPPED), // 1-bit output: Input clock stopped
|
|
.LOCKED(LOCKED), // 1-bit output: LOCK
|
|
// Clock Inputs: 1-bit (each) input: Clock inputs
|
|
.CLKIN1(CLKIN1), // 1-bit input: Primary clock
|
|
.CLKIN2(CLKIN2), // 1-bit input: Secondary clock
|
|
// Control Ports: 1-bit (each) input: MMCM control ports
|
|
.CLKINSEL(CLKINSEL), // 1-bit input: Clock select, High=CLKIN1 Low=CLKIN2
|
|
.PWRDWN(PWRDWN), // 1-bit input: Power-down
|
|
.RST(RST), // 1-bit input: Reset
|
|
// DRP Ports: 7-bit (each) input: Dynamic reconfiguration ports
|
|
.DADDR(DADDR), // 7-bit input: DRP address
|
|
.DCLK(DCLK), // 1-bit input: DRP clock
|
|
.DEN(DEN), // 1-bit input: DRP enable
|
|
.DI(DI), // 16-bit input: DRP data
|
|
.DWE(DWE), // 1-bit input: DRP write enable
|
|
// Dynamic Phase Shift Ports: 1-bit (each) input: Ports used for dynamic phase shifting of the outputs
|
|
.PSCLK(PSCLK), // 1-bit input: Phase shift clock
|
|
.PSEN(PSEN), // 1-bit input: Phase shift enable
|
|
.PSINCDEC(PSINCDEC), // 1-bit input: Phase shift increment/decrement
|
|
// Feedback Clocks: 1-bit (each) input: Clock feedback ports
|
|
.CLKFBIN(CLKFBIN) // 1-bit input: Feedback clock
|
|
);
|
|
|
|
// End of MMCME2_ADV_inst instantiation
|
|
</Template>
|
|
<Template label="Base Mixed Mode Clock Manager (MMCME2_BASE)" treetype="template">
|
|
// MMCME2_BASE : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MMCME2_BASE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MMCME2_BASE: Base Mixed Mode Clock Manager
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MMCME2_BASE #(
|
|
.BANDWIDTH("OPTIMIZED"), // Jitter programming (OPTIMIZED, HIGH, LOW)
|
|
.CLKFBOUT_MULT_F(5.0), // Multiply value for all CLKOUT (2.000-64.000).
|
|
.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB (-360.000-360.000).
|
|
.CLKIN1_PERIOD(0.0), // Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
|
|
// CLKOUT0_DIVIDE - CLKOUT6_DIVIDE: Divide amount for each CLKOUT (1-128)
|
|
.CLKOUT1_DIVIDE(1),
|
|
.CLKOUT2_DIVIDE(1),
|
|
.CLKOUT3_DIVIDE(1),
|
|
.CLKOUT4_DIVIDE(1),
|
|
.CLKOUT5_DIVIDE(1),
|
|
.CLKOUT6_DIVIDE(1),
|
|
.CLKOUT0_DIVIDE_F(1.0), // Divide amount for CLKOUT0 (1.000-128.000).
|
|
// CLKOUT0_DUTY_CYCLE - CLKOUT6_DUTY_CYCLE: Duty cycle for each CLKOUT (0.01-0.99).
|
|
.CLKOUT0_DUTY_CYCLE(0.5),
|
|
.CLKOUT1_DUTY_CYCLE(0.5),
|
|
.CLKOUT2_DUTY_CYCLE(0.5),
|
|
.CLKOUT3_DUTY_CYCLE(0.5),
|
|
.CLKOUT4_DUTY_CYCLE(0.5),
|
|
.CLKOUT5_DUTY_CYCLE(0.5),
|
|
.CLKOUT6_DUTY_CYCLE(0.5),
|
|
// CLKOUT0_PHASE - CLKOUT6_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
|
|
.CLKOUT0_PHASE(0.0),
|
|
.CLKOUT1_PHASE(0.0),
|
|
.CLKOUT2_PHASE(0.0),
|
|
.CLKOUT3_PHASE(0.0),
|
|
.CLKOUT4_PHASE(0.0),
|
|
.CLKOUT5_PHASE(0.0),
|
|
.CLKOUT6_PHASE(0.0),
|
|
.CLKOUT4_CASCADE("FALSE"), // Cascade CLKOUT4 counter with CLKOUT6 (FALSE, TRUE)
|
|
.DIVCLK_DIVIDE(1), // Master division value (1-106)
|
|
.REF_JITTER1(0.0), // Reference input jitter in UI (0.000-0.999).
|
|
.STARTUP_WAIT("FALSE") // Delays DONE until MMCM is locked (FALSE, TRUE)
|
|
)
|
|
MMCME2_BASE_inst (
|
|
// Clock Outputs: 1-bit (each) output: User configurable clock outputs
|
|
.CLKOUT0(CLKOUT0), // 1-bit output: CLKOUT0
|
|
.CLKOUT0B(CLKOUT0B), // 1-bit output: Inverted CLKOUT0
|
|
.CLKOUT1(CLKOUT1), // 1-bit output: CLKOUT1
|
|
.CLKOUT1B(CLKOUT1B), // 1-bit output: Inverted CLKOUT1
|
|
.CLKOUT2(CLKOUT2), // 1-bit output: CLKOUT2
|
|
.CLKOUT2B(CLKOUT2B), // 1-bit output: Inverted CLKOUT2
|
|
.CLKOUT3(CLKOUT3), // 1-bit output: CLKOUT3
|
|
.CLKOUT3B(CLKOUT3B), // 1-bit output: Inverted CLKOUT3
|
|
.CLKOUT4(CLKOUT4), // 1-bit output: CLKOUT4
|
|
.CLKOUT5(CLKOUT5), // 1-bit output: CLKOUT5
|
|
.CLKOUT6(CLKOUT6), // 1-bit output: CLKOUT6
|
|
// Feedback Clocks: 1-bit (each) output: Clock feedback ports
|
|
.CLKFBOUT(CLKFBOUT), // 1-bit output: Feedback clock
|
|
.CLKFBOUTB(CLKFBOUTB), // 1-bit output: Inverted CLKFBOUT
|
|
// Status Ports: 1-bit (each) output: MMCM status ports
|
|
.LOCKED(LOCKED), // 1-bit output: LOCK
|
|
// Clock Inputs: 1-bit (each) input: Clock input
|
|
.CLKIN1(CLKIN1), // 1-bit input: Clock
|
|
// Control Ports: 1-bit (each) input: MMCM control ports
|
|
.PWRDWN(PWRDWN), // 1-bit input: Power-down
|
|
.RST(RST), // 1-bit input: Reset
|
|
// Feedback Clocks: 1-bit (each) input: Clock feedback ports
|
|
.CLKFBIN(CLKFBIN) // 1-bit input: Feedback clock
|
|
);
|
|
|
|
// End of MMCME2_BASE_inst instantiation
|
|
</Template>
|
|
<Template label="Advanced Phase Locked Loop (PLLE2_ADV)" treetype="template">
|
|
// PLLE2_ADV : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (PLLE2_ADV_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// PLLE2_ADV: Advanced Phase Locked Loop (PLL)
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
PLLE2_ADV #(
|
|
.BANDWIDTH("OPTIMIZED"), // OPTIMIZED, HIGH, LOW
|
|
.CLKFBOUT_MULT(5), // Multiply value for all CLKOUT, (2-64)
|
|
.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB, (-360.000-360.000).
|
|
// CLKIN_PERIOD: Input clock period in nS to ps resolution (i.e. 33.333 is 30 MHz).
|
|
.CLKIN1_PERIOD(0.0),
|
|
.CLKIN2_PERIOD(0.0),
|
|
// CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for CLKOUT (1-128)
|
|
.CLKOUT0_DIVIDE(1),
|
|
.CLKOUT1_DIVIDE(1),
|
|
.CLKOUT2_DIVIDE(1),
|
|
.CLKOUT3_DIVIDE(1),
|
|
.CLKOUT4_DIVIDE(1),
|
|
.CLKOUT5_DIVIDE(1),
|
|
// CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for CLKOUT outputs (0.001-0.999).
|
|
.CLKOUT0_DUTY_CYCLE(0.5),
|
|
.CLKOUT1_DUTY_CYCLE(0.5),
|
|
.CLKOUT2_DUTY_CYCLE(0.5),
|
|
.CLKOUT3_DUTY_CYCLE(0.5),
|
|
.CLKOUT4_DUTY_CYCLE(0.5),
|
|
.CLKOUT5_DUTY_CYCLE(0.5),
|
|
// CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for CLKOUT outputs (-360.000-360.000).
|
|
.CLKOUT0_PHASE(0.0),
|
|
.CLKOUT1_PHASE(0.0),
|
|
.CLKOUT2_PHASE(0.0),
|
|
.CLKOUT3_PHASE(0.0),
|
|
.CLKOUT4_PHASE(0.0),
|
|
.CLKOUT5_PHASE(0.0),
|
|
.COMPENSATION("ZHOLD"), // ZHOLD, BUF_IN, EXTERNAL, INTERNAL
|
|
.DIVCLK_DIVIDE(1), // Master division value (1-56)
|
|
// REF_JITTER: Reference input jitter in UI (0.000-0.999).
|
|
.REF_JITTER1(0.0),
|
|
.REF_JITTER2(0.0),
|
|
.STARTUP_WAIT("FALSE") // Delay DONE until PLL Locks, ("TRUE"/"FALSE")
|
|
)
|
|
PLLE2_ADV_inst (
|
|
// Clock Outputs: 1-bit (each) output: User configurable clock outputs
|
|
.CLKOUT0(CLKOUT0), // 1-bit output: CLKOUT0
|
|
.CLKOUT1(CLKOUT1), // 1-bit output: CLKOUT1
|
|
.CLKOUT2(CLKOUT2), // 1-bit output: CLKOUT2
|
|
.CLKOUT3(CLKOUT3), // 1-bit output: CLKOUT3
|
|
.CLKOUT4(CLKOUT4), // 1-bit output: CLKOUT4
|
|
.CLKOUT5(CLKOUT5), // 1-bit output: CLKOUT5
|
|
// DRP Ports: 16-bit (each) output: Dynamic reconfiguration ports
|
|
.DO(DO), // 16-bit output: DRP data
|
|
.DRDY(DRDY), // 1-bit output: DRP ready
|
|
// Feedback Clocks: 1-bit (each) output: Clock feedback ports
|
|
.CLKFBOUT(CLKFBOUT), // 1-bit output: Feedback clock
|
|
.LOCKED(LOCKED), // 1-bit output: LOCK
|
|
// Clock Inputs: 1-bit (each) input: Clock inputs
|
|
.CLKIN1(CLKIN1), // 1-bit input: Primary clock
|
|
.CLKIN2(CLKIN2), // 1-bit input: Secondary clock
|
|
// Control Ports: 1-bit (each) input: PLL control ports
|
|
.CLKINSEL(CLKINSEL), // 1-bit input: Clock select, High=CLKIN1 Low=CLKIN2
|
|
.PWRDWN(PWRDWN), // 1-bit input: Power-down
|
|
.RST(RST), // 1-bit input: Reset
|
|
// DRP Ports: 7-bit (each) input: Dynamic reconfiguration ports
|
|
.DADDR(DADDR), // 7-bit input: DRP address
|
|
.DCLK(DCLK), // 1-bit input: DRP clock
|
|
.DEN(DEN), // 1-bit input: DRP enable
|
|
.DI(DI), // 16-bit input: DRP data
|
|
.DWE(DWE), // 1-bit input: DRP write enable
|
|
// Feedback Clocks: 1-bit (each) input: Clock feedback ports
|
|
.CLKFBIN(CLKFBIN) // 1-bit input: Feedback clock
|
|
);
|
|
|
|
// End of PLLE2_ADV_inst instantiation
|
|
</Template>
|
|
<Template label="Base Phase Locked Loop (PLLE2_BASE)" treetype="template">
|
|
// PLLE2_BASE : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (PLLE2_BASE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// PLLE2_BASE: Base Phase Locked Loop (PLL)
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
PLLE2_BASE #(
|
|
.BANDWIDTH("OPTIMIZED"), // OPTIMIZED, HIGH, LOW
|
|
.CLKFBOUT_MULT(5), // Multiply value for all CLKOUT, (2-64)
|
|
.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB, (-360.000-360.000).
|
|
.CLKIN1_PERIOD(0.0), // Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
|
|
// CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128)
|
|
.CLKOUT0_DIVIDE(1),
|
|
.CLKOUT1_DIVIDE(1),
|
|
.CLKOUT2_DIVIDE(1),
|
|
.CLKOUT3_DIVIDE(1),
|
|
.CLKOUT4_DIVIDE(1),
|
|
.CLKOUT5_DIVIDE(1),
|
|
// CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for each CLKOUT (0.001-0.999).
|
|
.CLKOUT0_DUTY_CYCLE(0.5),
|
|
.CLKOUT1_DUTY_CYCLE(0.5),
|
|
.CLKOUT2_DUTY_CYCLE(0.5),
|
|
.CLKOUT3_DUTY_CYCLE(0.5),
|
|
.CLKOUT4_DUTY_CYCLE(0.5),
|
|
.CLKOUT5_DUTY_CYCLE(0.5),
|
|
// CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
|
|
.CLKOUT0_PHASE(0.0),
|
|
.CLKOUT1_PHASE(0.0),
|
|
.CLKOUT2_PHASE(0.0),
|
|
.CLKOUT3_PHASE(0.0),
|
|
.CLKOUT4_PHASE(0.0),
|
|
.CLKOUT5_PHASE(0.0),
|
|
.DIVCLK_DIVIDE(1), // Master division value, (1-56)
|
|
.REF_JITTER1(0.0), // Reference input jitter in UI, (0.000-0.999).
|
|
.STARTUP_WAIT("FALSE") // Delay DONE until PLL Locks, ("TRUE"/"FALSE")
|
|
)
|
|
PLLE2_BASE_inst (
|
|
// Clock Outputs: 1-bit (each) output: User configurable clock outputs
|
|
.CLKOUT0(CLKOUT0), // 1-bit output: CLKOUT0
|
|
.CLKOUT1(CLKOUT1), // 1-bit output: CLKOUT1
|
|
.CLKOUT2(CLKOUT2), // 1-bit output: CLKOUT2
|
|
.CLKOUT3(CLKOUT3), // 1-bit output: CLKOUT3
|
|
.CLKOUT4(CLKOUT4), // 1-bit output: CLKOUT4
|
|
.CLKOUT5(CLKOUT5), // 1-bit output: CLKOUT5
|
|
// Feedback Clocks: 1-bit (each) output: Clock feedback ports
|
|
.CLKFBOUT(CLKFBOUT), // 1-bit output: Feedback clock
|
|
.LOCKED(LOCKED), // 1-bit output: LOCK
|
|
.CLKIN1(CLKIN1), // 1-bit input: Input clock
|
|
// Control Ports: 1-bit (each) input: PLL control ports
|
|
.PWRDWN(PWRDWN), // 1-bit input: Power-down
|
|
.RST(RST), // 1-bit input: Reset
|
|
// Feedback Clocks: 1-bit (each) input: Clock feedback ports
|
|
.CLKFBIN(CLKFBIN) // 1-bit input: Feedback clock
|
|
);
|
|
|
|
// End of PLLE2_BASE_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="I/O Components" treetype="folder">
|
|
<Template label="Digitally Controlled Impedance Reset Component (DCIRESET)" treetype="template">
|
|
// DCIRESET : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (DCIRESET_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// DCIRESET: Digitally Controlled Impedance Reset Component
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
DCIRESET DCIRESET_inst (
|
|
.LOCKED(LOCKED), // 1-bit output: LOCK status output
|
|
.RST(RST) // 1-bit input: Active-high asynchronous reset input
|
|
);
|
|
|
|
// End of DCIRESET_inst instantiation
|
|
</Template>
|
|
<SubFolder label="I/O Delay Components" treetype="folder">
|
|
<Template label="Delay Calibration (IDELAYCTRL)" treetype="template">
|
|
// IDELAYCTRL : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IDELAYCTRL_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IDELAYCTRL: IDELAYE2/ODELAYE2 Tap Delay Value Control
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
(* IODELAY_GROUP = <iodelay_group_name> *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTRL
|
|
|
|
IDELAYCTRL IDELAYCTRL_inst (
|
|
.RDY(RDY), // 1-bit output: Ready output
|
|
.REFCLK(REFCLK), // 1-bit input: Reference clock input
|
|
.RST(RST) // 1-bit input: Active high reset input
|
|
);
|
|
|
|
// End of IDELAYCTRL_inst instantiation
|
|
</Template>
|
|
<Template label="Input Delay Element (IDELAYE2)" treetype="template">
|
|
// IDELAYE2 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IDELAYE2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IDELAYE2: Input Fixed or Variable Delay Element
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
(* IODELAY_GROUP = <iodelay_group_name> *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTRL
|
|
|
|
IDELAYE2 #(
|
|
.CINVCTRL_SEL("FALSE"), // Enable dynamic clock inversion (FALSE, TRUE)
|
|
.DELAY_SRC("IDATAIN"), // Delay input (IDATAIN, DATAIN)
|
|
.HIGH_PERFORMANCE_MODE("FALSE"), // Reduced jitter ("TRUE"), Reduced power ("FALSE")
|
|
.IDELAY_TYPE("FIXED"), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
|
|
.IDELAY_VALUE(0), // Input delay tap setting (0-31)
|
|
.PIPE_SEL("FALSE"), // Select pipelined mode, FALSE, TRUE
|
|
.REFCLK_FREQUENCY(200.0), // IDELAYCTRL clock input frequency in MHz (190.0-210.0, 290.0-310.0).
|
|
.SIGNAL_PATTERN("DATA") // DATA, CLOCK input signal
|
|
)
|
|
IDELAYE2_inst (
|
|
.CNTVALUEOUT(CNTVALUEOUT), // 5-bit output: Counter value output
|
|
.DATAOUT(DATAOUT), // 1-bit output: Delayed data output
|
|
.C(C), // 1-bit input: Clock input
|
|
.CE(CE), // 1-bit input: Active high enable increment/decrement input
|
|
.CINVCTRL(CINVCTRL), // 1-bit input: Dynamic clock inversion input
|
|
.CNTVALUEIN(CNTVALUEIN), // 5-bit input: Counter value input
|
|
.DATAIN(DATAIN), // 1-bit input: Internal delay data input
|
|
.IDATAIN(IDATAIN), // 1-bit input: Data input from the I/O
|
|
.INC(INC), // 1-bit input: Increment / Decrement tap delay input
|
|
.LD(LD), // 1-bit input: Load IDELAY_VALUE input
|
|
.LDPIPEEN(LDPIPEEN), // 1-bit input: Enable PIPELINE register to load data input
|
|
.REGRST(REGRST) // 1-bit input: Active-high reset tap-delay input
|
|
);
|
|
|
|
// End of IDELAYE2_inst instantiation
|
|
</Template>
|
|
<Template label="Output Delay Element (ODELAYE2)" treetype="template">
|
|
// ODELAYE2 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ODELAYE2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ODELAYE2: Output Fixed or Variable Delay Element
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
(* IODELAY_GROUP = <iodelay_group_name> *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTRL
|
|
|
|
ODELAYE2 #(
|
|
.CINVCTRL_SEL("FALSE"), // Enable dynamic clock inversion (FALSE, TRUE)
|
|
.DELAY_SRC("ODATAIN"), // Delay input (ODATAIN, CLKIN)
|
|
.HIGH_PERFORMANCE_MODE("FALSE"), // Reduced jitter ("TRUE"), Reduced power ("FALSE")
|
|
.ODELAY_TYPE("FIXED"), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
|
|
.ODELAY_VALUE(0), // Output delay tap setting (0-31)
|
|
.PIPE_SEL("FALSE"), // Select pipelined mode, FALSE, TRUE
|
|
.REFCLK_FREQUENCY(200.0), // IDELAYCTRL clock input frequency in MHz (190.0-210.0, 290.0-310.0).
|
|
.SIGNAL_PATTERN("DATA") // DATA, CLOCK input signal
|
|
)
|
|
ODELAYE2_inst (
|
|
.CNTVALUEOUT(CNTVALUEOUT), // 5-bit output: Counter value output
|
|
.DATAOUT(DATAOUT), // 1-bit output: Delayed data/clock output
|
|
.C(C), // 1-bit input: Clock input
|
|
.CE(CE), // 1-bit input: Active high enable increment/decrement input
|
|
.CINVCTRL(CINVCTRL), // 1-bit input: Dynamic clock inversion input
|
|
.CLKIN(CLKIN), // 1-bit input: Clock delay input
|
|
.CNTVALUEIN(CNTVALUEIN), // 5-bit input: Counter value input
|
|
.INC(INC), // 1-bit input: Increment / Decrement tap delay input
|
|
.LD(LD), // 1-bit input: Loads ODELAY_VALUE tap delay in VARIABLE mode, in VAR_LOAD or
|
|
// VAR_LOAD_PIPE mode, loads the value of CNTVALUEIN
|
|
|
|
.LDPIPEEN(LDPIPEEN), // 1-bit input: Enables the pipeline register to load data
|
|
.ODATAIN(ODATAIN), // 1-bit input: Output delay data input
|
|
.REGRST(REGRST) // 1-bit input: Active-high reset tap-delay input
|
|
);
|
|
|
|
// End of ODELAYE2_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="FIFOs" treetype="folder">
|
|
<Template label="Input FIFO (IN_FIFO)" treetype="template">
|
|
// IN_FIFO : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IN_FIFO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IN_FIFO: Input First-In, First-Out (FIFO)
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IN_FIFO #(
|
|
.ALMOST_EMPTY_VALUE(1), // Almost empty offset (1-2)
|
|
.ALMOST_FULL_VALUE(1), // Almost full offset (1-2)
|
|
.ARRAY_MODE("ARRAY_MODE_4_X_8"), // ARRAY_MODE_4_X_8, ARRAY_MODE_4_X_4
|
|
.SYNCHRONOUS_MODE("FALSE") // Clock synchronous (FALSE)
|
|
)
|
|
IN_FIFO_inst (
|
|
// FIFO Status Flags: 1-bit (each) output: Flags and other FIFO status outputs
|
|
.ALMOSTEMPTY(ALMOSTEMPTY), // 1-bit output: Almost empty
|
|
.ALMOSTFULL(ALMOSTFULL), // 1-bit output: Almost full
|
|
.EMPTY(EMPTY), // 1-bit output: Empty
|
|
.FULL(FULL), // 1-bit output: Full
|
|
// Q0-Q9: 8-bit (each) output: FIFO Outputs
|
|
.Q0(Q0), // 8-bit output: Channel 0
|
|
.Q1(Q1), // 8-bit output: Channel 1
|
|
.Q2(Q2), // 8-bit output: Channel 2
|
|
.Q3(Q3), // 8-bit output: Channel 3
|
|
.Q4(Q4), // 8-bit output: Channel 4
|
|
.Q5(Q5), // 8-bit output: Channel 5
|
|
.Q6(Q6), // 8-bit output: Channel 6
|
|
.Q7(Q7), // 8-bit output: Channel 7
|
|
.Q8(Q8), // 8-bit output: Channel 8
|
|
.Q9(Q9), // 8-bit output: Channel 9
|
|
// D0-D9: 4-bit (each) input: FIFO inputs
|
|
.D0(D0), // 4-bit input: Channel 0
|
|
.D1(D1), // 4-bit input: Channel 1
|
|
.D2(D2), // 4-bit input: Channel 2
|
|
.D3(D3), // 4-bit input: Channel 3
|
|
.D4(D4), // 4-bit input: Channel 4
|
|
.D5(D5), // 8-bit input: Channel 5
|
|
.D6(D6), // 8-bit input: Channel 6
|
|
.D7(D7), // 4-bit input: Channel 7
|
|
.D8(D8), // 4-bit input: Channel 8
|
|
.D9(D9), // 4-bit input: Channel 9
|
|
// FIFO Control Signals: 1-bit (each) input: Clocks, Resets and Enables
|
|
.RDCLK(RDCLK), // 1-bit input: Read clock
|
|
.RDEN(RDEN), // 1-bit input: Read enable
|
|
.RESET(RESET), // 1-bit input: Reset
|
|
.WRCLK(WRCLK), // 1-bit input: Write clock
|
|
.WREN(WREN) // 1-bit input: Write enable
|
|
);
|
|
|
|
// End of IN_FIFO_inst instantiation
|
|
</Template>
|
|
<Template label="Output FIFO (OUT_FIFO)" treetype="template">
|
|
// OUT_FIFO : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OUT_FIFO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OUT_FIFO: Output First-In, First-Out (FIFO) Buffer
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OUT_FIFO #(
|
|
.ALMOST_EMPTY_VALUE(1), // Almost empty offset (1-2)
|
|
.ALMOST_FULL_VALUE(1), // Almost full offset (1-2)
|
|
.ARRAY_MODE("ARRAY_MODE_8_X_4"), // ARRAY_MODE_8_X_4, ARRAY_MODE_4_X_4
|
|
.OUTPUT_DISABLE("FALSE"), // Disable output (FALSE, TRUE)
|
|
.SYNCHRONOUS_MODE("FALSE") // Must always be set to false.
|
|
)
|
|
OUT_FIFO_inst (
|
|
// FIFO Status Flags: 1-bit (each) output: Flags and other FIFO status outputs
|
|
.ALMOSTEMPTY(ALMOSTEMPTY), // 1-bit output: Almost empty flag
|
|
.ALMOSTFULL(ALMOSTFULL), // 1-bit output: Almost full flag
|
|
.EMPTY(EMPTY), // 1-bit output: Empty flag
|
|
.FULL(FULL), // 1-bit output: Full flag
|
|
// Q0-Q9: 4-bit (each) output: FIFO Outputs
|
|
.Q0(Q0), // 4-bit output: Channel 0 output bus
|
|
.Q1(Q1), // 4-bit output: Channel 1 output bus
|
|
.Q2(Q2), // 4-bit output: Channel 2 output bus
|
|
.Q3(Q3), // 4-bit output: Channel 3 output bus
|
|
.Q4(Q4), // 4-bit output: Channel 4 output bus
|
|
.Q5(Q5), // 8-bit output: Channel 5 output bus
|
|
.Q6(Q6), // 8-bit output: Channel 6 output bus
|
|
.Q7(Q7), // 4-bit output: Channel 7 output bus
|
|
.Q8(Q8), // 4-bit output: Channel 8 output bus
|
|
.Q9(Q9), // 4-bit output: Channel 9 output bus
|
|
// D0-D9: 8-bit (each) input: FIFO inputs
|
|
.D0(D0), // 8-bit input: Channel 0 input bus
|
|
.D1(D1), // 8-bit input: Channel 1 input bus
|
|
.D2(D2), // 8-bit input: Channel 2 input bus
|
|
.D3(D3), // 8-bit input: Channel 3 input bus
|
|
.D4(D4), // 8-bit input: Channel 4 input bus
|
|
.D5(D5), // 8-bit input: Channel 5 input bus
|
|
.D6(D6), // 8-bit input: Channel 6 input bus
|
|
.D7(D7), // 8-bit input: Channel 7 input bus
|
|
.D8(D8), // 8-bit input: Channel 8 input bus
|
|
.D9(D9), // 8-bit input: Channel 9 input bus
|
|
// FIFO Control Signals: 1-bit (each) input: Clocks, Resets and Enables
|
|
.RDCLK(RDCLK), // 1-bit input: Read clock
|
|
.RDEN(RDEN), // 1-bit input: Read enable
|
|
.RESET(RESET), // 1-bit input: Active high reset
|
|
.WRCLK(WRCLK), // 1-bit input: Write clock
|
|
.WREN(WREN) // 1-bit input: Write enable
|
|
);
|
|
|
|
// End of OUT_FIFO_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="I/O SERDES" treetype="folder">
|
|
<Template label="Input SERial/DESerializer with Bitslip (ISERDESE2)" treetype="template">
|
|
// ISERDESE2 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ISERDESE2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ISERDESE2: Input SERial/DESerializer with Bitslip
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ISERDESE2 #(
|
|
.DATA_RATE("DDR"), // DDR, SDR
|
|
.DATA_WIDTH(4), // Parallel data width (2-8,10,14)
|
|
.DYN_CLKDIV_INV_EN("FALSE"), // Enable DYNCLKDIVINVSEL inversion (FALSE, TRUE)
|
|
.DYN_CLK_INV_EN("FALSE"), // Enable DYNCLKINVSEL inversion (FALSE, TRUE)
|
|
// INIT_Q1 - INIT_Q4: Initial value on the Q outputs (0/1)
|
|
.INIT_Q1(1'b0),
|
|
.INIT_Q2(1'b0),
|
|
.INIT_Q3(1'b0),
|
|
.INIT_Q4(1'b0),
|
|
.INTERFACE_TYPE("MEMORY"), // MEMORY, MEMORY_DDR3, MEMORY_QDR, NETWORKING, OVERSAMPLE
|
|
.IOBDELAY("NONE"), // NONE, BOTH, IBUF, IFD
|
|
.NUM_CE(2), // Number of clock enables (1,2)
|
|
.OFB_USED("FALSE"), // Select OFB path (FALSE, TRUE)
|
|
.SERDES_MODE("MASTER"), // MASTER, SLAVE
|
|
// SRVAL_Q1 - SRVAL_Q4: Q output values when SR is used (0/1)
|
|
.SRVAL_Q1(1'b0),
|
|
.SRVAL_Q2(1'b0),
|
|
.SRVAL_Q3(1'b0),
|
|
.SRVAL_Q4(1'b0)
|
|
)
|
|
ISERDESE2_inst (
|
|
.O(O), // 1-bit output: Combinatorial output
|
|
// Q1 - Q8: 1-bit (each) output: Registered data outputs
|
|
.Q1(Q1),
|
|
.Q2(Q2),
|
|
.Q3(Q3),
|
|
.Q4(Q4),
|
|
.Q5(Q5),
|
|
.Q6(Q6),
|
|
.Q7(Q7),
|
|
.Q8(Q8),
|
|
// SHIFTOUT1, SHIFTOUT2: 1-bit (each) output: Data width expansion output ports
|
|
.SHIFTOUT1(SHIFTOUT1),
|
|
.SHIFTOUT2(SHIFTOUT2),
|
|
.BITSLIP(BITSLIP), // 1-bit input: The BITSLIP pin performs a Bitslip operation synchronous to
|
|
// CLKDIV when asserted (active High). Subsequently, the data seen on the Q1
|
|
// to Q8 output ports will shift, as in a barrel-shifter operation, one
|
|
// position every time Bitslip is invoked (DDR operation is different from
|
|
// SDR).
|
|
|
|
// CE1, CE2: 1-bit (each) input: Data register clock enable inputs
|
|
.CE1(CE1),
|
|
.CE2(CE2),
|
|
.CLKDIVP(CLKDIVP), // 1-bit input: TBD
|
|
// Clocks: 1-bit (each) input: ISERDESE2 clock input ports
|
|
.CLK(CLK), // 1-bit input: High-speed clock
|
|
.CLKB(CLKB), // 1-bit input: High-speed secondary clock
|
|
.CLKDIV(CLKDIV), // 1-bit input: Divided clock
|
|
.OCLK(OCLK), // 1-bit input: High speed output clock used when INTERFACE_TYPE="MEMORY"
|
|
// Dynamic Clock Inversions: 1-bit (each) input: Dynamic clock inversion pins to switch clock polarity
|
|
.DYNCLKDIVSEL(DYNCLKDIVSEL), // 1-bit input: Dynamic CLKDIV inversion
|
|
.DYNCLKSEL(DYNCLKSEL), // 1-bit input: Dynamic CLK/CLKB inversion
|
|
// Input Data: 1-bit (each) input: ISERDESE2 data input ports
|
|
.D(D), // 1-bit input: Data input
|
|
.DDLY(DDLY), // 1-bit input: Serial data from IDELAYE2
|
|
.OFB(OFB), // 1-bit input: Data feedback from OSERDESE2
|
|
.OCLKB(OCLKB), // 1-bit input: High speed negative edge output clock
|
|
.RST(RST), // 1-bit input: Active high asynchronous reset
|
|
// SHIFTIN1, SHIFTIN2: 1-bit (each) input: Data width expansion input ports
|
|
.SHIFTIN1(SHIFTIN1),
|
|
.SHIFTIN2(SHIFTIN2)
|
|
);
|
|
|
|
// End of ISERDESE2_inst instantiation
|
|
</Template>
|
|
<Template label="Output SERial/DESerializer with bitslip (OSERDESE2)" treetype="template">
|
|
// OSERDESE2 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OSERDESE2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OSERDESE2: Output SERial/DESerializer with bitslip
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OSERDESE2 #(
|
|
.DATA_RATE_OQ("DDR"), // DDR, SDR
|
|
.DATA_RATE_TQ("DDR"), // DDR, BUF, SDR
|
|
.DATA_WIDTH(4), // Parallel data width (2-8,10,14)
|
|
.INIT_OQ(1'b0), // Initial value of OQ output (1'b0,1'b1)
|
|
.INIT_TQ(1'b0), // Initial value of TQ output (1'b0,1'b1)
|
|
.SERDES_MODE("MASTER"), // MASTER, SLAVE
|
|
.SRVAL_OQ(1'b0), // OQ output value when SR is used (1'b0,1'b1)
|
|
.SRVAL_TQ(1'b0), // TQ output value when SR is used (1'b0,1'b1)
|
|
.TBYTE_CTL("FALSE"), // Enable tristate byte operation (FALSE, TRUE)
|
|
.TBYTE_SRC("FALSE"), // Tristate byte source (FALSE, TRUE)
|
|
.TRISTATE_WIDTH(4) // 3-state converter width (1,4)
|
|
)
|
|
OSERDESE2_inst (
|
|
.OFB(OFB), // 1-bit output: Feedback path for data
|
|
.OQ(OQ), // 1-bit output: Data path output
|
|
// SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
|
|
.SHIFTOUT1(SHIFTOUT1),
|
|
.SHIFTOUT2(SHIFTOUT2),
|
|
.TBYTEOUT(TBYTEOUT), // 1-bit output: Byte group tristate
|
|
.TFB(TFB), // 1-bit output: 3-state control
|
|
.TQ(TQ), // 1-bit output: 3-state control
|
|
.CLK(CLK), // 1-bit input: High speed clock
|
|
.CLKDIV(CLKDIV), // 1-bit input: Divided clock
|
|
// D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
|
|
.D1(D1),
|
|
.D2(D2),
|
|
.D3(D3),
|
|
.D4(D4),
|
|
.D5(D5),
|
|
.D6(D6),
|
|
.D7(D7),
|
|
.D8(D8),
|
|
.OCE(OCE), // 1-bit input: Output data clock enable
|
|
.RST(RST), // 1-bit input: Reset
|
|
// SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
|
|
.SHIFTIN1(SHIFTIN1),
|
|
.SHIFTIN2(SHIFTIN2),
|
|
// T1 - T4: 1-bit (each) input: Parallel 3-state inputs
|
|
.T1(T1),
|
|
.T2(T2),
|
|
.T3(T3),
|
|
.T4(T4),
|
|
.TBYTEIN(TBYTEIN), // 1-bit input: Byte group tristate
|
|
.TCE(TCE) // 1-bit input: 3-state clock enable
|
|
);
|
|
|
|
// End of OSERDESE2_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Input Buffers" treetype="folder">
|
|
<Template label="Single-ended Buffer (IBUF)" treetype="template">
|
|
// IBUF : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUF_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUF: Single-ended Input Buffer
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUF #(
|
|
.IBUF_LOW_PWR("TRUE"), // Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
) IBUF_inst (
|
|
.O(O), // Buffer output
|
|
.I(I) // Buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUF_inst instantiation
|
|
</Template>
|
|
<Template label="Single-ended Buffer w/ Disable (IBUF_IBUFDISABLE)" treetype="template">
|
|
// IBUF_IBUFDISABLE : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUF_IBUFDISABLE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUF_IBUFDISABLE: Single-ended Input Buffer with Disable
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUF_IBUFDISABLE #(
|
|
.IBUF_LOW_PWR("TRUE"), // Low power ("TRUE") vs. performance ("FALSE") for referenced I/O standards
|
|
.IOSTANDARD("DEFAULT"), // Specify the input I/O standard
|
|
.USE_IBUFDISABLE("TRUE") // Set to "TRUE" to enable IBUFDISABLE feature
|
|
) IBUF_IBUFDISABLE_inst (
|
|
.O(O), // Buffer output
|
|
.I(I), // Buffer input (connect directly to top-level port)
|
|
.IBUFDISABLE(IBUFDISABLE) // Buffer disable input, low=disable
|
|
);
|
|
|
|
// End of IBUF_IBUFDISABLE_inst instantiation
|
|
</Template>
|
|
<Template label="Single-ended Buffer w/ Termination Disable (IBUF_INTERMDISABLE)" treetype="template">
|
|
// IBUF_INTERMDISABLE : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUF_INTERMDISABLE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUF_INTERMDISABLE: Single-ended Input Buffer with Termination Input Disable
|
|
// May only be placed in High Range (HR) Banks
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUF_INTERMDISABLE #(
|
|
.IBUF_LOW_PWR("TRUE"), // Low power ("TRUE") vs. performance ("FALSE") for referenced I/O standards
|
|
.IOSTANDARD("DEFAULT"), // Specify the input I/O standard
|
|
.USE_IBUFDISABLE("TRUE") // Set to "TRUE" to enable IBUFDISABLE feature
|
|
) IBUF_INTERMDISABLE_inst (
|
|
.O(O), // Buffer output
|
|
.I(I), // Buffer input (connect directly to top-level port)
|
|
.IBUFDISABLE(IBUFDISABLE), // Buffer disable input, low=disable
|
|
.INTERMDISABLE(INTERMDISABLE) // Input Termination Disable
|
|
);
|
|
|
|
// End of IBUF_INTERMDISABLE_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer (IBUFDS)" treetype="template">
|
|
// IBUFDS : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFDS: Differential Input Buffer
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFDS #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination
|
|
.IBUF_LOW_PWR("TRUE"), // Low power="TRUE", Highest performance="FALSE"
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
) IBUFDS_inst (
|
|
.O(O), // Buffer output
|
|
.I(I), // Diff_p buffer input (connect directly to top-level port)
|
|
.IB(IB) // Diff_n buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUFDS_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer w/ Disable (IBUFDS_IBUFDISABLE)" treetype="template">
|
|
// IBUFDS_IBUFDISABLE : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFDS_IBUFDISABLE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFDS_IBUFDISABLE: Differential Input Buffer with Input Disable
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFDS_IBUFDISABLE #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination
|
|
.IBUF_LOW_PWR("TRUE"), // Low power="TRUE", Highest performance="FALSE"
|
|
.IOSTANDARD("DEFAULT"), // Specify the input I/O standard
|
|
.USE_IBUFDISABLE("TRUE") // Set to "TRUE" to enable IBUFDISABLE feature
|
|
) IBUFDS_IBUFDISABLE_inst (
|
|
.O(O), // Buffer output
|
|
.I(I), // Diff_p buffer input (connect directly to top-level port)
|
|
.IB(IB), // Diff_n buffer input (connect directly to top-level port)
|
|
.IBUFDISABLE(IBUFDISABLE) // Buffer disable input, low=disable
|
|
);
|
|
|
|
// End of IBUFDS_IBUFDISABLE_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer w/ Termination Disable (IBUFDS_INTERMDISABLE)" treetype="template">
|
|
// IBUFDS_INTERMDISABLE : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFDS_INTERMDISABLE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFDS_INTERMDISABLE: Differential Input Buffer with Input Termination Disable
|
|
// May only be placed in High Range (HR) Banks
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFDS_INTERMDISABLE #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination
|
|
.IBUF_LOW_PWR("TRUE"), // Low power="TRUE", Highest performance="FALSE"
|
|
.IOSTANDARD("DEFAULT"), // Specify the input I/O standard
|
|
.USE_IBUFDISABLE("TRUE") // Set to "TRUE" to enable IBUFDISABLE feature
|
|
) IBUFDS_INTERMDISABLE_inst (
|
|
.O(O), // Buffer output
|
|
.I(I), // Diff_p buffer input (connect directly to top-level port)
|
|
.IB(IB), // Diff_n buffer input (connect directly to top-level port)
|
|
.IBUFDISABLE(IBUFDISABLE), // Buffer disable input, low=disable
|
|
.INTERMDISABLE(INTERMDISABLE) // Input Termination Disable
|
|
);
|
|
|
|
// End of IBUFDS_INTERMDISABLE_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer with Differential Output (IBUFDS_DIFF_OUT)" treetype="template">
|
|
// IBUFDS_DIFF_OUT : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFDS_DIFF_OUT_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFDS_DIFF_OUT: Differential Input Buffer with Differential Output
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFDS_DIFF_OUT #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination, "TRUE"/"FALSE"
|
|
.IBUF_LOW_PWR("TRUE"), // Low power="TRUE", Highest performance="FALSE"
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
) IBUFDS_DIFF_OUT_inst (
|
|
.O(O), // Buffer diff_p output
|
|
.OB(OB), // Buffer diff_n output
|
|
.I(I), // Diff_p buffer input (connect directly to top-level port)
|
|
.IB(IB) // Diff_n buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUFDS_DIFF_OUT_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer with Differential Output w/ Input Disable (IBUFDS_DIFF_OUT_IBUFDISABLE)" treetype="template">
|
|
// IBUFDS_DIFF_OUT_IBUFDISABLE : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFDS_DIFF_OUT_IBUFDISABLE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFDS_DIFF_OUT_IBUFDISABLE: Differential Input Buffer with Differential Output with Input Disable
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFDS_DIFF_OUT_IBUFDISABLE #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination, "TRUE"/"FALSE"
|
|
.IBUF_LOW_PWR("TRUE"), // Low power="TRUE", Highest performance="FALSE"
|
|
.IOSTANDARD("DEFAULT"), // Specify the input I/O standard
|
|
.USE_IBUFDISABLE("TRUE") // Set to "TRUE" to enable IBUFDISABLE feature
|
|
) IBUFDS_DIFF_OUT_IBUFDISABLE_inst (
|
|
.O(O), // Buffer diff_p output
|
|
.OB(OB), // Buffer diff_n output
|
|
.I(I), // Diff_p buffer input (connect directly to top-level port)
|
|
.IB(IB), // Diff_n buffer input (connect directly to top-level port)
|
|
.IBUFDISABLE(IBUFDISABLE) // Buffer disable input, low=disable
|
|
);
|
|
|
|
// End of IBUFDS_DIFF_OUT_IBUFDISABLE_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer with Differential Output w/ Input Termination Disable (IBUFDS_DIFF_OUT_INTERMDISABLE)" treetype="template">
|
|
// IBUFDS_DIFF_OUT_INTERMDISABLE : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFDS_DIFF_OUT_INTERMDISABLE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFDS_DIFF_OUT_INTERMDISABLE: Differential Input Buffer with Differential Output with Input Termination Disable
|
|
// May only be placed in High Range (HR) Banks
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFDS_DIFF_OUT_INTERMDISABLE #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination, "TRUE"/"FALSE"
|
|
.IBUF_LOW_PWR("TRUE"), // Low power="TRUE", Highest performance="FALSE"
|
|
.IOSTANDARD("DEFAULT"), // Specify the input I/O standard
|
|
.USE_IBUFDISABLE("TRUE") // Set to "TRUE" to enable IBUFDISABLE feature
|
|
) IBUFDS_DIFF_OUT_INTERMDISABLE_inst (
|
|
.O(O), // Buffer diff_p output
|
|
.OB(OB), // Buffer diff_n output
|
|
.I(I), // Diff_p buffer input (connect directly to top-level port)
|
|
.IB(IB), // Diff_n buffer input (connect directly to top-level port)
|
|
.IBUFDISABLE(IBUFDISABLE), // Buffer disable input, low=disable
|
|
.INTERMDISABLE(INTERMDISABLE) // Input Termination Disable
|
|
);
|
|
|
|
// End of IBUFDS_DIFF_OUT_INTERMDISABLE_inst instantiation
|
|
</Template>
|
|
<Template label="Single-ended Global Clock Buffer (IBUFG)" treetype="template">
|
|
// IBUFG : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFG_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFG: Single-ended global clock input buffer
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFG #(
|
|
.IBUF_LOW_PWR("TRUE"), // Low power="TRUE", Highest performance="FALSE"
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
) IBUFG_inst (
|
|
.O(O), // Clock buffer output
|
|
.I(I) // Clock buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUFG_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Global Clock (IBUFGDS)" treetype="template">
|
|
// IBUFGDS : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFGDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFGDS: Differential Global Clock Input Buffer
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFGDS #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination
|
|
.IBUF_LOW_PWR("TRUE"), // Low power="TRUE", Highest performance="FALSE"
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
) IBUFGDS_inst (
|
|
.O(O), // Clock buffer output
|
|
.I(I), // Diff_p clock buffer input (connect directly to top-level port)
|
|
.IB(IB) // Diff_n clock buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUFGDS_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Global Clock Buffer with Differential Output (IBUFGDS_DIFF_OUT)" treetype="template">
|
|
// IBUFGDS_DIFF_OUT : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFGDS_DIFF_OUT_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFGDS_DIFF_OUT: Differential Global Clock Buffer with Differential Output
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFGDS_DIFF_OUT #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination, "TRUE"/"FALSE"
|
|
.IBUF_LOW_PWR("TRUE"), // Low power="TRUE", Highest performance="FALSE"
|
|
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
|
|
) IBUFGDS_DIFF_OUT_inst (
|
|
.O(O), // Buffer diff_p output
|
|
.OB(OB), // Buffer diff_n output
|
|
.I(I), // Diff_p buffer input (connect directly to top-level port)
|
|
.IB(IB) // Diff_n buffer input (connect directly to top-level port)
|
|
);
|
|
|
|
// End of IBUFGDS_DIFF_OUT_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Output Buffers" treetype="folder">
|
|
<Template label="Single-ended Buffer (OBUF)" treetype="template">
|
|
// OBUF : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OBUF_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OBUF: Single-ended Output Buffer
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OBUF #(
|
|
.DRIVE(12), // Specify the output drive strength
|
|
.IOSTANDARD("DEFAULT"), // Specify the output I/O standard
|
|
.SLEW("SLOW") // Specify the output slew rate
|
|
) OBUF_inst (
|
|
.O(O), // Buffer output (connect directly to top-level port)
|
|
.I(I) // Buffer input
|
|
);
|
|
|
|
// End of OBUF_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer (OBUFDS)" treetype="template">
|
|
|
|
// OBUFDS : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OBUFDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OBUFDS: Differential Output Buffer
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OBUFDS #(
|
|
.IOSTANDARD("DEFAULT"), // Specify the output I/O standard
|
|
.SLEW("SLOW") // Specify the output slew rate
|
|
) OBUFDS_inst (
|
|
.O(O), // Diff_p output (connect directly to top-level port)
|
|
.OB(OB), // Diff_n output (connect directly to top-level port)
|
|
.I(I) // Buffer input
|
|
);
|
|
|
|
// End of OBUFDS_inst instantiation
|
|
</Template>
|
|
<Template label="Single-ended 3-state Buffer (OBUFT)" treetype="template">
|
|
// OBUFT : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OBUFT_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OBUFT: Single-ended 3-state Output Buffer
|
|
// All devices
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OBUFT #(
|
|
.DRIVE(12), // Specify the output drive strength
|
|
.IOSTANDARD("DEFAULT"), // Specify the output I/O standard
|
|
.SLEW("SLOW") // Specify the output slew rate
|
|
) OBUFT_inst (
|
|
.O(O), // Buffer output (connect directly to top-level port)
|
|
.I(I), // Buffer input
|
|
.T(T) // 3-state enable input
|
|
);
|
|
|
|
// End of OBUFT_inst instantiation
|
|
</Template>
|
|
<Template label="Differential 3-state Buffer (OBUFTDS)" treetype="template">
|
|
// OBUFTDS : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (OBUFTDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// OBUFTDS: Differential 3-state Output Buffer
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OBUFTDS #(
|
|
.IOSTANDARD("DEFAULT"), // Specify the output I/O standard
|
|
.SLEW("SLOW") // Specify the output slew rate
|
|
) OBUFTDS_inst (
|
|
.O(O), // Diff_p output (connect directly to top-level port)
|
|
.OB(OB), // Diff_n output (connect directly to top-level port)
|
|
.I(I), // Buffer input
|
|
.T(T) // 3-state enable input
|
|
);
|
|
|
|
// End of OBUFTDS_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Bi-directional Buffers" treetype="folder">
|
|
<Template label="Single-ended Buffer (IOBUF)" treetype="template">
|
|
// IOBUF : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IOBUF_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IOBUF: Single-ended Bi-directional Buffer
|
|
// All devices
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IOBUF #(
|
|
.DRIVE(12), // Specify the output drive strength
|
|
.IBUF_LOW_PWR("TRUE"), // Low Power - "TRUE", High Performance = "FALSE"
|
|
.IOSTANDARD("DEFAULT"), // Specify the I/O standard
|
|
.SLEW("SLOW") // Specify the output slew rate
|
|
) IOBUF_inst (
|
|
.O(O), // Buffer output
|
|
.IO(IO), // Buffer inout port (connect directly to top-level port)
|
|
.I(I), // Buffer input
|
|
.T(T) // 3-state enable input, high=input, low=output
|
|
);
|
|
|
|
// End of IOBUF_inst instantiation
|
|
</Template>
|
|
<Template label="Single-ended Buffer w/ input and DCI disable (IOBUF_DCIEN)" treetype="template">
|
|
// IOBUF_DCIEN : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IOBUF_DCIEN_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IOBUF_DCIEN: Single-ended Bi-directional Buffer with Digital Controlled Impedance (DCI)
|
|
// and Input path enable/disable
|
|
// May only be placed in High Performance (HP) Banks
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IOBUF_DCIEN #(
|
|
.DRIVE(12), // Specify the output drive strength
|
|
.IBUF_LOW_PWR("TRUE"), // Low Power - "TRUE", High Performance = "FALSE"
|
|
.IOSTANDARD("DEFAULT"), // Specify the I/O standard
|
|
.SLEW("SLOW"), // Specify the output slew rate
|
|
.USE_IBUFDISABLE("TRUE") // Use IBUFDISABLE function, "TRUE" or "FALSE"
|
|
) IOBUF_DCIEN_inst (
|
|
.O(O), // Buffer output
|
|
.IO(IO), // Buffer inout port (connect directly to top-level port)
|
|
.DCITERMDISABLE(DCITERMDISABLE), // DCI Termination enable input
|
|
.I(I), // Buffer input
|
|
.IBUFDISABLE(IBUFDISABLE), // Input disable input, low=disable
|
|
.T(T) // 3-state enable input, high=input, low=output
|
|
);
|
|
|
|
// End of IOBUF_DCIEN_inst instantiation
|
|
</Template>
|
|
<Template label="Single-ended Buffer w/ input and INTERM disable (IOBUF_INTERMDISABLE)" treetype="template">
|
|
// IOBUF_INTERMDISABLE : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IOBUF_INTERMDISABLE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IOBUF_INTERMDISABLE: Single-ended Bi-directional Buffer with Input Termination
|
|
// and Input path enable/disable
|
|
// May only be placed in High Range (HR) Banks
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IOBUF_INTERMDISABLE #(
|
|
.DRIVE(12), // Specify the output drive strength
|
|
.IBUF_LOW_PWR("TRUE"), // Low Power - "TRUE", High Performance = "FALSE"
|
|
.IOSTANDARD("DEFAULT"), // Specify the I/O standard
|
|
.SLEW("SLOW"), // Specify the output slew rate
|
|
.USE_IBUFDISABLE("TRUE") // Use IBUFDISABLE function, "TRUE" or "FALSE"
|
|
) IOBUF_INTERMDISABLE_inst (
|
|
.O(O), // Buffer output
|
|
.IO(IO), // Buffer inout port (connect directly to top-level port)
|
|
.I(I), // Buffer input
|
|
.IBUFDISABLE(IBUFDISABLE), // Input disable input, low=disable
|
|
.INTERMDISABLE(INTERMDISABLE), // Input termination disable input
|
|
.T(T) // 3-state enable input, high=input, low=output
|
|
);
|
|
|
|
// End of IOBUF_INTERMDISABLE_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer (IOBUFDS)" treetype="template">
|
|
// IOBUFDS : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IOBUFDS_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IOBUFDS: Differential Bi-directional Buffer
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IOBUFDS #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination ("TRUE"/"FALSE")
|
|
.IBUF_LOW_PWR("TRUE"), // Low Power - "TRUE", High Performance = "FALSE"
|
|
.IOSTANDARD("BLVDS_25"), // Specify the I/O standard
|
|
.SLEW("SLOW") // Specify the output slew rate
|
|
) IOBUFDS_inst (
|
|
.O(O), // Buffer output
|
|
.IO(IO), // Diff_p inout (connect directly to top-level port)
|
|
.IOB(IOB), // Diff_n inout (connect directly to top-level port)
|
|
.I(I), // Buffer input
|
|
.T(T) // 3-state enable input, high=input, low=output
|
|
);
|
|
|
|
// End of IOBUFDS_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer w/ input and DCI disable (IOBUFDS_DCIEN)" treetype="template">
|
|
// IOBUFDS_DCIEN : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IOBUFDS_DCIEN_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IOBUFDS_DCIEN: Differential Bi-directional Buffer with Digital Controlled Impedance (DCI)
|
|
// and Input path enable/disable
|
|
// May only be placed in High Performance (HP) Banks
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IOBUFDS_DCIEN #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination ("TRUE"/"FALSE")
|
|
.IBUF_LOW_PWR("TRUE"), // Low Power - "TRUE", High Performance = "FALSE"
|
|
.IOSTANDARD("BLVDS_25"), // Specify the I/O standard
|
|
.SLEW("SLOW"), // Specify the output slew rate
|
|
.USE_IBUFDISABLE("TRUE") // Use IBUFDISABLE function, "TRUE" or "FALSE"
|
|
) IOBUFDS_DCIEN_inst (
|
|
.O(O), // Buffer output
|
|
.IO(IO), // Diff_p inout (connect directly to top-level port)
|
|
.IOB(IOB), // Diff_n inout (connect directly to top-level port)
|
|
.DCITERMDISABLE(DCITERMDISABLE), // DCI Termination enable input
|
|
.I(I), // Buffer input
|
|
.IBUFDISABLE(IBUFDISABLE), // Input disable input, low=disable
|
|
.T(T) // 3-state enable input, high=input, low=output
|
|
);
|
|
|
|
// End of IOBUFDS_DCIEN_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer w/ input and input termination disable (IOBUFDS_INTERMDISABLE)" treetype="template">
|
|
// IOBUFDS_INTERMDISABLE : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IOBUFDS_INTERMDISABLE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IOBUFDS_INTERMDISABLE: Differential Bi-directional Buffer with Input Termination
|
|
// and Input path enable/disable
|
|
// May only be placed in High Range (HR) Banks
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IOBUFDS_INTERMDISABLE #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination ("TRUE"/"FALSE")
|
|
.IBUF_LOW_PWR("TRUE"), // Low Power - "TRUE", High Performance = "FALSE"
|
|
.IOSTANDARD("BLVDS_25"), // Specify the I/O standard
|
|
.SLEW("SLOW"), // Specify the output slew rate
|
|
.USE_IBUFDISABLE("TRUE") // Use IBUFDISABLE function, "TRUE" or "FALSE"
|
|
) IOBUFDS_INTERMDISABLE_inst (
|
|
.O(O), // Buffer output
|
|
.IO(IO), // Diff_p inout (connect directly to top-level port)
|
|
.IOB(IOB), // Diff_n inout (connect directly to top-level port)
|
|
.I(I), // Buffer input
|
|
.IBUFDISABLE(IBUFDISABLE), // Input disable input, low=disable
|
|
.INTERMDISABLE(INTERMDISABLE), // Input termination disable input
|
|
.T(T) // 3-state enable input, high=input, low=output
|
|
);
|
|
|
|
// End of IOBUFDS_INTERMDISABLE_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer with Differential Output (IOBUFDS_DIFF_OUT)" treetype="template">
|
|
// IOBUFDS_DIFF_OUT : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IOBUFDS_DIFF_OUT_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IOBUFDS_DIFF_OUT: Differential Bi-directional Buffer with Differential Output
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IOBUFDS_DIFF_OUT #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination ("TRUE"/"FALSE")
|
|
.IBUF_LOW_PWR("TRUE"), // Low Power - "TRUE", High Performance = "FALSE"
|
|
.IOSTANDARD("BLVDS_25") // Specify the I/O standard
|
|
) IOBUFDS_DIFF_OUT_inst (
|
|
.O(O), // Buffer p-side output
|
|
.OB(OB), // Buffer n-side output
|
|
.IO(IO), // Diff_p inout (connect directly to top-level port)
|
|
.IOB(IOB), // Diff_n inout (connect directly to top-level port)
|
|
.I(I), // Buffer input
|
|
.TM(TM), // 3-state enable input, high=input, low=output
|
|
.TS(TS) // 3-state enable input, high=output, low=input
|
|
);
|
|
|
|
// End of IOBUFDS_DIFF_OUT_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Buffer w/ Differential Output, input and DCI disable (IOBUFDS_DIFF_OUT_DCIEN)" treetype="template">
|
|
// IOBUFDS_DIFF_OUT_DCIEN : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IOBUFDS_DIFF_OUT_DCIEN_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IOBUFDS_DIFF_OUT_DCIEN: Differential Bi-directional Buffer with Differential Output,
|
|
// Digital Controlled Impedance (DCI)and Input path enable/disable
|
|
// May only be placed in High Performance (HP) Banks
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IOBUFDS_DIFF_OUT_DCIEN #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination ("TRUE"/"FALSE")
|
|
.IBUF_LOW_PWR("TRUE"), // Low Power - "TRUE", High Performance = "FALSE"
|
|
.IOSTANDARD("BLVDS_25"), // Specify the I/O standard
|
|
.USE_IBUFDISABLE("TRUE") // Use IBUFDISABLE function, "TRUE" or "FALSE"
|
|
) IOBUFDS_DIFF_OUT_DCIEN_inst (
|
|
.O(O), // Buffer p-side output
|
|
.OB(OB), // Buffer n-side output
|
|
.IO(IO), // Diff_p inout (connect directly to top-level port)
|
|
.IOB(IOB), // Diff_n inout (connect directly to top-level port)
|
|
.DCITERMDISABLE(DCITERMDISABLE), // DCI Termination enable input
|
|
.I(I), // Buffer input
|
|
.IBUFDISABLE(IBUFDISABLE), // Input disable input, low=disable
|
|
.TM(TM), // 3-state enable input, high=input, low=output
|
|
.TS(TS) // 3-state enable input, high=output, low=input
|
|
);
|
|
|
|
// End of IOBUFDS_DIFF_OUT_DCIEN_inst instantiation
|
|
</Template>
|
|
<Template label="Differential Global Clock Buffer w/ Differential Output, INTERM and IBUF disable (IOBUFDS_DIFF_OUT_INTERMDISABLE)" treetype="template">
|
|
// IOBUFDS_DIFF_OUT_INTERMDISABLE : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IOBUFDS_DIFF_OUT_INTERMDISABLE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IOBUFDS_DIFF_OUT_INTERMDISABLE: Differential Global Clock Buffer with Differential Output
|
|
// Input Termination and Input Path Disable
|
|
// May only be placed in High Range (HR) Banks
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IOBUFDS_DIFF_OUT_INTERMDISABLE #(
|
|
.DIFF_TERM("FALSE"), // Differential Termination, "TRUE"/"FALSE"
|
|
.IBUF_LOW_PWR("TRUE"), // Low power="TRUE", Highest performance="FALSE"
|
|
.IOSTANDARD("DEFAULT"), // Specify the input I/O standard
|
|
.USE_IBUFDISABLE("TRUE") // Set to "TRUE" to enable IBUFDISABLE feature
|
|
) IOBUFDS_DIFF_OUT_INTERMDISABLE_inst (
|
|
.O(O), // Buffer p-side output
|
|
.OB(OB), // Buffer n-side output
|
|
.IO(IO), // Diff_p inout (connect directly to top-level port)
|
|
.IOB(IOB), // Diff_n inout (connect directly to top-level port)
|
|
.I(I), // Buffer input
|
|
.INTERMDISABLE(INTERMDISABLE), // Input termination disable input
|
|
.IBUFDISABLE(IBUFDISABLE), // Input disable input, low=disable
|
|
.TM(TM), // 3-state enable input, high=input, low=output
|
|
.TS(TS) // 3-state enable input, high=output, low=input
|
|
);
|
|
|
|
// End of IOBUFDS_DIFF_OUT_INTERMDISABLE_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Weak drivers" treetype="folder">
|
|
<Template label="PULLUP" treetype="template">
|
|
// PULLUP : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (PULLUP_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design.
|
|
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// PULLUP: I/O Buffer Weak Pull-up
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
PULLUP PULLUP_inst (
|
|
.O(O) // Pullup output (connect directly to top-level port)
|
|
);
|
|
|
|
// End of PULLUP_inst instantiation
|
|
</Template>
|
|
<Template label="PULLDOWN" treetype="template">
|
|
// PULLDOWN : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (PULLDOWN_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// PULLDOWN: I/O Buffer Weak Pull-down
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
PULLDOWN PULLDOWN_inst (
|
|
.O(O) // Pulldown output (connect directly to top-level port)
|
|
);
|
|
|
|
// End of PULLDOWN_inst instantiation
|
|
</Template>
|
|
<Template label="KEEPER" treetype="template">
|
|
// KEEPER : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (KEEPER_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// KEEPER: I/O Buffer Weak Keeper
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
KEEPER KEEPER_inst (
|
|
.O(O) // Keeper output (connect directly to top-level port)
|
|
);
|
|
|
|
// End of KEEPER_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="DDR Registers" treetype="folder">
|
|
<Template label="Dual-Clock, Input DDR Register (IDDR_2CLK)" treetype="template">
|
|
// IDDR_2CLK : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IDDR_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IDDR_2CLK: Dual-Clock, Input Double Data Rate Input Register with
|
|
// Set, Reset and Clock Enable.
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IDDR_2CLK #(
|
|
.DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE", "SAME_EDGE"
|
|
// or "SAME_EDGE_PIPELINED"
|
|
.INIT_Q1(1'b0), // Initial value of Q1: 1'b0 or 1'b1
|
|
.INIT_Q2(1'b0), // Initial value of Q2: 1'b0 or 1'b1
|
|
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
|
|
) IDDR_2CLK_inst (
|
|
.Q1(Q1), // 1-bit output for positive edge of clock
|
|
.Q2(Q2), // 1-bit output for negative edge of clock
|
|
.C(C), // 1-bit primary clock input
|
|
.CB(CB), // 1-bit secondary clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.D(D), // 1-bit DDR data input
|
|
.R(R), // 1-bit reset
|
|
.S(S) // 1-bit set
|
|
);
|
|
|
|
// End of IDDR_2CLK_inst instantiation
|
|
</Template>
|
|
<Template label="Input DDR Register (IDDR)" treetype="template">
|
|
// IDDR : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IDDR_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IDDR: Input Double Data Rate Input Register with Set, Reset
|
|
// and Clock Enable.
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IDDR #(
|
|
.DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE", "SAME_EDGE"
|
|
// or "SAME_EDGE_PIPELINED"
|
|
.INIT_Q1(1'b0), // Initial value of Q1: 1'b0 or 1'b1
|
|
.INIT_Q2(1'b0), // Initial value of Q2: 1'b0 or 1'b1
|
|
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
|
|
) IDDR_inst (
|
|
.Q1(Q1), // 1-bit output for positive edge of clock
|
|
.Q2(Q2), // 1-bit output for negative edge of clock
|
|
.C(C), // 1-bit clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.D(D), // 1-bit DDR data input
|
|
.R(R), // 1-bit reset
|
|
.S(S) // 1-bit set
|
|
);
|
|
|
|
// End of IDDR_inst instantiation
|
|
</Template>
|
|
<Template label="Output DDR Register (ODDR)" treetype="template">
|
|
// ODDR : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ODDR_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ODDR: Output Double Data Rate Output Register with Set, Reset
|
|
// and Clock Enable.
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ODDR #(
|
|
.DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE"
|
|
.INIT(1'b0), // Initial value of Q: 1'b0 or 1'b1
|
|
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
|
|
) ODDR_inst (
|
|
.Q(Q), // 1-bit DDR output
|
|
.C(C), // 1-bit clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.D1(D1), // 1-bit data input (positive edge)
|
|
.D2(D2), // 1-bit data input (negative edge)
|
|
.R(R), // 1-bit reset
|
|
.S(S) // 1-bit set
|
|
);
|
|
|
|
// End of ODDR_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Arithmetic Functions" treetype="folder">
|
|
<Template label="48-bit Multi-Functional Arithmetic Block (DSP48E1)" treetype="template">
|
|
// DSP48E1 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (DSP48E1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// DSP48E1: 48-bit Multi-Functional Arithmetic Block
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
DSP48E1 #(
|
|
// Feature Control Attributes: Data Path Selection
|
|
.A_INPUT("DIRECT"), // Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
|
|
.B_INPUT("DIRECT"), // Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
|
|
.USE_DPORT("FALSE"), // Select D port usage (TRUE or FALSE)
|
|
.USE_MULT("MULTIPLY"), // Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE")
|
|
.USE_SIMD("ONE48"), // SIMD selection ("ONE48", "TWO24", "FOUR12")
|
|
// Pattern Detector Attributes: Pattern Detection Configuration
|
|
.AUTORESET_PATDET("NO_RESET"), // "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH"
|
|
.MASK(48'h3fffffffffff), // 48-bit mask value for pattern detect (1=ignore)
|
|
.PATTERN(48'h000000000000), // 48-bit pattern match for pattern detect
|
|
.SEL_MASK("MASK"), // "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2"
|
|
.SEL_PATTERN("PATTERN"), // Select pattern value ("PATTERN" or "C")
|
|
.USE_PATTERN_DETECT("NO_PATDET"), // Enable pattern detect ("PATDET" or "NO_PATDET")
|
|
// Register Control Attributes: Pipeline Register Configuration
|
|
.ACASCREG(1), // Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2)
|
|
.ADREG(1), // Number of pipeline stages for pre-adder (0 or 1)
|
|
.ALUMODEREG(1), // Number of pipeline stages for ALUMODE (0 or 1)
|
|
.AREG(1), // Number of pipeline stages for A (0, 1 or 2)
|
|
.BCASCREG(1), // Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2)
|
|
.BREG(1), // Number of pipeline stages for B (0, 1 or 2)
|
|
.CARRYINREG(1), // Number of pipeline stages for CARRYIN (0 or 1)
|
|
.CARRYINSELREG(1), // Number of pipeline stages for CARRYINSEL (0 or 1)
|
|
.CREG(1), // Number of pipeline stages for C (0 or 1)
|
|
.DREG(1), // Number of pipeline stages for D (0 or 1)
|
|
.INMODEREG(1), // Number of pipeline stages for INMODE (0 or 1)
|
|
.MREG(1), // Number of multiplier pipeline stages (0 or 1)
|
|
.OPMODEREG(1), // Number of pipeline stages for OPMODE (0 or 1)
|
|
.PREG(1) // Number of pipeline stages for P (0 or 1)
|
|
)
|
|
DSP48E1_inst (
|
|
// Cascade: 30-bit (each) output: Cascade Ports
|
|
.ACOUT(ACOUT), // 30-bit output: A port cascade output
|
|
.BCOUT(BCOUT), // 18-bit output: B port cascade output
|
|
.CARRYCASCOUT(CARRYCASCOUT), // 1-bit output: Cascade carry output
|
|
.MULTSIGNOUT(MULTSIGNOUT), // 1-bit output: Multiplier sign cascade output
|
|
.PCOUT(PCOUT), // 48-bit output: Cascade output
|
|
// Control: 1-bit (each) output: Control Inputs/Status Bits
|
|
.OVERFLOW(OVERFLOW), // 1-bit output: Overflow in add/acc output
|
|
.PATTERNBDETECT(PATTERNBDETECT), // 1-bit output: Pattern bar detect output
|
|
.PATTERNDETECT(PATTERNDETECT), // 1-bit output: Pattern detect output
|
|
.UNDERFLOW(UNDERFLOW), // 1-bit output: Underflow in add/acc output
|
|
// Data: 4-bit (each) output: Data Ports
|
|
.CARRYOUT(CARRYOUT), // 4-bit output: Carry output
|
|
.P(P), // 48-bit output: Primary data output
|
|
// Cascade: 30-bit (each) input: Cascade Ports
|
|
.ACIN(ACIN), // 30-bit input: A cascade data input
|
|
.BCIN(BCIN), // 18-bit input: B cascade input
|
|
.CARRYCASCIN(CARRYCASCIN), // 1-bit input: Cascade carry input
|
|
.MULTSIGNIN(MULTSIGNIN), // 1-bit input: Multiplier sign input
|
|
.PCIN(PCIN), // 48-bit input: P cascade input
|
|
// Control: 4-bit (each) input: Control Inputs/Status Bits
|
|
.ALUMODE(ALUMODE), // 4-bit input: ALU control input
|
|
.CARRYINSEL(CARRYINSEL), // 3-bit input: Carry select input
|
|
.CLK(CLK), // 1-bit input: Clock input
|
|
.INMODE(INMODE), // 5-bit input: INMODE control input
|
|
.OPMODE(OPMODE), // 7-bit input: Operation mode input
|
|
// Data: 30-bit (each) input: Data Ports
|
|
.A(A), // 30-bit input: A data input
|
|
.B(B), // 18-bit input: B data input
|
|
.C(C), // 48-bit input: C data input
|
|
.CARRYIN(CARRYIN), // 1-bit input: Carry input signal
|
|
.D(D), // 25-bit input: D data input
|
|
// Reset/Clock Enable: 1-bit (each) input: Reset/Clock Enable Inputs
|
|
.CEA1(CEA1), // 1-bit input: Clock enable input for 1st stage AREG
|
|
.CEA2(CEA2), // 1-bit input: Clock enable input for 2nd stage AREG
|
|
.CEAD(CEAD), // 1-bit input: Clock enable input for ADREG
|
|
.CEALUMODE(CEALUMODE), // 1-bit input: Clock enable input for ALUMODE
|
|
.CEB1(CEB1), // 1-bit input: Clock enable input for 1st stage BREG
|
|
.CEB2(CEB2), // 1-bit input: Clock enable input for 2nd stage BREG
|
|
.CEC(CEC), // 1-bit input: Clock enable input for CREG
|
|
.CECARRYIN(CECARRYIN), // 1-bit input: Clock enable input for CARRYINREG
|
|
.CECTRL(CECTRL), // 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
|
|
.CED(CED), // 1-bit input: Clock enable input for DREG
|
|
.CEINMODE(CEINMODE), // 1-bit input: Clock enable input for INMODEREG
|
|
.CEM(CEM), // 1-bit input: Clock enable input for MREG
|
|
.CEP(CEP), // 1-bit input: Clock enable input for PREG
|
|
.RSTA(RSTA), // 1-bit input: Reset input for AREG
|
|
.RSTALLCARRYIN(RSTALLCARRYIN), // 1-bit input: Reset input for CARRYINREG
|
|
.RSTALUMODE(RSTALUMODE), // 1-bit input: Reset input for ALUMODEREG
|
|
.RSTB(RSTB), // 1-bit input: Reset input for BREG
|
|
.RSTC(RSTC), // 1-bit input: Reset input for CREG
|
|
.RSTCTRL(RSTCTRL), // 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
|
|
.RSTD(RSTD), // 1-bit input: Reset input for DREG and ADREG
|
|
.RSTINMODE(RSTINMODE), // 1-bit input: Reset input for INMODEREG
|
|
.RSTM(RSTM), // 1-bit input: Reset input for MREG
|
|
.RSTP(RSTP) // 1-bit input: Reset input for PREG
|
|
);
|
|
|
|
// End of DSP48E1_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="RAM/ROM" treetype="folder">
|
|
<SubFolder label="FIFO" treetype="folder">
|
|
<Template label="18Kb First-In-First-Out (FIFO) Buffer Memory (FIFO18E1)" treetype="template">
|
|
// FIFO18E1 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FIFO18E1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FIFO18E1: 18Kb FIFO (First-In-First-Out) Block RAM Memory
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FIFO18E1 #(
|
|
.ALMOST_EMPTY_OFFSET(13'h0080), // Sets the almost empty threshold
|
|
.ALMOST_FULL_OFFSET(13'h0080), // Sets almost full threshold
|
|
.DATA_WIDTH(4), // Sets data width to 4-36
|
|
.DO_REG(1), // Enable output register (1-0) Must be 1 if EN_SYN = FALSE
|
|
.EN_SYN("FALSE"), // Specifies FIFO as dual-clock (FALSE) or Synchronous (TRUE)
|
|
.FIFO_MODE("FIFO18"), // Sets mode to FIFO18 or FIFO18_36
|
|
.FIRST_WORD_FALL_THROUGH("FALSE"), // Sets the FIFO FWFT to FALSE, TRUE
|
|
.INIT(36'h000000000), // Initial values on output port
|
|
.SIM_DEVICE("7SERIES"), // Must be set to "7SERIES" for simulation behavior
|
|
.SRVAL(36'h000000000) // Set/Reset value for output port
|
|
)
|
|
FIFO18E1_inst (
|
|
// Read Data: 32-bit (each) output: Read output data
|
|
.DO(DO), // 32-bit output: Data output
|
|
.DOP(DOP), // 4-bit output: Parity data output
|
|
// Status: 1-bit (each) output: Flags and other FIFO status outputs
|
|
.ALMOSTEMPTY(ALMOSTEMPTY), // 1-bit output: Almost empty flag
|
|
.ALMOSTFULL(ALMOSTFULL), // 1-bit output: Almost full flag
|
|
.EMPTY(EMPTY), // 1-bit output: Empty flag
|
|
.FULL(FULL), // 1-bit output: Full flag
|
|
.RDCOUNT(RDCOUNT), // 12-bit output: Read count
|
|
.RDERR(RDERR), // 1-bit output: Read error
|
|
.WRCOUNT(WRCOUNT), // 12-bit output: Write count
|
|
.WRERR(WRERR), // 1-bit output: Write error
|
|
// Read Control Signals: 1-bit (each) input: Read clock, enable and reset input signals
|
|
.RDCLK(RDCLK), // 1-bit input: Read clock
|
|
.RDEN(RDEN), // 1-bit input: Read enable
|
|
.REGCE(REGCE), // 1-bit input: Clock enable
|
|
.RST(RST), // 1-bit input: Asynchronous Reset
|
|
.RSTREG(RSTREG), // 1-bit input: Output register set/reset
|
|
// Write Control Signals: 1-bit (each) input: Write clock and enable input signals
|
|
.WRCLK(WRCLK), // 1-bit input: Write clock
|
|
.WREN(WREN), // 1-bit input: Write enable
|
|
// Write Data: 32-bit (each) input: Write input data
|
|
.DI(DI), // 32-bit input: Data input
|
|
.DIP(DIP) // 4-bit input: Parity input
|
|
);
|
|
|
|
// End of FIFO18E1_inst instantiation
|
|
</Template>
|
|
<Template label="36Kb First-In-First-Out (FIFO) Buffer Memory (FIFO36E1)" treetype="template">
|
|
// FIFO36E1 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FIFO36E1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FIFO36E1: 36Kb FIFO (First-In-First-Out) Block RAM Memory
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FIFO36E1 #(
|
|
.ALMOST_EMPTY_OFFSET(13'h0080), // Sets the almost empty threshold
|
|
.ALMOST_FULL_OFFSET(13'h0080), // Sets almost full threshold
|
|
.DATA_WIDTH(4), // Sets data width to 4-72
|
|
.DO_REG(1), // Enable output register (1-0) Must be 1 if EN_SYN = FALSE
|
|
.EN_ECC_READ("FALSE"), // Enable ECC decoder, FALSE, TRUE
|
|
.EN_ECC_WRITE("FALSE"), // Enable ECC encoder, FALSE, TRUE
|
|
.EN_SYN("FALSE"), // Specifies FIFO as Asynchronous (FALSE) or Synchronous (TRUE)
|
|
.FIFO_MODE("FIFO36"), // Sets mode to "FIFO36" or "FIFO36_72"
|
|
.FIRST_WORD_FALL_THROUGH("FALSE"), // Sets the FIFO FWFT to FALSE, TRUE
|
|
.INIT(72'h000000000000000000), // Initial values on output port
|
|
.SIM_DEVICE("7SERIES"), // Must be set to "7SERIES" for simulation behavior
|
|
.SRVAL(72'h000000000000000000) // Set/Reset value for output port
|
|
)
|
|
FIFO36E1_inst (
|
|
// ECC Signals: 1-bit (each) output: Error Correction Circuitry ports
|
|
.DBITERR(DBITERR), // 1-bit output: Double bit error status
|
|
.ECCPARITY(ECCPARITY), // 8-bit output: Generated error correction parity
|
|
.SBITERR(SBITERR), // 1-bit output: Single bit error status
|
|
// Read Data: 64-bit (each) output: Read output data
|
|
.DO(DO), // 64-bit output: Data output
|
|
.DOP(DOP), // 8-bit output: Parity data output
|
|
// Status: 1-bit (each) output: Flags and other FIFO status outputs
|
|
.ALMOSTEMPTY(ALMOSTEMPTY), // 1-bit output: Almost empty flag
|
|
.ALMOSTFULL(ALMOSTFULL), // 1-bit output: Almost full flag
|
|
.EMPTY(EMPTY), // 1-bit output: Empty flag
|
|
.FULL(FULL), // 1-bit output: Full flag
|
|
.RDCOUNT(RDCOUNT), // 13-bit output: Read count
|
|
.RDERR(RDERR), // 1-bit output: Read error
|
|
.WRCOUNT(WRCOUNT), // 13-bit output: Write count
|
|
.WRERR(WRERR), // 1-bit output: Write error
|
|
// ECC Signals: 1-bit (each) input: Error Correction Circuitry ports
|
|
.INJECTDBITERR(INJECTDBITERR), // 1-bit input: Inject a double bit error input
|
|
.INJECTSBITERR(INJECTSBITERR),
|
|
// Read Control Signals: 1-bit (each) input: Read clock, enable and reset input signals
|
|
.RDCLK(RDCLK), // 1-bit input: Read clock
|
|
.RDEN(RDEN), // 1-bit input: Read enable
|
|
.REGCE(REGCE), // 1-bit input: Clock enable
|
|
.RST(RST), // 1-bit input: Reset
|
|
.RSTREG(RSTREG), // 1-bit input: Output register set/reset
|
|
// Write Control Signals: 1-bit (each) input: Write clock and enable input signals
|
|
.WRCLK(WRCLK), // 1-bit input: Rising edge write clock.
|
|
.WREN(WREN), // 1-bit input: Write enable
|
|
// Write Data: 64-bit (each) input: Write input data
|
|
.DI(DI), // 64-bit input: Data input
|
|
.DIP(DIP) // 8-bit input: Parity input
|
|
);
|
|
|
|
// End of FIFO36E1_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="BlockRAM" treetype="folder">
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<Template label="18Kb Block RAM Memory (RAMB18E1)" treetype="template">
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// RAMB18E1 : In order to incorporate this function into the design,
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// Verilog : the following instance declaration needs to be placed
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// instance : in the body of the design code. The instance name
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// declaration : (RAMB18E1_inst) and/or the port declarations within the
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// code : parenthesis may be changed to properly reference and
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// : connect this function to the design. All inputs
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// : and outputs must be connected.
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// <-----Cut code below this line---->
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// RAMB18E1: 18K-bit Configurable Synchronous Block RAM
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// Virtex-7
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// Xilinx HDL Language Template, version 14.7
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RAMB18E1 #(
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// Address Collision Mode: "PERFORMANCE" or "DELAYED_WRITE"
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.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
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// Collision check: Values ("ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE")
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.SIM_COLLISION_CHECK("ALL"),
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// DOA_REG, DOB_REG: Optional output register (0 or 1)
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.DOA_REG(0),
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.DOB_REG(0),
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// INITP_00 to INITP_07: Initial contents of parity memory array
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.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
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// INIT_00 to INIT_3F: Initial contents of data memory array
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.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
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// INIT_A, INIT_B: Initial values on output ports
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.INIT_A(18'h00000),
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.INIT_B(18'h00000),
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// Initialization File: RAM initialization file
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.INIT_FILE("NONE"),
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// RAM Mode: "SDP" or "TDP"
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.RAM_MODE("TDP"),
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// READ_WIDTH_A/B, WRITE_WIDTH_A/B: Read/write width per port
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.READ_WIDTH_A(0), // 0-72
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.READ_WIDTH_B(0), // 0-18
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.WRITE_WIDTH_A(0), // 0-18
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.WRITE_WIDTH_B(0), // 0-72
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// RSTREG_PRIORITY_A, RSTREG_PRIORITY_B: Reset or enable priority ("RSTREG" or "REGCE")
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.RSTREG_PRIORITY_A("RSTREG"),
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.RSTREG_PRIORITY_B("RSTREG"),
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// SRVAL_A, SRVAL_B: Set/reset value for output
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.SRVAL_A(18'h00000),
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.SRVAL_B(18'h00000),
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// Simulation Device: Must be set to "7SERIES" for simulation behavior
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.SIM_DEVICE("7SERIES"),
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// WriteMode: Value on output upon a write ("WRITE_FIRST", "READ_FIRST", or "NO_CHANGE")
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.WRITE_MODE_A("WRITE_FIRST"),
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.WRITE_MODE_B("WRITE_FIRST")
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)
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RAMB18E1_inst (
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// Port A Data: 16-bit (each) output: Port A data
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.DOADO(DOADO), // 16-bit output: A port data/LSB data
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.DOPADOP(DOPADOP), // 2-bit output: A port parity/LSB parity
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// Port B Data: 16-bit (each) output: Port B data
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.DOBDO(DOBDO), // 16-bit output: B port data/MSB data
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.DOPBDOP(DOPBDOP), // 2-bit output: B port parity/MSB parity
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// Port A Address/Control Signals: 14-bit (each) input: Port A address and control signals (read port
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// when RAM_MODE="SDP")
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.ADDRARDADDR(ADDRARDADDR), // 14-bit input: A port address/Read address
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.CLKARDCLK(CLKARDCLK), // 1-bit input: A port clock/Read clock
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.ENARDEN(ENARDEN), // 1-bit input: A port enable/Read enable
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.REGCEAREGCE(REGCEAREGCE), // 1-bit input: A port register enable/Register enable
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.RSTRAMARSTRAM(RSTRAMARSTRAM), // 1-bit input: A port set/reset
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.RSTREGARSTREG(RSTREGARSTREG), // 1-bit input: A port register set/reset
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.WEA(WEA), // 2-bit input: A port write enable
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// Port A Data: 16-bit (each) input: Port A data
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.DIADI(DIADI), // 16-bit input: A port data/LSB data
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.DIPADIP(DIPADIP), // 2-bit input: A port parity/LSB parity
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// Port B Address/Control Signals: 14-bit (each) input: Port B address and control signals (write port
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// when RAM_MODE="SDP")
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.ADDRBWRADDR(ADDRBWRADDR), // 14-bit input: B port address/Write address
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.CLKBWRCLK(CLKBWRCLK), // 1-bit input: B port clock/Write clock
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.ENBWREN(ENBWREN), // 1-bit input: B port enable/Write enable
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.REGCEB(REGCEB), // 1-bit input: B port register enable
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.RSTRAMB(RSTRAMB), // 1-bit input: B port set/reset
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.RSTREGB(RSTREGB), // 1-bit input: B port register set/reset
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.WEBWE(WEBWE), // 4-bit input: B port write enable/Write enable
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// Port B Data: 16-bit (each) input: Port B data
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.DIBDI(DIBDI), // 16-bit input: B port data/MSB data
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.DIPBDIP(DIPBDIP) // 2-bit input: B port parity/MSB parity
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);
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// End of RAMB18E1_inst instantiation
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</Template>
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<Template label="36Kb Block RAM Memory (RAMB36E1)" treetype="template">
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// RAMB36E1 : In order to incorporate this function into the design,
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// Verilog : the following instance declaration needs to be placed
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|
// instance : in the body of the design code. The instance name
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|
// declaration : (RAMB36E1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
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// RAMB36E1: 36K-bit Configurable Synchronous Block RAM
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// Virtex-7
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// Xilinx HDL Language Template, version 14.7
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RAMB36E1 #(
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// Address Collision Mode: "PERFORMANCE" or "DELAYED_WRITE"
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.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
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// Collision check: Values ("ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE")
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.SIM_COLLISION_CHECK("ALL"),
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// DOA_REG, DOB_REG: Optional output register (0 or 1)
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.DOA_REG(0),
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.DOB_REG(0),
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.EN_ECC_READ("FALSE"), // Enable ECC decoder,
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// FALSE, TRUE
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.EN_ECC_WRITE("FALSE"), // Enable ECC encoder,
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// FALSE, TRUE
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// INITP_00 to INITP_0F: Initial contents of the parity memory array
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.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
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// INIT_00 to INIT_7F: Initial contents of the data memory array
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.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
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.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
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.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
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.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
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.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
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.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
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.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
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// INIT_A, INIT_B: Initial values on output ports
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.INIT_A(36'h000000000),
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.INIT_B(36'h000000000),
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// Initialization File: RAM initialization file
|
|
.INIT_FILE("NONE"),
|
|
// RAM Mode: "SDP" or "TDP"
|
|
.RAM_MODE("TDP"),
|
|
// RAM_EXTENSION_A, RAM_EXTENSION_B: Selects cascade mode ("UPPER", "LOWER", or "NONE")
|
|
.RAM_EXTENSION_A("NONE"),
|
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.RAM_EXTENSION_B("NONE"),
|
|
// READ_WIDTH_A/B, WRITE_WIDTH_A/B: Read/write width per port
|
|
.READ_WIDTH_A(0), // 0-72
|
|
.READ_WIDTH_B(0), // 0-36
|
|
.WRITE_WIDTH_A(0), // 0-36
|
|
.WRITE_WIDTH_B(0), // 0-72
|
|
// RSTREG_PRIORITY_A, RSTREG_PRIORITY_B: Reset or enable priority ("RSTREG" or "REGCE")
|
|
.RSTREG_PRIORITY_A("RSTREG"),
|
|
.RSTREG_PRIORITY_B("RSTREG"),
|
|
// SRVAL_A, SRVAL_B: Set/reset value for output
|
|
.SRVAL_A(36'h000000000),
|
|
.SRVAL_B(36'h000000000),
|
|
// Simulation Device: Must be set to "7SERIES" for simulation behavior
|
|
.SIM_DEVICE("7SERIES"),
|
|
// WriteMode: Value on output upon a write ("WRITE_FIRST", "READ_FIRST", or "NO_CHANGE")
|
|
.WRITE_MODE_A("WRITE_FIRST"),
|
|
.WRITE_MODE_B("WRITE_FIRST")
|
|
)
|
|
RAMB36E1_inst (
|
|
// Cascade Signals: 1-bit (each) output: BRAM cascade ports (to create 64kx1)
|
|
.CASCADEOUTA(CASCADEOUTA), // 1-bit output: A port cascade
|
|
.CASCADEOUTB(CASCADEOUTB), // 1-bit output: B port cascade
|
|
// ECC Signals: 1-bit (each) output: Error Correction Circuitry ports
|
|
.DBITERR(DBITERR), // 1-bit output: Double bit error status
|
|
.ECCPARITY(ECCPARITY), // 8-bit output: Generated error correction parity
|
|
.RDADDRECC(RDADDRECC), // 9-bit output: ECC read address
|
|
.SBITERR(SBITERR), // 1-bit output: Single bit error status
|
|
// Port A Data: 32-bit (each) output: Port A data
|
|
.DOADO(DOADO), // 32-bit output: A port data/LSB data
|
|
.DOPADOP(DOPADOP), // 4-bit output: A port parity/LSB parity
|
|
// Port B Data: 32-bit (each) output: Port B data
|
|
.DOBDO(DOBDO), // 32-bit output: B port data/MSB data
|
|
.DOPBDOP(DOPBDOP), // 4-bit output: B port parity/MSB parity
|
|
// Cascade Signals: 1-bit (each) input: BRAM cascade ports (to create 64kx1)
|
|
.CASCADEINA(CASCADEINA), // 1-bit input: A port cascade
|
|
.CASCADEINB(CASCADEINB), // 1-bit input: B port cascade
|
|
// ECC Signals: 1-bit (each) input: Error Correction Circuitry ports
|
|
.INJECTDBITERR(INJECTDBITERR), // 1-bit input: Inject a double bit error
|
|
.INJECTSBITERR(INJECTSBITERR), // 1-bit input: Inject a single bit error
|
|
// Port A Address/Control Signals: 16-bit (each) input: Port A address and control signals (read port
|
|
// when RAM_MODE="SDP")
|
|
.ADDRARDADDR(ADDRARDADDR), // 16-bit input: A port address/Read address
|
|
.CLKARDCLK(CLKARDCLK), // 1-bit input: A port clock/Read clock
|
|
.ENARDEN(ENARDEN), // 1-bit input: A port enable/Read enable
|
|
.REGCEAREGCE(REGCEAREGCE), // 1-bit input: A port register enable/Register enable
|
|
.RSTRAMARSTRAM(RSTRAMARSTRAM), // 1-bit input: A port set/reset
|
|
.RSTREGARSTREG(RSTREGARSTREG), // 1-bit input: A port register set/reset
|
|
.WEA(WEA), // 4-bit input: A port write enable
|
|
// Port A Data: 32-bit (each) input: Port A data
|
|
.DIADI(DIADI), // 32-bit input: A port data/LSB data
|
|
.DIPADIP(DIPADIP), // 4-bit input: A port parity/LSB parity
|
|
// Port B Address/Control Signals: 16-bit (each) input: Port B address and control signals (write port
|
|
// when RAM_MODE="SDP")
|
|
.ADDRBWRADDR(ADDRBWRADDR), // 16-bit input: B port address/Write address
|
|
.CLKBWRCLK(CLKBWRCLK), // 1-bit input: B port clock/Write clock
|
|
.ENBWREN(ENBWREN), // 1-bit input: B port enable/Write enable
|
|
.REGCEB(REGCEB), // 1-bit input: B port register enable
|
|
.RSTRAMB(RSTRAMB), // 1-bit input: B port set/reset
|
|
.RSTREGB(RSTREGB), // 1-bit input: B port register set/reset
|
|
.WEBWE(WEBWE), // 8-bit input: B port write enable/Write enable
|
|
// Port B Data: 32-bit (each) input: Port B data
|
|
.DIBDI(DIBDI), // 32-bit input: B port data/MSB data
|
|
.DIPBDIP(DIPBDIP) // 4-bit input: B port parity/MSB parity
|
|
);
|
|
|
|
// End of RAMB36E1_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Distributed ROM" treetype="folder">
|
|
<Template label="32 X 1 (ROM32X1)" treetype="template">
|
|
// ROM32X1 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ROM32X1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ROM32X1: 32 x 1 Asynchronous Distributed (LUT) ROM (Mapped to a SliceM LUT6)
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ROM32X1 #(
|
|
.INIT(32'h00000000) // Contents of ROM
|
|
) ROM32X1_inst (
|
|
.O(O), // ROM output
|
|
.A0(A0), // ROM address[0]
|
|
.A1(A1), // ROM address[1]
|
|
.A2(A2), // ROM address[2]
|
|
.A3(A3), // ROM address[3]
|
|
.A4(A4) // ROM address[4]
|
|
);
|
|
|
|
// End of ROM32X1_inst instantiation
|
|
</Template>
|
|
<Template label="64 X 1 (ROM64X1)" treetype="template">
|
|
// ROM64X1 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ROM64X1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ROM64X1: 64 x 1 Asynchronous Distributed (LUT) ROM (Mapped to a SliceM LUT6)
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ROM64X1 #(
|
|
.INIT(64'h0000000000000000) // Contents of ROM
|
|
) ROM64X1_inst (
|
|
.O(O), // ROM output
|
|
.A0(A0), // ROM address[0]
|
|
.A1(A1), // ROM address[1]
|
|
.A2(A2), // ROM address[2]
|
|
.A3(A3), // ROM address[3]
|
|
.A4(A4), // ROM address[4]
|
|
.A5(A5) // ROM address[5]
|
|
);
|
|
|
|
// End of ROM64X1_inst instantiation
|
|
</Template>
|
|
<Template label="128 X 1 (ROM128X1)" treetype="template">
|
|
// ROM128X1 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ROM128X1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ROM128X1: 128 x 1 Asynchronous Distributed (LUT) ROM (Mapped to two SliceM LUT6s)
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ROM128X1 #(
|
|
.INIT(128'h00000000000000000000000000000000) // Contents of ROM
|
|
) ROM128X1_inst (
|
|
.O(O), // ROM output
|
|
.A0(A0), // ROM address[0]
|
|
.A1(A1), // ROM address[1]
|
|
.A2(A2), // ROM address[2]
|
|
.A3(A3), // ROM address[3]
|
|
.A4(A4), // ROM address[4]
|
|
.A5(A5), // ROM address[5]
|
|
.A6(A6) // ROM address[6]
|
|
);
|
|
|
|
// End of ROM128X1_inst instantiation
|
|
</Template>
|
|
<Template label="256 X 1 (ROM256X1)" treetype="template">
|
|
// ROM256X1 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ROM256X1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ROM256X1: 256 x 1 Asynchronous Distributed (LUT) ROM (Mapped to four SliceM LUT6s)
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ROM256X1 #(
|
|
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000) // Contents of ROM
|
|
) ROM256X1_inst (
|
|
.O(O), // ROM output
|
|
.A0(A0), // ROM address[0]
|
|
.A1(A1), // ROM address[1]
|
|
.A2(A2), // ROM address[2]
|
|
.A3(A3), // ROM address[3]
|
|
.A4(A4), // ROM address[4]
|
|
.A5(A5), // ROM address[5]
|
|
.A6(A6), // ROM address[6]
|
|
.A7(A7) // ROM address[7]
|
|
);
|
|
|
|
// End of ROM256X1_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Distributed RAM" treetype="folder">
|
|
<SubFolder label="Single-Port" treetype="folder">
|
|
<SubFolder label="32 Deep (5-bit address)" treetype="folder">
|
|
<Template label="32 x 1 posedge write (RAM32X1S)" treetype="template">
|
|
// RAM32X1S : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM32X1S_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM32X1S: 32 x 1 posedge write distributed (LUT) RAM (Mapped to a SliceM LUT6)
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM32X1S #(
|
|
.INIT(32'h00000000) // Initial contents of RAM
|
|
) RAM32X1S_inst (
|
|
.O(O), // RAM output
|
|
.A0(A0), // RAM address[0] input
|
|
.A1(A1), // RAM address[1] input
|
|
.A2(A2), // RAM address[2] input
|
|
.A3(A3), // RAM address[3] input
|
|
.A4(A4), // RAM address[4] input
|
|
.D(D), // RAM data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM32X1S_inst instantiation
|
|
</Template>
|
|
<Template label="32 x 1 negedge write (RAM32X1S_1)" treetype="template">
|
|
// RAM32X1S_1 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM32X1S_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM32X1S_1: 32 x 1 negedge write distributed (LUT) RAM (Mapped to a SliceM LUT6)
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM32X1S_1 #(
|
|
.INIT(32'h00000000) // Initial contents of RAM
|
|
)RAM32X1S_1_inst (
|
|
.O(O), // RAM output
|
|
.A0(A0), // RAM address[0] input
|
|
.A1(A1), // RAM address[1] input
|
|
.A2(A2), // RAM address[2] input
|
|
.A3(A3), // RAM address[3] input
|
|
.A4(A4), // RAM address[4] input
|
|
.D(D), // RAM data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM32X1S_1_inst instantiation
|
|
</Template>
|
|
<Template label="32 x 2 posedge write (RAM32X2S)" treetype="template">
|
|
// RAM32X2S : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM16X2S_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM32X2S: 32 x 2 posedge write distributed (LUT) RAM (Mapped to a SliceM LUT6)
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM32X2S #(
|
|
.INIT_00(32'h00000000), // INIT for bit 0 of RAM
|
|
.INIT_01(32'h00000000) // INIT for bit 1 of RAM
|
|
) RAM32X2S_inst (
|
|
.O0(O0), // RAM data[0] output
|
|
.O1(O1), // RAM data[1] output
|
|
.A0(A0), // RAM address[0] input
|
|
.A1(A1), // RAM address[1] input
|
|
.A2(A2), // RAM address[2] input
|
|
.A3(A3), // RAM address[3] input
|
|
.A4(A4), // RAM address[4] input
|
|
.D0(D0), // RAM data[0] input
|
|
.D1(D1), // RAM data[1] input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM32X2S_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="64 Deep (6-bit address)" treetype="folder">
|
|
<Template label="64 X 1 posedge write (RAM64X1S)" treetype="template">
|
|
// RAM64X1S : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM64X1S_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM64X1S: 64 x 1 positive edge write, asynchronous read single-port distributed RAM (Mapped to a SliceM LUT6)
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM64X1S #(
|
|
.INIT(64'h0000000000000000) // Initial contents of RAM
|
|
) RAM64X1S_inst (
|
|
.O(O), // 1-bit data output
|
|
.A0(A0), // Address[0] input bit
|
|
.A1(A1), // Address[1] input bit
|
|
.A2(A2), // Address[2] input bit
|
|
.A3(A3), // Address[3] input bit
|
|
.A4(A4), // Address[4] input bit
|
|
.A5(A5), // Address[5] input bit
|
|
.D(D), // 1-bit data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM64X1S_inst instantiation
|
|
</Template>
|
|
<Template label="64 X 1 negedge write (RAM64X1S_1)" treetype="template">
|
|
// RAM64X1S_1 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM64X1S_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM64X1S_1: 64 x 1 negative edge write, asynchronous read single-port distributed RAM (Mapped to a SliceM LUT6)
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM64X1S_1 #(
|
|
.INIT(64'h0000000000000000) // Initial contents of RAM
|
|
) RAM64X1S_1_inst (
|
|
.O(O), // 1-bit data output
|
|
.A0(A0), // Address[0] input bit
|
|
.A1(A1), // Address[1] input bit
|
|
.A2(A2), // Address[2] input bit
|
|
.A3(A3), // Address[3] input bit
|
|
.A4(A4), // Address[4] input bit
|
|
.A5(A5), // Address[5] input bit
|
|
.D(D), // 1-bit data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM64X1S_1_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="128 Deep (7-bit address)" treetype="folder">
|
|
<Template label="128 X 1 posedge write (RAM128X1S)" treetype="template">
|
|
// RAM128X1S : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM128X1S_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM128X1S: 128 x 1 positive edge write, asynchronous read single-port distributed RAM (Mapped to two SliceM LUT6s)
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM128X1S #(
|
|
.INIT(128'h00000000000000000000000000000000) // Initial contents of RAM
|
|
) RAM128X1S_inst (
|
|
.O(O), // 1-bit data output
|
|
.A0(A0), // Address[0] input bit
|
|
.A1(A1), // Address[1] input bit
|
|
.A2(A2), // Address[2] input bit
|
|
.A3(A3), // Address[3] input bit
|
|
.A4(A4), // Address[4] input bit
|
|
.A5(A5), // Address[5] input bit
|
|
.A6(A6), // Address[6] input bit
|
|
.D(D), // 1-bit data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM128X1S_inst instantiation
|
|
</Template>
|
|
<Template label="128 X 1 negedge write (RAM128X1S_1)" treetype="template">
|
|
// RAM128X1S_1 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM128X1S_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM128X1S_1: 128 x 1 negative edge write, asynchronous read single-port distributed RAM (Mapped to two SliceM LUT6s)
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM128X1S_1 #(
|
|
.INIT(128'h00000000000000000000000000000000) // Initial contents of RAM
|
|
) RAM128X1S_1_inst (
|
|
.O(O), // 1-bit data output
|
|
.A0(A0), // Address[0] input bit
|
|
.A1(A1), // Address[1] input bit
|
|
.A2(A2), // Address[2] input bit
|
|
.A3(A3), // Address[3] input bit
|
|
.A4(A4), // Address[4] input bit
|
|
.A5(A5), // Address[5] input bit
|
|
.A6(A6), // Address[6] input bit
|
|
.D(D), // 1-bit data input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM128X1S_1_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="256 Deep (8-bit address)" treetype="folder">
|
|
<Template label="256 X 1 posedge write (RAM256X1S)" treetype="template">
|
|
// RAM256X1S : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM256X1S_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM256X1S: 256-deep by 1-wide positive edge write, asynchronous read (Mapped to four SliceM LUT6s)
|
|
// single-port distributed LUT RAM
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM256X1S #(
|
|
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) RAM256X1S_inst (
|
|
.O(O), // Read/write port 1-bit output
|
|
.A(A), // Read/write port 8-bit address input
|
|
.WE(WE), // Write enable input
|
|
.WCLK(WCLK), // Write clock input
|
|
.D(D) // RAM data input
|
|
);
|
|
|
|
// End of RAM256X1S_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Dual-Port" treetype="folder">
|
|
<Template label="32 X 1 posedge write (RAM32X1D)" treetype="template">
|
|
// RAM32X1D : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM32X1D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM32X1D: 32 x 1 positive edge write, asynchronous read dual-port distributed RAM (Mapped to a SliceM LUT6)
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM32X1D #(
|
|
.INIT(32'h00000000) // Initial contents of RAM
|
|
) RAM32X1D_inst (
|
|
.DPO(DPO), // Read-only 1-bit data output
|
|
.SPO(SPO), // Rw/ 1-bit data output
|
|
.A0(A0), // Rw/ address[0] input bit
|
|
.A1(A1), // Rw/ address[1] input bit
|
|
.A2(A2), // Rw/ address[2] input bit
|
|
.A3(A3), // Rw/ address[3] input bit
|
|
.A4(A4), // Rw/ address[4] input bit
|
|
.D(D), // Write 1-bit data input
|
|
.DPRA0(DPRA0), // Read-only address[0] input bit
|
|
.DPRA1(DPRA1), // Read-only address[1] input bit
|
|
.DPRA2(DPRA2), // Read-only address[2] input bit
|
|
.DPRA3(DPRA3), // Read-only address[3] input bit
|
|
.DPRA4(DPRA4), // Read-only address[4] input bit
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM32X1D_inst instantiation
|
|
</Template>
|
|
<Template label="32 X 1 negedge write (RAM32X1D_1)" treetype="template">
|
|
// RAM32X1D_1 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM32X1D_1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM32X1D_1: 32 x 1 negative edge write, asynchronous read dual-port distributed RAM (Mapped to a SliceM LUT6)
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM32X1D_1 #(
|
|
.INIT(32'h00000000) // Initial contents of RAM
|
|
) RAM32X1D_1_inst (
|
|
.DPO(DPO), // Read-only 1-bit data output
|
|
.SPO(SPO), // Rw/ 1-bit data output
|
|
.A0(A0), // Rw/ address[0] input bit
|
|
.A1(A1), // Rw/ address[1] input bit
|
|
.A2(A2), // Rw/ address[2] input bit
|
|
.A3(A3), // Rw/ address[3] input bit
|
|
.A4(A4), // Rw/ address[4] input bit
|
|
.D(D), // Write 1-bit data input
|
|
.DPRA0(DPRA0), // Read-only address[0] input bit
|
|
.DPRA1(DPRA1), // Read-only address[1] input bit
|
|
.DPRA2(DPRA2), // Read-only address[2] input bit
|
|
.DPRA3(DPRA3), // Read-only address[3] input bit
|
|
.DPRA4(DPRA4), // Read-only address[4] input bit
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM32X1D_1_inst instantiation
|
|
</Template>
|
|
<Template label="64 X 1 posedge write (RAM64X1D)" treetype="template">
|
|
// RAM64X1D : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM64X1D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM64X1D: 64 x 1 positive edge write, asynchronous read dual-port distributed RAM (Mapped to a SliceM LUT6)
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM64X1D #(
|
|
.INIT(64'h0000000000000000) // Initial contents of RAM
|
|
) RAM64X1D_inst (
|
|
.DPO(DPO), // Read-only 1-bit data output
|
|
.SPO(SPO), // Rw/ 1-bit data output
|
|
.A0(A0), // Rw/ address[0] input bit
|
|
.A1(A1), // Rw/ address[1] input bit
|
|
.A2(A2), // Rw/ address[2] input bit
|
|
.A3(A3), // Rw/ address[3] input bit
|
|
.A4(A4), // Rw/ address[4] input bit
|
|
.A5(A5), // Rw/ address[5] input bit
|
|
.D(D), // Write 1-bit data input
|
|
.DPRA0(DPRA0), // Read-only address[0] input bit
|
|
.DPRA1(DPRA1), // Read-only address[1] input bit
|
|
.DPRA2(DPRA2), // Read-only address[2] input bit
|
|
.DPRA3(DPRA3), // Read-only address[3] input bit
|
|
.DPRA4(DPRA4), // Read-only address[4] input bit
|
|
.DPRA5(DPRA5), // Read-only address[5] input bit
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM64X1D_inst instantiation
|
|
</Template>
|
|
<Template label="128 X 1 posedge write (RAM128X1D)" treetype="template">
|
|
// RAM128X1D : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM128X1D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM128X1D: 128-deep by 1-wide positive edge write, asynchronous read (Mapped to two SliceM LUT6s)
|
|
// dual-port distributed LUT RAM
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM128X1D #(
|
|
.INIT(128'h00000000000000000000000000000000)
|
|
) RAM128X1D_inst (
|
|
.DPO(DPO), // Read port 1-bit output
|
|
.SPO(SPO), // Read/write port 1-bit output
|
|
.A(A), // Read/write port 7-bit address input
|
|
.D(D), // RAM data input
|
|
.DPRA(DPRA), // Read port 7-bit address input
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM128X1D_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Multi-Port" treetype="folder">
|
|
<Template label="32 X 8 (RAM32M)" treetype="template">
|
|
// RAM32M : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM32M_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM32M: 32-deep by 8-wide Multi Port LUT RAM (Mapped to four SliceM LUT6s)
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM32M #(
|
|
.INIT_A(64'h0000000000000000), // Initial contents of A Port
|
|
.INIT_B(64'h0000000000000000), // Initial contents of B Port
|
|
.INIT_C(64'h0000000000000000), // Initial contents of C Port
|
|
.INIT_D(64'h0000000000000000) // Initial contents of D Port
|
|
) RAM32M_inst (
|
|
.DOA(DOA), // Read port A 2-bit output
|
|
.DOB(DOB), // Read port B 2-bit output
|
|
.DOC(DOC), // Read port C 2-bit output
|
|
.DOD(DOD), // Read/write port D 2-bit output
|
|
.ADDRA(ADDRA), // Read port A 5-bit address input
|
|
.ADDRB(ADDRB), // Read port B 5-bit address input
|
|
.ADDRC(ADDRC), // Read port C 5-bit address input
|
|
.ADDRD(ADDRD), // Read/write port D 5-bit address input
|
|
.DIA(DIA), // RAM 2-bit data write input addressed by ADDRD,
|
|
// read addressed by ADDRA
|
|
.DIB(DIB), // RAM 2-bit data write input addressed by ADDRD,
|
|
// read addressed by ADDRB
|
|
.DIC(DIC), // RAM 2-bit data write input addressed by ADDRD,
|
|
// read addressed by ADDRC
|
|
.DID(DID), // RAM 2-bit data write input addressed by ADDRD,
|
|
// read addressed by ADDRD
|
|
.WCLK(WCLK), // Write clock input
|
|
.WE(WE) // Write enable input
|
|
);
|
|
|
|
// End of RAM32M_inst instantiation
|
|
</Template>
|
|
<Template label="64 X 4 (RAM64M)" treetype="template">
|
|
// RAM64M : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (RAM64M_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// RAM64M: 64-deep by 4-wide Multi Port LUT RAM (Mapped to four SliceM LUT6s)
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
RAM64M #(
|
|
.INIT_A(64'h0000000000000000), // Initial contents of A Port
|
|
.INIT_B(64'h0000000000000000), // Initial contents of B Port
|
|
.INIT_C(64'h0000000000000000), // Initial contents of C Port
|
|
.INIT_D(64'h0000000000000000) // Initial contents of D Port
|
|
) RAM64M_inst (
|
|
.DOA(DOA), // Read port A 1-bit output
|
|
.DOB(DOB), // Read port B 1-bit output
|
|
.DOC(DOC), // Read port C 1-bit output
|
|
.DOD(DOD), // Read/write port D 1-bit output
|
|
.DIA(DIA), // RAM 1-bit data write input addressed by ADDRD,
|
|
// read addressed by ADDRA
|
|
.DIB(DIB), // RAM 1-bit data write input addressed by ADDRD,
|
|
// read addressed by ADDRB
|
|
.DIC(DIC), // RAM 1-bit data write input addressed by ADDRD,
|
|
// read addressed by ADDRC
|
|
.DID(DID), // RAM 1-bit data write input addressed by ADDRD,
|
|
// read addressed by ADDRD
|
|
.ADDRA(ADDRA), // Read port A 6-bit address input
|
|
.ADDRB(ADDRB), // Read port B 6-bit address input
|
|
.ADDRC(ADDRC), // Read port C 6-bit address input
|
|
.ADDRD(ADDRD), // Read/write port D 6-bit address input
|
|
.WE(WE), // Write enable input
|
|
.WCLK(WCLK) // Write clock input
|
|
);
|
|
|
|
// End of RAM64M_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Advanced" treetype="folder">
|
|
<Template label="Gigabit Transceiver Buffer (IBUFDS_GTE2)" treetype="template">
|
|
// IBUFDS_GTE2 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IBUFDS_GTE2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IBUFDS_GTE2: Gigabit Transceiver Buffer
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IBUFDS_GTE2 #(
|
|
.CLKCM_CFG("TRUE"), // Refer to Transceiver User Guide
|
|
.CLKRCV_TRST("TRUE"), // Refer to Transceiver User Guide
|
|
.CLKSWING_CFG(2'b11) // Refer to Transceiver User Guide
|
|
)
|
|
IBUFDS_GTE2_inst (
|
|
.O(O), // 1-bit output: Refer to Transceiver User Guide
|
|
.ODIV2(ODIV2), // 1-bit output: Refer to Transceiver User Guide
|
|
.CEB(CEB), // 1-bit input: Refer to Transceiver User Guide
|
|
.I(I), // 1-bit input: Refer to Transceiver User Guide
|
|
.IB(IB) // 1-bit input: Refer to Transceiver User Guide
|
|
);
|
|
|
|
// End of IBUFDS_GTE2_inst instantiation
|
|
</Template>
|
|
<Template label="Xilinx Analog-to-Digital Converter (XADC)" treetype="template">
|
|
// XADC : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (XADC_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// XADC: Dual 12-Bit 1MSPS Analog-to-Digital Converter
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
XADC #(
|
|
// INIT_40 - INIT_42: XADC configuration registers
|
|
.INIT_40(16'h0000),
|
|
.INIT_41(16'h0000),
|
|
.INIT_42(16'h0800),
|
|
// INIT_48 - INIT_4F: Sequence Registers
|
|
.INIT_48(16'h0000),
|
|
.INIT_49(16'h0000),
|
|
.INIT_4A(16'h0000),
|
|
.INIT_4B(16'h0000),
|
|
.INIT_4C(16'h0000),
|
|
.INIT_4D(16'h0000),
|
|
.INIT_4F(16'h0000),
|
|
.INIT_4E(16'h0000), // Sequence register 6
|
|
// INIT_50 - INIT_58, INIT5C: Alarm Limit Registers
|
|
.INIT_50(16'h0000),
|
|
.INIT_51(16'h0000),
|
|
.INIT_52(16'h0000),
|
|
.INIT_53(16'h0000),
|
|
.INIT_54(16'h0000),
|
|
.INIT_55(16'h0000),
|
|
.INIT_56(16'h0000),
|
|
.INIT_57(16'h0000),
|
|
.INIT_58(16'h0000),
|
|
.INIT_5C(16'h0000),
|
|
// Simulation attributes: Set for proper simulation behavior
|
|
.SIM_DEVICE("7SERIES"), // Select target device (values)
|
|
.SIM_MONITOR_FILE(""design.txt"") // Analog simulation data file name
|
|
)
|
|
XADC_inst (
|
|
// ALARMS: 8-bit (each) output: ALM, OT
|
|
.ALM(ALM), // 8-bit output: Output alarm for temp, Vccint, Vccaux and Vccbram
|
|
.OT(OT), // 1-bit output: Over-Temperature alarm
|
|
// Dynamic Reconfiguration Port (DRP): 16-bit (each) output: Dynamic Reconfiguration Ports
|
|
.DO(DO), // 16-bit output: DRP output data bus
|
|
.DRDY(DRDY), // 1-bit output: DRP data ready
|
|
// STATUS: 1-bit (each) output: XADC status ports
|
|
.BUSY(BUSY), // 1-bit output: ADC busy output
|
|
.CHANNEL(CHANNEL), // 5-bit output: Channel selection outputs
|
|
.EOC(EOC), // 1-bit output: End of Conversion
|
|
.EOS(EOS), // 1-bit output: End of Sequence
|
|
.JTAGBUSY(JTAGBUSY), // 1-bit output: JTAG DRP transaction in progress output
|
|
.JTAGLOCKED(JTAGLOCKED), // 1-bit output: JTAG requested DRP port lock
|
|
.JTAGMODIFIED(JTAGMODIFIED), // 1-bit output: JTAG Write to the DRP has occurred
|
|
.MUXADDR(MUXADDR), // 5-bit output: External MUX channel decode
|
|
// Auxiliary Analog-Input Pairs: 16-bit (each) input: VAUXP[15:0], VAUXN[15:0]
|
|
.VAUXN(VAUXN), // 16-bit input: N-side auxiliary analog input
|
|
.VAUXP(VAUXP), // 16-bit input: P-side auxiliary analog input
|
|
// CONTROL and CLOCK: 1-bit (each) input: Reset, conversion start and clock inputs
|
|
.CONVST(CONVST), // 1-bit input: Convert start input
|
|
.CONVSTCLK(CONVSTCLK), // 1-bit input: Convert start input
|
|
.RESET(RESET), // 1-bit input: Active-high reset
|
|
// Dedicated Analog Input Pair: 1-bit (each) input: VP/VN
|
|
.VN(VN), // 1-bit input: N-side analog input
|
|
.VP(VP), // 1-bit input: P-side analog input
|
|
// Dynamic Reconfiguration Port (DRP): 7-bit (each) input: Dynamic Reconfiguration Ports
|
|
.DADDR(DADDR), // 7-bit input: DRP address bus
|
|
.DCLK(DCLK), // 1-bit input: DRP clock
|
|
.DEN(DEN), // 1-bit input: DRP enable signal
|
|
.DI(DI), // 16-bit input: DRP input data bus
|
|
.DWE(DWE) // 1-bit input: DRP write enable
|
|
);
|
|
|
|
// End of XADC_inst instantiation
|
|
</Template>
|
|
<Template label="XADC Simulation File" treetype="template">
|
|
// Must use valid headers on all columns
|
|
// Comments can be added to the stimulus file using '//'
|
|
|
|
TIME TEMP VCCAUX VCCINT VBRAM VP VN VAUXP[0] VAUXN[0]
|
|
00000 45 1.8 1.0 1.0 0.5 0.0 0.7 0.0
|
|
05000 85 1.77 1.01 1.01 0.3 0.0 0.2 0.0
|
|
|
|
// Time stamp data is in nano seconds (ns)
|
|
// Temperature is recorded in C (degrees centigrade)
|
|
// All other channels are recorded as V (Volts)
|
|
// Valid column headers are:
|
|
// TIME, TEMP, VCCAUX, VCCINT, VBRAM, VCCPINT, VCCPAUX, VCCDDRO, VP, VN,
|
|
// VAUXP[0], VAUXN[0],...............VAUXP[15], VAUXN[15]
|
|
// External analog inputs are differential so VP = 0.5 and VN = 0.1 the
|
|
// input on channel VP/VN in 0.5 - 0.1 = 0.4V
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Slice/CLB Primitives" treetype="folder">
|
|
<SubFolder label="MUXFx" treetype="folder">
|
|
<Template label="MUXF7" treetype="template">
|
|
// MUXF7 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF7_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF7: CLB MUX to tie two LUT6's together with general output
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF7 MUXF7_inst (
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie to LUT6 O6 pin)
|
|
.I1(I1), // Input (tie to LUT6 O6 pin)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF7_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF7_L" treetype="template">
|
|
// MUXF7_L : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF7_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF7_L: CLB MUX to tie two LUT6's together with local output
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF7_L MUXF7_L_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.I0(I0), // Input (tie to LUT6 O6 pin)
|
|
.I1(I1), // Input (tie to LUT6 O6 pin)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF7_L_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF7_D" treetype="template">
|
|
// MUXF7_D : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF7_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF7_D: CLB MUX to tie two LUT6's together with general and local outputs
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF7_D MUXF7_D_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie to LUT6 O6 pin)
|
|
.I1(I1), // Input (tie to LUT6 O6 pin)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF7_D_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF8" treetype="template">
|
|
// MUXF8 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF8_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF8: CLB MUX to tie two MUXF7's together with general output
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF8 MUXF8_inst (
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie to MUXF7 L/LO out)
|
|
.I1(I1), // Input (tie to MUXF7 L/LO out)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF8_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF8_L" treetype="template">
|
|
// MUXF8_L : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF8_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF8_L: CLB MUX to tie two MUXF7's together with local output
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF8_L MUXF8_L_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.I0(I0), // Input (tie to MUXF7 L/LO out)
|
|
.I1(I1), // Input (tie to MUXF7 L/LO out)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF8_L_inst instantiation
|
|
</Template>
|
|
<Template label="MUXF8_D" treetype="template">
|
|
// MUXF8_D : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MUXF8_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MUXF8_D: CLB MUX to tie two MUXF7's together with general and local outputs
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MUXF8_D MUXF8_D_inst (
|
|
.LO(LO), // Output of MUX to local routing
|
|
.O(O), // Output of MUX to general routing
|
|
.I0(I0), // Input (tie to MUXF7 L/LO out)
|
|
.I1(I1), // Input (tie to MUXF7 L/LO out)
|
|
.S(S) // Input select to MUX
|
|
);
|
|
|
|
// End of MUXF8_D_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="LUTs" treetype="folder">
|
|
<SubFolder label="Info" treetype="folder">
|
|
<Template label="Info (LUT INIT)" treetype="template">
|
|
// The INIT parameter for the FPGA LUT primitive is what gives the LUT its
|
|
// logical value. By default this value is zero thus driving the output to a
|
|
// zero regardless of the input values (acting as a ground) however in most
|
|
// cases an new INIT value must be determined in order to specify the logic
|
|
// function for the LUT primitive. There are a few methods in which the LUT
|
|
// value can be determined and two of those methods will be discussed here.
|
|
//
|
|
// The Truth Table Method
|
|
// ----------------------
|
|
//
|
|
// A common method to determine the desired INIT value for a LUT is using a
|
|
// truth table. To do so, simply create a binary truth table of all possible
|
|
// inputs, specify the desired logic value of the output and then create the
|
|
// INIT string from those output values. An example is shown below:
|
|
//
|
|
// Example of determining an XOR INIT equation for a LUT4:
|
|
//
|
|
// _________________
|
|
// | I3 I2 I1 I0 | O |
|
|
// |-----------------|
|
|
// | 0 0 0 0 | 0 |\
|
|
// | 0 0 0 1 | 1 | \ = 4'b0110 = 4'h6 ---------------+
|
|
// | 0 0 1 0 | 1 | / |
|
|
// | 0 0 1 1 | 0 |/ |
|
|
// |-------------|---| |
|
|
// | 0 1 0 0 | 1 |\ |
|
|
// | 0 1 0 1 | 0 | \ = 4'b1001 = 4'h9 |
|
|
// | 0 1 1 0 | 0 | / |
|
|
// | 0 1 1 1 | 1 |/ |
|
|
// |-------------|---| INIT = 16'h6996
|
|
// | 1 0 0 0 | 1 |\ |
|
|
// | 1 0 0 1 | 0 | \ = 4'b0110 = 4'h9 |
|
|
// | 1 0 1 0 | 0 | / |
|
|
// | 1 0 1 1 | 1 |/ |
|
|
// |-------------|---| |
|
|
// | 1 1 0 0 | 0 |\ |
|
|
// | 1 1 0 1 | 1 | \ = 4'b1001 = 4'h6 ------------+
|
|
// | 1 1 1 0 | 1 | /
|
|
// | 1 1 1 1 | 0 |/
|
|
// -------------------
|
|
//
|
|
// Example of determining a 3-input AND gate:
|
|
//
|
|
// ______________
|
|
// | I2 I1 I0 | O |
|
|
// |--------------|
|
|
// | 0 0 0 | 0 |\
|
|
// | 0 0 1 | 0 | \ = 4'b0000 = 4'h0 --------------+
|
|
// | 0 1 0 | 0 | / |
|
|
// | 0 1 1 | 0 |/ |
|
|
// |----------|---| INIT = 8'h80
|
|
// | 1 0 0 | 0 |\ |
|
|
// | 1 0 1 | 0 | \ = 4'b1000 = 4'h8 -------------+
|
|
// | 1 1 0 | 0 | /
|
|
// | 1 1 1 | 1 |/
|
|
// ----------------
|
|
//
|
|
// The Equation Method
|
|
// -------------------
|
|
//
|
|
// Another method to determine the LUT value is to define parameters for each
|
|
// input to the LUT that correspond to their listed truth value and use those to
|
|
// build the logic equation you are after. This method is easier to understand
|
|
// once you have grasped the concept and more self-documenting that the above
|
|
// method however does require the code to first specify the appropriate
|
|
// parameters. See the example below.
|
|
//
|
|
// Example of specifying the equation (A and B) or (C and D) for a LUT4:
|
|
//
|
|
// The following parameters are defined to allow for
|
|
// equation-based INIT specification.
|
|
parameter I0 = 16'haaaa;
|
|
parameter I1 = 16'hcccc;
|
|
parameter I2 = 16'hf0f0;
|
|
parameter I3 = 16'hff00;
|
|
|
|
// LUT4: 4-input Look-Up Table with general output (Mapped to a LUT6)
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT4 #(
|
|
.INIT((I0&I1)|(I2&I3)) // Specify LUT Contents
|
|
) LUT4_inst (
|
|
.O(O_LUT), // LUT general output
|
|
.I0(A), // LUT input
|
|
.I1(B), // LUT input
|
|
.I2(C), // LUT input
|
|
.I3(D) // LUT input
|
|
);
|
|
|
|
// End of LUT4_inst instantiation
|
|
|
|
// With the parameters specifying all possible cases for the truth table, a
|
|
// Verilog equation can be written to determine the end INIT value.
|
|
</Template>
|
|
<SubFolder label="INIT Parameters" treetype="folder">
|
|
<Template label="LUT1" treetype="template">
|
|
// The following parameter is defined to allow for
|
|
// equation-based INIT specification for a LUT1.
|
|
parameter I0 = 2'b10;
|
|
</Template>
|
|
<Template label="LUT2" treetype="template">
|
|
// The following parameters are defined to allow for
|
|
// equation-based INIT specification for a LUT2.
|
|
parameter I0 = 4'ha;
|
|
parameter I1 = 4'hc;
|
|
</Template>
|
|
<Template label="LUT3" treetype="template">
|
|
// The following parameters are defined to allow for
|
|
// equation-based INIT specification for a LUT3.
|
|
parameter I0 = 8'haa;
|
|
parameter I1 = 8'hcc;
|
|
parameter I2 = 8'hf0;
|
|
</Template>
|
|
<Template label="LUT4" treetype="template">
|
|
// The following parameters are defined to allow for
|
|
// equation-based INIT specification for a LUT4.
|
|
parameter I0 = 16'haaaa;
|
|
parameter I1 = 16'hcccc;
|
|
parameter I2 = 16'hf0f0;
|
|
parameter I3 = 16'hff00;
|
|
</Template>
|
|
<Template label="LUT5" treetype="template">
|
|
// The following parameters are defined to allow for
|
|
// equation-based INIT specification for a LUT5.
|
|
parameter I0 = 32'haaaaaaaa;
|
|
parameter I1 = 32'hcccccccc;
|
|
parameter I2 = 32'hf0f0f0f0;
|
|
parameter I3 = 32'hff00ff00;
|
|
parameter I4 = 32'hffff0000;
|
|
</Template>
|
|
<Template label="LUT6" treetype="template">
|
|
// The following parameters are defined to allow for
|
|
// equation-based INIT specification for a LUT6.
|
|
parameter I0 = 64'haaaaaaaaaaaaaaaa;
|
|
parameter I1 = 64'hcccccccccccccccc;
|
|
parameter I2 = 64'hf0f0f0f0f0f0f0f0;
|
|
parameter I3 = 64'hff00ff00ff00ff00;
|
|
parameter I4 = 64'hffff0000ffff0000;
|
|
parameter I5 = 64'hffffffff00000000;
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="INIT Truth Tables" treetype="folder">
|
|
<Template label="LUT1" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT1
|
|
// ________
|
|
// | I0 | O |
|
|
// |--------|
|
|
// | 0 | ? |\
|
|
// | 1 | ? |/ = 2'b??
|
|
// ----------
|
|
</Template>
|
|
<Template label="LUT2" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT2
|
|
// ______________
|
|
// | I2 I1 I0 | O |
|
|
// |--------------|
|
|
// | 0 0 0 | ? |\
|
|
// | 0 0 1 | ? | \ = INIT = 4'b???? = 4'h?
|
|
// | 0 1 0 | ? | /
|
|
// | 0 1 1 | ? |/
|
|
// ---------- ---
|
|
</Template>
|
|
<Template label="LUT3" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT3
|
|
// ______________
|
|
// | I2 I1 I0 | O |
|
|
// |--------------|
|
|
// | 0 0 0 | ? |\
|
|
// | 0 0 1 | ? | \ = 4'b???? = 4'h? --------------+
|
|
// | 0 1 0 | ? | / |
|
|
// | 0 1 1 | ? |/ |
|
|
// |----------|---| INIT = 8'h??
|
|
// | 1 0 0 | ? |\ |
|
|
// | 1 0 1 | ? | \ = 4'b???? = 4'h? -------------+
|
|
// | 1 1 0 | ? | /
|
|
// | 1 1 1 | ? |/
|
|
// ----------------
|
|
</Template>
|
|
<Template label="LUT4" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT4
|
|
// _________________
|
|
// | I3 I2 I1 I0 | O |
|
|
// |-----------------|
|
|
// | 0 0 0 0 | ? |\
|
|
// | 0 0 0 1 | ? | \ = 4'b???? = 4'h? ---------------+
|
|
// | 0 0 1 0 | ? | / |
|
|
// | 0 0 1 1 | ? |/ |
|
|
// |-------------|---| |
|
|
// | 0 1 0 0 | ? |\ |
|
|
// | 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 1 0 | ? | / |
|
|
// | 0 1 1 1 | ? |/ |
|
|
// |-------------|---| INIT = 16'h????
|
|
// | 1 0 0 0 | ? |\ |
|
|
// | 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 1 0 | ? | / |
|
|
// | 1 0 1 1 | ? |/ |
|
|
// |-------------|---| |
|
|
// | 1 1 0 0 | ? |\ |
|
|
// | 1 1 0 1 | ? | \ = 4'b???? = 4'h? ------------+
|
|
// | 1 1 1 0 | ? | /
|
|
// | 1 1 1 1 | ? |/
|
|
// -------------------
|
|
</Template>
|
|
<Template label="LUT5" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT5
|
|
// ____________________
|
|
// | I4 I3 I2 I1 I0 | O |
|
|
// |--------------------|
|
|
// | 0 0 0 0 0 | ? |\
|
|
// | 0 0 0 0 1 | ? | \ = 4'b???? = 4'h? -------------------+
|
|
// | 0 0 0 1 0 | ? | / |
|
|
// | 0 0 0 1 1 | ? |/ |
|
|
// |----------------|---| |
|
|
// | 0 0 1 0 0 | ? |\ |
|
|
// | 0 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 0 1 1 0 | ? | / |
|
|
// | 0 0 1 1 1 | ? |/ |
|
|
// |----------------|---| |
|
|
// | 0 1 0 0 0 | ? |\ |
|
|
// | 0 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 0 1 0 | ? | / |
|
|
// | 0 1 0 1 1 | ? |/ |
|
|
// |----------------|---| |
|
|
// | 0 1 1 0 0 | ? |\ |
|
|
// | 0 1 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 1 1 0 | ? | / |
|
|
// | 0 1 1 1 1 | ? |/ |
|
|
// ---------------------- INIT = 32'h????????
|
|
// | 1 0 0 0 0 | ? |\ |
|
|
// | 1 0 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 0 1 0 | ? | / |
|
|
// | 1 0 0 1 1 | ? |/ |
|
|
// |----------------|---| |
|
|
// | 1 0 1 0 0 | ? |\ |
|
|
// | 1 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 1 1 0 | ? | / |
|
|
// | 1 0 1 1 1 | ? |/ |
|
|
// |----------------|---| |
|
|
// | 1 1 0 0 0 | ? |\ |
|
|
// | 1 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 1 0 1 0 | ? | / |
|
|
// | 1 1 0 1 1 | ? |/ |
|
|
// |----------------|---| |
|
|
// | 1 1 1 0 0 | ? |\ |
|
|
// | 1 1 1 0 1 | ? | \ = 4'b???? = 4'h? ------------+
|
|
// | 1 1 1 1 0 | ? | /
|
|
// | 1 1 1 1 1 | ? |/
|
|
// ----------------------
|
|
</Template>
|
|
<Template label="LUT6" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT6
|
|
// _______________________
|
|
// | I5 I4 I3 I2 I1 I0 | O |
|
|
// |-----------------------|
|
|
// | 0 0 0 0 0 0 | ? |\
|
|
// | 0 0 0 0 0 1 | ? | \ = 4'b???? = 4'h? -------------------+
|
|
// | 0 0 0 0 1 0 | ? | / |
|
|
// | 0 0 0 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 0 0 0 1 0 0 | ? |\ |
|
|
// | 0 0 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 0 0 1 1 0 | ? | / |
|
|
// | 0 0 0 1 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 0 0 1 0 0 0 | ? |\ |
|
|
// | 0 0 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 0 1 0 1 0 | ? | / |
|
|
// | 0 0 1 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 0 0 1 1 0 0 | ? |\ |
|
|
// | 0 0 1 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 0 1 1 1 0 | ? | / |
|
|
// | 0 0 1 1 1 1 | ? |/ |
|
|
// ------------------------- |
|
|
// | 0 1 0 0 0 0 | ? |\ |
|
|
// | 0 1 0 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 0 0 1 0 | ? | / |
|
|
// | 0 1 0 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 0 1 0 1 0 0 | ? |\ |
|
|
// | 0 1 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 0 1 1 0 | ? | / |
|
|
// | 0 1 0 1 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 0 1 1 0 0 0 | ? |\ |
|
|
// | 0 1 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 1 0 1 0 | ? | / |
|
|
// | 0 1 1 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 0 1 1 1 0 0 | ? |\ |
|
|
// | 0 1 1 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 1 1 1 0 | ? | / |
|
|
// | 0 1 1 1 1 1 | ? |/ |
|
|
// ------------------------ INIT = 64'h????????????????
|
|
// | 1 0 0 0 0 0 | ? |\ |
|
|
// | 1 0 0 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 0 0 1 0 | ? | / |
|
|
// | 1 0 0 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 0 0 1 0 0 | ? |\ |
|
|
// | 1 0 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 0 1 1 0 | ? | / |
|
|
// | 1 0 0 1 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 0 1 0 0 0 | ? |\ |
|
|
// | 1 0 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 1 0 1 0 | ? | / |
|
|
// | 1 0 1 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 0 1 1 0 0 | ? |\ |
|
|
// | 1 0 1 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 1 1 1 0 | ? | / |
|
|
// | 1 0 1 1 1 1 | ? |/ |
|
|
// ------------------------- |
|
|
// | 1 1 0 0 0 0 | ? |\ |
|
|
// | 1 1 0 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 1 0 0 1 0 | ? | / |
|
|
// | 1 1 0 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 1 0 1 0 0 | ? |\ |
|
|
// | 1 1 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 1 0 1 1 0 | ? | / |
|
|
// | 1 1 0 1 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 1 1 0 0 0 | ? |\ |
|
|
// | 1 1 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 1 1 0 1 0 | ? | / |
|
|
// | 1 1 1 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 1 1 1 0 0 | ? |\ |
|
|
// | 1 1 1 1 0 1 | ? | \ = 4'b???? = 4'h? ----+
|
|
// | 1 1 1 1 1 0 | ? | /
|
|
// | 1 1 1 1 1 1 | ? |/
|
|
// ------------------------
|
|
</Template>
|
|
<Template label="LUT6_2" treetype="template">
|
|
// Truth Table to determine INIT value for a LUT6_2
|
|
// _____________________________
|
|
// | I5 I4 I3 I2 I1 I0 | O6 | O5 |
|
|
// |-----------------------------|
|
|
// | 0 0 0 0 0 0 | ? |\
|
|
// | 0 0 0 0 0 1 | ? | \ = 4'b???? = 4'h? -------------+
|
|
// | 0 0 0 0 1 0 | ? | / |
|
|
// | 0 0 0 0 1 1 | ? |/ |
|
|
// |-------------------|---------| |
|
|
// | 0 0 0 1 0 0 | ? |\ |
|
|
// | 0 0 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 0 0 1 1 0 | ? | / |
|
|
// | 0 0 0 1 1 1 | ? |/ |
|
|
// |-------------------|---------| |
|
|
// | 0 0 1 0 0 0 | ? |\ |
|
|
// | 0 0 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 0 1 0 1 0 | ? | / |
|
|
// | 0 0 1 0 1 1 | ? |/ |
|
|
// |-------------------|---------| |
|
|
// | 0 0 1 1 0 0 | ? |\ |
|
|
// | 0 0 1 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 0 1 1 1 0 | ? | / |
|
|
// | 0 0 1 1 1 1 | ? |/ |
|
|
// ------------------------------- |
|
|
// | 0 1 0 0 0 0 | ? |\ |
|
|
// | 0 1 0 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 0 0 1 0 | ? | / |
|
|
// | 0 1 0 0 1 1 | ? |/ |
|
|
// |-------------------|---------| |
|
|
// | 0 1 0 1 0 0 | ? |\ |
|
|
// | 0 1 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 0 1 1 0 | ? | / |
|
|
// | 0 1 0 1 1 1 | ? |/ |
|
|
// |-------------------|---------| |
|
|
// | 0 1 1 0 0 0 | ? |\ |
|
|
// | 0 1 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 1 0 1 0 | ? | / |
|
|
// | 0 1 1 0 1 1 | ? |/ |
|
|
// |-------------------|---------| |
|
|
// | 0 1 1 1 0 0 | ? |\ |
|
|
// | 0 1 1 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 0 1 1 1 1 0 | ? | / |
|
|
// | 0 1 1 1 1 1 | ? |/ |
|
|
// ------------------------------ INIT = 64'h????????????????
|
|
// | 1 0 0 0 0 0 | ? |\ |
|
|
// | 1 0 0 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 0 0 1 0 | ? | / |
|
|
// | 1 0 0 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 0 0 1 0 0 | ? |\ |
|
|
// | 1 0 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 0 1 1 0 | ? | / |
|
|
// | 1 0 0 1 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 0 1 0 0 0 | ? |\ |
|
|
// | 1 0 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 1 0 1 0 | ? | / |
|
|
// | 1 0 1 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 0 1 1 0 0 | ? |\ |
|
|
// | 1 0 1 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 0 1 1 1 0 | ? | / |
|
|
// | 1 0 1 1 1 1 | ? |/ |
|
|
// ------------------------- |
|
|
// | 1 1 0 0 0 0 | ? |\ |
|
|
// | 1 1 0 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 1 0 0 1 0 | ? | / |
|
|
// | 1 1 0 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 1 0 1 0 0 | ? |\ |
|
|
// | 1 1 0 1 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 1 0 1 1 0 | ? | / |
|
|
// | 1 1 0 1 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 1 1 0 0 0 | ? |\ |
|
|
// | 1 1 1 0 0 1 | ? | \ = 4'b???? = 4'h? |
|
|
// | 1 1 1 0 1 0 | ? | / |
|
|
// | 1 1 1 0 1 1 | ? |/ |
|
|
// |-------------------|---| |
|
|
// | 1 1 1 1 0 0 | ? |\ |
|
|
// | 1 1 1 1 0 1 | ? | \ = 4'b???? = 4'h? ----+
|
|
// | 1 1 1 1 1 0 | ? | /
|
|
// | 1 1 1 1 1 1 | ? |/
|
|
// ------------------------
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<Template label="LUT4" treetype="template">
|
|
// LUT4 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT4_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT4: 4-input Look-Up Table with general output (Mapped to a LUT6)
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT4 #(
|
|
.INIT(16'h0000) // Specify LUT Contents
|
|
) LUT4_inst (
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3) // LUT input
|
|
);
|
|
|
|
// End of LUT4_inst instantiation
|
|
</Template>
|
|
<Template label="LUT4_L" treetype="template">
|
|
// LUT4_L : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT4_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT4_L: 4-input Look-Up Table with local output (Mapped to a LUT6)
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT4_L #(
|
|
.INIT(16'h0000) // Specify LUT Contents
|
|
) LUT4_L_inst (
|
|
.LO(LO), // LUT local output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3) // LUT input
|
|
);
|
|
|
|
// End of LUT4_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT4_D" treetype="template">
|
|
// LUT4_D : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT4_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT4_D: 4-input Look-Up Table with general and local outputs (Mapped to a LUT6)
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT4_D #(
|
|
.INIT(16'h0000) // Specify LUT Contents
|
|
) LUT4_D_inst (
|
|
.LO(LO), // LUT local output
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3) // LUT input
|
|
);
|
|
|
|
// End of LUT4_D_inst instantiation
|
|
</Template>
|
|
<Template label="LUT3" treetype="template">
|
|
// LUT3 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT3_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT3: 3-input Look-Up Table with general output (Mapped to a LUT6)
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT3 #(
|
|
.INIT(8'h00) // Specify LUT Contents
|
|
) LUT3_inst (
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2) // LUT input
|
|
);
|
|
|
|
// End of LUT3_inst instantiation
|
|
</Template>
|
|
<Template label="LUT3_L" treetype="template">
|
|
// LUT3_L : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT3_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT3_L: 3-input Look-Up Table with local output (Mapped to a LUT6)
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT3_L #(
|
|
.INIT(8'h00) // Specify LUT Contents
|
|
) LUT3_L_inst (
|
|
.LO(LO), // LUT local output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2) // LUT input
|
|
);
|
|
|
|
// End of LUT3_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT3_D" treetype="template">
|
|
// LUT3_D : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT3_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT3_D: 3-input Look-Up Table with general and local outputs (Mapped to a LUT6)
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT3_D #(
|
|
.INIT(8'h00) // Specify LUT Contents
|
|
) LUT3_D_inst (
|
|
.LO(LO), // LUT local output
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2) // LUT input
|
|
);
|
|
|
|
// End of LUT3_D_inst instantiation
|
|
</Template>
|
|
<Template label="LUT2" treetype="template">
|
|
// LUT2 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT2: 2-input Look-Up Table with general output (Mapped to a LUT6)
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT2 #(
|
|
.INIT(4'h0) // Specify LUT Contents
|
|
) LUT2_inst (
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1) // LUT input
|
|
);
|
|
|
|
// End of LUT2_inst instantiation
|
|
</Template>
|
|
<Template label="LUT2_L" treetype="template">
|
|
// LUT2_L : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT2_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT2_L: 2-input Look-Up Table with local output (Mapped to a LUT6)
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT2_L #(
|
|
.INIT(4'h0) // Specify LUT Contents
|
|
) LUT2_L_inst (
|
|
.LO(LO), // LUT local output
|
|
.I0(I0), // LUT input
|
|
.I1(I1) // LUT input
|
|
);
|
|
|
|
// End of LUT2_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT2_D" treetype="template">
|
|
// LUT2_D : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT2_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT2_D: 2-input Look-Up Table with general and local outputs (Mapped to a LUT6)
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT2_D #(
|
|
.INIT(4'h0) // Specify LUT Contents
|
|
) LUT2_D_inst (
|
|
.LO(LO), // LUT local output
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1) // LUT input
|
|
);
|
|
|
|
// End of LUT2_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT1" treetype="template">
|
|
// LUT1 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT1_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT1: 1-input Look-Up Table with general output (Mapped to a LUT6)
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT1 #(
|
|
.INIT(2'b00) // Specify LUT Contents
|
|
) LUT1_inst (
|
|
.O(O), // LUT general output
|
|
.I0(I0) // LUT input
|
|
);
|
|
|
|
// End of LUT1_inst instantiation
|
|
</Template>
|
|
<Template label="LUT1_L" treetype="template">
|
|
// LUT1_L : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT1_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT1_L: 1-input Look-Up Table with local output (Mapped to a LUT6)
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT1_L #(
|
|
.INIT(2'b00) // Specify LUT Contents
|
|
) LUT1_L_inst (
|
|
.LO(LO), // LUT local output
|
|
.I0(I0) // LUT input
|
|
);
|
|
|
|
// End of LUT1_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT1_D" treetype="template">
|
|
// LUT1_D : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT1_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT1_D: 1-input Look-Up Table with general and local outputs (Mapped to a LUT6)
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT1_D #(
|
|
.INIT(2'b00) // Specify LUT Contents
|
|
) LUT1_D_inst (
|
|
.LO(LO), // LUT local output
|
|
.O(O), // LUT general output
|
|
.I0(I0) // LUT input
|
|
);
|
|
|
|
// End of LUT1_D_inst instantiation
|
|
</Template>
|
|
<Template label="Reconfigurable LUT (CFGLUT5)" treetype="template">
|
|
// CFGLUT5 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (CFGLUT5_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// CFGLUT5: Reconfigurable 5-input LUT (Mapped to a SliceM LUT6)
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
CFGLUT5 #(
|
|
.INIT(32'h00000000) // Specify initial LUT contents
|
|
) CFGLUT5_inst (
|
|
.CDO(CDO), // Reconfiguration cascade output
|
|
.O5(O5), // 4-LUT output
|
|
.O6(O6), // 5-LUT output
|
|
.CDI(CDI), // Reconfiguration data input
|
|
.CE(CE), // Reconfiguration enable input
|
|
.CLK(CLK), // Clock input
|
|
.I0(I0), // Logic data input
|
|
.I1(I1), // Logic data input
|
|
.I2(I2), // Logic data input
|
|
.I3(I3), // Logic data input
|
|
.I4(I4) // Logic data input
|
|
);
|
|
|
|
// End of CFGLUT5_inst instantiation
|
|
</Template>
|
|
<Template label="LUT5" treetype="template">
|
|
// LUT5 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT5_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT5: 5-input Look-Up Table with general output (Mapped to a LUT6)
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT5 #(
|
|
.INIT(32'h00000000) // Specify LUT Contents
|
|
) LUT5_inst (
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3), // LUT input
|
|
.I4(I4) // LUT input
|
|
);
|
|
|
|
// End of LUT5_inst instantiation
|
|
</Template>
|
|
<Template label="LUT5_L" treetype="template">
|
|
// LUT5_L : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT5_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT5_L: 5-input Look-Up Table with local output (Mapped to a LUT6)
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT5_L #(
|
|
.INIT(32'h0000000) // Specify LUT Contents
|
|
) LUT5_L_inst (
|
|
.LO(LO), // LUT local output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3), // LUT input
|
|
.I4(I4) // LUT input
|
|
);
|
|
|
|
// End of LUT5_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT5_D" treetype="template">
|
|
// LUT5_D : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT5_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT5_D: 5-input Look-Up Table with general and local outputs (Mapped to a LUT6)
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT5_D #(
|
|
.INIT(32'h0000000) // Specify LUT Contents
|
|
) LUT5_D_inst (
|
|
.LO(LO), // LUT local output
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3), // LUT input
|
|
.I4(I4) // LUT input
|
|
);
|
|
|
|
// End of LUT5_D_inst instantiation
|
|
</Template>
|
|
<Template label="LUT6" treetype="template">
|
|
// LUT6 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT6_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT6: 6-input Look-Up Table with general output
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT6 #(
|
|
.INIT(64'h0000000000000000) // Specify LUT Contents
|
|
) LUT6_inst (
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3), // LUT input
|
|
.I4(I4), // LUT input
|
|
.I5(I5) // LUT input
|
|
);
|
|
|
|
// End of LUT6_inst instantiation
|
|
</Template>
|
|
<Template label="LUT6_L" treetype="template">
|
|
// LUT6_L : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT6_L_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT6_L: 6-input Look-Up Table with local output
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT6_L #(
|
|
.INIT(64'h0000000000000000) // Specify LUT Contents
|
|
) LUT6_L_inst (
|
|
.LO(LO), // LUT local output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3), // LUT input
|
|
.I4(I4), // LUT input
|
|
.I5(I5) // LUT input
|
|
);
|
|
|
|
// End of LUT6_L_inst instantiation
|
|
</Template>
|
|
<Template label="LUT6_D" treetype="template">
|
|
// LUT6_D : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT6_D_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT6_D: 6-input Look-Up Table with general and local outputs
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT6_D #(
|
|
.INIT(64'h0000000000000000) // Specify LUT Contents
|
|
) LUT6_D_inst (
|
|
.LO(LO), // LUT local output
|
|
.O(O), // LUT general output
|
|
.I0(I0), // LUT input
|
|
.I1(I1), // LUT input
|
|
.I2(I2), // LUT input
|
|
.I3(I3), // LUT input
|
|
.I4(I4), // LUT input
|
|
.I5(I5) // LUT input
|
|
);
|
|
|
|
// End of LUT6_D_inst instantiation
|
|
</Template>
|
|
<Template label="LUT6_2" treetype="template">
|
|
// LUT6_2 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LUT6_2_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LUT6_2: 6-input, 2 output Look-Up Table
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LUT6_2 #(
|
|
.INIT(64'h0000000000000000) // Specify LUT Contents
|
|
) LUT6_2_inst (
|
|
.O6(O6), // 1-bit LUT6 output
|
|
.O5(O5), // 1-bit lower LUT5 output
|
|
.I0(I0), // 1-bit LUT input
|
|
.I1(I1), // 1-bit LUT input
|
|
.I2(I2), // 1-bit LUT input
|
|
.I3(I3), // 1-bit LUT input
|
|
.I4(I4), // 1-bit LUT input
|
|
.I5(I5) // 1-bit LUT input (fast MUX select only available to O6 output)
|
|
);
|
|
|
|
// End of LUT6_2_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Shift Register LUT" treetype="folder">
|
|
<Template label="16-bit w/ CE posedge SR (SRL16E)" treetype="template">
|
|
// SRL16E : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SRL16E_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SRL16E: 16-bit shift register LUT with clock enable operating on posedge of clock (Mapped to a SliceM LUT6)
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SRL16E #(
|
|
.INIT(16'h0000) // Initial Value of Shift Register
|
|
) SRL16E_inst (
|
|
.Q(Q), // SRL data output
|
|
.A0(A0), // Select[0] input
|
|
.A1(A1), // Select[1] input
|
|
.A2(A2), // Select[2] input
|
|
.A3(A3), // Select[3] input
|
|
.CE(CE), // Clock enable input
|
|
.CLK(CLK), // Clock input
|
|
.D(D) // SRL data input
|
|
);
|
|
|
|
// End of SRL16E_inst instantiation
|
|
</Template>
|
|
<Template label="32-bit w/ CE posedge SR (SRLC32E)" treetype="template">
|
|
// SRLC32E : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (SRL32E_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// SRLC32E: 32-bit variable length cascadable shift register LUT (Mapped to a SliceM LUT6)
|
|
// with clock enable
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
SRLC32E #(
|
|
.INIT(32'h00000000) // Initial Value of Shift Register
|
|
) SRLC32E_inst (
|
|
.Q(Q), // SRL data output
|
|
.Q31(Q31), // SRL cascade output pin
|
|
.A(A), // 5-bit shift depth select input
|
|
.CE(CE), // Clock enable input
|
|
.CLK(CLK), // Clock input
|
|
.D(D) // SRL data input
|
|
);
|
|
|
|
// End of SRLC32E_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<Template label="Carry (CARRY4)" treetype="template">
|
|
// CARRY4 : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (CARRY4_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs and
|
|
// : and outputs of this primitive should be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// CARRY4: Fast Carry Logic Component
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
CARRY4 CARRY4_inst (
|
|
.CO(CO), // 4-bit carry out
|
|
.O(O), // 4-bit carry chain XOR data out
|
|
.CI(CI), // 1-bit carry cascade input
|
|
.CYINIT(CYINIT), // 1-bit carry initialization
|
|
.DI(DI), // 4-bit carry-MUX data in
|
|
.S(S) // 4-bit carry-MUX select input
|
|
);
|
|
|
|
// End of CARRY4_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Registers & Latches" treetype="folder">
|
|
<SubFolder label="Single Data Rate" treetype="folder">
|
|
<Template label="Posedge D-FF w/ Async Clear and CE (FDCE)" treetype="template">
|
|
// FDCE : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FDCE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FDCE: Single Data Rate D Flip-Flop with Asynchronous Clear and
|
|
// Clock Enable (posedge clk).
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FDCE #(
|
|
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
|
|
) FDCE_inst (
|
|
.Q(Q), // 1-bit Data output
|
|
.C(C), // 1-bit Clock input
|
|
.CE(CE), // 1-bit Clock enable input
|
|
.CLR(CLR), // 1-bit Asynchronous clear input
|
|
.D(D) // 1-bit Data input
|
|
);
|
|
|
|
// End of FDCE_inst instantiation
|
|
</Template>
|
|
<Template label="Posedge D-FF w/ Async Preset and CE (FDPE)" treetype="template">
|
|
// FDPE : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FDPE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FDPE: Single Data Rate D Flip-Flop with Asynchronous Preset and
|
|
// Clock Enable (posedge clk).
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FDPE #(
|
|
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
|
|
) FDPE_inst (
|
|
.Q(Q), // 1-bit Data output
|
|
.C(C), // 1-bit Clock input
|
|
.CE(CE), // 1-bit Clock enable input
|
|
.PRE(PRE), // 1-bit Asynchronous preset input
|
|
.D(D) // 1-bit Data input
|
|
);
|
|
|
|
// End of FDPE_inst instantiation
|
|
</Template>
|
|
<Template label="Posedge D-FF w/ Sync Reset and CE (FDRE)" treetype="template">
|
|
// FDRE : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FDRE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FDRE: Single Data Rate D Flip-Flop with Synchronous Reset and
|
|
// Clock Enable (posedge clk).
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FDRE #(
|
|
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
|
|
) FDRE_inst (
|
|
.Q(Q), // 1-bit Data output
|
|
.C(C), // 1-bit Clock input
|
|
.CE(CE), // 1-bit Clock enable input
|
|
.R(R), // 1-bit Synchronous reset input
|
|
.D(D) // 1-bit Data input
|
|
);
|
|
|
|
// End of FDRE_inst instantiation
|
|
</Template>
|
|
<Template label="Posedge D-FF w/ Sync Set and CE (FDSE)" treetype="template">
|
|
// FDSE : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FDSE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FDSE: Single Data Rate D Flip-Flop with Synchronous Set and
|
|
// Clock Enable (posedge clk).
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
FDSE #(
|
|
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
|
|
) FDSE_inst (
|
|
.Q(Q), // 1-bit Data output
|
|
.C(C), // 1-bit Clock input
|
|
.CE(CE), // 1-bit Clock enable input
|
|
.S(S), // 1-bit Synchronous set input
|
|
.D(D) // 1-bit Data input
|
|
);
|
|
|
|
// End of FDSE_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Transparent Latch" treetype="folder">
|
|
<Template label="Latch with Async Reset and Gate Enable (LDCE)" treetype="template">
|
|
// LDCE : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LDCE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LDCE: Transparent latch with Asynchronous Reset and Gate Enable.
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LDCE #(
|
|
.INIT(1'b0) // Initial value of latch (1'b0 or 1'b1)
|
|
) LDCE_inst (
|
|
.Q(Q), // Data output
|
|
.CLR(CLR), // Asynchronous clear/reset input
|
|
.D(D), // Data input
|
|
.G(G), // Gate input
|
|
.GE(GE) // Gate enable input
|
|
);
|
|
|
|
// End of LDCE_inst instantiation
|
|
</Template>
|
|
<Template label="Latch with Async Set and Gate Enable (LDPE)" treetype="template">
|
|
// LDPE : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (LDPE_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// LDPE: Transparent latch with Asynchronous Preset and Gate Enable.
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
LDPE #(
|
|
.INIT(1'b1) // Initial value of latch (1'b0 or 1'b1)
|
|
) LDPE_inst (
|
|
.Q(Q), // Data output
|
|
.PRE(PRE), // Asynchronous preset/set input
|
|
.D(D), // Data input
|
|
.G(G), // Gate input
|
|
.GE(GE) // Gate enable input
|
|
);
|
|
|
|
// End of LDPE_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Double Data Rate" treetype="folder">
|
|
<Template label="Dual-Clock, Input DDR Register (IDDR_2CLK)" treetype="template">
|
|
// IDDR_2CLK : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IDDR_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IDDR_2CLK: Dual-Clock, Input Double Data Rate Input Register with
|
|
// Set, Reset and Clock Enable.
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IDDR_2CLK #(
|
|
.DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE", "SAME_EDGE"
|
|
// or "SAME_EDGE_PIPELINED"
|
|
.INIT_Q1(1'b0), // Initial value of Q1: 1'b0 or 1'b1
|
|
.INIT_Q2(1'b0), // Initial value of Q2: 1'b0 or 1'b1
|
|
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
|
|
) IDDR_2CLK_inst (
|
|
.Q1(Q1), // 1-bit output for positive edge of clock
|
|
.Q2(Q2), // 1-bit output for negative edge of clock
|
|
.C(C), // 1-bit primary clock input
|
|
.CB(CB), // 1-bit secondary clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.D(D), // 1-bit DDR data input
|
|
.R(R), // 1-bit reset
|
|
.S(S) // 1-bit set
|
|
);
|
|
|
|
// End of IDDR_2CLK_inst instantiation
|
|
</Template>
|
|
<Template label="Input DDR Register (IDDR)" treetype="template">
|
|
// IDDR : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (IDDR_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// IDDR: Input Double Data Rate Input Register with Set, Reset
|
|
// and Clock Enable.
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
IDDR #(
|
|
.DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE", "SAME_EDGE"
|
|
// or "SAME_EDGE_PIPELINED"
|
|
.INIT_Q1(1'b0), // Initial value of Q1: 1'b0 or 1'b1
|
|
.INIT_Q2(1'b0), // Initial value of Q2: 1'b0 or 1'b1
|
|
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
|
|
) IDDR_inst (
|
|
.Q1(Q1), // 1-bit output for positive edge of clock
|
|
.Q2(Q2), // 1-bit output for negative edge of clock
|
|
.C(C), // 1-bit clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.D(D), // 1-bit DDR data input
|
|
.R(R), // 1-bit reset
|
|
.S(S) // 1-bit set
|
|
);
|
|
|
|
// End of IDDR_inst instantiation
|
|
</Template>
|
|
<Template label="Output DDR Register (ODDR)" treetype="template">
|
|
// ODDR : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ODDR_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. Delete or comment
|
|
// : out inputs/outs that are not necessary.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ODDR: Output Double Data Rate Output Register with Set, Reset
|
|
// and Clock Enable.
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ODDR #(
|
|
.DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE"
|
|
.INIT(1'b0), // Initial value of Q: 1'b0 or 1'b1
|
|
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
|
|
) ODDR_inst (
|
|
.Q(Q), // 1-bit DDR output
|
|
.C(C), // 1-bit clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.D1(D1), // 1-bit data input (positive edge)
|
|
.D2(D2), // 1-bit data input (negative edge)
|
|
.R(R), // 1-bit reset
|
|
.S(S) // 1-bit set
|
|
);
|
|
|
|
// End of ODDR_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
</Folder>
|
|
<Folder label="Device Macro Instantiation" treetype="folder">
|
|
<SubFolder label="Artix-7" treetype="folder">
|
|
<SubFolder label="RAM" treetype="folder">
|
|
<Template label="Single Port RAM (BRAM_SINGLE_MACRO)" treetype="template">
|
|
// BRAM_SINGLE_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BRAM_SINGLE_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BRAM_SINGLE_MACRO: Single Port RAM
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
/////////////////////////////////////////////////////////////////////
|
|
// READ_WIDTH | BRAM_SIZE | READ Depth | ADDR Width | //
|
|
// WRITE_WIDTH | | WRITE Depth | | WE Width //
|
|
// ============|===========|=============|============|============//
|
|
// 37-72 | "36Kb" | 512 | 9-bit | 8-bit //
|
|
// 19-36 | "36Kb" | 1024 | 10-bit | 4-bit //
|
|
// 19-36 | "18Kb" | 512 | 9-bit | 4-bit //
|
|
// 10-18 | "36Kb" | 2048 | 11-bit | 2-bit //
|
|
// 10-18 | "18Kb" | 1024 | 10-bit | 2-bit //
|
|
// 5-9 | "36Kb" | 4096 | 12-bit | 1-bit //
|
|
// 5-9 | "18Kb" | 2048 | 11-bit | 1-bit //
|
|
// 3-4 | "36Kb" | 8192 | 13-bit | 1-bit //
|
|
// 3-4 | "18Kb" | 4096 | 12-bit | 1-bit //
|
|
// 2 | "36Kb" | 16384 | 14-bit | 1-bit //
|
|
// 2 | "18Kb" | 8192 | 13-bit | 1-bit //
|
|
// 1 | "36Kb" | 32768 | 15-bit | 1-bit //
|
|
// 1 | "18Kb" | 16384 | 14-bit | 1-bit //
|
|
/////////////////////////////////////////////////////////////////////
|
|
|
|
BRAM_SINGLE_MACRO #(
|
|
.BRAM_SIZE("18Kb"), // Target BRAM, "18Kb" or "36Kb"
|
|
.DEVICE("7SERIES"), // Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6", "7SERIES"
|
|
.DO_REG(0), // Optional output register (0 or 1)
|
|
.INIT(36'h000000000), // Initial values on output port
|
|
.INIT_FILE ("NONE"),
|
|
.WRITE_WIDTH(0), // Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
|
|
.READ_WIDTH(0), // Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
|
|
.SRVAL(36'h000000000), // Set/Reset value for port output
|
|
.WRITE_MODE("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INIT_xx are valid when configured as 36Kb
|
|
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INIT_xx are valid when configured as 36Kb
|
|
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) BRAM_SINGLE_MACRO_inst (
|
|
.DO(DO), // Output data, width defined by READ_WIDTH parameter
|
|
.ADDR(ADDR), // Input address, width defined by read/write port depth
|
|
.CLK(CLK), // 1-bit input clock
|
|
.DI(DI), // Input data port, width defined by WRITE_WIDTH parameter
|
|
.EN(EN), // 1-bit input RAM enable
|
|
.REGCE(REGCE), // 1-bit input output register enable
|
|
.RST(RST), // 1-bit input reset
|
|
.WE(WE) // Input write enable, width defined by write port depth
|
|
);
|
|
|
|
// End of BRAM_SINGLE_MACRO_inst instantiation
|
|
</Template>
|
|
<Template label="Simple Dual Port RAM (BRAM_SDP_MACRO)" treetype="template">
|
|
// BRAM_SDP_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BRAM_SDP_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BRAM_SDP_MACRO: Simple Dual Port RAM
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
///////////////////////////////////////////////////////////////////////
|
|
// READ_WIDTH | BRAM_SIZE | READ Depth | RDADDR Width | //
|
|
// WRITE_WIDTH | | WRITE Depth | WRADDR Width | WE Width //
|
|
// ============|===========|=============|==============|============//
|
|
// 37-72 | "36Kb" | 512 | 9-bit | 8-bit //
|
|
// 19-36 | "36Kb" | 1024 | 10-bit | 4-bit //
|
|
// 19-36 | "18Kb" | 512 | 9-bit | 4-bit //
|
|
// 10-18 | "36Kb" | 2048 | 11-bit | 2-bit //
|
|
// 10-18 | "18Kb" | 1024 | 10-bit | 2-bit //
|
|
// 5-9 | "36Kb" | 4096 | 12-bit | 1-bit //
|
|
// 5-9 | "18Kb" | 2048 | 11-bit | 1-bit //
|
|
// 3-4 | "36Kb" | 8192 | 13-bit | 1-bit //
|
|
// 3-4 | "18Kb" | 4096 | 12-bit | 1-bit //
|
|
// 2 | "36Kb" | 16384 | 14-bit | 1-bit //
|
|
// 2 | "18Kb" | 8192 | 13-bit | 1-bit //
|
|
// 1 | "36Kb" | 32768 | 15-bit | 1-bit //
|
|
// 1 | "18Kb" | 16384 | 14-bit | 1-bit //
|
|
///////////////////////////////////////////////////////////////////////
|
|
|
|
BRAM_SDP_MACRO #(
|
|
.BRAM_SIZE("18Kb"), // Target BRAM, "18Kb" or "36Kb"
|
|
.DEVICE("7SERIES"), // Target device: "VIRTEX5", "VIRTEX6", "SPARTAN6", "7SERIES"
|
|
.WRITE_WIDTH(0), // Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
|
|
.READ_WIDTH(0), // Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
|
|
.DO_REG(0), // Optional output register (0 or 1)
|
|
.INIT_FILE ("NONE"),
|
|
.SIM_COLLISION_CHECK ("ALL"), // Collision check enable "ALL", "WARNING_ONLY",
|
|
// "GENERATE_X_ONLY" or "NONE"
|
|
.SRVAL(72'h000000000000000000), // Set/Reset value for port output
|
|
.INIT(72'h000000000000000000), // Initial values on output port
|
|
.WRITE_MODE("WRITE_FIRST"), // Specify "READ_FIRST" for same clock or synchronous clocks
|
|
// Specify "WRITE_FIRST for asynchronous clocks on ports
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INIT_xx are valid when configured as 36Kb
|
|
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are valid when configured as 36Kb
|
|
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) BRAM_SDP_MACRO_inst (
|
|
.DO(DO), // Output read data port, width defined by READ_WIDTH parameter
|
|
.DI(DI), // Input write data port, width defined by WRITE_WIDTH parameter
|
|
.RDADDR(RDADDR), // Input read address, width defined by read port depth
|
|
.RDCLK(RDCLK), // 1-bit input read clock
|
|
.RDEN(RDEN), // 1-bit input read port enable
|
|
.REGCE(REGCE), // 1-bit input read output register enable
|
|
.RST(RST), // 1-bit input reset
|
|
.WE(WE), // Input write enable, width defined by write port depth
|
|
.WRADDR(WRADDR), // Input write address, width defined by write port depth
|
|
.WRCLK(WRCLK), // 1-bit input write clock
|
|
.WREN(WREN) // 1-bit input write port enable
|
|
);
|
|
|
|
// End of BRAM_SDP_MACRO_inst instantiation
|
|
</Template>
|
|
<Template label="True Dual Port RAM (BRAM_TDP_MACRO)" treetype="template">
|
|
// BRAM_TDP_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BRAM_TDP_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BRAM_TDP_MACRO: True Dual Port RAM
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
//////////////////////////////////////////////////////////////////////////
|
|
// DATA_WIDTH_A/B | BRAM_SIZE | RAM Depth | ADDRA/B Width | WEA/B Width //
|
|
// ===============|===========|===========|===============|=============//
|
|
// 19-36 | "36Kb" | 1024 | 10-bit | 4-bit //
|
|
// 10-18 | "36Kb" | 2048 | 11-bit | 2-bit //
|
|
// 10-18 | "18Kb" | 1024 | 10-bit | 2-bit //
|
|
// 5-9 | "36Kb" | 4096 | 12-bit | 1-bit //
|
|
// 5-9 | "18Kb" | 2048 | 11-bit | 1-bit //
|
|
// 3-4 | "36Kb" | 8192 | 13-bit | 1-bit //
|
|
// 3-4 | "18Kb" | 4096 | 12-bit | 1-bit //
|
|
// 2 | "36Kb" | 16384 | 14-bit | 1-bit //
|
|
// 2 | "18Kb" | 8192 | 13-bit | 1-bit //
|
|
// 1 | "36Kb" | 32768 | 15-bit | 1-bit //
|
|
// 1 | "18Kb" | 16384 | 14-bit | 1-bit //
|
|
//////////////////////////////////////////////////////////////////////////
|
|
|
|
BRAM_TDP_MACRO #(
|
|
.BRAM_SIZE("18Kb"), // Target BRAM: "18Kb" or "36Kb"
|
|
.DEVICE("7SERIES"), // Target device: "VIRTEX5", "VIRTEX6", "SPARTAN6", "7SERIES"
|
|
.DOA_REG(0), // Optional port A output register (0 or 1)
|
|
.DOB_REG(0), // Optional port B output register (0 or 1)
|
|
.INIT_A(36'h0000000), // Initial values on port A output port
|
|
.INIT_B(36'h00000000), // Initial values on port B output port
|
|
.INIT_FILE ("NONE"),
|
|
.READ_WIDTH_A (0), // Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
|
|
.READ_WIDTH_B (0), // Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
|
|
.SIM_COLLISION_CHECK ("ALL"), // Collision check enable "ALL", "WARNING_ONLY",
|
|
// "GENERATE_X_ONLY" or "NONE"
|
|
.SRVAL_A(36'h00000000), // Set/Reset value for port A output
|
|
.SRVAL_B(36'h00000000), // Set/Reset value for port B output
|
|
.WRITE_MODE_A("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
|
|
.WRITE_MODE_B("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
|
|
.WRITE_WIDTH_A(0), // Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
|
|
.WRITE_WIDTH_B(0), // Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INIT_xx are valid when configured as 36Kb
|
|
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
.INIT_FF(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are valid when configured as 36Kb
|
|
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) BRAM_TDP_MACRO_inst (
|
|
.DOA(DOA), // Output port-A data, width defined by READ_WIDTH_A parameter
|
|
.DOB(DOB), // Output port-B data, width defined by READ_WIDTH_B parameter
|
|
.ADDRA(ADDRA), // Input port-A address, width defined by Port A depth
|
|
.ADDRB(ADDRB), // Input port-B address, width defined by Port B depth
|
|
.CLKA(CLKA), // 1-bit input port-A clock
|
|
.CLKB(CLKB), // 1-bit input port-B clock
|
|
.DIA(DIA), // Input port-A data, width defined by WRITE_WIDTH_A parameter
|
|
.DIB(DIB), // Input port-B data, width defined by WRITE_WIDTH_B parameter
|
|
.ENA(ENA), // 1-bit input port-A enable
|
|
.ENB(ENB), // 1-bit input port-B enable
|
|
.REGCEA(REGCEA), // 1-bit input port-A output register enable
|
|
.REGCEB(REGCEB), // 1-bit input port-B output register enable
|
|
.RSTA(RSTA), // 1-bit input port-A reset
|
|
.RSTB(RSTB), // 1-bit input port-B reset
|
|
.WEA(WEA), // Input port-A write enable, width defined by Port A depth
|
|
.WEB(WEB) // Input port-B write enable, width defined by Port B depth
|
|
);
|
|
|
|
// End of BRAM_TDP_MACRO_inst instantiation
|
|
</Template>
|
|
<Template label="Dual Clock FIfor (FIFO_DUALCLOCK_MACRO)" treetype="template">
|
|
// FIFO_DUALCLOCK_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FIFO_DUALCLOCK_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FIFO_DUALCLOCK_MACRO: Dual Clock First-In, First-Out (FIfor) RAM Buffer
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
/////////////////////////////////////////////////////////////////
|
|
// DATA_WIDTH | FIFO_SIZE | FIfor Depth | RDCOUNT/WRCOUNT Width //
|
|
// ===========|===========|============|=======================//
|
|
// 37-72 | "36Kb" | 512 | 9-bit //
|
|
// 19-36 | "36Kb" | 1024 | 10-bit //
|
|
// 19-36 | "18Kb" | 512 | 9-bit //
|
|
// 10-18 | "36Kb" | 2048 | 11-bit //
|
|
// 10-18 | "18Kb" | 1024 | 10-bit //
|
|
// 5-9 | "36Kb" | 4096 | 12-bit //
|
|
// 5-9 | "18Kb" | 2048 | 11-bit //
|
|
// 1-4 | "36Kb" | 8192 | 13-bit //
|
|
// 1-4 | "18Kb" | 4096 | 12-bit //
|
|
/////////////////////////////////////////////////////////////////
|
|
|
|
FIFO_DUALCLOCK_MACRO #(
|
|
.ALMOST_EMPTY_OFFSET(9'h080), // Sets the almost empty threshold
|
|
.ALMOST_FULL_OFFSET(9'h080), // Sets almost full threshold
|
|
.DATA_WIDTH(0), // Valid values are 1-72 (37-72 only valid when FIFO_SIZE="36Kb")
|
|
.DEVICE("7SERIES"), // Target device: "VIRTEX5", "VIRTEX6", "7SERIES"
|
|
.FIFO_SIZE ("18Kb"), // Target BRAM: "18Kb" or "36Kb"
|
|
.FIRST_WORD_FALL_THROUGH ("FALSE") // Sets the FIfor FWFT to "TRUE" or "FALSE"
|
|
) FIFO_DUALCLOCK_MACRO_inst (
|
|
.ALMOSTEMPTY(ALMOSTEMPTY), // 1-bit output almost empty
|
|
.ALMOSTFULL(ALMOSTFULL), // 1-bit output almost full
|
|
.DO(DO), // Output data, width defined by DATA_WIDTH parameter
|
|
.EMPTY(EMPTY), // 1-bit output empty
|
|
.FULL(FULL), // 1-bit output full
|
|
.RDCOUNT(RDCOUNT), // Output read count, width determined by FIfor depth
|
|
.RDERR(RDERR), // 1-bit output read error
|
|
.WRCOUNT(WRCOUNT), // Output write count, width determined by FIfor depth
|
|
.WRERR(WRERR), // 1-bit output write error
|
|
.DI(DI), // Input data, width defined by DATA_WIDTH parameter
|
|
.RDCLK(RDCLK), // 1-bit input read clock
|
|
.RDEN(RDEN), // 1-bit input read enable
|
|
.RST(RST), // 1-bit input reset
|
|
.WRCLK(WRCLK), // 1-bit input write clock
|
|
.WREN(WREN) // 1-bit input write enable
|
|
);
|
|
|
|
// End of FIFO_DUALCLOCK_MACRO_inst instantiation
|
|
</Template>
|
|
<Template label="Synchronous FIfor (FIFO_SYNC_MACRO)" treetype="template">
|
|
// FIFO_SYNC_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FIFO_SYNC_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FIFO_SYNC_MACRO: Synchronous First-In, First-Out (FIfor) RAM Buffer
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
/////////////////////////////////////////////////////////////////
|
|
// DATA_WIDTH | FIFO_SIZE | FIfor Depth | RDCOUNT/WRCOUNT Width //
|
|
// ===========|===========|============|=======================//
|
|
// 37-72 | "36Kb" | 512 | 9-bit //
|
|
// 19-36 | "36Kb" | 1024 | 10-bit //
|
|
// 19-36 | "18Kb" | 512 | 9-bit //
|
|
// 10-18 | "36Kb" | 2048 | 11-bit //
|
|
// 10-18 | "18Kb" | 1024 | 10-bit //
|
|
// 5-9 | "36Kb" | 4096 | 12-bit //
|
|
// 5-9 | "18Kb" | 2048 | 11-bit //
|
|
// 1-4 | "36Kb" | 8192 | 13-bit //
|
|
// 1-4 | "18Kb" | 4096 | 12-bit //
|
|
/////////////////////////////////////////////////////////////////
|
|
|
|
FIFO_SYNC_MACRO #(
|
|
.DEVICE("7SERIES"), // Target Device: "VIRTEX5", "VIRTEX6", "7SERIES"
|
|
.ALMOST_EMPTY_OFFSET(9'h080), // Sets the almost empty threshold
|
|
.ALMOST_FULL_OFFSET(9'h080), // Sets almost full threshold
|
|
.DATA_WIDTH(0), // Valid values are 1-72 (37-72 only valid when FIFO_SIZE="36Kb")
|
|
.DO_REG(0), // Optional output register (0 or 1)
|
|
.FIFO_SIZE ("18Kb") // Target BRAM: "18Kb" or "36Kb"
|
|
) FIFO_SYNC_MACRO_inst (
|
|
.ALMOSTEMPTY(ALMOSTEMPTY), // 1-bit output almost empty
|
|
.ALMOSTFULL(ALMOSTFULL), // 1-bit output almost full
|
|
.DO(DO), // Output data, width defined by DATA_WIDTH parameter
|
|
.EMPTY(EMPTY), // 1-bit output empty
|
|
.FULL(FULL), // 1-bit output full
|
|
.RDCOUNT(RDCOUNT), // Output read count, width determined by FIfor depth
|
|
.RDERR(RDERR), // 1-bit output read error
|
|
.WRCOUNT(WRCOUNT), // Output write count, width determined by FIfor depth
|
|
.WRERR(WRERR), // 1-bit output write error
|
|
.CLK(CLK), // 1-bit input clock
|
|
.DI(DI), // Input data, width defined by DATA_WIDTH parameter
|
|
.RDEN(RDEN), // 1-bit input read enable
|
|
.RST(RST), // 1-bit input reset
|
|
.WREN(WREN) // 1-bit input write enable
|
|
);
|
|
|
|
// End of FIFO_SYNC_MACRO_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="DSP48" treetype="folder">
|
|
<Template label="Add / Multiply Accumulate (ADDMACC_MACRO)" treetype="template">
|
|
// ADDMACC_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ADDMACC_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ADDMACC_MACRO: Variable width & latency - Pre-Add -> Multiplier -> Accumulate
|
|
// function implemented in a DSP48E
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ADDMACC_MACRO #(
|
|
.DEVICE("7SERIES"), // Target Device: "VIRTEX6", "SPARTAN6", "7SERIES"
|
|
.LATENCY(4), // Desired clock cycle latency, 0-4
|
|
.WIDTH_PREADD(25), // Pre-adder input width, 1-25
|
|
.WIDTH_MULTIPLIER(18), // Multiplier input width, 1-18
|
|
.WIDTH_PRODUCT(48) // MACC output width, 1-48
|
|
) ADDMACC_MACRO_inst (
|
|
.PRODUCT(PRODUCT), // MACC result output, width defined by WIDTH_PRODUCT parameter
|
|
.CARRYIN(CARRYIN), // 1-bit carry-in input
|
|
.CLK(CLK), // 1-bit clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.LOAD(LOAD), // 1-bit accumulator load input
|
|
.LOAD_DATA(LOAD_DATA), // Accumulator load data input, width defined by WIDTH_PRODUCT parameter
|
|
.MULTIPLIER(MULTIPLIER), // Multiplier data input, width defined by WIDTH_MULTIPLIER parameter
|
|
.PREADD2(PREADD2), // Preadder data input, width defined by WIDTH_PREADD parameter
|
|
.PREADD1(PREADD1), // Preadder data input, width defined by WIDTH_PREADD parameter
|
|
.RST(RST) // 1-bit active high synchronous reset
|
|
);
|
|
|
|
// End of ADDMACC_MACRO_inst instantiation
|
|
</Template>
|
|
<Template label="Add / Subtract (ADDSUB_MACRO)" treetype="template">
|
|
// ADDSUB_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ADDSUB_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ADDSUB_MACRO: Variable width & latency - Adder / Subtracter implemented in a DSP48E
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ADDSUB_MACRO #(
|
|
.DEVICE("7SERIES"), // Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6", "7SERIES"
|
|
.LATENCY(2), // Desired clock cycle latency, 0-2
|
|
.WIDTH(48) // Input / output bus width, 1-48
|
|
) ADDSUB_MACRO_inst (
|
|
.CARRYOUT(CARRYOUT), // 1-bit carry-out output signal
|
|
.RESULT(RESULT), // Add/sub result output, width defined by WIDTH parameter
|
|
.A(A), // Input A bus, width defined by WIDTH parameter
|
|
.ADD_SUB(ADD_SUB), // 1-bit add/sub input, high selects add, low selects subtract
|
|
.B(B), // Input B bus, width defined by WIDTH parameter
|
|
.CARRYIN(CARRYIN), // 1-bit carry-in input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.CLK(CLK), // 1-bit clock input
|
|
.RST(RST) // 1-bit active high synchronous reset
|
|
);
|
|
|
|
// End of ADDSUB_MACRO_inst instantiation
|
|
</Template>
|
|
<Template label="Loadable Counter (COUNTER_LOAD_MACRO)" treetype="template">
|
|
// COUNTER_LOAD_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (COUNTER_LOAD_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// COUNTER_LOAD_MACRO: Loadable variable counter implemented in a DSP48E
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
COUNTER_LOAD_MACRO #(
|
|
.COUNT_BY(48'h000000000001), // Count by value
|
|
.DEVICE("7SERIES"), // Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6", "7SERIES"
|
|
.WIDTH_DATA(48) // Counter output bus width, 1-48
|
|
) COUNTER_LOAD_MACRO_inst (
|
|
.Q(Q), // Counter output, width determined by WIDTH_DATA parameter
|
|
.CLK(CLK), // 1-bit clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.DIRECTION(DIRECTION), // 1-bit up/down count direction input, high is count up
|
|
.LOAD(LOAD), // 1-bit active high load input
|
|
.LOAD_DATA(LOAD_DATA), // Counter load data, width determined by WIDTH_DATA parameter
|
|
.RST(RST) // 1-bit active high synchronous reset
|
|
);
|
|
|
|
// End of COUNTER_LOAD_MACRO_inst instantiation
|
|
</Template>
|
|
<Template label="Counter w/ Terminal Count (COUNTER_TC_MACRO)" treetype="template">
|
|
// COUNTER_TC_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (COUNTER_TC_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// COUNTER_TC_MACRO: Counter with terminal count implemented in a DSP48E
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
COUNTER_TC_MACRO #(
|
|
.COUNT_BY(48'h000000000001), // Count by value
|
|
.DEVICE("7SERIES"), // Target Device: "VIRTEX5", "VIRTEX6", "7SERIES"
|
|
.DIRECTION("UP"), // Counter direction, "UP" or "DOWN"
|
|
.RESET_UPON_TC("FALSE"), // Reset counter upon terminal count, "TRUE" or "FALSE"
|
|
.TC_VALUE(48'h000000000000), // Terminal count value
|
|
.WIDTH_DATA(48) // Counter output bus width, 1-48
|
|
) COUNTER_TC_MACRO_inst (
|
|
.Q(Q), // Counter output bus, width determined by WIDTH_DATA parameter
|
|
.TC(TC), // 1-bit terminal count output, high = terminal count is reached
|
|
.CLK(CLK), // 1-bit positive edge clock input
|
|
.CE(CE), // 1-bit active high clock enable input
|
|
.RST(RST) // 1-bit active high synchronous reset
|
|
);
|
|
|
|
// End of COUNTER_TC_MACRO_inst instantiation
|
|
</Template>
|
|
<Template label="Equality Comparator (EQ_COMPARE_MACRO)" treetype="template">
|
|
// EQ_COMPARE_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (EQ_COMPARE_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// EQ_COMPARE_MACRO: Equality Comparator implemented in a DSP48E
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
EQ_COMPARE_MACRO #(
|
|
.DEVICE("7SERIES"), // Target Device: "VIRTEX5", "VIRTEX6","7SERIES"
|
|
.LATENCY(2), // Desired clock cycle latency, 0-2
|
|
.MASK(48'h000000000000), // Select bits to be masked, must set SEL_MASK="MASK"
|
|
.SEL_MASK("MASK"), // "MASK" = use MASK parameter,
|
|
// "DYNAMIC_PATTERN" = use DYNAMIC_PATTERN input bus
|
|
.SEL_PATTERN("STATIC_PATTERN"), // "STATIC_PATTERN" = use STATIC_PATTERN parameter,
|
|
// "DYNAMIC_PATTERN = use DYNAMIC_PATTERN input bus
|
|
.STATIC_PATTERN(48'h000000000000), // Specify static pattern, must set SEL_PATTERN = "STATIC_PATTERN"
|
|
.WIDTH(48) // Comparator output bus width, 1-48
|
|
) EQ_COMPARE_MACRO_inst (
|
|
.Q(Q), // 1-bit output indicating a match
|
|
.CE(CE), // 1-bit active high input clock enable
|
|
.CLK(CLK), // 1-bit positive edge clock input
|
|
.DATA_IN(DATA_IN), // Input Data Bus, width determined by WIDTH parameter
|
|
.DYNAMIC_PATTERN(DYNAMIC_PATTERN), // Input Dynamic Match/Mask Bus, width determined by WIDTH parameter
|
|
.RST(RST) // 1-bit input active high reset
|
|
);
|
|
|
|
// End of EQ_COMPARE_MACRO_inst instantiation
|
|
</Template>
|
|
<Template label="Multiply Accumulate (MACC_MACRO)" treetype="template">
|
|
// MACC_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MACC_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MACC_MACRO: Multiply Accumulate Function implemented in a DSP48E
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MACC_MACRO #(
|
|
.DEVICE("7SERIES"), // Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6", "7SERIES"
|
|
.LATENCY(3), // Desired clock cycle latency, 1-4
|
|
.WIDTH_A(25), // Multiplier A-input bus width, 1-25
|
|
.WIDTH_B(18), // Multiplier B-input bus width, 1-18
|
|
.WIDTH_P(48) // Accumulator output bus width, 1-48
|
|
) MACC_MACRO_inst (
|
|
.P(P), // MACC output bus, width determined by WIDTH_P parameter
|
|
.A(A), // MACC input A bus, width determined by WIDTH_A parameter
|
|
.ADDSUB(ADDSUB), // 1-bit add/sub input, high selects add, low selects subtract
|
|
.B(B), // MACC input B bus, width determined by WIDTH_B parameter
|
|
.CARRYIN(CARRYIN), // 1-bit carry-in input to accumulator
|
|
.CE(CE), // 1-bit active high input clock enable
|
|
.CLK(CLK), // 1-bit positive edge clock input
|
|
.LOAD(LOAD), // 1-bit active high input load accumulator enable
|
|
.LOAD_DATA(LOAD_DATA), // Load accumulator input data, width determined by WIDTH_P parameter
|
|
.RST(RST) // 1-bit input active high reset
|
|
);
|
|
|
|
// End of MACC_MACRO_inst instantiation
|
|
</Template>
|
|
<Template label="Multiplier (MULT_MACRO)" treetype="template">
|
|
// MULT_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MULT_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MULT_MACRO: Multiply Function implemented in a DSP48E
|
|
// Artix-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MULT_MACRO #(
|
|
.DEVICE("7SERIES"), // Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6","7SERIES"
|
|
.LATENCY(3), // Desired clock cycle latency, 0-4
|
|
.WIDTH_A(18), // Multiplier A-input bus width, 1-25
|
|
.WIDTH_B(18) // Multiplier B-input bus width, 1-18
|
|
) MULT_MACRO_inst (
|
|
.P(P), // Multiplier output bus, width determined by WIDTH_P parameter
|
|
.A(A), // Multiplier input A bus, width determined by WIDTH_A parameter
|
|
.B(B), // Multiplier input B bus, width determined by WIDTH_B parameter
|
|
.CE(CE), // 1-bit active high input clock enable
|
|
.CLK(CLK), // 1-bit positive edge clock input
|
|
.RST(RST) // 1-bit input active high reset
|
|
);
|
|
|
|
// End of MULT_MACRO_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Kintex-7" treetype="folder">
|
|
<SubFolder label="RAM" treetype="folder">
|
|
<Template label="Single Port RAM (BRAM_SINGLE_MACRO)" treetype="template">
|
|
// BRAM_SINGLE_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BRAM_SINGLE_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BRAM_SINGLE_MACRO: Single Port RAM
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
/////////////////////////////////////////////////////////////////////
|
|
// READ_WIDTH | BRAM_SIZE | READ Depth | ADDR Width | //
|
|
// WRITE_WIDTH | | WRITE Depth | | WE Width //
|
|
// ============|===========|=============|============|============//
|
|
// 37-72 | "36Kb" | 512 | 9-bit | 8-bit //
|
|
// 19-36 | "36Kb" | 1024 | 10-bit | 4-bit //
|
|
// 19-36 | "18Kb" | 512 | 9-bit | 4-bit //
|
|
// 10-18 | "36Kb" | 2048 | 11-bit | 2-bit //
|
|
// 10-18 | "18Kb" | 1024 | 10-bit | 2-bit //
|
|
// 5-9 | "36Kb" | 4096 | 12-bit | 1-bit //
|
|
// 5-9 | "18Kb" | 2048 | 11-bit | 1-bit //
|
|
// 3-4 | "36Kb" | 8192 | 13-bit | 1-bit //
|
|
// 3-4 | "18Kb" | 4096 | 12-bit | 1-bit //
|
|
// 2 | "36Kb" | 16384 | 14-bit | 1-bit //
|
|
// 2 | "18Kb" | 8192 | 13-bit | 1-bit //
|
|
// 1 | "36Kb" | 32768 | 15-bit | 1-bit //
|
|
// 1 | "18Kb" | 16384 | 14-bit | 1-bit //
|
|
/////////////////////////////////////////////////////////////////////
|
|
|
|
BRAM_SINGLE_MACRO #(
|
|
.BRAM_SIZE("18Kb"), // Target BRAM, "18Kb" or "36Kb"
|
|
.DEVICE("7SERIES"), // Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6", "7SERIES"
|
|
.DO_REG(0), // Optional output register (0 or 1)
|
|
.INIT(36'h000000000), // Initial values on output port
|
|
.INIT_FILE ("NONE"),
|
|
.WRITE_WIDTH(0), // Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
|
|
.READ_WIDTH(0), // Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
|
|
.SRVAL(36'h000000000), // Set/Reset value for port output
|
|
.WRITE_MODE("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INIT_xx are valid when configured as 36Kb
|
|
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INIT_xx are valid when configured as 36Kb
|
|
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) BRAM_SINGLE_MACRO_inst (
|
|
.DO(DO), // Output data, width defined by READ_WIDTH parameter
|
|
.ADDR(ADDR), // Input address, width defined by read/write port depth
|
|
.CLK(CLK), // 1-bit input clock
|
|
.DI(DI), // Input data port, width defined by WRITE_WIDTH parameter
|
|
.EN(EN), // 1-bit input RAM enable
|
|
.REGCE(REGCE), // 1-bit input output register enable
|
|
.RST(RST), // 1-bit input reset
|
|
.WE(WE) // Input write enable, width defined by write port depth
|
|
);
|
|
|
|
// End of BRAM_SINGLE_MACRO_inst instantiation
|
|
</Template>
|
|
<Template label="Simple Dual Port RAM (BRAM_SDP_MACRO)" treetype="template">
|
|
// BRAM_SDP_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BRAM_SDP_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BRAM_SDP_MACRO: Simple Dual Port RAM
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
///////////////////////////////////////////////////////////////////////
|
|
// READ_WIDTH | BRAM_SIZE | READ Depth | RDADDR Width | //
|
|
// WRITE_WIDTH | | WRITE Depth | WRADDR Width | WE Width //
|
|
// ============|===========|=============|==============|============//
|
|
// 37-72 | "36Kb" | 512 | 9-bit | 8-bit //
|
|
// 19-36 | "36Kb" | 1024 | 10-bit | 4-bit //
|
|
// 19-36 | "18Kb" | 512 | 9-bit | 4-bit //
|
|
// 10-18 | "36Kb" | 2048 | 11-bit | 2-bit //
|
|
// 10-18 | "18Kb" | 1024 | 10-bit | 2-bit //
|
|
// 5-9 | "36Kb" | 4096 | 12-bit | 1-bit //
|
|
// 5-9 | "18Kb" | 2048 | 11-bit | 1-bit //
|
|
// 3-4 | "36Kb" | 8192 | 13-bit | 1-bit //
|
|
// 3-4 | "18Kb" | 4096 | 12-bit | 1-bit //
|
|
// 2 | "36Kb" | 16384 | 14-bit | 1-bit //
|
|
// 2 | "18Kb" | 8192 | 13-bit | 1-bit //
|
|
// 1 | "36Kb" | 32768 | 15-bit | 1-bit //
|
|
// 1 | "18Kb" | 16384 | 14-bit | 1-bit //
|
|
///////////////////////////////////////////////////////////////////////
|
|
|
|
BRAM_SDP_MACRO #(
|
|
.BRAM_SIZE("18Kb"), // Target BRAM, "18Kb" or "36Kb"
|
|
.DEVICE("7SERIES"), // Target device: "VIRTEX5", "VIRTEX6", "SPARTAN6", "7SERIES"
|
|
.WRITE_WIDTH(0), // Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
|
|
.READ_WIDTH(0), // Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
|
|
.DO_REG(0), // Optional output register (0 or 1)
|
|
.INIT_FILE ("NONE"),
|
|
.SIM_COLLISION_CHECK ("ALL"), // Collision check enable "ALL", "WARNING_ONLY",
|
|
// "GENERATE_X_ONLY" or "NONE"
|
|
.SRVAL(72'h000000000000000000), // Set/Reset value for port output
|
|
.INIT(72'h000000000000000000), // Initial values on output port
|
|
.WRITE_MODE("WRITE_FIRST"), // Specify "READ_FIRST" for same clock or synchronous clocks
|
|
// Specify "WRITE_FIRST for asynchronous clocks on ports
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INIT_xx are valid when configured as 36Kb
|
|
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are valid when configured as 36Kb
|
|
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) BRAM_SDP_MACRO_inst (
|
|
.DO(DO), // Output read data port, width defined by READ_WIDTH parameter
|
|
.DI(DI), // Input write data port, width defined by WRITE_WIDTH parameter
|
|
.RDADDR(RDADDR), // Input read address, width defined by read port depth
|
|
.RDCLK(RDCLK), // 1-bit input read clock
|
|
.RDEN(RDEN), // 1-bit input read port enable
|
|
.REGCE(REGCE), // 1-bit input read output register enable
|
|
.RST(RST), // 1-bit input reset
|
|
.WE(WE), // Input write enable, width defined by write port depth
|
|
.WRADDR(WRADDR), // Input write address, width defined by write port depth
|
|
.WRCLK(WRCLK), // 1-bit input write clock
|
|
.WREN(WREN) // 1-bit input write port enable
|
|
);
|
|
|
|
// End of BRAM_SDP_MACRO_inst instantiation
|
|
</Template>
|
|
<Template label="True Dual Port RAM (BRAM_TDP_MACRO)" treetype="template">
|
|
// BRAM_TDP_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BRAM_TDP_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BRAM_TDP_MACRO: True Dual Port RAM
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
//////////////////////////////////////////////////////////////////////////
|
|
// DATA_WIDTH_A/B | BRAM_SIZE | RAM Depth | ADDRA/B Width | WEA/B Width //
|
|
// ===============|===========|===========|===============|=============//
|
|
// 19-36 | "36Kb" | 1024 | 10-bit | 4-bit //
|
|
// 10-18 | "36Kb" | 2048 | 11-bit | 2-bit //
|
|
// 10-18 | "18Kb" | 1024 | 10-bit | 2-bit //
|
|
// 5-9 | "36Kb" | 4096 | 12-bit | 1-bit //
|
|
// 5-9 | "18Kb" | 2048 | 11-bit | 1-bit //
|
|
// 3-4 | "36Kb" | 8192 | 13-bit | 1-bit //
|
|
// 3-4 | "18Kb" | 4096 | 12-bit | 1-bit //
|
|
// 2 | "36Kb" | 16384 | 14-bit | 1-bit //
|
|
// 2 | "18Kb" | 8192 | 13-bit | 1-bit //
|
|
// 1 | "36Kb" | 32768 | 15-bit | 1-bit //
|
|
// 1 | "18Kb" | 16384 | 14-bit | 1-bit //
|
|
//////////////////////////////////////////////////////////////////////////
|
|
|
|
BRAM_TDP_MACRO #(
|
|
.BRAM_SIZE("18Kb"), // Target BRAM: "18Kb" or "36Kb"
|
|
.DEVICE("7SERIES"), // Target device: "VIRTEX5", "VIRTEX6", "SPARTAN6", "7SERIES"
|
|
.DOA_REG(0), // Optional port A output register (0 or 1)
|
|
.DOB_REG(0), // Optional port B output register (0 or 1)
|
|
.INIT_A(36'h0000000), // Initial values on port A output port
|
|
.INIT_B(36'h00000000), // Initial values on port B output port
|
|
.INIT_FILE ("NONE"),
|
|
.READ_WIDTH_A (0), // Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
|
|
.READ_WIDTH_B (0), // Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
|
|
.SIM_COLLISION_CHECK ("ALL"), // Collision check enable "ALL", "WARNING_ONLY",
|
|
// "GENERATE_X_ONLY" or "NONE"
|
|
.SRVAL_A(36'h00000000), // Set/Reset value for port A output
|
|
.SRVAL_B(36'h00000000), // Set/Reset value for port B output
|
|
.WRITE_MODE_A("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
|
|
.WRITE_MODE_B("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
|
|
.WRITE_WIDTH_A(0), // Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
|
|
.WRITE_WIDTH_B(0), // Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INIT_xx are valid when configured as 36Kb
|
|
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
.INIT_FF(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are valid when configured as 36Kb
|
|
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) BRAM_TDP_MACRO_inst (
|
|
.DOA(DOA), // Output port-A data, width defined by READ_WIDTH_A parameter
|
|
.DOB(DOB), // Output port-B data, width defined by READ_WIDTH_B parameter
|
|
.ADDRA(ADDRA), // Input port-A address, width defined by Port A depth
|
|
.ADDRB(ADDRB), // Input port-B address, width defined by Port B depth
|
|
.CLKA(CLKA), // 1-bit input port-A clock
|
|
.CLKB(CLKB), // 1-bit input port-B clock
|
|
.DIA(DIA), // Input port-A data, width defined by WRITE_WIDTH_A parameter
|
|
.DIB(DIB), // Input port-B data, width defined by WRITE_WIDTH_B parameter
|
|
.ENA(ENA), // 1-bit input port-A enable
|
|
.ENB(ENB), // 1-bit input port-B enable
|
|
.REGCEA(REGCEA), // 1-bit input port-A output register enable
|
|
.REGCEB(REGCEB), // 1-bit input port-B output register enable
|
|
.RSTA(RSTA), // 1-bit input port-A reset
|
|
.RSTB(RSTB), // 1-bit input port-B reset
|
|
.WEA(WEA), // Input port-A write enable, width defined by Port A depth
|
|
.WEB(WEB) // Input port-B write enable, width defined by Port B depth
|
|
);
|
|
|
|
// End of BRAM_TDP_MACRO_inst instantiation
|
|
</Template>
|
|
<Template label="Dual Clock FIfor (FIFO_DUALCLOCK_MACRO)" treetype="template">
|
|
// FIFO_DUALCLOCK_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FIFO_DUALCLOCK_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FIFO_DUALCLOCK_MACRO: Dual Clock First-In, First-Out (FIfor) RAM Buffer
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
/////////////////////////////////////////////////////////////////
|
|
// DATA_WIDTH | FIFO_SIZE | FIfor Depth | RDCOUNT/WRCOUNT Width //
|
|
// ===========|===========|============|=======================//
|
|
// 37-72 | "36Kb" | 512 | 9-bit //
|
|
// 19-36 | "36Kb" | 1024 | 10-bit //
|
|
// 19-36 | "18Kb" | 512 | 9-bit //
|
|
// 10-18 | "36Kb" | 2048 | 11-bit //
|
|
// 10-18 | "18Kb" | 1024 | 10-bit //
|
|
// 5-9 | "36Kb" | 4096 | 12-bit //
|
|
// 5-9 | "18Kb" | 2048 | 11-bit //
|
|
// 1-4 | "36Kb" | 8192 | 13-bit //
|
|
// 1-4 | "18Kb" | 4096 | 12-bit //
|
|
/////////////////////////////////////////////////////////////////
|
|
|
|
FIFO_DUALCLOCK_MACRO #(
|
|
.ALMOST_EMPTY_OFFSET(9'h080), // Sets the almost empty threshold
|
|
.ALMOST_FULL_OFFSET(9'h080), // Sets almost full threshold
|
|
.DATA_WIDTH(0), // Valid values are 1-72 (37-72 only valid when FIFO_SIZE="36Kb")
|
|
.DEVICE("7SERIES"), // Target device: "VIRTEX5", "VIRTEX6", "7SERIES"
|
|
.FIFO_SIZE ("18Kb"), // Target BRAM: "18Kb" or "36Kb"
|
|
.FIRST_WORD_FALL_THROUGH ("FALSE") // Sets the FIfor FWFT to "TRUE" or "FALSE"
|
|
) FIFO_DUALCLOCK_MACRO_inst (
|
|
.ALMOSTEMPTY(ALMOSTEMPTY), // 1-bit output almost empty
|
|
.ALMOSTFULL(ALMOSTFULL), // 1-bit output almost full
|
|
.DO(DO), // Output data, width defined by DATA_WIDTH parameter
|
|
.EMPTY(EMPTY), // 1-bit output empty
|
|
.FULL(FULL), // 1-bit output full
|
|
.RDCOUNT(RDCOUNT), // Output read count, width determined by FIfor depth
|
|
.RDERR(RDERR), // 1-bit output read error
|
|
.WRCOUNT(WRCOUNT), // Output write count, width determined by FIfor depth
|
|
.WRERR(WRERR), // 1-bit output write error
|
|
.DI(DI), // Input data, width defined by DATA_WIDTH parameter
|
|
.RDCLK(RDCLK), // 1-bit input read clock
|
|
.RDEN(RDEN), // 1-bit input read enable
|
|
.RST(RST), // 1-bit input reset
|
|
.WRCLK(WRCLK), // 1-bit input write clock
|
|
.WREN(WREN) // 1-bit input write enable
|
|
);
|
|
|
|
// End of FIFO_DUALCLOCK_MACRO_inst instantiation
|
|
</Template>
|
|
<Template label="Synchronous FIfor (FIFO_SYNC_MACRO)" treetype="template">
|
|
// FIFO_SYNC_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FIFO_SYNC_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FIFO_SYNC_MACRO: Synchronous First-In, First-Out (FIfor) RAM Buffer
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
/////////////////////////////////////////////////////////////////
|
|
// DATA_WIDTH | FIFO_SIZE | FIfor Depth | RDCOUNT/WRCOUNT Width //
|
|
// ===========|===========|============|=======================//
|
|
// 37-72 | "36Kb" | 512 | 9-bit //
|
|
// 19-36 | "36Kb" | 1024 | 10-bit //
|
|
// 19-36 | "18Kb" | 512 | 9-bit //
|
|
// 10-18 | "36Kb" | 2048 | 11-bit //
|
|
// 10-18 | "18Kb" | 1024 | 10-bit //
|
|
// 5-9 | "36Kb" | 4096 | 12-bit //
|
|
// 5-9 | "18Kb" | 2048 | 11-bit //
|
|
// 1-4 | "36Kb" | 8192 | 13-bit //
|
|
// 1-4 | "18Kb" | 4096 | 12-bit //
|
|
/////////////////////////////////////////////////////////////////
|
|
|
|
FIFO_SYNC_MACRO #(
|
|
.DEVICE("7SERIES"), // Target Device: "VIRTEX5", "VIRTEX6", "7SERIES"
|
|
.ALMOST_EMPTY_OFFSET(9'h080), // Sets the almost empty threshold
|
|
.ALMOST_FULL_OFFSET(9'h080), // Sets almost full threshold
|
|
.DATA_WIDTH(0), // Valid values are 1-72 (37-72 only valid when FIFO_SIZE="36Kb")
|
|
.DO_REG(0), // Optional output register (0 or 1)
|
|
.FIFO_SIZE ("18Kb") // Target BRAM: "18Kb" or "36Kb"
|
|
) FIFO_SYNC_MACRO_inst (
|
|
.ALMOSTEMPTY(ALMOSTEMPTY), // 1-bit output almost empty
|
|
.ALMOSTFULL(ALMOSTFULL), // 1-bit output almost full
|
|
.DO(DO), // Output data, width defined by DATA_WIDTH parameter
|
|
.EMPTY(EMPTY), // 1-bit output empty
|
|
.FULL(FULL), // 1-bit output full
|
|
.RDCOUNT(RDCOUNT), // Output read count, width determined by FIfor depth
|
|
.RDERR(RDERR), // 1-bit output read error
|
|
.WRCOUNT(WRCOUNT), // Output write count, width determined by FIfor depth
|
|
.WRERR(WRERR), // 1-bit output write error
|
|
.CLK(CLK), // 1-bit input clock
|
|
.DI(DI), // Input data, width defined by DATA_WIDTH parameter
|
|
.RDEN(RDEN), // 1-bit input read enable
|
|
.RST(RST), // 1-bit input reset
|
|
.WREN(WREN) // 1-bit input write enable
|
|
);
|
|
|
|
// End of FIFO_SYNC_MACRO_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="DSP48" treetype="folder">
|
|
<Template label="Add / Multiply Accumulate (ADDMACC_MACRO)" treetype="template">
|
|
// ADDMACC_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ADDMACC_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ADDMACC_MACRO: Variable width & latency - Pre-Add -> Multiplier -> Accumulate
|
|
// function implemented in a DSP48E
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ADDMACC_MACRO #(
|
|
.DEVICE("7SERIES"), // Target Device: "VIRTEX6", "SPARTAN6", "7SERIES"
|
|
.LATENCY(4), // Desired clock cycle latency, 0-4
|
|
.WIDTH_PREADD(25), // Pre-adder input width, 1-25
|
|
.WIDTH_MULTIPLIER(18), // Multiplier input width, 1-18
|
|
.WIDTH_PRODUCT(48) // MACC output width, 1-48
|
|
) ADDMACC_MACRO_inst (
|
|
.PRODUCT(PRODUCT), // MACC result output, width defined by WIDTH_PRODUCT parameter
|
|
.CARRYIN(CARRYIN), // 1-bit carry-in input
|
|
.CLK(CLK), // 1-bit clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.LOAD(LOAD), // 1-bit accumulator load input
|
|
.LOAD_DATA(LOAD_DATA), // Accumulator load data input, width defined by WIDTH_PRODUCT parameter
|
|
.MULTIPLIER(MULTIPLIER), // Multiplier data input, width defined by WIDTH_MULTIPLIER parameter
|
|
.PREADD2(PREADD2), // Preadder data input, width defined by WIDTH_PREADD parameter
|
|
.PREADD1(PREADD1), // Preadder data input, width defined by WIDTH_PREADD parameter
|
|
.RST(RST) // 1-bit active high synchronous reset
|
|
);
|
|
|
|
// End of ADDMACC_MACRO_inst instantiation
|
|
</Template>
|
|
<Template label="Add / Subtract (ADDSUB_MACRO)" treetype="template">
|
|
// ADDSUB_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ADDSUB_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ADDSUB_MACRO: Variable width & latency - Adder / Subtracter implemented in a DSP48E
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ADDSUB_MACRO #(
|
|
.DEVICE("7SERIES"), // Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6", "7SERIES"
|
|
.LATENCY(2), // Desired clock cycle latency, 0-2
|
|
.WIDTH(48) // Input / output bus width, 1-48
|
|
) ADDSUB_MACRO_inst (
|
|
.CARRYOUT(CARRYOUT), // 1-bit carry-out output signal
|
|
.RESULT(RESULT), // Add/sub result output, width defined by WIDTH parameter
|
|
.A(A), // Input A bus, width defined by WIDTH parameter
|
|
.ADD_SUB(ADD_SUB), // 1-bit add/sub input, high selects add, low selects subtract
|
|
.B(B), // Input B bus, width defined by WIDTH parameter
|
|
.CARRYIN(CARRYIN), // 1-bit carry-in input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.CLK(CLK), // 1-bit clock input
|
|
.RST(RST) // 1-bit active high synchronous reset
|
|
);
|
|
|
|
// End of ADDSUB_MACRO_inst instantiation
|
|
</Template>
|
|
<Template label="Loadable Counter (COUNTER_LOAD_MACRO)" treetype="template">
|
|
// COUNTER_LOAD_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (COUNTER_LOAD_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// COUNTER_LOAD_MACRO: Loadable variable counter implemented in a DSP48E
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
COUNTER_LOAD_MACRO #(
|
|
.COUNT_BY(48'h000000000001), // Count by value
|
|
.DEVICE("7SERIES"), // Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6", "7SERIES"
|
|
.WIDTH_DATA(48) // Counter output bus width, 1-48
|
|
) COUNTER_LOAD_MACRO_inst (
|
|
.Q(Q), // Counter output, width determined by WIDTH_DATA parameter
|
|
.CLK(CLK), // 1-bit clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.DIRECTION(DIRECTION), // 1-bit up/down count direction input, high is count up
|
|
.LOAD(LOAD), // 1-bit active high load input
|
|
.LOAD_DATA(LOAD_DATA), // Counter load data, width determined by WIDTH_DATA parameter
|
|
.RST(RST) // 1-bit active high synchronous reset
|
|
);
|
|
|
|
// End of COUNTER_LOAD_MACRO_inst instantiation
|
|
</Template>
|
|
<Template label="Counter w/ Terminal Count (COUNTER_TC_MACRO)" treetype="template">
|
|
// COUNTER_TC_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (COUNTER_TC_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// COUNTER_TC_MACRO: Counter with terminal count implemented in a DSP48E
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
COUNTER_TC_MACRO #(
|
|
.COUNT_BY(48'h000000000001), // Count by value
|
|
.DEVICE("7SERIES"), // Target Device: "VIRTEX5", "VIRTEX6", "7SERIES"
|
|
.DIRECTION("UP"), // Counter direction, "UP" or "DOWN"
|
|
.RESET_UPON_TC("FALSE"), // Reset counter upon terminal count, "TRUE" or "FALSE"
|
|
.TC_VALUE(48'h000000000000), // Terminal count value
|
|
.WIDTH_DATA(48) // Counter output bus width, 1-48
|
|
) COUNTER_TC_MACRO_inst (
|
|
.Q(Q), // Counter output bus, width determined by WIDTH_DATA parameter
|
|
.TC(TC), // 1-bit terminal count output, high = terminal count is reached
|
|
.CLK(CLK), // 1-bit positive edge clock input
|
|
.CE(CE), // 1-bit active high clock enable input
|
|
.RST(RST) // 1-bit active high synchronous reset
|
|
);
|
|
|
|
// End of COUNTER_TC_MACRO_inst instantiation
|
|
</Template>
|
|
<Template label="Equality Comparator (EQ_COMPARE_MACRO)" treetype="template">
|
|
// EQ_COMPARE_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (EQ_COMPARE_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// EQ_COMPARE_MACRO: Equality Comparator implemented in a DSP48E
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
EQ_COMPARE_MACRO #(
|
|
.DEVICE("7SERIES"), // Target Device: "VIRTEX5", "VIRTEX6","7SERIES"
|
|
.LATENCY(2), // Desired clock cycle latency, 0-2
|
|
.MASK(48'h000000000000), // Select bits to be masked, must set SEL_MASK="MASK"
|
|
.SEL_MASK("MASK"), // "MASK" = use MASK parameter,
|
|
// "DYNAMIC_PATTERN" = use DYNAMIC_PATTERN input bus
|
|
.SEL_PATTERN("STATIC_PATTERN"), // "STATIC_PATTERN" = use STATIC_PATTERN parameter,
|
|
// "DYNAMIC_PATTERN = use DYNAMIC_PATTERN input bus
|
|
.STATIC_PATTERN(48'h000000000000), // Specify static pattern, must set SEL_PATTERN = "STATIC_PATTERN"
|
|
.WIDTH(48) // Comparator output bus width, 1-48
|
|
) EQ_COMPARE_MACRO_inst (
|
|
.Q(Q), // 1-bit output indicating a match
|
|
.CE(CE), // 1-bit active high input clock enable
|
|
.CLK(CLK), // 1-bit positive edge clock input
|
|
.DATA_IN(DATA_IN), // Input Data Bus, width determined by WIDTH parameter
|
|
.DYNAMIC_PATTERN(DYNAMIC_PATTERN), // Input Dynamic Match/Mask Bus, width determined by WIDTH parameter
|
|
.RST(RST) // 1-bit input active high reset
|
|
);
|
|
|
|
// End of EQ_COMPARE_MACRO_inst instantiation
|
|
</Template>
|
|
<Template label="Multiply Accumulate (MACC_MACRO)" treetype="template">
|
|
// MACC_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MACC_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MACC_MACRO: Multiply Accumulate Function implemented in a DSP48E
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MACC_MACRO #(
|
|
.DEVICE("7SERIES"), // Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6", "7SERIES"
|
|
.LATENCY(3), // Desired clock cycle latency, 1-4
|
|
.WIDTH_A(25), // Multiplier A-input bus width, 1-25
|
|
.WIDTH_B(18), // Multiplier B-input bus width, 1-18
|
|
.WIDTH_P(48) // Accumulator output bus width, 1-48
|
|
) MACC_MACRO_inst (
|
|
.P(P), // MACC output bus, width determined by WIDTH_P parameter
|
|
.A(A), // MACC input A bus, width determined by WIDTH_A parameter
|
|
.ADDSUB(ADDSUB), // 1-bit add/sub input, high selects add, low selects subtract
|
|
.B(B), // MACC input B bus, width determined by WIDTH_B parameter
|
|
.CARRYIN(CARRYIN), // 1-bit carry-in input to accumulator
|
|
.CE(CE), // 1-bit active high input clock enable
|
|
.CLK(CLK), // 1-bit positive edge clock input
|
|
.LOAD(LOAD), // 1-bit active high input load accumulator enable
|
|
.LOAD_DATA(LOAD_DATA), // Load accumulator input data, width determined by WIDTH_P parameter
|
|
.RST(RST) // 1-bit input active high reset
|
|
);
|
|
|
|
// End of MACC_MACRO_inst instantiation
|
|
</Template>
|
|
<Template label="Multiplier (MULT_MACRO)" treetype="template">
|
|
// MULT_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MULT_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MULT_MACRO: Multiply Function implemented in a DSP48E
|
|
// Kintex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MULT_MACRO #(
|
|
.DEVICE("7SERIES"), // Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6","7SERIES"
|
|
.LATENCY(3), // Desired clock cycle latency, 0-4
|
|
.WIDTH_A(18), // Multiplier A-input bus width, 1-25
|
|
.WIDTH_B(18) // Multiplier B-input bus width, 1-18
|
|
) MULT_MACRO_inst (
|
|
.P(P), // Multiplier output bus, width determined by WIDTH_P parameter
|
|
.A(A), // Multiplier input A bus, width determined by WIDTH_A parameter
|
|
.B(B), // Multiplier input B bus, width determined by WIDTH_B parameter
|
|
.CE(CE), // 1-bit active high input clock enable
|
|
.CLK(CLK), // 1-bit positive edge clock input
|
|
.RST(RST) // 1-bit input active high reset
|
|
);
|
|
|
|
// End of MULT_MACRO_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Spartan-6" treetype="folder">
|
|
<SubFolder label="RAM" treetype="folder">
|
|
<Template label="Single Port RAM (BRAM_SINGLE_MACRO)" treetype="template">
|
|
// BRAM_SINGLE_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BRAM_SINGLE_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BRAM_SINGLE_MACRO: Single Port RAM
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
/////////////////////////////////////////////////////////////////////
|
|
// READ_WIDTH | BRAM_SIZE | READ Depth | ADDR Width | //
|
|
// WRITE_WIDTH | | WRITE Depth | | WE Width //
|
|
// ============|===========|=============|============|============//
|
|
// 19-36 | "18Kb" | 512 | 9-bit | 4-bit //
|
|
// 10-18 | "18Kb" | 1024 | 10-bit | 2-bit //
|
|
// 10-18 | "9Kb" | 512 | 9-bit | 2-bit //
|
|
// 5-9 | "18Kb" | 2048 | 11-bit | 1-bit //
|
|
// 5-9 | "9Kb" | 1024 | 10-bit | 1-bit //
|
|
// 3-4 | "18Kb" | 4096 | 12-bit | 1-bit //
|
|
// 3-4 | "9Kb" | 2048 | 11-bit | 1-bit //
|
|
// 2 | "18Kb" | 8192 | 13-bit | 1-bit //
|
|
// 2 | "9Kb" | 4096 | 12-bit | 1-bit //
|
|
// 1 | "18Kb" | 16384 | 14-bit | 1-bit //
|
|
// 1 | "9Kb" | 8192 | 13-bit | 1-bit //
|
|
/////////////////////////////////////////////////////////////////////
|
|
|
|
BRAM_SINGLE_MACRO #(
|
|
.BRAM_SIZE("18Kb"), // Target BRAM, "9Kb" or "18Kb"
|
|
.DEVICE("SPARTAN6"), // Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6"
|
|
.DO_REG(0), // Optional output register (0 or 1)
|
|
.INIT(36'h000000000), // Initial values on output port
|
|
.INIT_FILE ("NONE"),
|
|
.WRITE_WIDTH(0), // Valid values are 1-36 (19-36 only valid when BRAM_SIZE="18Kb")
|
|
.READ_WIDTH(0), // Valid values are 1-36 (19-36 only valid when BRAM_SIZE="18Kb")
|
|
.SRVAL(36'h000000000), // Set/Reset value for port output
|
|
.WRITE_MODE("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INIT_xx are for "18Kb" configuration only
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for "18Kb" configuration only
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) BRAM_SINGLE_MACRO_inst (
|
|
.DO(DO), // Output data, width defined by READ_WIDTH parameter
|
|
.ADDR(ADDR), // Input address, width defined by read/write port depth
|
|
.CLK(CLK), // 1-bit input clock
|
|
.DI(DI), // Input data port, width defined by WRITE_WIDTH parameter
|
|
.EN(EN), // 1-bit input RAM enable
|
|
.REGCE(REGCE), // 1-bit input output register enable
|
|
.RST(RST), // 1-bit input reset
|
|
.WE(WE) // Input write enable, width defined by write port depth
|
|
);
|
|
|
|
// End of BRAM_SINGLE_MACRO_inst instantiation
|
|
</Template>
|
|
<Template label="Simple Dual Port RAM (BRAM_SDP_MACRO)" treetype="template">
|
|
// BRAM_SDP_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BRAM_SDP_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BRAM_SDP_MACRO: Simple Dual Port RAM
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
///////////////////////////////////////////////////////////////////////
|
|
// READ_WIDTH | BRAM_SIZE | READ Depth | RDADDR Width | //
|
|
// WRITE_WIDTH | | WRITE Depth | WRADDR Width | WE Width //
|
|
// ============|===========|=============|==============|============//
|
|
// 19-36 | "18Kb" | 512 | 9-bit | 4-bit //
|
|
// 10-18 | "18Kb" | 1024 | 10-bit | 2-bit //
|
|
// 10-18 | "9Kb" | 512 | 9-bit | 2-bit //
|
|
// 5-9 | "18Kb" | 2048 | 11-bit | 1-bit //
|
|
// 5-9 | "9Kb" | 1024 | 10-bit | 1-bit //
|
|
// 3-4 | "18Kb" | 4096 | 12-bit | 1-bit //
|
|
// 3-4 | "9Kb" | 2048 | 11-bit | 1-bit //
|
|
// 2 | "18Kb" | 8192 | 13-bit | 1-bit //
|
|
// 2 | " 9Kb" | 4096 | 12-bit | 1-bit //
|
|
// 1 | "18Kb" | 16384 | 14-bit | 1-bit //
|
|
// 1 | "9Kb" | 8192 | 13-bit | 1-bit //
|
|
///////////////////////////////////////////////////////////////////////
|
|
|
|
BRAM_SDP_MACRO #(
|
|
.BRAM_SIZE("18Kb"), // Target BRAM, "9Kb" or "18Kb"
|
|
.DEVICE("SPARTAN6"), // Target device: "VIRTEX5", "VIRTEX6", "SPARTAN6"
|
|
.WRITE_WIDTH(0), // Valid values are 1-36
|
|
.READ_WIDTH(0), // Valid values are 1-36
|
|
.DO_REG(0), // Optional output register (0 or 1)
|
|
.INIT_FILE ("NONE"),
|
|
.SIM_COLLISION_CHECK ("ALL"), // Collision check enable "ALL", "WARNING_ONLY",
|
|
// "GENERATE_X_ONLY" or "NONE"
|
|
.SRVAL(72'h000000000000000000), // Set/Reset value for port output
|
|
.INIT(72'h000000000000000000), // Initial values on output port
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INIT_xx are for "18Kb" configuration only
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for "18Kb" configuration only
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) BRAM_SDP_MACRO_inst (
|
|
.DO(DO), // Output read data port, width defined by READ_WIDTH parameter
|
|
.DI(DI), // Input write data port, width defined by WRITE_WIDTH parameter
|
|
.RDADDR(RDADDR), // Input read address, width defined by read port depth
|
|
.RDCLK(RDCLK), // 1-bit input read clock
|
|
.RDEN(RDEN), // 1-bit input read port enable
|
|
.REGCE(REGCE), // 1-bit input read output register enable
|
|
.RST(RST), // 1-bit input reset
|
|
.WE(WE), // Input write enable, width defined by write port depth
|
|
.WRADDR(WRADDR), // Input write address, width defined by write port depth
|
|
.WRCLK(WRCLK), // 1-bit input write clock
|
|
.WREN(WREN) // 1-bit input write port enable
|
|
);
|
|
|
|
// End of BRAM_SDP_MACRO_inst instantiation
|
|
</Template>
|
|
<Template label="True Dual Port RAM (BRAM_TDP_MACRO)" treetype="template">
|
|
// BRAM_TDP_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BRAM_TDP_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BRAM_TDP_MACRO: True Dual Port RAM
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
//////////////////////////////////////////////////////////////////////////
|
|
// DATA_WIDTH_A/B | BRAM_SIZE | RAM Depth | ADDRA/B Width | WEA/B Width //
|
|
// ===============|===========|===========|===============|=============//
|
|
// 19-36 | "18Kb" | 512 | 9-bit | 4-bit //
|
|
// 10-18 | "18Kb" | 1024 | 10-bit | 2-bit //
|
|
// 10-18 | "9Kb" | 512 | 9-bit | 2-bit //
|
|
// 5-9 | "18Kb" | 2048 | 11-bit | 1-bit //
|
|
// 5-9 | "9Kb" | 1024 | 10-bit | 1-bit //
|
|
// 3-4 | "18Kb" | 4096 | 12-bit | 1-bit //
|
|
// 3-4 | "9Kb" | 2048 | 11-bit | 1-bit //
|
|
// 2 | "18Kb" | 8192 | 13-bit | 1-bit //
|
|
// 2 | "9Kb" | 4096 | 12-bit | 1-bit //
|
|
// 1 | "18Kb" | 16384 | 14-bit | 1-bit //
|
|
// 1 | "9Kb" | 8192 | 12-bit | 1-bit //
|
|
//////////////////////////////////////////////////////////////////////////
|
|
|
|
BRAM_TDP_MACRO #(
|
|
.BRAM_SIZE("18Kb"), // Target BRAM: "9Kb" or "18Kb"
|
|
.DEVICE("SPARTAN6"), // Target device: "VIRTEX5", "VIRTEX6", "SPARTAN6"
|
|
.DOA_REG(0), // Optional port A output register (0 or 1)
|
|
.DOB_REG(0), // Optional port B output register (0 or 1)
|
|
.INIT_A(36'h0000000), // Initial values on port A output port
|
|
.INIT_B(36'h00000000), // Initial values on port B output port
|
|
.INIT_FILE ("NONE"),
|
|
.READ_WIDTH_A (0), // Valid values are 1-36
|
|
.READ_WIDTH_B (0), // Valid values are 1-36
|
|
.SIM_COLLISION_CHECK ("ALL"), // Collision check enable "ALL", "WARNING_ONLY",
|
|
// "GENERATE_X_ONLY" or "NONE"
|
|
.SRVAL_A(36'h00000000), // Set/Reset value for port A output
|
|
.SRVAL_B(36'h00000000), // Set/Reset value for port B output
|
|
.WRITE_MODE_A("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
|
|
.WRITE_MODE_B("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
|
|
.WRITE_WIDTH_A(0), // Valid values are 1-36
|
|
.WRITE_WIDTH_B(0), // Valid values are 1-36
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INIT_xx are for "18Kb" configuration only
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
.INIT_FF(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for "18Kb" configuration only
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) BRAM_TDP_MACRO_inst (
|
|
.DOA(DOA), // Output port-A data, width defined by READ_WIDTH_A parameter
|
|
.DOB(DOB), // Output port-B data, width defined by READ_WIDTH_B parameter
|
|
.ADDRA(ADDRA), // Input port-A address, width defined by Port A depth
|
|
.ADDRB(ADDRB), // Input port-B address, width defined by Port B depth
|
|
.CLKA(CLKA), // 1-bit input port-A clock
|
|
.CLKB(CLKB), // 1-bit input port-B clock
|
|
.DIA(DIA), // Input port-A data, width defined by WRITE_WIDTH_A parameter
|
|
.DIB(DIB), // Input port-B data, width defined by WRITE_WIDTH_B parameter
|
|
.ENA(ENA), // 1-bit input port-A enable
|
|
.ENB(ENB), // 1-bit input port-B enable
|
|
.REGCEA(REGCEA), // 1-bit input port-A output register enable
|
|
.REGCEB(REGCEB), // 1-bit input port-B output register enable
|
|
.RSTA(RSTA), // 1-bit input port-A reset
|
|
.RSTB(RSTB), // 1-bit input port-B reset
|
|
.WEA(WEA), // Input port-A write enable, width defined by Port A depth
|
|
.WEB(WEB) // Input port-B write enable, width defined by Port B depth
|
|
);
|
|
|
|
// End of BRAM_TDP_MACRO_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="DSP48" treetype="folder">
|
|
<Template label="Add / Multiply Accumulate (ADDMACC_MACRO)" treetype="template">
|
|
// ADDMACC_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ADDMACC_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ADDMACC_MACRO: Variable width & latency - Pre-Add -> Multiplier -> Accumulate
|
|
// function implemented in a DSP48E
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ADDMACC_MACRO #(
|
|
.DEVICE("SPARTAN6"), // Target Device: "VIRTEX6", "SPARTAN6"
|
|
.LATENCY(4), // Desired clock cycle latency, 0-4
|
|
.WIDTH_PREADD(18), // Pre-adder input width, 1-18
|
|
.WIDTH_MULTIPLIER(18), // Multiplier input width, 1-18
|
|
.WIDTH_PRODUCT(48) // MACC output width, 1-48
|
|
) ADDMACC_MACRO_inst (
|
|
.PRODUCT(PRODUCT), // MACC result output, width defined by WIDTH_PRODUCT parameter
|
|
.CARRYIN(CARRYIN), // 1-bit carry-in input
|
|
.CLK(CLK), // 1-bit clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.LOAD(LOAD), // 1-bit accumulator load input
|
|
.LOAD_DATA(LOAD_DATA), // Accumulator load data input, width defined by WIDTH_PRODUCT parameter
|
|
.MULTIPLIER(MULTIPLIER), // Multiplier data input, width defined by WIDTH_MULTIPLIER parameter
|
|
.PREADD2(PREADD2), // Preadder data input, width defined by WIDTH_PREADD parameter
|
|
.PREADD1(PREADD1), // Preadder data input, width defined by WIDTH_PREADD parameter
|
|
.RST(RST) // 1-bit active high synchronous reset
|
|
);
|
|
|
|
// End of ADDMACC_MACRO_inst instantiation
|
|
</Template>
|
|
<Template label="Add / Subtract (ADDSUB_MACRO)" treetype="template">
|
|
// ADDSUB_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ADDSUB_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ADDSUB_MACRO: Variable width & latency - Adder / Subtracter implemented in a DSP48E
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ADDSUB_MACRO #(
|
|
.DEVICE("SPARTAN6"), // Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6"
|
|
.LATENCY(2), // Desired clock cycle latency, 0-2
|
|
.WIDTH(48) // Input / output bus width, 1-48
|
|
) ADDSUB_MACRO_inst (
|
|
.CARRYOUT(CARRYOUT), // 1-bit carry-out output signal
|
|
.RESULT(RESULT), // Add/sub result output, width defined by WIDTH parameter
|
|
.A(A), // Input A bus, width defined by WIDTH parameter
|
|
.ADD_SUB(ADD_SUB), // 1-bit add/sub input, high selects add, low selects subtract
|
|
.B(B), // Input B bus, width defined by WIDTH parameter
|
|
.CARRYIN(CARRYIN), // 1-bit carry-in input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.CLK(CLK), // 1-bit clock input
|
|
.RST(RST) // 1-bit active high synchronous reset
|
|
);
|
|
|
|
// End of ADDSUB_MACRO_inst instantiation
|
|
</Template>
|
|
<Template label="Loadable Counter (COUNTER_LOAD_MACRO)" treetype="template">
|
|
// COUNTER_LOAD_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (COUNTER_LOAD_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// COUNTER_LOAD_MACRO: Loadable variable counter implemented in a DSP48E
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
COUNTER_LOAD_MACRO #(
|
|
.COUNT_BY(48'h000000000001), // Count by value
|
|
.DEVICE("SPARTAN6"), // Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6"
|
|
.WIDTH_DATA(48) // Counter output bus width, 1-48
|
|
) COUNTER_LOAD_MACRO_inst (
|
|
.Q(Q), // Counter output, width determined by WIDTH_DATA parameter
|
|
.CLK(CLK), // 1-bit clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.DIRECTION(DIRECTION), // 1-bit up/down count direction input, high is count up
|
|
.LOAD(LOAD), // 1-bit active high load input
|
|
.LOAD_DATA(LOAD_DATA), // Counter load data, width determined by WIDTH_DATA parameter
|
|
.RST(RST) // 1-bit active high synchronous reset
|
|
);
|
|
|
|
// End of COUNTER_LOAD_MACRO_inst instantiation
|
|
</Template>
|
|
<Template label="Multiply Accumulate (MACC_MACRO)" treetype="template">
|
|
// MACC_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MACC_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MACC_MACRO: Multiply Accumulate Function implemented in a DSP48E
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MACC_MACRO #(
|
|
.DEVICE("SPARTAN6"), // Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6"
|
|
.LATENCY(3), // Desired clock cycle latency, 1-4
|
|
.WIDTH_A(18), // Multiplier A-input bus width, 1-18
|
|
.WIDTH_B(18), // Multiplier B-input bus width, 1-18
|
|
.WIDTH_P(48) // Accumulator output bus width, 1-48
|
|
) MACC_MACRO_inst (
|
|
.P(P), // MACC output bus, width determined by WIDTH_P parameter
|
|
.A(A), // MACC input A bus, width determined by WIDTH_A parameter
|
|
.ADDSUB(ADDSUB), // 1-bit add/sub input, high selects add, low selects subtract
|
|
.B(B), // MACC input B bus, width determined by WIDTH_B parameter
|
|
.CARRYIN(CARRYIN), // 1-bit carry-in input to accumulator
|
|
.CE(CE), // 1-bit active high input clock enable
|
|
.CLK(CLK), // 1-bit positive edge clock input
|
|
.LOAD(LOAD), // 1-bit active high input load accumulator enable
|
|
.LOAD_DATA(LOAD_DATA), // Load accumulator input data, width determined by WIDTH_P parameter
|
|
.RST(RST) // 1-bit input active high reset
|
|
);
|
|
|
|
// End of MACC_MACRO_inst instantiation
|
|
</Template>
|
|
<Template label="Multiplier (MULT_MACRO)" treetype="template">
|
|
// MULT_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MULT_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MULT_MACRO: Multiply Function implemented in a DSP48E
|
|
// Spartan-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MULT_MACRO #(
|
|
.DEVICE("SPARTAN6"), // Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6"
|
|
.LATENCY(3), // Desired clock cycle latency, 0-4
|
|
.WIDTH_A(18), // Multiplier A-input bus width, 1-18
|
|
.WIDTH_B(18) // Multiplier B-input bus width, 1-18
|
|
) MULT_MACRO_inst (
|
|
.P(P), // Multiplier output bus, width determined by WIDTH_P parameter
|
|
.A(A), // Multiplier input A bus, width determined by WIDTH_A parameter
|
|
.B(B), // Multiplier input B bus, width determined by WIDTH_B parameter
|
|
.CE(CE), // 1-bit active high input clock enable
|
|
.CLK(CLK), // 1-bit positive edge clock input
|
|
.RST(RST) // 1-bit input active high reset
|
|
);
|
|
|
|
// End of MULT_MACRO_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Virtex-5" treetype="folder">
|
|
<SubFolder label="RAM" treetype="folder">
|
|
<Template label="Single Port RAM (BRAM_SINGLE_MACRO)" treetype="template">
|
|
// BRAM_SINGLE_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BRAM_SINGLE_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BRAM_SINGLE_MACRO: Single Port RAM
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
/////////////////////////////////////////////////////////////////////
|
|
// READ_WIDTH | BRAM_SIZE | READ Depth | ADDR Width | //
|
|
// WRITE_WIDTH | | WRITE Depth | | WE Width //
|
|
// ============|===========|=============|============|============//
|
|
// 37-72 | "36Kb" | 512 | 9-bit | 8-bit //
|
|
// 19-36 | "36Kb" | 1024 | 10-bit | 4-bit //
|
|
// 19-36 | "18Kb" | 512 | 9-bit | 4-bit //
|
|
// 10-18 | "36Kb" | 2048 | 11-bit | 2-bit //
|
|
// 10-18 | "18Kb" | 1024 | 10-bit | 2-bit //
|
|
// 5-9 | "36Kb" | 4096 | 12-bit | 1-bit //
|
|
// 5-9 | "18Kb" | 2048 | 11-bit | 1-bit //
|
|
// 3-4 | "36Kb" | 8192 | 13-bit | 1-bit //
|
|
// 3-4 | "18Kb" | 4096 | 12-bit | 1-bit //
|
|
// 2 | "36Kb" | 16384 | 13-bit | 1-bit //
|
|
// 2 | "18Kb" | 8192 | 12-bit | 1-bit //
|
|
// 1 | "36Kb" | 32768 | 13-bit | 1-bit //
|
|
// 1 | "18Kb" | 16384 | 12-bit | 1-bit //
|
|
/////////////////////////////////////////////////////////////////////
|
|
|
|
BRAM_SINGLE_MACRO #(
|
|
.BRAM_SIZE("18Kb"), // Target BRAM, "18Kb" or "36Kb"
|
|
.DEVICE("VIRTEX5"), // Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6"
|
|
.DO_REG(0), // Optional output register (0 or 1)
|
|
.INIT(36'h000000000), // Initial values on output port
|
|
.INIT_FILE ("NONE"),
|
|
.WRITE_WIDTH(0), // Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
|
|
.READ_WIDTH(0), // Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
|
|
.SIM_MODE("SAFE"), // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details
|
|
.SRVAL(36'h000000000), // Set/Reset value for port output
|
|
.WRITE_MODE("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INIT_xx are valid when configured as 36Kb
|
|
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INIT_xx are valid when configured as 36Kb
|
|
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) BRAM_SINGLE_MACRO_inst (
|
|
.DO(DO), // Output data
|
|
.ADDR(ADDR), // Input address
|
|
.CLK(CLK), // Input clock
|
|
.DI(DI), // Input data port
|
|
.EN(EN), // Input RAM enable
|
|
.REGCE(REGCE), // Input output register enable
|
|
.RST(RST), // Input reset
|
|
.WE(WE) // Input write enable
|
|
);
|
|
|
|
// End of BRAM_SINGLE_MACRO_inst instantiation
|
|
</Template>
|
|
<Template label="Simple Dual Port RAM (BRAM_SDP_MACRO)" treetype="template">
|
|
// BRAM_SDP_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BRAM_SDP_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BRAM_SDP_MACRO: Simple Dual Port RAM
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
///////////////////////////////////////////////////////////////////////
|
|
// READ_WIDTH | BRAM_SIZE | READ Depth | RDADDR Width | //
|
|
// WRITE_WIDTH | | WRITE Depth | WRADDR Width | WE Width //
|
|
// ============|===========|=============|==============|============//
|
|
// 37-72 | "36Kb" | 512 | 9-bit | 8-bit //
|
|
// 19-36 | "36Kb" | 1024 | 10-bit | 4-bit //
|
|
// 19-36 | "18Kb" | 512 | 9-bit | 4-bit //
|
|
// 10-18 | "36Kb" | 2048 | 11-bit | 2-bit //
|
|
// 10-18 | "18Kb" | 1024 | 10-bit | 2-bit //
|
|
// 5-9 | "36Kb" | 4096 | 12-bit | 1-bit //
|
|
// 5-9 | "18Kb" | 2048 | 11-bit | 1-bit //
|
|
// 3-4 | "36Kb" | 8192 | 13-bit | 1-bit //
|
|
// 3-4 | "18Kb" | 4096 | 12-bit | 1-bit //
|
|
// 2 | "36Kb" | 16384 | 13-bit | 1-bit //
|
|
// 2 | "18Kb" | 8192 | 12-bit | 1-bit //
|
|
// 1 | "36Kb" | 32768 | 13-bit | 1-bit //
|
|
// 1 | "18Kb" | 16384 | 12-bit | 1-bit //
|
|
///////////////////////////////////////////////////////////////////////
|
|
|
|
BRAM_SDP_MACRO #(
|
|
.BRAM_SIZE("18Kb"), // Target BRAM, "18Kb" or "36Kb"
|
|
.DEVICE("VIRTEX5"), // Target device: "VIRTEX5", "VIRTEX6", "SPARTAN6"
|
|
.WRITE_WIDTH(0), // Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
|
|
.READ_WIDTH(0), // Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
|
|
.DO_REG(0), // Optional output register (0 or 1)
|
|
.INIT_FILE ("NONE"),
|
|
.SIM_COLLISION_CHECK ("ALL"), // Collision check enable "ALL", "WARNING_ONLY",
|
|
// "GENERATE_X_ONLY" or "NONE"
|
|
.SIM_MODE("SAFE"), // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details
|
|
.SRVAL(72'h000000000000000000), // Set/Reset value for port output
|
|
.INIT(72'h000000000000000000), // Initial values on output port
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INIT_xx are valid when configured as 36Kb
|
|
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are valid when configured as 36Kb
|
|
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) BRAM_SDP_MACRO_inst (
|
|
.DO(DO), // Output read data port
|
|
.DI(DI), // Input write data port
|
|
.RDADDR(RDADDR), // Input read address
|
|
.RDCLK(RDCLK), // Input read clock
|
|
.RDEN(RDEN), // Input read port enable
|
|
.REGCE(REGCE), // Input read output register enable
|
|
.RST(RST), // Input reset
|
|
.WE(WE), // Input write enable
|
|
.WRADDR(WRADDR), // Input write address
|
|
.WRCLK(WRCLK), // Input write clock
|
|
.WREN(WREN) // Input write port enable
|
|
);
|
|
|
|
// End of BRAM_SDP_MACRO_inst instantiation
|
|
</Template>
|
|
<Template label="True Dual Port RAM (BRAM_TDP_MACRO)" treetype="template">
|
|
// BRAM_TDP_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BRAM_TDP_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BRAM_TDP_MACRO: True Dual Port RAM
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
//////////////////////////////////////////////////////////////////////////
|
|
// DATA_WIDTH_A/B | BRAM_SIZE | RAM Depth | ADDRA/B Width | WEA/B Width //
|
|
// ===============|===========|===========|===============|=============//
|
|
// 19-36 | "36Kb" | 1024 | 10-bit | 4-bit //
|
|
// 10-18 | "36Kb" | 2048 | 11-bit | 2-bit //
|
|
// 10-18 | "18Kb" | 1024 | 10-bit | 2-bit //
|
|
// 5-9 | "36Kb" | 4096 | 12-bit | 1-bit //
|
|
// 5-9 | "18Kb" | 2048 | 11-bit | 1-bit //
|
|
// 3-4 | "36Kb" | 8192 | 13-bit | 1-bit //
|
|
// 3-4 | "18Kb" | 4096 | 12-bit | 1-bit //
|
|
// 2 | "36Kb" | 16384 | 13-bit | 1-bit //
|
|
// 2 | "18Kb" | 8192 | 12-bit | 1-bit //
|
|
// 1 | "36Kb" | 32768 | 13-bit | 1-bit //
|
|
// 1 | "18Kb" | 16384 | 12-bit | 1-bit //
|
|
//////////////////////////////////////////////////////////////////////////
|
|
|
|
BRAM_TDP_MACRO #(
|
|
.BRAM_SIZE("18Kb"), // Target BRAM: "18Kb" or "36Kb"
|
|
.DEVICE("VIRTEX5"), // Target device: "VIRTEX5", "VIRTEX6", "SPARTAN6"
|
|
.DOA_REG(0), // Optional port A output register (0 or 1)
|
|
.DOB_REG(0), // Optional port B output register (0 or 1)
|
|
.INIT_A(36'h0000000), // Initial values on port A output port
|
|
.INIT_B(36'h00000000), // Initial values on port B output port
|
|
.INIT_FILE ("NONE"),
|
|
.READ_WIDTH_A (0), // Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
|
|
.READ_WIDTH_B (0), // Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
|
|
.SIM_COLLISION_CHECK ("ALL"), // Collision check enable "ALL", "WARNING_ONLY",
|
|
// "GENERATE_X_ONLY" or "NONE"
|
|
.SIM_MODE("SAFE"), // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details
|
|
.SRVAL_A(36'h00000000), // Set/Reset value for port A output
|
|
.SRVAL_B(36'h00000000), // Set/Reset value for port B output
|
|
.WRITE_MODE_A("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
|
|
.WRITE_MODE_B("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
|
|
.WRITE_WIDTH_A(0), // Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
|
|
.WRITE_WIDTH_B(0), // Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INIT_xx are valid when configured as 36Kb
|
|
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
.INIT_FF(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are valid when configured as 36Kb
|
|
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) BRAM_TDP_MACRO_inst (
|
|
.DOA(DOA), // Output port-A data
|
|
.DOB(DOB), // Output port-B data
|
|
.ADDRA(ADDRA), // Input port-A address
|
|
.ADDRB(ADDRB), // Input port-B address
|
|
.CLKA(CLKA), // Input port-A clock
|
|
.CLKB(CLKB), // Input port-B clock
|
|
.DIA(DIA), // Input port-A data
|
|
.DIB(DIB), // Input port-B data
|
|
.ENA(ENA), // Input port-A enable
|
|
.ENB(ENB), // Input port-B enable
|
|
.REGCEA(REGCEA), // Input port-A output register enable
|
|
.REGCEB(REGCEB), // Input port-B output register enable
|
|
.RSTA(RSTA), // Input port-A reset
|
|
.RSTB(RSTB), // Input port-B reset
|
|
.WEA(WEA), // Input port-A write enable
|
|
.WEB(WEB) // Input port-B write enable
|
|
);
|
|
|
|
// End of BRAM_TDP_MACRO_inst instantiation
|
|
</Template>
|
|
<Template label="Dual Clock FIFO (FIFO_DUALCLOCK_MACRO)" treetype="template">
|
|
// FIFO_DUALCLOCK_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FIFO_DUALCLOCK_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FIFO_DUALCLOCK_MACRO: Dual Clock First-In, First-Out (FIFO) RAM Buffer
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
/////////////////////////////////////////////////////////////////
|
|
// DATA_WIDTH | FIFO_SIZE | FIFO Depth | RDCOUNT/WRCOUNT Width //
|
|
// ===========|===========|============|=======================//
|
|
// 37-72 | "36Kb" | 512 | 9-bit //
|
|
// 19-36 | "36Kb" | 1024 | 10-bit //
|
|
// 19-36 | "18Kb" | 512 | 9-bit //
|
|
// 10-18 | "36Kb" | 2048 | 11-bit //
|
|
// 10-18 | "18Kb" | 1024 | 10-bit //
|
|
// 5-9 | "36Kb" | 4096 | 12-bit //
|
|
// 5-9 | "18Kb" | 2048 | 11-bit //
|
|
// 1-4 | "36Kb" | 8192 | 13-bit //
|
|
// 1-4 | "18Kb" | 4096 | 12-bit //
|
|
/////////////////////////////////////////////////////////////////
|
|
|
|
FIFO_DUALCLOCK_MACRO #(
|
|
.ALMOST_EMPTY_OFFSET(9'h080), // Sets the almost empty threshold
|
|
.ALMOST_FULL_OFFSET(9'h080), // Sets almost full threshold
|
|
.DATA_WIDTH(0), // Valid values are 1-72 (37-72 only valid when FIFO_SIZE="36Kb")
|
|
.DEVICE("VIRTEX5"), // Target device: "VIRTEX5", "VIRTEX6"
|
|
.FIFO_SIZE ("18Kb"), // Target BRAM: "18Kb" or "36Kb"
|
|
.FIRST_WORD_FALL_THROUGH ("FALSE"), // Sets the FIFO FWFT to "TRUE" or "FALSE"
|
|
.SIM_MODE("SAFE") // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details
|
|
) FIFO_DUALCLOCK_MACRO_inst (
|
|
.ALMOSTEMPTY(ALMOSTEMPTY), // Output almost empty
|
|
.ALMOSTFULL(ALMOSTFULL), // Output almost full
|
|
.DO(DO), // Output data
|
|
.EMPTY(EMPTY), // Output empty
|
|
.FULL(FULL), // Output full
|
|
.RDCOUNT(RDCOUNT), // Output read count
|
|
.RDERR(RDERR), // Output read error
|
|
.WRCOUNT(WRCOUNT), // Output write count
|
|
.WRERR(WRERR), // Output write error
|
|
.DI(DI), // Input data
|
|
.RDCLK(RDCLK), // Input read clock
|
|
.RDEN(RDEN), // Input read enable
|
|
.RST(RST), // Input reset
|
|
.WRCLK(WRCLK), // Input write clock
|
|
.WREN(WREN) // Input write enable
|
|
);
|
|
|
|
// End of FIFO_DUALCLOCK_MACRO_inst instantiation
|
|
</Template>
|
|
<Template label="Synchronous FIFO (FIFO_SYNC_MACRO)" treetype="template">
|
|
// FIFO_SYNC_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FIFO_SYNC_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FIFO_SYNC_MACRO: Synchronous First-In, First-Out (FIFO) RAM Buffer
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
/////////////////////////////////////////////////////////////////
|
|
// DATA_WIDTH | FIFO_SIZE | FIFO Depth | RDCOUNT/WRCOUNT Width //
|
|
// ===========|===========|============|=======================//
|
|
// 37-72 | "36Kb" | 512 | 9-bit //
|
|
// 19-36 | "36Kb" | 1024 | 10-bit //
|
|
// 19-36 | "18Kb" | 512 | 9-bit //
|
|
// 10-18 | "36Kb" | 2048 | 11-bit //
|
|
// 10-18 | "18Kb" | 1024 | 10-bit //
|
|
// 5-9 | "36Kb" | 4096 | 12-bit //
|
|
// 5-9 | "18Kb" | 2048 | 11-bit //
|
|
// 1-4 | "36Kb" | 8192 | 13-bit //
|
|
// 1-4 | "18Kb" | 4096 | 12-bit //
|
|
/////////////////////////////////////////////////////////////////
|
|
|
|
FIFO_SYNC_MACRO #(
|
|
.DEVICE("VIRTEX5"), // Target device: "VIRTEX5", "VIRTEX6"
|
|
.ALMOST_EMPTY_OFFSET(9'h080), // Sets the almost empty threshold
|
|
.ALMOST_FULL_OFFSET(9'h080), // Sets almost full threshold
|
|
.DATA_WIDTH(0), // Valid values are 1-72 (37-72 only valid when FIFO_SIZE="36Kb")
|
|
.DO_REG(0), // Optional output register (0 or 1)
|
|
.FIFO_SIZE ("18Kb"), // Target BRAM: "18Kb" or "36Kb"
|
|
.SIM_MODE("SAFE") // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details
|
|
) FIFO_SYNC_MACRO_inst (
|
|
.ALMOSTEMPTY(ALMOSTEMPTY), // Output almost empty
|
|
.ALMOSTFULL(ALMOSTFULL), // Output almost full
|
|
.DO(DO), // Output data
|
|
.EMPTY(EMPTY), // Output empty
|
|
.FULL(FULL), // Output full
|
|
.RDCOUNT(RDCOUNT), // Output read count
|
|
.RDERR(RDERR), // Output read error
|
|
.WRCOUNT(WRCOUNT), // Output write count
|
|
.WRERR(WRERR), // Output write error
|
|
.CLK(CLK), // Input clock
|
|
.DI(DI), // Input data
|
|
.RDEN(RDEN), // Input read enable
|
|
.RST(RST), // Input reset
|
|
.WREN(WREN) // Input write enable
|
|
);
|
|
|
|
// End of FIFO_SYNC_MACRO_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="DSP48" treetype="folder">
|
|
<Template label="Add / Subtract (ADDSUB_MACRO)" treetype="template">
|
|
// ADDSUB_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ADDSUB_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ADDSUB_MACRO: Variable width & latency - Adder / Subtracter implemented in a DSP48E
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ADDSUB_MACRO #(
|
|
.DEVICE("VIRTEX5"), // Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6"
|
|
.LATENCY(2), // Desired clock cycle latency, 0-2
|
|
.WIDTH(48) // Input / output bus width, 1-48
|
|
) ADDSUB_MACRO_inst (
|
|
.CARRYOUT(CARRYOUT), // 1-bit carry-out output signal
|
|
.RESULT(RESULT), // Add/sub result output, width defined by WIDTH parameter
|
|
.A(A), // Input A bus, width defined by WIDTH parameter
|
|
.ADD_SUB(ADD_SUB), // 1-bit add/sub input, high selects add, low selects subtract
|
|
.B(B), // Input B bus, width defined by WIDTH parameter
|
|
.CARRYIN(CARRYIN), // 1-bit carry-in input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.CLK(CLK), // 1-bit clock input
|
|
.RST(RST) // 1-bit active high synchronous reset
|
|
);
|
|
|
|
// End of ADDSUB_MACRO_inst instantiation
|
|
</Template>
|
|
<Template label="Loadable Counter (COUNTER_LOAD_MACRO)" treetype="template">
|
|
// COUNTER_LOAD_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (COUNTER_LOAD_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// COUNTER_LOAD_MACRO: Loadable variable counter implemented in a DSP48E
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
COUNTER_LOAD_MACRO #(
|
|
.COUNT_BY(48'h000000000001), // Count by value
|
|
.DEVICE("VIRTEX5"), // Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6"
|
|
.WIDTH_DATA(48) // Counter output bus width, 1-48
|
|
) COUNTER_LOAD_MACRO_inst (
|
|
.Q(Q), // Counter output, width determined by WIDTH_DATA parameter
|
|
.CLK(CLK), // 1-bit clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.DIRECTION(DIRECTION), // 1-bit up/down count direction input, high is count up
|
|
.LOAD(LOAD), // 1-bit active high load input
|
|
.LOAD_DATA(LOAD_DATA), // Counter load data, width determined by WIDTH_DATA parameter
|
|
.RST(RST) // 1-bit active high synchronous reset
|
|
);
|
|
|
|
// End of COUNTER_LOAD_MACRO_inst instantiation
|
|
</Template>
|
|
<Template label="Counter w/ Terminal Count (COUNTER_TC_MACRO)" treetype="template">
|
|
// COUNTER_TC_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (COUNTER_TC_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// COUNTER_TC_MACRO: Counter with terminal count implemented in a DSP48E
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
COUNTER_TC_MACRO #(
|
|
.COUNT_BY(48'h000000000001), // Count by value
|
|
.DEVICE("VIRTEX5"), // Target Device: "VIRTEX5", "VIRTEX6"
|
|
.DIRECTION("UP"), // Counter direction, "UP" or "DOWN"
|
|
.RESET_UPON_TC("FALSE"), // Reset counter upon terminal count, "TRUE" or "FALSE"
|
|
.TC_VALUE(48'h000000000000), // Terminal count value
|
|
.WIDTH_DATA(48) // Counter output bus width, 1-48
|
|
) COUNTER_TC_MACRO_inst (
|
|
.Q(Q), // Counter output bus, width determined by WIDTH_DATA parameter
|
|
.TC(TC), // 1-bit terminal count output, high = terminal count is reached
|
|
.CLK(CLK), // 1-bit positive edge clock input
|
|
.CE(CE), // 1-bit active high clock enable input
|
|
.RST(RST) // 1-bit active high synchronous reset
|
|
);
|
|
|
|
// End of COUNTER_TC_MACRO_inst instantiation
|
|
</Template>
|
|
<Template label="Equality Comparator (EQ_COMPARE_MACRO)" treetype="template">
|
|
// EQ_COMPARE_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (EQ_COMPARE_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// EQ_COMPARE_MACRO: Equality Comparator implemented in a DSP48E
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
EQ_COMPARE_MACRO #(
|
|
.DEVICE("VIRTEX5"), // Target Device: "VIRTEX5", "VIRTEX6"
|
|
.LATENCY(2), // Desired clock cycle latency, 0-2
|
|
.MASK(48'h000000000000), // Select bits to be masked, must set SEL_MASK="MASK"
|
|
.SEL_MASK("MASK"), // "MASK" = use MASK parameter,
|
|
// "DYNAMIC_PATTERN" = use DYNAMIC_PATTERN input bus
|
|
.SEL_PATTERN("STATIC_PATTERN"), // "STATIC_PATTERN" = use STATIC_PATTERN parameter,
|
|
// "DYNAMIC_PATTERN = use DYNAMIC_PATTERN input bus
|
|
.STATIC_PATTERN(48'h000000000000), // Specify static pattern, must set SEL_PATTERN = "STATIC_PATTERN"
|
|
.WIDTH(48) // Comparator output bus width, 1-48
|
|
) EQ_COMPARE_MACRO_inst (
|
|
.Q(Q), // 1-bit output indicating a match
|
|
.CE(CE), // 1-bit active high input clock enable
|
|
.CLK(CLK), // 1-bit positive edge clock input
|
|
.DATA_IN(DATA_IN), // Input Data Bus, width determined by WIDTH parameter
|
|
.DYNAMIC_PATTERN(DYNAMIC_PATTERN), // Input Dynamic Match/Mask Bus, width determined by WIDTH parameter
|
|
.RST(RST) // 1-bit input active high reset
|
|
);
|
|
|
|
// End of EQ_COMPARE_MACRO_inst instantiation
|
|
</Template>
|
|
<Template label="Multiply Accumulate (MACC_MACRO)" treetype="template">
|
|
// MACC_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MACC_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MACC_MACRO: Multiply Accumulate Function implemented in a DSP48E
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MACC_MACRO #(
|
|
.DEVICE("VIRTEX5"), // Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6"
|
|
.LATENCY(3), // Desired clock cycle latency, 1-4
|
|
.WIDTH_A(25), // Multiplier A-input bus width, 1-25
|
|
.WIDTH_B(18), // Multiplier B-input bus width, 1-18
|
|
.WIDTH_P(48) // Accumulator output bus width, 1-48
|
|
) MACC_MACRO_inst (
|
|
.P(P), // MACC output bus, width determined by WIDTH_P parameter
|
|
.A(A), // MACC input A bus, width determined by WIDTH_A parameter
|
|
.ADDSUB(ADDSUB), // 1-bit add/sub input, high selects add, low selects subtract
|
|
.B(B), // MACC input B bus, width determined by WIDTH_B parameter
|
|
.CARRYIN(CARRYIN), // 1-bit carry-in input to accumulator
|
|
.CE(CE), // 1-bit active high input clock enable
|
|
.CLK(CLK), // 1-bit positive edge clock input
|
|
.LOAD(LOAD), // 1-bit active high input load accumulator enable
|
|
.LOAD_DATA(LOAD_DATA), // Load accumulator input data, width determined by WIDTH_P parameter
|
|
.RST(RST) // 1-bit input active high reset
|
|
);
|
|
|
|
// End of MACC_MACRO_inst instantiation
|
|
</Template>
|
|
<Template label="Multiplier (MULT_MACRO)" treetype="template">
|
|
// MULT_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MULT_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MULT_MACRO: Multiply Function implemented in a DSP48E
|
|
// Virtex-5
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MULT_MACRO #(
|
|
.DEVICE("VIRTEX5"), // Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6"
|
|
.LATENCY(3), // Desired clock cycle latency, 0-4
|
|
.WIDTH_A(18), // Multiplier A-input bus width, 1-25
|
|
.WIDTH_B(18) // Multiplier B-input bus width, 1-18
|
|
) MULT_MACRO_inst (
|
|
.P(P), // Multiplier output bus, width determined by WIDTH_P parameter
|
|
.A(A), // Multiplier input A bus, width determined by WIDTH_A parameter
|
|
.B(B), // Multiplier input B bus, width determined by WIDTH_B parameter
|
|
.CE(CE), // 1-bit active high input clock enable
|
|
.CLK(CLK), // 1-bit positive edge clock input
|
|
.RST(RST) // 1-bit input active high reset
|
|
);
|
|
|
|
// End of MULT_MACRO_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Virtex-6" treetype="folder">
|
|
<SubFolder label="RAM" treetype="folder">
|
|
<Template label="Single Port RAM (BRAM_SINGLE_MACRO)" treetype="template">
|
|
// BRAM_SINGLE_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BRAM_SINGLE_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BRAM_SINGLE_MACRO: Single Port RAM
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
/////////////////////////////////////////////////////////////////////
|
|
// READ_WIDTH | BRAM_SIZE | READ Depth | ADDR Width | //
|
|
// WRITE_WIDTH | | WRITE Depth | | WE Width //
|
|
// ============|===========|=============|============|============//
|
|
// 37-72 | "36Kb" | 512 | 9-bit | 8-bit //
|
|
// 19-36 | "36Kb" | 1024 | 10-bit | 4-bit //
|
|
// 19-36 | "18Kb" | 512 | 9-bit | 4-bit //
|
|
// 10-18 | "36Kb" | 2048 | 11-bit | 2-bit //
|
|
// 10-18 | "18Kb" | 1024 | 10-bit | 2-bit //
|
|
// 5-9 | "36Kb" | 4096 | 12-bit | 1-bit //
|
|
// 5-9 | "18Kb" | 2048 | 11-bit | 1-bit //
|
|
// 3-4 | "36Kb" | 8192 | 13-bit | 1-bit //
|
|
// 3-4 | "18Kb" | 4096 | 12-bit | 1-bit //
|
|
// 2 | "36Kb" | 16384 | 14-bit | 1-bit //
|
|
// 2 | "18Kb" | 8192 | 13-bit | 1-bit //
|
|
// 1 | "36Kb" | 32768 | 15-bit | 1-bit //
|
|
// 1 | "18Kb" | 16384 | 14-bit | 1-bit //
|
|
/////////////////////////////////////////////////////////////////////
|
|
|
|
BRAM_SINGLE_MACRO #(
|
|
.BRAM_SIZE("18Kb"), // Target BRAM, "18Kb" or "36Kb"
|
|
.DEVICE("VIRTEX6"), // Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6"
|
|
.DO_REG(0), // Optional output register (0 or 1)
|
|
.INIT(36'h000000000), // Initial values on output port
|
|
.INIT_FILE ("NONE"),
|
|
.WRITE_WIDTH(0), // Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
|
|
.READ_WIDTH(0), // Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
|
|
.SRVAL(36'h000000000), // Set/Reset value for port output
|
|
.WRITE_MODE("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INIT_xx are valid when configured as 36Kb
|
|
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INIT_xx are valid when configured as 36Kb
|
|
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) BRAM_SINGLE_MACRO_inst (
|
|
.DO(DO), // Output data, width defined by READ_WIDTH parameter
|
|
.ADDR(ADDR), // Input address, width defined by read/write port depth
|
|
.CLK(CLK), // 1-bit input clock
|
|
.DI(DI), // Input data port, width defined by WRITE_WIDTH parameter
|
|
.EN(EN), // 1-bit input RAM enable
|
|
.REGCE(REGCE), // 1-bit input output register enable
|
|
.RST(RST), // 1-bit input reset
|
|
.WE(WE) // Input write enable, width defined by write port depth
|
|
);
|
|
|
|
// End of BRAM_SINGLE_MACRO_inst instantiation
|
|
</Template>
|
|
<Template label="Simple Dual Port RAM (BRAM_SDP_MACRO)" treetype="template">
|
|
// BRAM_SDP_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BRAM_SDP_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BRAM_SDP_MACRO: Simple Dual Port RAM
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
///////////////////////////////////////////////////////////////////////
|
|
// READ_WIDTH | BRAM_SIZE | READ Depth | RDADDR Width | //
|
|
// WRITE_WIDTH | | WRITE Depth | WRADDR Width | WE Width //
|
|
// ============|===========|=============|==============|============//
|
|
// 37-72 | "36Kb" | 512 | 9-bit | 8-bit //
|
|
// 19-36 | "36Kb" | 1024 | 10-bit | 4-bit //
|
|
// 19-36 | "18Kb" | 512 | 9-bit | 4-bit //
|
|
// 10-18 | "36Kb" | 2048 | 11-bit | 2-bit //
|
|
// 10-18 | "18Kb" | 1024 | 10-bit | 2-bit //
|
|
// 5-9 | "36Kb" | 4096 | 12-bit | 1-bit //
|
|
// 5-9 | "18Kb" | 2048 | 11-bit | 1-bit //
|
|
// 3-4 | "36Kb" | 8192 | 13-bit | 1-bit //
|
|
// 3-4 | "18Kb" | 4096 | 12-bit | 1-bit //
|
|
// 2 | "36Kb" | 16384 | 14-bit | 1-bit //
|
|
// 2 | "18Kb" | 8192 | 13-bit | 1-bit //
|
|
// 1 | "36Kb" | 32768 | 15-bit | 1-bit //
|
|
// 1 | "18Kb" | 16384 | 14-bit | 1-bit //
|
|
///////////////////////////////////////////////////////////////////////
|
|
|
|
BRAM_SDP_MACRO #(
|
|
.BRAM_SIZE("18Kb"), // Target BRAM, "18Kb" or "36Kb"
|
|
.DEVICE("VIRTEX6"), // Target device: "VIRTEX5", "VIRTEX6", "SPARTAN6"
|
|
.WRITE_WIDTH(0), // Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
|
|
.READ_WIDTH(0), // Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
|
|
.DO_REG(0), // Optional output register (0 or 1)
|
|
.INIT_FILE ("NONE"),
|
|
.SIM_COLLISION_CHECK ("ALL"), // Collision check enable "ALL", "WARNING_ONLY",
|
|
// "GENERATE_X_ONLY" or "NONE"
|
|
.SRVAL(72'h000000000000000000), // Set/Reset value for port output
|
|
.INIT(72'h000000000000000000), // Initial values on output port
|
|
.WRITE_MODE("WRITE_FIRST"), // Specify "READ_FIRST" for same clock or synchronous clocks
|
|
// Specify "WRITE_FIRST for asynchronous clocks on ports
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INIT_xx are valid when configured as 36Kb
|
|
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are valid when configured as 36Kb
|
|
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) BRAM_SDP_MACRO_inst (
|
|
.DO(DO), // Output read data port, width defined by READ_WIDTH parameter
|
|
.DI(DI), // Input write data port, width defined by WRITE_WIDTH parameter
|
|
.RDADDR(RDADDR), // Input read address, width defined by read port depth
|
|
.RDCLK(RDCLK), // 1-bit input read clock
|
|
.RDEN(RDEN), // 1-bit input read port enable
|
|
.REGCE(REGCE), // 1-bit input read output register enable
|
|
.RST(RST), // 1-bit input reset
|
|
.WE(WE), // Input write enable, width defined by write port depth
|
|
.WRADDR(WRADDR), // Input write address, width defined by write port depth
|
|
.WRCLK(WRCLK), // 1-bit input write clock
|
|
.WREN(WREN) // 1-bit input write port enable
|
|
);
|
|
|
|
// End of BRAM_SDP_MACRO_inst instantiation
|
|
</Template>
|
|
<Template label="True Dual Port RAM (BRAM_TDP_MACRO)" treetype="template">
|
|
// BRAM_TDP_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BRAM_TDP_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BRAM_TDP_MACRO: True Dual Port RAM
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
//////////////////////////////////////////////////////////////////////////
|
|
// DATA_WIDTH_A/B | BRAM_SIZE | RAM Depth | ADDRA/B Width | WEA/B Width //
|
|
// ===============|===========|===========|===============|=============//
|
|
// 19-36 | "36Kb" | 1024 | 10-bit | 4-bit //
|
|
// 10-18 | "36Kb" | 2048 | 11-bit | 2-bit //
|
|
// 10-18 | "18Kb" | 1024 | 10-bit | 2-bit //
|
|
// 5-9 | "36Kb" | 4096 | 12-bit | 1-bit //
|
|
// 5-9 | "18Kb" | 2048 | 11-bit | 1-bit //
|
|
// 3-4 | "36Kb" | 8192 | 13-bit | 1-bit //
|
|
// 3-4 | "18Kb" | 4096 | 12-bit | 1-bit //
|
|
// 2 | "36Kb" | 16384 | 14-bit | 1-bit //
|
|
// 2 | "18Kb" | 8192 | 13-bit | 1-bit //
|
|
// 1 | "36Kb" | 32768 | 15-bit | 1-bit //
|
|
// 1 | "18Kb" | 16384 | 14-bit | 1-bit //
|
|
//////////////////////////////////////////////////////////////////////////
|
|
|
|
BRAM_TDP_MACRO #(
|
|
.BRAM_SIZE("18Kb"), // Target BRAM: "18Kb" or "36Kb"
|
|
.DEVICE("VIRTEX6"), // Target device: "VIRTEX5", "VIRTEX6", "SPARTAN6"
|
|
.DOA_REG(0), // Optional port A output register (0 or 1)
|
|
.DOB_REG(0), // Optional port B output register (0 or 1)
|
|
.INIT_A(36'h0000000), // Initial values on port A output port
|
|
.INIT_B(36'h00000000), // Initial values on port B output port
|
|
.INIT_FILE ("NONE"),
|
|
.READ_WIDTH_A (0), // Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
|
|
.READ_WIDTH_B (0), // Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
|
|
.SIM_COLLISION_CHECK ("ALL"), // Collision check enable "ALL", "WARNING_ONLY",
|
|
// "GENERATE_X_ONLY" or "NONE"
|
|
.SRVAL_A(36'h00000000), // Set/Reset value for port A output
|
|
.SRVAL_B(36'h00000000), // Set/Reset value for port B output
|
|
.WRITE_MODE_A("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
|
|
.WRITE_MODE_B("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
|
|
.WRITE_WIDTH_A(0), // Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
|
|
.WRITE_WIDTH_B(0), // Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INIT_xx are valid when configured as 36Kb
|
|
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
.INIT_FF(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are valid when configured as 36Kb
|
|
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) BRAM_TDP_MACRO_inst (
|
|
.DOA(DOA), // Output port-A data, width defined by READ_WIDTH_A parameter
|
|
.DOB(DOB), // Output port-B data, width defined by READ_WIDTH_B parameter
|
|
.ADDRA(ADDRA), // Input port-A address, width defined by Port A depth
|
|
.ADDRB(ADDRB), // Input port-B address, width defined by Port B depth
|
|
.CLKA(CLKA), // 1-bit input port-A clock
|
|
.CLKB(CLKB), // 1-bit input port-B clock
|
|
.DIA(DIA), // Input port-A data, width defined by WRITE_WIDTH_A parameter
|
|
.DIB(DIB), // Input port-B data, width defined by WRITE_WIDTH_B parameter
|
|
.ENA(ENA), // 1-bit input port-A enable
|
|
.ENB(ENB), // 1-bit input port-B enable
|
|
.REGCEA(REGCEA), // 1-bit input port-A output register enable
|
|
.REGCEB(REGCEB), // 1-bit input port-B output register enable
|
|
.RSTA(RSTA), // 1-bit input port-A reset
|
|
.RSTB(RSTB), // 1-bit input port-B reset
|
|
.WEA(WEA), // Input port-A write enable, width defined by Port A depth
|
|
.WEB(WEB) // Input port-B write enable, width defined by Port B depth
|
|
);
|
|
|
|
// End of BRAM_TDP_MACRO_inst instantiation
|
|
</Template>
|
|
<Template label="Dual Clock FIFO (FIFO_DUALCLOCK_MACRO)" treetype="template">
|
|
// FIFO_DUALCLOCK_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FIFO_DUALCLOCK_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FIFO_DUALCLOCK_MACRO: Dual Clock First-In, First-Out (FIFO) RAM Buffer
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
/////////////////////////////////////////////////////////////////
|
|
// DATA_WIDTH | FIFO_SIZE | FIFO Depth | RDCOUNT/WRCOUNT Width //
|
|
// ===========|===========|============|=======================//
|
|
// 37-72 | "36Kb" | 512 | 9-bit //
|
|
// 19-36 | "36Kb" | 1024 | 10-bit //
|
|
// 19-36 | "18Kb" | 512 | 9-bit //
|
|
// 10-18 | "36Kb" | 2048 | 11-bit //
|
|
// 10-18 | "18Kb" | 1024 | 10-bit //
|
|
// 5-9 | "36Kb" | 4096 | 12-bit //
|
|
// 5-9 | "18Kb" | 2048 | 11-bit //
|
|
// 1-4 | "36Kb" | 8192 | 13-bit //
|
|
// 1-4 | "18Kb" | 4096 | 12-bit //
|
|
/////////////////////////////////////////////////////////////////
|
|
|
|
FIFO_DUALCLOCK_MACRO #(
|
|
.ALMOST_EMPTY_OFFSET(9'h080), // Sets the almost empty threshold
|
|
.ALMOST_FULL_OFFSET(9'h080), // Sets almost full threshold
|
|
.DATA_WIDTH(0), // Valid values are 1-72 (37-72 only valid when FIFO_SIZE="36Kb")
|
|
.DEVICE("VIRTEX6"), // Target device: "VIRTEX5", "VIRTEX6"
|
|
.FIFO_SIZE ("18Kb"), // Target BRAM: "18Kb" or "36Kb"
|
|
.FIRST_WORD_FALL_THROUGH ("FALSE") // Sets the FIFO FWFT to "TRUE" or "FALSE"
|
|
) FIFO_DUALCLOCK_MACRO_inst (
|
|
.ALMOSTEMPTY(ALMOSTEMPTY), // 1-bit output almost empty
|
|
.ALMOSTFULL(ALMOSTFULL), // 1-bit output almost full
|
|
.DO(DO), // Output data, width defined by DATA_WIDTH parameter
|
|
.EMPTY(EMPTY), // 1-bit output empty
|
|
.FULL(FULL), // 1-bit output full
|
|
.RDCOUNT(RDCOUNT), // Output read count, width determined by FIFO depth
|
|
.RDERR(RDERR), // 1-bit output read error
|
|
.WRCOUNT(WRCOUNT), // Output write count, width determined by FIFO depth
|
|
.WRERR(WRERR), // 1-bit output write error
|
|
.DI(DI), // Input data, width defined by DATA_WIDTH parameter
|
|
.RDCLK(RDCLK), // 1-bit input read clock
|
|
.RDEN(RDEN), // 1-bit input read enable
|
|
.RST(RST), // 1-bit input reset
|
|
.WRCLK(WRCLK), // 1-bit input write clock
|
|
.WREN(WREN) // 1-bit input write enable
|
|
);
|
|
|
|
// End of FIFO_DUALCLOCK_MACRO_inst instantiation
|
|
</Template>
|
|
<Template label="Synchronous FIFO (FIFO_SYNC_MACRO)" treetype="template">
|
|
// FIFO_SYNC_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FIFO_SYNC_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FIFO_SYNC_MACRO: Synchronous First-In, First-Out (FIFO) RAM Buffer
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
/////////////////////////////////////////////////////////////////
|
|
// DATA_WIDTH | FIFO_SIZE | FIFO Depth | RDCOUNT/WRCOUNT Width //
|
|
// ===========|===========|============|=======================//
|
|
// 37-72 | "36Kb" | 512 | 9-bit //
|
|
// 19-36 | "36Kb" | 1024 | 10-bit //
|
|
// 19-36 | "18Kb" | 512 | 9-bit //
|
|
// 10-18 | "36Kb" | 2048 | 11-bit //
|
|
// 10-18 | "18Kb" | 1024 | 10-bit //
|
|
// 5-9 | "36Kb" | 4096 | 12-bit //
|
|
// 5-9 | "18Kb" | 2048 | 11-bit //
|
|
// 1-4 | "36Kb" | 8192 | 13-bit //
|
|
// 1-4 | "18Kb" | 4096 | 12-bit //
|
|
/////////////////////////////////////////////////////////////////
|
|
|
|
FIFO_SYNC_MACRO #(
|
|
.DEVICE("VIRTEX6"), // Target Device: "VIRTEX5", "VIRTEX6"
|
|
.ALMOST_EMPTY_OFFSET(9'h080), // Sets the almost empty threshold
|
|
.ALMOST_FULL_OFFSET(9'h080), // Sets almost full threshold
|
|
.DATA_WIDTH(0), // Valid values are 1-72 (37-72 only valid when FIFO_SIZE="36Kb")
|
|
.DO_REG(0), // Optional output register (0 or 1)
|
|
.FIFO_SIZE ("18Kb") // Target BRAM: "18Kb" or "36Kb"
|
|
) FIFO_SYNC_MACRO_inst (
|
|
.ALMOSTEMPTY(ALMOSTEMPTY), // 1-bit output almost empty
|
|
.ALMOSTFULL(ALMOSTFULL), // 1-bit output almost full
|
|
.DO(DO), // Output data, width defined by DATA_WIDTH parameter
|
|
.EMPTY(EMPTY), // 1-bit output empty
|
|
.FULL(FULL), // 1-bit output full
|
|
.RDCOUNT(RDCOUNT), // Output read count, width determined by FIFO depth
|
|
.RDERR(RDERR), // 1-bit output read error
|
|
.WRCOUNT(WRCOUNT), // Output write count, width determined by FIFO depth
|
|
.WRERR(WRERR), // 1-bit output write error
|
|
.CLK(CLK), // 1-bit input clock
|
|
.DI(DI), // Input data, width defined by DATA_WIDTH parameter
|
|
.RDEN(RDEN), // 1-bit input read enable
|
|
.RST(RST), // 1-bit input reset
|
|
.WREN(WREN) // 1-bit input write enable
|
|
);
|
|
|
|
// End of FIFO_SYNC_MACRO_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="DSP48" treetype="folder">
|
|
<Template label="Add / Multiply Accumulate (ADDMACC_MACRO)" treetype="template">
|
|
// ADDMACC_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ADDMACC_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ADDMACC_MACRO: Variable width & latency - Pre-Add -> Multiplier -> Accumulate
|
|
// function implemented in a DSP48E
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ADDMACC_MACRO #(
|
|
.DEVICE("VIRTEX6"), // Target Device: "VIRTEX6", "SPARTAN6"
|
|
.LATENCY(4), // Desired clock cycle latency, 0-4
|
|
.WIDTH_PREADD(25), // Pre-adder input width, 1-25
|
|
.WIDTH_MULTIPLIER(18), // Multiplier input width, 1-18
|
|
.WIDTH_PRODUCT(48) // MACC output width, 1-48
|
|
) ADDMACC_MACRO_inst (
|
|
.PRODUCT(PRODUCT), // MACC result output, width defined by WIDTH_PRODUCT parameter
|
|
.CARRYIN(CARRYIN), // 1-bit carry-in input
|
|
.CLK(CLK), // 1-bit clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.LOAD(LOAD), // 1-bit accumulator load input
|
|
.LOAD_DATA(LOAD_DATA), // Accumulator load data input, width defined by WIDTH_PRODUCT parameter
|
|
.MULTIPLIER(MULTIPLIER), // Multiplier data input, width defined by WIDTH_MULTIPLIER parameter
|
|
.PREADD2(PREADD2), // Preadder data input, width defined by WIDTH_PREADD parameter
|
|
.PREADD1(PREADD1), // Preadder data input, width defined by WIDTH_PREADD parameter
|
|
.RST(RST) // 1-bit active high synchronous reset
|
|
);
|
|
|
|
// End of ADDMACC_MACRO_inst instantiation
|
|
</Template>
|
|
<Template label="Add / Subtract (ADDSUB_MACRO)" treetype="template">
|
|
// ADDSUB_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ADDSUB_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ADDSUB_MACRO: Variable width & latency - Adder / Subtracter implemented in a DSP48E
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ADDSUB_MACRO #(
|
|
.DEVICE("VIRTEX6"), // Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6"
|
|
.LATENCY(2), // Desired clock cycle latency, 0-2
|
|
.WIDTH(48) // Input / output bus width, 1-48
|
|
) ADDSUB_MACRO_inst (
|
|
.CARRYOUT(CARRYOUT), // 1-bit carry-out output signal
|
|
.RESULT(RESULT), // Add/sub result output, width defined by WIDTH parameter
|
|
.A(A), // Input A bus, width defined by WIDTH parameter
|
|
.ADD_SUB(ADD_SUB), // 1-bit add/sub input, high selects add, low selects subtract
|
|
.B(B), // Input B bus, width defined by WIDTH parameter
|
|
.CARRYIN(CARRYIN), // 1-bit carry-in input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.CLK(CLK), // 1-bit clock input
|
|
.RST(RST) // 1-bit active high synchronous reset
|
|
);
|
|
|
|
// End of ADDSUB_MACRO_inst instantiation
|
|
</Template>
|
|
<Template label="Loadable Counter (COUNTER_LOAD_MACRO)" treetype="template">
|
|
// COUNTER_LOAD_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (COUNTER_LOAD_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// COUNTER_LOAD_MACRO: Loadable variable counter implemented in a DSP48E
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
COUNTER_LOAD_MACRO #(
|
|
.COUNT_BY(48'h000000000001), // Count by value
|
|
.DEVICE("VIRTEX6"), // Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6"
|
|
.WIDTH_DATA(48) // Counter output bus width, 1-48
|
|
) COUNTER_LOAD_MACRO_inst (
|
|
.Q(Q), // Counter output, width determined by WIDTH_DATA parameter
|
|
.CLK(CLK), // 1-bit clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.DIRECTION(DIRECTION), // 1-bit up/down count direction input, high is count up
|
|
.LOAD(LOAD), // 1-bit active high load input
|
|
.LOAD_DATA(LOAD_DATA), // Counter load data, width determined by WIDTH_DATA parameter
|
|
.RST(RST) // 1-bit active high synchronous reset
|
|
);
|
|
|
|
// End of COUNTER_LOAD_MACRO_inst instantiation
|
|
</Template>
|
|
<Template label="Counter w/ Terminal Count (COUNTER_TC_MACRO)" treetype="template">
|
|
// COUNTER_TC_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (COUNTER_TC_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// COUNTER_TC_MACRO: Counter with terminal count implemented in a DSP48E
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
COUNTER_TC_MACRO #(
|
|
.COUNT_BY(48'h000000000001), // Count by value
|
|
.DEVICE("VIRTEX6"), // Target Device: "VIRTEX5", "VIRTEX6"
|
|
.DIRECTION("UP"), // Counter direction, "UP" or "DOWN"
|
|
.RESET_UPON_TC("FALSE"), // Reset counter upon terminal count, "TRUE" or "FALSE"
|
|
.TC_VALUE(48'h000000000000), // Terminal count value
|
|
.WIDTH_DATA(48) // Counter output bus width, 1-48
|
|
) COUNTER_TC_MACRO_inst (
|
|
.Q(Q), // Counter output bus, width determined by WIDTH_DATA parameter
|
|
.TC(TC), // 1-bit terminal count output, high = terminal count is reached
|
|
.CLK(CLK), // 1-bit positive edge clock input
|
|
.CE(CE), // 1-bit active high clock enable input
|
|
.RST(RST) // 1-bit active high synchronous reset
|
|
);
|
|
|
|
// End of COUNTER_TC_MACRO_inst instantiation
|
|
</Template>
|
|
<Template label="Equality Comparator (EQ_COMPARE_MACRO)" treetype="template">
|
|
// EQ_COMPARE_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (EQ_COMPARE_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// EQ_COMPARE_MACRO: Equality Comparator implemented in a DSP48E
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
EQ_COMPARE_MACRO #(
|
|
.DEVICE("VIRTEX6"), // Target Device: "VIRTEX5", "VIRTEX6"
|
|
.LATENCY(2), // Desired clock cycle latency, 0-2
|
|
.MASK(48'h000000000000), // Select bits to be masked, must set SEL_MASK="MASK"
|
|
.SEL_MASK("MASK"), // "MASK" = use MASK parameter,
|
|
// "DYNAMIC_PATTERN" = use DYNAMIC_PATTERN input bus
|
|
.SEL_PATTERN("STATIC_PATTERN"), // "STATIC_PATTERN" = use STATIC_PATTERN parameter,
|
|
// "DYNAMIC_PATTERN = use DYNAMIC_PATTERN input bus
|
|
.STATIC_PATTERN(48'h000000000000), // Specify static pattern, must set SEL_PATTERN = "STATIC_PATTERN"
|
|
.WIDTH(48) // Comparator output bus width, 1-48
|
|
) EQ_COMPARE_MACRO_inst (
|
|
.Q(Q), // 1-bit output indicating a match
|
|
.CE(CE), // 1-bit active high input clock enable
|
|
.CLK(CLK), // 1-bit positive edge clock input
|
|
.DATA_IN(DATA_IN), // Input Data Bus, width determined by WIDTH parameter
|
|
.DYNAMIC_PATTERN(DYNAMIC_PATTERN), // Input Dynamic Match/Mask Bus, width determined by WIDTH parameter
|
|
.RST(RST) // 1-bit input active high reset
|
|
);
|
|
|
|
// End of EQ_COMPARE_MACRO_inst instantiation
|
|
</Template>
|
|
<Template label="Multiply Accumulate (MACC_MACRO)" treetype="template">
|
|
// MACC_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MACC_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MACC_MACRO: Multiply Accumulate Function implemented in a DSP48E
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MACC_MACRO #(
|
|
.DEVICE("VIRTEX6"), // Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6"
|
|
.LATENCY(3), // Desired clock cycle latency, 1-4
|
|
.WIDTH_A(25), // Multiplier A-input bus width, 1-25
|
|
.WIDTH_B(18), // Multiplier B-input bus width, 1-18
|
|
.WIDTH_P(48) // Accumulator output bus width, 1-48
|
|
) MACC_MACRO_inst (
|
|
.P(P), // MACC output bus, width determined by WIDTH_P parameter
|
|
.A(A), // MACC input A bus, width determined by WIDTH_A parameter
|
|
.ADDSUB(ADDSUB), // 1-bit add/sub input, high selects add, low selects subtract
|
|
.B(B), // MACC input B bus, width determined by WIDTH_B parameter
|
|
.CARRYIN(CARRYIN), // 1-bit carry-in input to accumulator
|
|
.CE(CE), // 1-bit active high input clock enable
|
|
.CLK(CLK), // 1-bit positive edge clock input
|
|
.LOAD(LOAD), // 1-bit active high input load accumulator enable
|
|
.LOAD_DATA(LOAD_DATA), // Load accumulator input data, width determined by WIDTH_P parameter
|
|
.RST(RST) // 1-bit input active high reset
|
|
);
|
|
|
|
// End of MACC_MACRO_inst instantiation
|
|
</Template>
|
|
<Template label="Multiplier (MULT_MACRO)" treetype="template">
|
|
// MULT_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the forllowing instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MULT_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MULT_MACRO: Multiply Function implemented in a DSP48E
|
|
// Virtex-6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MULT_MACRO #(
|
|
.DEVICE("VIRTEX6"), // Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6"
|
|
.LATENCY(3), // Desired clock cycle latency, 0-4
|
|
.WIDTH_A(18), // Multiplier A-input bus width, 1-25
|
|
.WIDTH_B(18) // Multiplier B-input bus width, 1-18
|
|
) MULT_MACRO_inst (
|
|
.P(P), // Multiplier output bus, width determined by WIDTH_P parameter
|
|
.A(A), // Multiplier input A bus, width determined by WIDTH_A parameter
|
|
.B(B), // Multiplier input B bus, width determined by WIDTH_B parameter
|
|
.CE(CE), // 1-bit active high input clock enable
|
|
.CLK(CLK), // 1-bit positive edge clock input
|
|
.RST(RST) // 1-bit input active high reset
|
|
);
|
|
|
|
// End of MULT_MACRO_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Virtex-7" treetype="folder">
|
|
<SubFolder label="RAM" treetype="folder">
|
|
<Template label="Single Port RAM (BRAM_SINGLE_MACRO)" treetype="template">
|
|
// BRAM_SINGLE_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BRAM_SINGLE_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BRAM_SINGLE_MACRO: Single Port RAM
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
/////////////////////////////////////////////////////////////////////
|
|
// READ_WIDTH | BRAM_SIZE | READ Depth | ADDR Width | //
|
|
// WRITE_WIDTH | | WRITE Depth | | WE Width //
|
|
// ============|===========|=============|============|============//
|
|
// 37-72 | "36Kb" | 512 | 9-bit | 8-bit //
|
|
// 19-36 | "36Kb" | 1024 | 10-bit | 4-bit //
|
|
// 19-36 | "18Kb" | 512 | 9-bit | 4-bit //
|
|
// 10-18 | "36Kb" | 2048 | 11-bit | 2-bit //
|
|
// 10-18 | "18Kb" | 1024 | 10-bit | 2-bit //
|
|
// 5-9 | "36Kb" | 4096 | 12-bit | 1-bit //
|
|
// 5-9 | "18Kb" | 2048 | 11-bit | 1-bit //
|
|
// 3-4 | "36Kb" | 8192 | 13-bit | 1-bit //
|
|
// 3-4 | "18Kb" | 4096 | 12-bit | 1-bit //
|
|
// 2 | "36Kb" | 16384 | 14-bit | 1-bit //
|
|
// 2 | "18Kb" | 8192 | 13-bit | 1-bit //
|
|
// 1 | "36Kb" | 32768 | 15-bit | 1-bit //
|
|
// 1 | "18Kb" | 16384 | 14-bit | 1-bit //
|
|
/////////////////////////////////////////////////////////////////////
|
|
|
|
BRAM_SINGLE_MACRO #(
|
|
.BRAM_SIZE("18Kb"), // Target BRAM, "18Kb" or "36Kb"
|
|
.DEVICE("7SERIES"), // Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6", "7SERIES"
|
|
.DO_REG(0), // Optional output register (0 or 1)
|
|
.INIT(36'h000000000), // Initial values on output port
|
|
.INIT_FILE ("NONE"),
|
|
.WRITE_WIDTH(0), // Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
|
|
.READ_WIDTH(0), // Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
|
|
.SRVAL(36'h000000000), // Set/Reset value for port output
|
|
.WRITE_MODE("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INIT_xx are valid when configured as 36Kb
|
|
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INIT_xx are valid when configured as 36Kb
|
|
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) BRAM_SINGLE_MACRO_inst (
|
|
.DO(DO), // Output data, width defined by READ_WIDTH parameter
|
|
.ADDR(ADDR), // Input address, width defined by read/write port depth
|
|
.CLK(CLK), // 1-bit input clock
|
|
.DI(DI), // Input data port, width defined by WRITE_WIDTH parameter
|
|
.EN(EN), // 1-bit input RAM enable
|
|
.REGCE(REGCE), // 1-bit input output register enable
|
|
.RST(RST), // 1-bit input reset
|
|
.WE(WE) // Input write enable, width defined by write port depth
|
|
);
|
|
|
|
// End of BRAM_SINGLE_MACRO_inst instantiation
|
|
</Template>
|
|
<Template label="Simple Dual Port RAM (BRAM_SDP_MACRO)" treetype="template">
|
|
// BRAM_SDP_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BRAM_SDP_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BRAM_SDP_MACRO: Simple Dual Port RAM
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
///////////////////////////////////////////////////////////////////////
|
|
// READ_WIDTH | BRAM_SIZE | READ Depth | RDADDR Width | //
|
|
// WRITE_WIDTH | | WRITE Depth | WRADDR Width | WE Width //
|
|
// ============|===========|=============|==============|============//
|
|
// 37-72 | "36Kb" | 512 | 9-bit | 8-bit //
|
|
// 19-36 | "36Kb" | 1024 | 10-bit | 4-bit //
|
|
// 19-36 | "18Kb" | 512 | 9-bit | 4-bit //
|
|
// 10-18 | "36Kb" | 2048 | 11-bit | 2-bit //
|
|
// 10-18 | "18Kb" | 1024 | 10-bit | 2-bit //
|
|
// 5-9 | "36Kb" | 4096 | 12-bit | 1-bit //
|
|
// 5-9 | "18Kb" | 2048 | 11-bit | 1-bit //
|
|
// 3-4 | "36Kb" | 8192 | 13-bit | 1-bit //
|
|
// 3-4 | "18Kb" | 4096 | 12-bit | 1-bit //
|
|
// 2 | "36Kb" | 16384 | 14-bit | 1-bit //
|
|
// 2 | "18Kb" | 8192 | 13-bit | 1-bit //
|
|
// 1 | "36Kb" | 32768 | 15-bit | 1-bit //
|
|
// 1 | "18Kb" | 16384 | 14-bit | 1-bit //
|
|
///////////////////////////////////////////////////////////////////////
|
|
|
|
BRAM_SDP_MACRO #(
|
|
.BRAM_SIZE("18Kb"), // Target BRAM, "18Kb" or "36Kb"
|
|
.DEVICE("7SERIES"), // Target device: "VIRTEX5", "VIRTEX6", "SPARTAN6", "7SERIES"
|
|
.WRITE_WIDTH(0), // Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
|
|
.READ_WIDTH(0), // Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
|
|
.DO_REG(0), // Optional output register (0 or 1)
|
|
.INIT_FILE ("NONE"),
|
|
.SIM_COLLISION_CHECK ("ALL"), // Collision check enable "ALL", "WARNING_ONLY",
|
|
// "GENERATE_X_ONLY" or "NONE"
|
|
.SRVAL(72'h000000000000000000), // Set/Reset value for port output
|
|
.INIT(72'h000000000000000000), // Initial values on output port
|
|
.WRITE_MODE("WRITE_FIRST"), // Specify "READ_FIRST" for same clock or synchronous clocks
|
|
// Specify "WRITE_FIRST for asynchronous clocks on ports
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INIT_xx are valid when configured as 36Kb
|
|
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are valid when configured as 36Kb
|
|
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) BRAM_SDP_MACRO_inst (
|
|
.DO(DO), // Output read data port, width defined by READ_WIDTH parameter
|
|
.DI(DI), // Input write data port, width defined by WRITE_WIDTH parameter
|
|
.RDADDR(RDADDR), // Input read address, width defined by read port depth
|
|
.RDCLK(RDCLK), // 1-bit input read clock
|
|
.RDEN(RDEN), // 1-bit input read port enable
|
|
.REGCE(REGCE), // 1-bit input read output register enable
|
|
.RST(RST), // 1-bit input reset
|
|
.WE(WE), // Input write enable, width defined by write port depth
|
|
.WRADDR(WRADDR), // Input write address, width defined by write port depth
|
|
.WRCLK(WRCLK), // 1-bit input write clock
|
|
.WREN(WREN) // 1-bit input write port enable
|
|
);
|
|
|
|
// End of BRAM_SDP_MACRO_inst instantiation
|
|
</Template>
|
|
<Template label="True Dual Port RAM (BRAM_TDP_MACRO)" treetype="template">
|
|
// BRAM_TDP_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (BRAM_TDP_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// BRAM_TDP_MACRO: True Dual Port RAM
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
//////////////////////////////////////////////////////////////////////////
|
|
// DATA_WIDTH_A/B | BRAM_SIZE | RAM Depth | ADDRA/B Width | WEA/B Width //
|
|
// ===============|===========|===========|===============|=============//
|
|
// 19-36 | "36Kb" | 1024 | 10-bit | 4-bit //
|
|
// 10-18 | "36Kb" | 2048 | 11-bit | 2-bit //
|
|
// 10-18 | "18Kb" | 1024 | 10-bit | 2-bit //
|
|
// 5-9 | "36Kb" | 4096 | 12-bit | 1-bit //
|
|
// 5-9 | "18Kb" | 2048 | 11-bit | 1-bit //
|
|
// 3-4 | "36Kb" | 8192 | 13-bit | 1-bit //
|
|
// 3-4 | "18Kb" | 4096 | 12-bit | 1-bit //
|
|
// 2 | "36Kb" | 16384 | 14-bit | 1-bit //
|
|
// 2 | "18Kb" | 8192 | 13-bit | 1-bit //
|
|
// 1 | "36Kb" | 32768 | 15-bit | 1-bit //
|
|
// 1 | "18Kb" | 16384 | 14-bit | 1-bit //
|
|
//////////////////////////////////////////////////////////////////////////
|
|
|
|
BRAM_TDP_MACRO #(
|
|
.BRAM_SIZE("18Kb"), // Target BRAM: "18Kb" or "36Kb"
|
|
.DEVICE("7SERIES"), // Target device: "VIRTEX5", "VIRTEX6", "SPARTAN6", "7SERIES"
|
|
.DOA_REG(0), // Optional port A output register (0 or 1)
|
|
.DOB_REG(0), // Optional port B output register (0 or 1)
|
|
.INIT_A(36'h0000000), // Initial values on port A output port
|
|
.INIT_B(36'h00000000), // Initial values on port B output port
|
|
.INIT_FILE ("NONE"),
|
|
.READ_WIDTH_A (0), // Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
|
|
.READ_WIDTH_B (0), // Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
|
|
.SIM_COLLISION_CHECK ("ALL"), // Collision check enable "ALL", "WARNING_ONLY",
|
|
// "GENERATE_X_ONLY" or "NONE"
|
|
.SRVAL_A(36'h00000000), // Set/Reset value for port A output
|
|
.SRVAL_B(36'h00000000), // Set/Reset value for port B output
|
|
.WRITE_MODE_A("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
|
|
.WRITE_MODE_B("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
|
|
.WRITE_WIDTH_A(0), // Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
|
|
.WRITE_WIDTH_B(0), // Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
|
|
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INIT_xx are valid when configured as 36Kb
|
|
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are for the parity bits
|
|
.INIT_FF(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
|
|
// The next set of INITP_xx are valid when configured as 36Kb
|
|
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
|
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000)
|
|
) BRAM_TDP_MACRO_inst (
|
|
.DOA(DOA), // Output port-A data, width defined by READ_WIDTH_A parameter
|
|
.DOB(DOB), // Output port-B data, width defined by READ_WIDTH_B parameter
|
|
.ADDRA(ADDRA), // Input port-A address, width defined by Port A depth
|
|
.ADDRB(ADDRB), // Input port-B address, width defined by Port B depth
|
|
.CLKA(CLKA), // 1-bit input port-A clock
|
|
.CLKB(CLKB), // 1-bit input port-B clock
|
|
.DIA(DIA), // Input port-A data, width defined by WRITE_WIDTH_A parameter
|
|
.DIB(DIB), // Input port-B data, width defined by WRITE_WIDTH_B parameter
|
|
.ENA(ENA), // 1-bit input port-A enable
|
|
.ENB(ENB), // 1-bit input port-B enable
|
|
.REGCEA(REGCEA), // 1-bit input port-A output register enable
|
|
.REGCEB(REGCEB), // 1-bit input port-B output register enable
|
|
.RSTA(RSTA), // 1-bit input port-A reset
|
|
.RSTB(RSTB), // 1-bit input port-B reset
|
|
.WEA(WEA), // Input port-A write enable, width defined by Port A depth
|
|
.WEB(WEB) // Input port-B write enable, width defined by Port B depth
|
|
);
|
|
|
|
// End of BRAM_TDP_MACRO_inst instantiation
|
|
</Template>
|
|
<Template label="Dual Clock FIFO (FIFO_DUALCLOCK_MACRO)" treetype="template">
|
|
// FIFO_DUALCLOCK_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FIFO_DUALCLOCK_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FIFO_DUALCLOCK_MACRO: Dual Clock First-In, First-Out (FIFO) RAM Buffer
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
/////////////////////////////////////////////////////////////////
|
|
// DATA_WIDTH | FIFO_SIZE | FIFO Depth | RDCOUNT/WRCOUNT Width //
|
|
// ===========|===========|============|=======================//
|
|
// 37-72 | "36Kb" | 512 | 9-bit //
|
|
// 19-36 | "36Kb" | 1024 | 10-bit //
|
|
// 19-36 | "18Kb" | 512 | 9-bit //
|
|
// 10-18 | "36Kb" | 2048 | 11-bit //
|
|
// 10-18 | "18Kb" | 1024 | 10-bit //
|
|
// 5-9 | "36Kb" | 4096 | 12-bit //
|
|
// 5-9 | "18Kb" | 2048 | 11-bit //
|
|
// 1-4 | "36Kb" | 8192 | 13-bit //
|
|
// 1-4 | "18Kb" | 4096 | 12-bit //
|
|
/////////////////////////////////////////////////////////////////
|
|
|
|
FIFO_DUALCLOCK_MACRO #(
|
|
.ALMOST_EMPTY_OFFSET(9'h080), // Sets the almost empty threshold
|
|
.ALMOST_FULL_OFFSET(9'h080), // Sets almost full threshold
|
|
.DATA_WIDTH(0), // Valid values are 1-72 (37-72 only valid when FIFO_SIZE="36Kb")
|
|
.DEVICE("7SERIES"), // Target device: "VIRTEX5", "VIRTEX6", "7SERIES"
|
|
.FIFO_SIZE ("18Kb"), // Target BRAM: "18Kb" or "36Kb"
|
|
.FIRST_WORD_FALL_THROUGH ("FALSE") // Sets the FIFO FWFT to "TRUE" or "FALSE"
|
|
) FIFO_DUALCLOCK_MACRO_inst (
|
|
.ALMOSTEMPTY(ALMOSTEMPTY), // 1-bit output almost empty
|
|
.ALMOSTFULL(ALMOSTFULL), // 1-bit output almost full
|
|
.DO(DO), // Output data, width defined by DATA_WIDTH parameter
|
|
.EMPTY(EMPTY), // 1-bit output empty
|
|
.FULL(FULL), // 1-bit output full
|
|
.RDCOUNT(RDCOUNT), // Output read count, width determined by FIFO depth
|
|
.RDERR(RDERR), // 1-bit output read error
|
|
.WRCOUNT(WRCOUNT), // Output write count, width determined by FIFO depth
|
|
.WRERR(WRERR), // 1-bit output write error
|
|
.DI(DI), // Input data, width defined by DATA_WIDTH parameter
|
|
.RDCLK(RDCLK), // 1-bit input read clock
|
|
.RDEN(RDEN), // 1-bit input read enable
|
|
.RST(RST), // 1-bit input reset
|
|
.WRCLK(WRCLK), // 1-bit input write clock
|
|
.WREN(WREN) // 1-bit input write enable
|
|
);
|
|
|
|
// End of FIFO_DUALCLOCK_MACRO_inst instantiation
|
|
</Template>
|
|
<Template label="Synchronous FIFO (FIFO_SYNC_MACRO)" treetype="template">
|
|
// FIFO_SYNC_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (FIFO_SYNC_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// FIFO_SYNC_MACRO: Synchronous First-In, First-Out (FIFO) RAM Buffer
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
/////////////////////////////////////////////////////////////////
|
|
// DATA_WIDTH | FIFO_SIZE | FIFO Depth | RDCOUNT/WRCOUNT Width //
|
|
// ===========|===========|============|=======================//
|
|
// 37-72 | "36Kb" | 512 | 9-bit //
|
|
// 19-36 | "36Kb" | 1024 | 10-bit //
|
|
// 19-36 | "18Kb" | 512 | 9-bit //
|
|
// 10-18 | "36Kb" | 2048 | 11-bit //
|
|
// 10-18 | "18Kb" | 1024 | 10-bit //
|
|
// 5-9 | "36Kb" | 4096 | 12-bit //
|
|
// 5-9 | "18Kb" | 2048 | 11-bit //
|
|
// 1-4 | "36Kb" | 8192 | 13-bit //
|
|
// 1-4 | "18Kb" | 4096 | 12-bit //
|
|
/////////////////////////////////////////////////////////////////
|
|
|
|
FIFO_SYNC_MACRO #(
|
|
.DEVICE("7SERIES"), // Target Device: "VIRTEX5", "VIRTEX6", "7SERIES"
|
|
.ALMOST_EMPTY_OFFSET(9'h080), // Sets the almost empty threshold
|
|
.ALMOST_FULL_OFFSET(9'h080), // Sets almost full threshold
|
|
.DATA_WIDTH(0), // Valid values are 1-72 (37-72 only valid when FIFO_SIZE="36Kb")
|
|
.DO_REG(0), // Optional output register (0 or 1)
|
|
.FIFO_SIZE ("18Kb") // Target BRAM: "18Kb" or "36Kb"
|
|
) FIFO_SYNC_MACRO_inst (
|
|
.ALMOSTEMPTY(ALMOSTEMPTY), // 1-bit output almost empty
|
|
.ALMOSTFULL(ALMOSTFULL), // 1-bit output almost full
|
|
.DO(DO), // Output data, width defined by DATA_WIDTH parameter
|
|
.EMPTY(EMPTY), // 1-bit output empty
|
|
.FULL(FULL), // 1-bit output full
|
|
.RDCOUNT(RDCOUNT), // Output read count, width determined by FIFO depth
|
|
.RDERR(RDERR), // 1-bit output read error
|
|
.WRCOUNT(WRCOUNT), // Output write count, width determined by FIFO depth
|
|
.WRERR(WRERR), // 1-bit output write error
|
|
.CLK(CLK), // 1-bit input clock
|
|
.DI(DI), // Input data, width defined by DATA_WIDTH parameter
|
|
.RDEN(RDEN), // 1-bit input read enable
|
|
.RST(RST), // 1-bit input reset
|
|
.WREN(WREN) // 1-bit input write enable
|
|
);
|
|
|
|
// End of FIFO_SYNC_MACRO_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="DSP48" treetype="folder">
|
|
<Template label="Add / Multiply Accumulate (ADDMACC_MACRO)" treetype="template">
|
|
// ADDMACC_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ADDMACC_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ADDMACC_MACRO: Variable width & latency - Pre-Add -> Multiplier -> Accumulate
|
|
// function implemented in a DSP48E
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ADDMACC_MACRO #(
|
|
.DEVICE("7SERIES"), // Target Device: "VIRTEX6", "SPARTAN6", "7SERIES"
|
|
.LATENCY(4), // Desired clock cycle latency, 0-4
|
|
.WIDTH_PREADD(25), // Pre-adder input width, 1-25
|
|
.WIDTH_MULTIPLIER(18), // Multiplier input width, 1-18
|
|
.WIDTH_PRODUCT(48) // MACC output width, 1-48
|
|
) ADDMACC_MACRO_inst (
|
|
.PRODUCT(PRODUCT), // MACC result output, width defined by WIDTH_PRODUCT parameter
|
|
.CARRYIN(CARRYIN), // 1-bit carry-in input
|
|
.CLK(CLK), // 1-bit clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.LOAD(LOAD), // 1-bit accumulator load input
|
|
.LOAD_DATA(LOAD_DATA), // Accumulator load data input, width defined by WIDTH_PRODUCT parameter
|
|
.MULTIPLIER(MULTIPLIER), // Multiplier data input, width defined by WIDTH_MULTIPLIER parameter
|
|
.PREADD2(PREADD2), // Preadder data input, width defined by WIDTH_PREADD parameter
|
|
.PREADD1(PREADD1), // Preadder data input, width defined by WIDTH_PREADD parameter
|
|
.RST(RST) // 1-bit active high synchronous reset
|
|
);
|
|
|
|
// End of ADDMACC_MACRO_inst instantiation
|
|
</Template>
|
|
<Template label="Add / Subtract (ADDSUB_MACRO)" treetype="template">
|
|
// ADDSUB_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (ADDSUB_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// ADDSUB_MACRO: Variable width & latency - Adder / Subtracter implemented in a DSP48E
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ADDSUB_MACRO #(
|
|
.DEVICE("7SERIES"), // Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6", "7SERIES"
|
|
.LATENCY(2), // Desired clock cycle latency, 0-2
|
|
.WIDTH(48) // Input / output bus width, 1-48
|
|
) ADDSUB_MACRO_inst (
|
|
.CARRYOUT(CARRYOUT), // 1-bit carry-out output signal
|
|
.RESULT(RESULT), // Add/sub result output, width defined by WIDTH parameter
|
|
.A(A), // Input A bus, width defined by WIDTH parameter
|
|
.ADD_SUB(ADD_SUB), // 1-bit add/sub input, high selects add, low selects subtract
|
|
.B(B), // Input B bus, width defined by WIDTH parameter
|
|
.CARRYIN(CARRYIN), // 1-bit carry-in input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.CLK(CLK), // 1-bit clock input
|
|
.RST(RST) // 1-bit active high synchronous reset
|
|
);
|
|
|
|
// End of ADDSUB_MACRO_inst instantiation
|
|
</Template>
|
|
<Template label="Loadable Counter (COUNTER_LOAD_MACRO)" treetype="template">
|
|
// COUNTER_LOAD_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (COUNTER_LOAD_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// COUNTER_LOAD_MACRO: Loadable variable counter implemented in a DSP48E
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
COUNTER_LOAD_MACRO #(
|
|
.COUNT_BY(48'h000000000001), // Count by value
|
|
.DEVICE("7SERIES"), // Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6", "7SERIES"
|
|
.WIDTH_DATA(48) // Counter output bus width, 1-48
|
|
) COUNTER_LOAD_MACRO_inst (
|
|
.Q(Q), // Counter output, width determined by WIDTH_DATA parameter
|
|
.CLK(CLK), // 1-bit clock input
|
|
.CE(CE), // 1-bit clock enable input
|
|
.DIRECTION(DIRECTION), // 1-bit up/down count direction input, high is count up
|
|
.LOAD(LOAD), // 1-bit active high load input
|
|
.LOAD_DATA(LOAD_DATA), // Counter load data, width determined by WIDTH_DATA parameter
|
|
.RST(RST) // 1-bit active high synchronous reset
|
|
);
|
|
|
|
// End of COUNTER_LOAD_MACRO_inst instantiation
|
|
</Template>
|
|
<Template label="Counter w/ Terminal Count (COUNTER_TC_MACRO)" treetype="template">
|
|
// COUNTER_TC_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (COUNTER_TC_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// COUNTER_TC_MACRO: Counter with terminal count implemented in a DSP48E
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
COUNTER_TC_MACRO #(
|
|
.COUNT_BY(48'h000000000001), // Count by value
|
|
.DEVICE("7SERIES"), // Target Device: "VIRTEX5", "VIRTEX6", "7SERIES"
|
|
.DIRECTION("UP"), // Counter direction, "UP" or "DOWN"
|
|
.RESET_UPON_TC("FALSE"), // Reset counter upon terminal count, "TRUE" or "FALSE"
|
|
.TC_VALUE(48'h000000000000), // Terminal count value
|
|
.WIDTH_DATA(48) // Counter output bus width, 1-48
|
|
) COUNTER_TC_MACRO_inst (
|
|
.Q(Q), // Counter output bus, width determined by WIDTH_DATA parameter
|
|
.TC(TC), // 1-bit terminal count output, high = terminal count is reached
|
|
.CLK(CLK), // 1-bit positive edge clock input
|
|
.CE(CE), // 1-bit active high clock enable input
|
|
.RST(RST) // 1-bit active high synchronous reset
|
|
);
|
|
|
|
// End of COUNTER_TC_MACRO_inst instantiation
|
|
</Template>
|
|
<Template label="Equality Comparator (EQ_COMPARE_MACRO)" treetype="template">
|
|
// EQ_COMPARE_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (EQ_COMPARE_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// EQ_COMPARE_MACRO: Equality Comparator implemented in a DSP48E
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
EQ_COMPARE_MACRO #(
|
|
.DEVICE("7SERIES"), // Target Device: "VIRTEX5", "VIRTEX6","7SERIES"
|
|
.LATENCY(2), // Desired clock cycle latency, 0-2
|
|
.MASK(48'h000000000000), // Select bits to be masked, must set SEL_MASK="MASK"
|
|
.SEL_MASK("MASK"), // "MASK" = use MASK parameter,
|
|
// "DYNAMIC_PATTERN" = use DYNAMIC_PATTERN input bus
|
|
.SEL_PATTERN("STATIC_PATTERN"), // "STATIC_PATTERN" = use STATIC_PATTERN parameter,
|
|
// "DYNAMIC_PATTERN = use DYNAMIC_PATTERN input bus
|
|
.STATIC_PATTERN(48'h000000000000), // Specify static pattern, must set SEL_PATTERN = "STATIC_PATTERN"
|
|
.WIDTH(48) // Comparator output bus width, 1-48
|
|
) EQ_COMPARE_MACRO_inst (
|
|
.Q(Q), // 1-bit output indicating a match
|
|
.CE(CE), // 1-bit active high input clock enable
|
|
.CLK(CLK), // 1-bit positive edge clock input
|
|
.DATA_IN(DATA_IN), // Input Data Bus, width determined by WIDTH parameter
|
|
.DYNAMIC_PATTERN(DYNAMIC_PATTERN), // Input Dynamic Match/Mask Bus, width determined by WIDTH parameter
|
|
.RST(RST) // 1-bit input active high reset
|
|
);
|
|
|
|
// End of EQ_COMPARE_MACRO_inst instantiation
|
|
</Template>
|
|
<Template label="Multiply Accumulate (MACC_MACRO)" treetype="template">
|
|
// MACC_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MACC_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MACC_MACRO: Multiply Accumulate Function implemented in a DSP48E
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MACC_MACRO #(
|
|
.DEVICE("7SERIES"), // Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6", "7SERIES"
|
|
.LATENCY(3), // Desired clock cycle latency, 1-4
|
|
.WIDTH_A(25), // Multiplier A-input bus width, 1-25
|
|
.WIDTH_B(18), // Multiplier B-input bus width, 1-18
|
|
.WIDTH_P(48) // Accumulator output bus width, 1-48
|
|
) MACC_MACRO_inst (
|
|
.P(P), // MACC output bus, width determined by WIDTH_P parameter
|
|
.A(A), // MACC input A bus, width determined by WIDTH_A parameter
|
|
.ADDSUB(ADDSUB), // 1-bit add/sub input, high selects add, low selects subtract
|
|
.B(B), // MACC input B bus, width determined by WIDTH_B parameter
|
|
.CARRYIN(CARRYIN), // 1-bit carry-in input to accumulator
|
|
.CE(CE), // 1-bit active high input clock enable
|
|
.CLK(CLK), // 1-bit positive edge clock input
|
|
.LOAD(LOAD), // 1-bit active high input load accumulator enable
|
|
.LOAD_DATA(LOAD_DATA), // Load accumulator input data, width determined by WIDTH_P parameter
|
|
.RST(RST) // 1-bit input active high reset
|
|
);
|
|
|
|
// End of MACC_MACRO_inst instantiation
|
|
</Template>
|
|
<Template label="Multiplier (MULT_MACRO)" treetype="template">
|
|
// MULT_MACRO : In order to incorporate this function into the design,
|
|
// Verilog : the following instance declaration needs to be placed
|
|
// instance : in the body of the design code. The instance name
|
|
// declaration : (MULT_MACRO_inst) and/or the port declarations within the
|
|
// code : parenthesis may be changed to properly reference and
|
|
// : connect this function to the design. All inputs
|
|
// : and outputs must be connected.
|
|
|
|
// <-----Cut code below this line---->
|
|
|
|
// MULT_MACRO: Multiply Function implemented in a DSP48E
|
|
// Virtex-7
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
MULT_MACRO #(
|
|
.DEVICE("7SERIES"), // Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6","7SERIES"
|
|
.LATENCY(3), // Desired clock cycle latency, 0-4
|
|
.WIDTH_A(18), // Multiplier A-input bus width, 1-25
|
|
.WIDTH_B(18) // Multiplier B-input bus width, 1-18
|
|
) MULT_MACRO_inst (
|
|
.P(P), // Multiplier output bus, width determined by WIDTH_P parameter
|
|
.A(A), // Multiplier input A bus, width determined by WIDTH_A parameter
|
|
.B(B), // Multiplier input B bus, width determined by WIDTH_B parameter
|
|
.CE(CE), // 1-bit active high input clock enable
|
|
.CLK(CLK), // 1-bit positive edge clock input
|
|
.RST(RST) // 1-bit input active high reset
|
|
);
|
|
|
|
// End of MULT_MACRO_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
</Folder>
|
|
<Folder label="Simulation Constructs" treetype="folder">
|
|
<SubFolder label="Clock Stimulus" treetype="folder">
|
|
<SubFolder label="50% Duty Cycle" treetype="folder">
|
|
<Template label="Using forever" treetype="template">
|
|
// Note: CLK must be defined as a wire when using this method
|
|
|
|
parameter PERIOD = <value>;
|
|
|
|
initial begin
|
|
CLK = 1'b0;
|
|
#(PERIOD/2);
|
|
forever
|
|
#(PERIOD/2) CLK = ~CLK;
|
|
end
|
|
</Template>
|
|
<Template label="Using Always" treetype="template">
|
|
// Note: CLK must be defined as a reg when using this method
|
|
|
|
parameter PERIOD = <value>;
|
|
|
|
always begin
|
|
CLK = 1'b0;
|
|
#(PERIOD/2) CLK = 1'b1;
|
|
#(PERIOD/2);
|
|
end
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Differential, 50% Duty Cycle" treetype="folder">
|
|
<Template label="Using Always" treetype="template">
|
|
// Note: CLK_P and CLK_N must be defined as a reg when using this method
|
|
|
|
parameter PERIOD = <value>;
|
|
|
|
always begin
|
|
CLK_P = 1'b0;
|
|
CLK_N = 1'b1;
|
|
#(PERIOD/2) CLK_P = 1'b1;
|
|
CLK_N = 1'b0;
|
|
#(PERIOD/2);
|
|
end
|
|
</Template>
|
|
<Template label="Using forever" treetype="template">
|
|
// Note: CLK_P and CLK_N must be defined as a wire when using this method
|
|
|
|
parameter PERIOD = <value>;
|
|
|
|
initial begin
|
|
CLK_P = 1'b0;
|
|
CLK_N = 1'b1;
|
|
#(PERIOD/2);
|
|
forever
|
|
#(PERIOD/2) {CLK_P, CLK_N} = ~{CLK_P, CLK_N};
|
|
end
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Non-50% Duty Cycle" treetype="folder">
|
|
<Template label="Using forever" treetype="template">
|
|
// Note: CLK must be defined as a wire when using this method
|
|
|
|
parameter PERIOD = <value>;
|
|
parameter DUTY_CYCLE = <value_0.01_to_0.99>;
|
|
|
|
initial
|
|
forever begin
|
|
CLK = 1'b0;
|
|
#(PERIOD-(PERIOD*DUTY_CYCLE)) CLK = 1'b1;
|
|
#(PERIOD*DUTY_CYCLE);
|
|
end
|
|
</Template>
|
|
<Template label="Using Always" treetype="template">
|
|
// Note: CLK must be defined as a reg when using this method
|
|
|
|
parameter PERIOD = <value>;
|
|
parameter DUTY_CYCLE = <value_0.01_to_0.99>;
|
|
|
|
always begin
|
|
CLK = 1'b0;
|
|
#(PERIOD-(PERIOD*DUTY_CYCLE)) CLK = 1'b1;
|
|
#(PERIOD*DUTY_CYCLE);
|
|
end
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Differential, Non-50% Duty Cycle" treetype="folder">
|
|
<Template label="Using forever" treetype="template">
|
|
// Note: CLK_P and CLK_N must be defined as a wire when using this method
|
|
|
|
parameter PERIOD = <value>;
|
|
parameter DUTY_CYCLE = <value_0.01_to_0.99>;
|
|
|
|
initial
|
|
forever begin
|
|
CLK_P = 1'b0;
|
|
CLK_N = 1'b1;
|
|
#(PERIOD-(PERIOD*DUTY_CYCLE)) CLK_P = 1'b1;
|
|
CLK_N = 1'b0;
|
|
#(PERIOD*DUTY_CYCLE);
|
|
end
|
|
</Template>
|
|
<Template label="Using Always" treetype="template">
|
|
// Note: CLK_P and CLK_N must be defined as a reg when using this method
|
|
|
|
parameter PERIOD = <value>;
|
|
parameter DUTY_CYCLE = <value_0.01_to_0.99>;
|
|
|
|
always begin
|
|
CLK_P = 1'b0;
|
|
CLK_N = 1'b1;
|
|
#(PERIOD-(PERIOD*DUTY_CYCLE)) CLK_P = 1'b1;
|
|
CLK_N = 1'b0;
|
|
#(PERIOD*DUTY_CYCLE);
|
|
end
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Procedural Blocks" treetype="folder">
|
|
<Template label="Execute Once (Initial Specification)" treetype="template">
|
|
initial begin
|
|
// Wait for Global Reset to Complete
|
|
#100;
|
|
<statements>;
|
|
end
|
|
</Template>
|
|
<Template label="Repeated Execution (Always specification)" treetype="template">
|
|
always begin
|
|
<statements>;
|
|
end
|
|
</Template>
|
|
<Template label="Conditional Repeated Execution (Always specification)" treetype="template">
|
|
always @(<signals>) begin
|
|
<statements>;
|
|
end
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Loops" treetype="folder">
|
|
<Template label="Incrementing for Loop" treetype="template">
|
|
integer <var>;
|
|
|
|
for (<var> = <initial_value>; <var> <= <final_value>; <var>=<var>+1) begin
|
|
<statement>;
|
|
end
|
|
</Template>
|
|
<Template label="Decrementing for Loop" treetype="template">
|
|
integer <var>;
|
|
|
|
for (<var> = <initial_value>; <var> >= <final_value>; <var>=<var>-1) begin
|
|
<statement>;
|
|
end
|
|
</Template>
|
|
<Template label="forever Loop" treetype="template">
|
|
forever begin
|
|
<statement>;
|
|
end
|
|
</Template>
|
|
<Template label="Repeat Loop" treetype="template">
|
|
repeat (<value>) begin
|
|
<statements>;
|
|
end
|
|
</Template>
|
|
<Template label="Disable Loop" treetype="template">
|
|
disable <loop_identifier>;
|
|
</Template>
|
|
<Template label="While Loop" treetype="template">
|
|
while (<condition>) begin
|
|
<statement>;
|
|
end
|
|
</Template>
|
|
<Template label=" (Loops)" treetype="template">
|
|
// information for Verilog Looping Statements (i.e. while, repeat, forever, for, etc.)
|
|
// ===================================================================================
|
|
//
|
|
// There are several ways to create a looping statement within a verilog
|
|
// testbench. Each of these constructs must appear within an initial or
|
|
// always block and can be disabled if the block is labeled.
|
|
//
|
|
// Repeat - A repeat loop is generally the easiest construct if it is desired
|
|
// to perform an action a known, finite number of times and the loop
|
|
// variable is not needed for the function.
|
|
//
|
|
// Example: The forllowing example will apply random data to the
|
|
// DATA_IN signal 30 times at each clock signal.
|
|
|
|
initial begin
|
|
repeat (30) begin
|
|
@(posedge CLK);
|
|
#1 DATA_IN = $random;
|
|
end
|
|
end
|
|
|
|
// While - The while loop is a good way to create a conditional loop that will
|
|
// execute as long as a condition is met.
|
|
//
|
|
// Example: The forllowing example will read from a FIfor as long as the
|
|
// EMPTY flag is true.
|
|
|
|
initial begin
|
|
while (EMPTY==1'b0) begin
|
|
@(posedge CLK);
|
|
#1 read_fifor = 1'b1;
|
|
end
|
|
|
|
// for - The for loop is generally used when a finite loop is desired and it
|
|
// is necessary to key off the loop variable. Depending on how the for
|
|
// condition is created, an incrementing or decrementing loop can be created.
|
|
//
|
|
// Example: The forllowing will assign a 1'b0 to each bit in the 32 bit
|
|
// DATA signal at time zero. An incrementing for loop will be used.
|
|
|
|
parameter WIDTH=32;
|
|
reg [WIDTH-1:0] DATA;
|
|
integer i;
|
|
|
|
initial
|
|
for (i=0; i<WIDTH; i=i+1)
|
|
DATA[i] = 1'b0;
|
|
|
|
// forever - The forever loop is a construct generally used to create an infinite
|
|
// loop for simulation.
|
|
//
|
|
// Example: The forllowing will create a clock using a forever loop with
|
|
// a period of 10 ns and a 50% duty cycle.
|
|
|
|
`timescale 1ns/1ps
|
|
|
|
initial
|
|
forever begin
|
|
CLK = 1'b0;
|
|
#5 CLK = 1'b1;
|
|
#5;
|
|
end
|
|
|
|
// Disable - Any loop can be disabled by using the disable construct. In order
|
|
// to disable a loop, a loop identifier or label must be used on the
|
|
// loop to be disabled.
|
|
//
|
|
// Example: The forllowing will stop a clock created in a forever loop
|
|
// if a signal called stop_clock is 1'b1.
|
|
|
|
`timescale 1ns/1ps
|
|
|
|
initial
|
|
forever begin : clock_10ns
|
|
CLK = 1'b0;
|
|
#5 CLK = 1'b1;
|
|
#5;
|
|
end
|
|
|
|
always @(posedge stop_clock)
|
|
if (stop_clock)
|
|
disable clock_10ns;
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Signal Assignment" treetype="folder">
|
|
<Template label="force a value (force)" treetype="template">
|
|
force <wire_or_reg> = <value>;
|
|
</Template>
|
|
<Template label="Release a forced value (release)" treetype="template">
|
|
release <wire_or_reg>;
|
|
release <wire_or_reg>;
|
|
</Template>
|
|
<Template label="Assign a value (assign)" treetype="template">
|
|
assign <reg> = <value>;
|
|
</Template>
|
|
<Template label="Deassign a value (deassign)" treetype="template">
|
|
deassign <reg>;
|
|
</Template>
|
|
<SubFolder label="Initialize Values" treetype="folder">
|
|
<SubFolder label="Using initial" treetype="folder">
|
|
<Template label="1-bit Register" treetype="template">
|
|
initial begin
|
|
<reg> = 1'b0;
|
|
end
|
|
</Template>
|
|
<Template label="2-bit Register" treetype="template">
|
|
initial begin
|
|
<reg> = 2'b00;
|
|
end
|
|
</Template>
|
|
<Template label="3-bit Register" treetype="template">
|
|
initial begin
|
|
<reg> = 3'b000;
|
|
end
|
|
</Template>
|
|
<Template label="4-bit Register" treetype="template">
|
|
initial begin
|
|
<reg> = 4'h0;
|
|
end
|
|
</Template>
|
|
<Template label="8-bit Register" treetype="template">
|
|
initial begin
|
|
<reg> = 8'h00;
|
|
end
|
|
</Template>
|
|
<Template label="16-bit Register" treetype="template">
|
|
initial begin
|
|
<reg> = 16'h0000;
|
|
end
|
|
</Template>
|
|
<Template label="32-bit Register" treetype="template">
|
|
initial begin
|
|
<reg> = 32'h00000000;
|
|
end
|
|
</Template>
|
|
<Template label="64-bit Register" treetype="template">
|
|
initial begin
|
|
<reg> = 64'h0000000000000000;
|
|
end
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Using reg declaration" treetype="folder">
|
|
<Template label="1-bit Register" treetype="template">
|
|
reg <name> = 1'b0;
|
|
</Template>
|
|
<Template label="2-bit Register" treetype="template">
|
|
reg [1:0] <name> = 2'b00;
|
|
</Template>
|
|
<Template label="3-bit Register" treetype="template">
|
|
reg [2:0] <name> = 3'b000;
|
|
</Template>
|
|
<Template label="4-bit Register" treetype="template">
|
|
reg [3:0] <name> = 4'h0;
|
|
</Template>
|
|
<Template label="8-bit Register" treetype="template">
|
|
reg [7:0] <name> = 8'h00;
|
|
</Template>
|
|
<Template label="16-bit Register" treetype="template">
|
|
reg [15:0] <name> = 16'h0000;
|
|
</Template>
|
|
<Template label="32-bit Register" treetype="template">
|
|
reg [31:0] <name> = 32'h00000000;
|
|
reg [63:0] <name> = 64'h0000000000000000;
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Vcc/Gnd" treetype="folder">
|
|
<Template label="Vcc Rail" treetype="template">
|
|
supply1 <name>;
|
|
</Template>
|
|
<Template label="Ground Rail" treetype="template">
|
|
supply0 <name>;
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Delays" treetype="folder">
|
|
<Template label="Finite Delay" treetype="template">
|
|
#<delay_value>;
|
|
</Template>
|
|
<Template label="Wait for Positive Signal Transition" treetype="template">
|
|
@(posedge <signal>);
|
|
</Template>
|
|
<Template label="Wait for Negative Signal Transition" treetype="template">
|
|
@(negedge <signal>);
|
|
</Template>
|
|
<Template label="Wait for Any Signal Transition" treetype="template">
|
|
@(<signal>);
|
|
</Template>
|
|
<Template label="Wait for Signal Condition" treetype="template">
|
|
wait (<signal>==<value>);
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="System Tasks & Functions" treetype="folder">
|
|
<SubFolder label="Stop Simulation" treetype="folder">
|
|
<Template label="Pause Simulation ($stop)" treetype="template">
|
|
$stop;
|
|
</Template>
|
|
<Template label="Quit Simulation ($finish)" treetype="template">
|
|
$finish;
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Screen Output" treetype="folder">
|
|
<Template label="Info (Screen Output)" treetype="template">
|
|
// information of $display, $monitor, $write, and $strobe System Functions
|
|
// =======================================================================
|
|
//
|
|
// $display will display a string to the standard output (screen/console)
|
|
// of the simulator. Variables may be added to the string to indicate
|
|
// current time (as well as other system functions) and states of signals
|
|
// in the design. After the string is displayed, a carriage return is
|
|
// issued.
|
|
//
|
|
// $monitor will display a string to the standard output whenever a change
|
|
// in value is detected for one of the variables being displayed. After
|
|
// the string is displayed, a carriage return is issued.
|
|
//
|
|
// $write acts very similar to $display in that it can output a specified
|
|
// string to the standard out however it does not return a carriage return
|
|
// after performing this operation.
|
|
//
|
|
// $strobe is also similar to $display only waits for all simulation events
|
|
// in the queue to be executed before generating the message.
|
|
//
|
|
// When using these standard output commands, variables can be specified to
|
|
// the output in a variety of formats. Also, special escape characters can
|
|
// be used to specify special characters or formatting. These formats are
|
|
// listed below.
|
|
//
|
|
// Variables
|
|
// ---------
|
|
// %b .... Binary Value
|
|
// %h .... Hexadecimal Value
|
|
// %d .... Decimal Value
|
|
// %t .... Time
|
|
// %s .... String
|
|
// %c .... ASCII
|
|
// %f .... Real Value
|
|
// %e .... Exponential Value
|
|
// %o .... Octal Value
|
|
// %m .... Module Hierarchical Name
|
|
// %v .... Strength
|
|
//
|
|
// Escape Characters
|
|
// -----------------
|
|
// \t ........ Tab
|
|
// \n ........ Newline
|
|
// \\ ........ Backslash
|
|
// %% ........ Percent
|
|
// \" ........ Quote
|
|
// \<octal> .. ASCII representation
|
|
//
|
|
// $display and $strobe are general used within a conditional statement
|
|
// (i.e. if (error) $display) specified from an initial or always construct
|
|
// while the $monitor is generally specified from an initial statement without
|
|
// any other qualification. Display functions are for simulation purposes only
|
|
// and while very useful, should be used sparingly in order to increase the
|
|
// overall speed of simulation. It is very useful to use these constructs to
|
|
// indicate problems in the simulation however every time an output is written
|
|
// to the screen, a penalty of a longer simulation runtime is seen.
|
|
//
|
|
// Example of $display:
|
|
|
|
initial begin
|
|
#100000;
|
|
$display("Simulation Ended Normally at Time: %t", $realtime");
|
|
$stop;
|
|
end
|
|
|
|
// Example of $monitor:
|
|
|
|
initial
|
|
$monitor("time %t: out1=%d(decimal), out2=%h(hex), out3=%b(binary),
|
|
state=%s(string)", $realtime, out1, out2, out3, state);
|
|
|
|
// Example of $write:
|
|
|
|
always @(posedge check)
|
|
$write(".");
|
|
|
|
// Example of $strobe:
|
|
|
|
always @(out1)
|
|
if (out1 != correct_out1)
|
|
$strobe("Error at time %t: out1 is %h and should be %h",
|
|
$realtime, out1, correct_out1);
|
|
|
|
// Example of using a $monitor to display the state of a state-machine to the screen:
|
|
|
|
reg[8*22:0] ascii_state;
|
|
|
|
initial
|
|
$monitor("Current State is: %s", ascii_state);
|
|
|
|
always @(UUT.top.state_reg)
|
|
case (UUT.top.state_reg)
|
|
2'b00 : ascii_state = "Reset";
|
|
2'b01 : ascii_state = "Send";
|
|
2'b10 : ascii_state = "Poll";
|
|
2'b11 : ascii_state = "Receive";
|
|
default: ascii_state = "ERROR: Undefined State";
|
|
endcase
|
|
</Template>
|
|
<Template label="Display text ($display)" treetype="template">
|
|
$display("<string_and/or_variables>", <functions_or_signals>);
|
|
</Template>
|
|
<Template label="Monitor Signals ($monitor)" treetype="template">
|
|
$monitor("<string_and/or_variables>", <functions or signals>);
|
|
</Template>
|
|
<Template label="Write text w/o CRs ($write)" treetype="template">
|
|
$write ("<string_and/or_variables>", <functions_or_signals>);
|
|
</Template>
|
|
<Template label="Strobe text w/ delayed output ($strobe)" treetype="template">
|
|
$strobe ("<string_and/or_variables>", <functions_or_signals>);
|
|
</Template>
|
|
</SubFolder>
|
|
<Template label="Random Number Generation" treetype="template">
|
|
<reg> = $random(<seed>);
|
|
</Template>
|
|
<SubFolder label="Simulation Time" treetype="folder">
|
|
<Template label="Info (Simulation Time)" treetype="template">
|
|
// information on the system tasks $time, $stime, $realtime, and $timeformat
|
|
// =========================================================================
|
|
//
|
|
// $time is a system function in which returns the current simulation time
|
|
// as a 64-bit integer.
|
|
//
|
|
// $stime is a system function in which returns the lower 32-bits of the
|
|
// current simulation time.
|
|
//
|
|
// $realtime is a system function that returns the current simulation time
|
|
// as a real number.
|
|
//
|
|
// Generally, these system time functions are using within screen
|
|
// ($monitor and $display) and file output ($fwrite and $fmonitor) commands
|
|
// to specify within the message the simulation time at which the message is
|
|
// displayed or written.
|
|
//
|
|
//
|
|
// $timeformat is a system call which specifies the format in which the $time,
|
|
// $stime and $realtime should be displayed when used with the %t format
|
|
// variable in a display or write call. It is recommended to specify this
|
|
// within the testbench when using the %t variable to make the time value more
|
|
// readable. The $timeformat must be specified within an initial declaration.
|
|
// The format of $timeformat is the forllowing:
|
|
|
|
initial
|
|
$timeformat (<unit>, <precision>, <suffix_string>, <min_field_width>);
|
|
|
|
//
|
|
// Example:
|
|
//
|
|
// This specifies the output to be displayed in nano-seconds, a precision
|
|
// down to pico seconds, to append the string " ns" after the time and
|
|
// to allow for 13 numbers to be displayed to show this value.
|
|
initial
|
|
$timeformat (-9, 3, " ns", 13);
|
|
|
|
// This will display the system time in the format specified above after
|
|
// the string "Time=" as well as display the value of DATA_OUT every
|
|
// time DATA_OUT changes value.
|
|
initial
|
|
$monitor("Time=%t : DATA_OUT=%b", $realtime, DATA_OUT);
|
|
|
|
</Template>
|
|
<SubFolder label="format // ($timeformat)" treetype="folder">
|
|
<Template label="Nano-second Specification" treetype="template">
|
|
initial
|
|
$timeformat (-9, 3, " ns", 13);
|
|
</Template>
|
|
<Template label="Pico-second Specification" treetype="template">
|
|
initial
|
|
$timeformat (-12, 1, " ps", 13);
|
|
</Template>
|
|
<Template label="Micro-second Specification" treetype="template">
|
|
initial
|
|
$timeformat (-6, 6, " us", 10);
|
|
</Template>
|
|
<Template label="Mili-second Specification" treetype="template">
|
|
initial
|
|
$timeformat (-3, 0, " ms", 8);
|
|
</Template>
|
|
<Template label="Second Specification" treetype="template">
|
|
initial
|
|
$timeformat (0, 0, " sec", 6);
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="File I/O" treetype="folder">
|
|
<SubFolder label="Read Memory File" treetype="folder">
|
|
<Template label="Info ($readmemb/h)" treetype="template">
|
|
// information on the $readmemb and $readmemh system functions
|
|
// ===========================================================
|
|
//
|
|
// $readmemb is a system function which will read binary data from a
|
|
// specified file and place it in an array. The syntax is the forllowing:
|
|
// $readmemb ("<file_name>", <reg_name>, <start_address>, <end_address>);
|
|
// where the <file_name> is the name and location of the file containing
|
|
// the binary data, the <reg_name> is a 2-D register array in which the
|
|
// memory data is stored, and the last two optional comma separated numbers
|
|
// specify the beginning and ending address of the data. The data file
|
|
// may only contain binary data, white spaces and comments. This function
|
|
// must be executed within an initial block.
|
|
//
|
|
// $readmemh is the same as $readmemb with the exception that it
|
|
// inputs hex data as the read values.
|
|
//
|
|
// In the past, these functions could only be used for simulation
|
|
// purposes however synthesis tools now has the ability to initialize RAM
|
|
// and ROM arrays using this construct.
|
|
//
|
|
// Example of reading binary data from a file:
|
|
|
|
reg [31:0] rom_data[1023:0];
|
|
|
|
initial
|
|
$readmemb("../data/mem_file.dat", rom_data, 0, 7);
|
|
|
|
// The initialization file may only contain white spaces, address
|
|
// labels (denoted by @<address>), comments and the actual binary
|
|
// or hexadecimal data.
|
|
// The forllowing is a small example of a binary memory file data:
|
|
|
|
// This is a comment
|
|
|
|
1111000011110000 // This specifies these 16-bits to the first address
|
|
1010_0101_1010_0101 // This is for the second address with underscores
|
|
// to make this more readable
|
|
<more entries like above to fill up the array>
|
|
|
|
// Optionally, we can change addresses
|
|
@025 // Now at address 025
|
|
11111111_00000000
|
|
|
|
// Addresses can also be specified in-line
|
|
@035 00000000_11111111
|
|
|
|
// It is highly suggested to fill all memory contents with a known value
|
|
// when initializing memories.
|
|
</Template>
|
|
<Template label="Binary Data ($readmemb)" treetype="template">
|
|
reg [<memory_width>] <reg_name> [<memory_depth>];
|
|
|
|
initial
|
|
$readmemb ("<file_name>", <reg_name>, <start_address>, <end_address>);
|
|
</Template>
|
|
<Template label="Hex Data ($readmemh)" treetype="template">
|
|
reg [<memory_width>] <reg_name> [<memory_depth>];
|
|
|
|
initial
|
|
$readmemh ("<file_name>", <reg_name>, <start_address>, <end_address>);
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Read/write to a File" treetype="folder">
|
|
<Template label="Info (File I/O)" treetype="template">
|
|
// information on the $forpen, $fdisplay, $fstrobe, $fwrite, $ftell,
|
|
// $feof, $ferror, $fgetc, $fgets, and $fclose system functions
|
|
// ================================================================
|
|
//
|
|
// Opening Command
|
|
// ---------------
|
|
// $forpen is used to open a file for reading, writing and/or appending.
|
|
// This operation must precede any of the reading or writing commands
|
|
// specified in this document. When using the $forpen, you must specify
|
|
// the file name and file mode (read, write, etc.). The syntax looks like
|
|
// the forllowing: $forpen("<file_name>", "<file_mode>")
|
|
// Upon opening the file a handle number is issued for the file and must
|
|
// be used to reference the file in subsequent commands. Generally, this
|
|
// number should be assigned to a declared integer.
|
|
//
|
|
// The file mode can be one of the forllowing:
|
|
//
|
|
// "r" ...... Open ASCII file for reading
|
|
// "rb" ..... Open Binary file for reading
|
|
// "w" ...... Open ASCII file for writing (delete if exists)
|
|
// "wb" ..... Open Binary file for writing (delete if exists)
|
|
// "a" ...... Open ASCII file for writing (append to end of file)
|
|
// "ab" ..... Open Binary file for writing (append to end of file)
|
|
// "r+" ..... Open ASCII file for reading and writing
|
|
//
|
|
//
|
|
// Writing Commands
|
|
// ----------------
|
|
// $fdisplay will write formatted text to a specified file. Specific text,
|
|
// system functions/tasks and signal values can be output using this
|
|
// function. The file handle assigned by the $forpen function must be
|
|
// specified to indicate the destination file for the text. The syntax looks
|
|
// as forllows: $fdisplay(<file_desc>, "<string>", variables);
|
|
//
|
|
// $fwrite acts very similar to $fdisplay in that it can write a specified
|
|
// string to a file however it does not specify a carriage return after
|
|
// performing this operation.
|
|
//
|
|
// $fstrobe is also similar to $fdisplay only waits for all simulation events
|
|
// in the queue to be executed before writing the message.
|
|
//
|
|
// $fmonitor will write a string to the specified file whenever a change
|
|
// in value is detected for one of the variables being written. After
|
|
// the string is written, a carriage return is issued.
|
|
//
|
|
// When using these write commands ($fdisplay, $fwrite, $fstrobe, $fmonitor),
|
|
// variables can be specified to the output in a variety of formats. Also,
|
|
// special escape characters can be used to specify special characters or
|
|
// formatting. These formats are listed below.
|
|
//
|
|
// Variables
|
|
// ---------
|
|
// %b .... Binary Value
|
|
// %h .... Hexadecimal Value
|
|
// %d .... Decimal Value
|
|
// %t .... Time
|
|
// %s .... String
|
|
// %c .... ASCII
|
|
// %f .... Real Value
|
|
// %e .... Exponential Value
|
|
// %o .... Octal Value
|
|
// %m .... Module Hierarchical Name
|
|
// %v .... Strength
|
|
//
|
|
// Escape Characters
|
|
// -----------------
|
|
// \t ........ Tab
|
|
// \n ........ Newline
|
|
// \\ ........ Backslash
|
|
// %% ........ Percent
|
|
// \" ........ Quote
|
|
// \<octal> .. ASCII representation
|
|
//
|
|
//
|
|
// Reading Commands
|
|
// ----------------
|
|
// $fgets will read an entire line of text from a file and store it as a
|
|
// string. The format for $fgets is: $fgets(<string_reg>, <file_desc>);
|
|
// $fgets returns an integer value either indicating the number of characters
|
|
// read or a zero indication an error during the read attempt. The <string_reg>
|
|
// should be defined a width equal to the number of characters on the longest
|
|
// line multiplied by 8.
|
|
//
|
|
// $fgetc will read a character from a file and return it as an 8-bit string.
|
|
// If EOF is encountered, a value of -1 is written.
|
|
//
|
|
// $fscanf will read a line from a file and store it in a specified form. The
|
|
// format for the $fsacnf is: $fscanf(<file_desc>, <format>, <destination_regs>)
|
|
// where the format is specified similar to how it is specified in the read
|
|
// command above and the <destination_regs> is where the read data is stored.
|
|
// $fscanf will return an integer value indicating the number of matched
|
|
// formatted data read. If an error occurs during the read, this number will
|
|
// be zero.
|
|
//
|
|
//
|
|
// Special Functions
|
|
// -----------------
|
|
// $ferror tests and reports last error encountered during a file open, read
|
|
// or write. The written string can be up to 80 characters (640 bits) wide.
|
|
//
|
|
// $fseek will reposition the pointer within the file to the specified position.
|
|
// The format for the $fseek command is:
|
|
// $fseek(<file_desc>, <offset_value>, <operation_number>) where the operation
|
|
// number is one of three values:
|
|
// 0 - set position using the beginning of file as the reference point
|
|
// 1 - set position using the current location of the pointer as reference
|
|
// 2 - set position using the EOF as reference
|
|
// $fseek will return a zero if the command was successful and a -1 if not.
|
|
//
|
|
// $ftell specifies the position of the pointer within the file by outputting an
|
|
// integer value indicating the number of offset bytes from the beginning of the
|
|
// file.
|
|
//
|
|
// $fflush writes any buffered output to the specified file.
|
|
//
|
|
//
|
|
// Close File
|
|
// ----------
|
|
// $fclose closes a previous opened file. The format is $fclose(<file_desc>);
|
|
//
|
|
// In general, you may wish to limit the amount and occurrences of reading and
|
|
// writing to a file during simulation as it may have a negative impact on
|
|
// overall simulation runtime. File access can be a slow process and if done
|
|
// often can weigh down simulation quite a bit.
|
|
//
|
|
//
|
|
// Example of writing monitored signals:
|
|
// -------------------------------------
|
|
|
|
// Define file handle integer
|
|
integer outfile;
|
|
|
|
initial begin
|
|
// Open file output.dat for writing
|
|
outfile = $forpen("output.dat", "w");
|
|
|
|
// Check if file was properly opened and if not, produce error and exit
|
|
if (outfile == 0) begin
|
|
$display("Error: File, output.dat could not be opened.\nExiting Simulation.");
|
|
$finish;
|
|
end
|
|
|
|
// Write monitor data to a file
|
|
$fmonitor (outfile, "Time: %t\t Data_out = %h", $realtime, Data_out);
|
|
|
|
// Wait for 1 ms and end monitoring
|
|
#1000000;
|
|
|
|
// Close file to end monitoring
|
|
$fclose(outfile);
|
|
end
|
|
|
|
// Example of reading a file using $fscanf:
|
|
// ----------------------------------------
|
|
|
|
real number;
|
|
|
|
// Define integers for file handling
|
|
integer number_file;
|
|
integer i=1;
|
|
|
|
initial begin
|
|
// Open file numbers.txt for reading
|
|
number_file = $forpen("numbers.txt", "r");
|
|
// Produce error and exit if file could not be opened
|
|
if (number_file == 0) begin
|
|
$display("Error: Failed to open file, numbers.txt\nExiting Simulation.");
|
|
$finish;
|
|
end
|
|
// Loop while data is being read from file
|
|
// (i will be -1 when end of file or 0 for blank line)
|
|
while (i>0) begin
|
|
$display("i = %d", i);
|
|
i=$fscanf(number_file, "%f", number);
|
|
$display("Number read from file is %f", number);
|
|
@(posedge CLK);
|
|
end
|
|
// Close out file when finished reading
|
|
$fclose(number_file);
|
|
#100;
|
|
$display("Simulation ended normally");
|
|
$stop;
|
|
end
|
|
</Template>
|
|
<SubFolder label="Functions" treetype="folder">
|
|
<Template label="Test Error ($ferror)" treetype="template">
|
|
<640-bit_reg> = $ferror(<file_desc>);
|
|
</Template>
|
|
<Template label="Find the File Position ($ftell)" treetype="template">
|
|
<reg> = $ftell(<file_desc>);
|
|
</Template>
|
|
<Template label="Change the File Position ($fseek)" treetype="template">
|
|
<integer> = $fseek(<file_desc>, <offset_value>, <operation_number>);
|
|
</Template>
|
|
<Template label="Flush Buffer ($fflush)" treetype="template">
|
|
$fflush(<file_desc>);
|
|
</Template>
|
|
<Template label="Open a File ($forpen)" treetype="template">
|
|
integer <file_desc>;
|
|
<file_desc> = $forpen("<file_name>", "<file_mode>");
|
|
</Template>
|
|
<Template label="Close a File ($fclose)" treetype="template">
|
|
$fclose(<file_desc>);
|
|
</Template>
|
|
<Template label="Display Text to a File ($fdisplay)" treetype="template">
|
|
$fdisplay(<file_desc>, "<string>", variables);
|
|
</Template>
|
|
<Template label="Write Text to a File ($fwrite)" treetype="template">
|
|
$fwrite(<file_desc>, "<string>", variables);
|
|
</Template>
|
|
<Template label="Strobe Text to a File ($fstrobe)" treetype="template">
|
|
$fstrobe(<file_desc>, "<string>", variables);
|
|
</Template>
|
|
<Template label="Write Monitored Text to a File ($fmonitor)" treetype="template">
|
|
$fmonitor(<file_desc>, "<string>", variables);
|
|
</Template>
|
|
<Template label="Read a character from a file ($fgetc)" treetype="template">
|
|
reg [7:0] <8-bit_reg>;
|
|
<8-bit_reg> = $fgetc(<file_desc>);
|
|
</Template>
|
|
<Template label="Read a line from a file ($fgets)" treetype="template">
|
|
integer <integer>;
|
|
reg [8*<#_of_chars>:0] <string_reg>;
|
|
<integer> = $fgets(<string_reg>, <file_desc>);
|
|
</Template>
|
|
<Template label="Read a formatted line from a file ($fscanf)" treetype="template">
|
|
integer <integer>;
|
|
<integer> = $fscanf(<file_desc>, "<format>", <destination_regs>);
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Signed / Unsigned" treetype="folder">
|
|
<Template label=" Convert to a Signed Value" treetype="template">
|
|
$signed(<signal>);
|
|
</Template>
|
|
<Template label=" Convert to an Unsigned Value" treetype="template">
|
|
$unsigned(<signal>);
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Signal, Constant & Variable Declarations" treetype="folder">
|
|
<Template label="32-bit Integer" treetype="template">
|
|
integer <name>;
|
|
</Template>
|
|
<Template label="64-bit floating point (real)" treetype="template">
|
|
real <name>;
|
|
</Template>
|
|
<Template label="64-bit floating point (time)" treetype="template">
|
|
time <name>;
|
|
</Template>
|
|
<SubFolder label="Parameter" treetype="folder">
|
|
<SubFolder label="Local Parameter" treetype="folder">
|
|
<Template label="Un-typed, unranged local parameter" treetype="template">
|
|
localparam <name> = <value>;
|
|
</Template>
|
|
<Template label="Un-typed, ranged local parameter" treetype="template">
|
|
localparam [upper:lower] <name> = <value>;
|
|
</Template>
|
|
<Template label="Signed, unranged local parameter" treetype="template">
|
|
localparam signed <name> = <value>;
|
|
</Template>
|
|
<Template label="Signed, ranged local parameter" treetype="template">
|
|
localparam signed [upper:lower] <name> = <value>;
|
|
</Template>
|
|
<Template label="Integer local parameter" treetype="template">
|
|
localparam integer <name> = <value>;
|
|
</Template>
|
|
<Template label="Real local parameter" treetype="template">
|
|
localparam real <name> = <value>;
|
|
</Template>
|
|
<Template label="Realtime local parameter" treetype="template">
|
|
localparam realtime <name> = <value>;
|
|
</Template>
|
|
<Template label="Time local parameter" treetype="template">
|
|
localparam time <name> = <value>;
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Parameter" treetype="folder">
|
|
<Template label="Un-typed, unranged parameter" treetype="template">
|
|
parameter <name> = <value>;
|
|
</Template>
|
|
<Template label="Un-typed, ranged parameter" treetype="template">
|
|
parameter [upper:lower] <name> = <value>;
|
|
</Template>
|
|
<Template label="Signed, unranged parameter" treetype="template">
|
|
parameter signed <name> = <value>;
|
|
</Template>
|
|
<Template label="Signed, ranged parameter" treetype="template">
|
|
parameter signed [upper:lower] <name> = <value>;
|
|
</Template>
|
|
<Template label="Integer parameter" treetype="template">
|
|
parameter integer <name> = <value>;
|
|
</Template>
|
|
<Template label="Real parameter" treetype="template">
|
|
parameter real <name> = <value>;
|
|
</Template>
|
|
<Template label="Realtime parameter" treetype="template">
|
|
parameter realtime <name> = <value>;
|
|
</Template>
|
|
<Template label="Time parameter" treetype="template">
|
|
parameter time <name> = <value>;
|
|
</Template>
|
|
</SubFolder>
|
|
<Template label="Info (Parameter)" treetype="template">
|
|
// information on the Verilog Parameter, Local Parameter,
|
|
// Defparam and Named Parameter Value Assignment
|
|
// =======================================================
|
|
//
|
|
// Parameters are a method within Verilog in order to define constants
|
|
// within the code. They are very useful in order to define bus widths,
|
|
// memory depths, state-machine assignments, clock periods and other useful
|
|
// constants used throughout the design and testbench. Parameters can bring
|
|
// more meaning and documentation to the code or can be used to make the
|
|
// code more parameterizable and thus help enable re-use or help adjust to
|
|
// late changes in the design. There are two main types of parameters, the
|
|
// parameter and local parameter. A local parameter acts the same as a
|
|
// parameter however its contents cannot be modified via a defparam or a
|
|
// named parameter value assignment in the instantiation. A defparam allows
|
|
// the reassignment to the value of a parameter from a different level of
|
|
// hierarchy in the testbench or design. A named parameter value assignment
|
|
// allows a respecification of the parameter value within the instance
|
|
// declaration of the instantiation of the component. Both local parameters
|
|
// and parameters can be sized to a specified number of bits and/or can be typed
|
|
// to be either a signed value, an integer, a real number, a time (64-bit
|
|
// precision) or a realtime (double-precision floating point) value.
|
|
|
|
// Example declaring a parameter and local parameter
|
|
|
|
// Define pi as a local real number parameter since I do not want to ever change this
|
|
|
|
localparam real pi = 3.14;
|
|
|
|
// Define BUS_WIDTH as a parameter with a default value of 8
|
|
|
|
parameter BUS_WIDTH = 8;
|
|
|
|
// Use this parameter to define the width of a declared register
|
|
|
|
reg [BUS_WIDTH-1:0] my_reg;
|
|
|
|
// Use a defparam from my testbench to change BUS_WIDTH to 16 for the instantiated
|
|
// design instance UUT
|
|
|
|
defparam UUT.BUS_WIDTH = 16;
|
|
|
|
// Alternatively to the defparam, I could have done this using the named parameter value assignment when I instantiate UUT
|
|
|
|
my_design #(
|
|
.BUS_WIDTH(16)
|
|
) UUT (
|
|
.A(A),
|
|
.B(B),
|
|
.C(C)
|
|
);
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Wire" treetype="folder">
|
|
<SubFolder label="Wire Signal" treetype="folder">
|
|
<Template label="1-bit" treetype="template">
|
|
wire <name>;
|
|
</Template>
|
|
<Template label="2-bit" treetype="template">
|
|
wire [1:0] <name>;
|
|
</Template>
|
|
<Template label="3-bit" treetype="template">
|
|
wire [2:0] <name>;
|
|
</Template>
|
|
<Template label="4-bit" treetype="template">
|
|
wire [3:0] <name>;
|
|
</Template>
|
|
<Template label="8-bit" treetype="template">
|
|
wire [7:0] <name>;
|
|
</Template>
|
|
<Template label="16-bit" treetype="template">
|
|
wire [15:0] <name>;
|
|
</Template>
|
|
<Template label="32-bit" treetype="template">
|
|
wire [31:0] <name>;
|
|
</Template>
|
|
<Template label="64-bit" treetype="template">
|
|
wire [63:0] <name>;
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Signed Wire" treetype="folder">
|
|
<Template label="8-bit" treetype="template">
|
|
wire signed [7:0] <name>;
|
|
</Template>
|
|
<Template label="9-bit" treetype="template">
|
|
wire signed [8:0] <name>;
|
|
</Template>
|
|
<Template label="16-bit" treetype="template">
|
|
wire signed [15:0] <name>;
|
|
</Template>
|
|
<Template label="18-bit" treetype="template">
|
|
wire signed [17:0] <name>;
|
|
</Template>
|
|
<Template label="32-bit" treetype="template">
|
|
wire signed [31:0] <name>;
|
|
</Template>
|
|
<Template label="64-bit" treetype="template">
|
|
wire signed [63:0] <name>;
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Wire w/ Pullup" treetype="folder">
|
|
<Template label="1-bit" treetype="template">
|
|
tri1 <name>;
|
|
</Template>
|
|
<Template label="2-bit" treetype="template">
|
|
tri1 [1:0] <name>;
|
|
</Template>
|
|
<Template label="3-bit" treetype="template">
|
|
tri1 [2:0] <name>;
|
|
</Template>
|
|
<Template label="4-bit" treetype="template">
|
|
tri1 [3:0] <name>;
|
|
</Template>
|
|
<Template label="8-bit" treetype="template">
|
|
tri1 [7:0] <name>;
|
|
</Template>
|
|
<Template label="16-bit" treetype="template">
|
|
tri1 [15:0] <name>;
|
|
</Template>
|
|
<Template label="32-bit" treetype="template">
|
|
tri1 [31:0] <name>;
|
|
</Template>
|
|
<Template label="64-bit" treetype="template">
|
|
tri1 [63:0] <name>;
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Register" treetype="folder">
|
|
<SubFolder label="Uninitialized" treetype="folder">
|
|
<SubFolder label="Reg" treetype="folder">
|
|
<Template label="1-bit" treetype="template">
|
|
reg <name>;
|
|
</Template>
|
|
<Template label="2-bit" treetype="template">
|
|
reg [1:0] <name>;
|
|
</Template>
|
|
<Template label="3-bit" treetype="template">
|
|
reg [2:0] <name>;
|
|
</Template>
|
|
<Template label="4-bit" treetype="template">
|
|
reg [3:0] <name>;
|
|
</Template>
|
|
<Template label="8-bit" treetype="template">
|
|
reg [7:0] <name>;
|
|
</Template>
|
|
<Template label="16-bit" treetype="template">
|
|
reg [15:0] <name>;
|
|
</Template>
|
|
<Template label="32-bit" treetype="template">
|
|
reg [31:0] <name>;
|
|
</Template>
|
|
<Template label="64-bit" treetype="template">
|
|
reg [63:0] <name>;
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Signed Reg" treetype="folder">
|
|
<Template label="8-bit" treetype="template">
|
|
reg signed [7:0] <name>;
|
|
</Template>
|
|
<Template label="9-bit" treetype="template">
|
|
reg signed [8:0] <name>;
|
|
</Template>
|
|
<Template label="16-bit" treetype="template">
|
|
reg signed [15:0] <name>;
|
|
</Template>
|
|
<Template label="18-bit" treetype="template">
|
|
reg signed [17:0] <name>;
|
|
</Template>
|
|
<Template label="32-bit" treetype="template">
|
|
reg signed [31:0] <name>;
|
|
</Template>
|
|
<Template label="64-bit" treetype="template">
|
|
reg signed [63:0] <name>;
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Keeper Reg" treetype="folder">
|
|
<Template label="1-bit" treetype="template">
|
|
// Stores last value when 3-stated
|
|
trireg <name>;
|
|
</Template>
|
|
<Template label="2-bit" treetype="template">
|
|
// Stores last value when 3-stated
|
|
trireg [1:0] <name>;
|
|
</Template>
|
|
<Template label="3-bit" treetype="template">
|
|
// Stores last value when 3-stated
|
|
trireg [2:0] <name>;
|
|
</Template>
|
|
<Template label="4-bit" treetype="template">
|
|
// Stores last value when 3-stated
|
|
trireg [3:0] <name>;
|
|
</Template>
|
|
<Template label="8-bit" treetype="template">
|
|
// Stores last value when 3-stated
|
|
trireg [7:0] <name>;
|
|
</Template>
|
|
<Template label="16-bit" treetype="template">
|
|
// Stores last value when 3-stated
|
|
trireg [15:0] <name>;
|
|
</Template>
|
|
<Template label="32-bit" treetype="template">
|
|
// Stores last value when 3-stated
|
|
trireg [31:0] <name>;
|
|
</Template>
|
|
<Template label="64-bit" treetype="template">
|
|
// Stores last value when 3-stated
|
|
trireg [63:0] <name>;
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="2-dimensional" treetype="folder">
|
|
<Template label="16 x 1" treetype="template">
|
|
reg <name> [15:0];
|
|
</Template>
|
|
<Template label="32 x 1" treetype="template">
|
|
reg <name> [31:0];
|
|
reg <name> [31:0];
|
|
</Template>
|
|
<Template label="16k x 1" treetype="template">
|
|
reg <name> [16383:0];
|
|
</Template>
|
|
<Template label="8k x 2" treetype="template">
|
|
reg [1:0] <name> [8191:0];
|
|
</Template>
|
|
<Template label="4k x 4" treetype="template">
|
|
reg [3:0] <name> [4095:0];
|
|
</Template>
|
|
<Template label="2k x 9" treetype="template">
|
|
reg [8:0] <name> [2047:0];
|
|
</Template>
|
|
<Template label="1k x 18" treetype="template">
|
|
reg [17:0] <name> [1023:0];
|
|
</Template>
|
|
<Template label="512 x 36" treetype="template">
|
|
reg [35:0] <name> [511:0];
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Initialized" treetype="folder">
|
|
<SubFolder label="Reg" treetype="folder">
|
|
<Template label="1-bit" treetype="template">
|
|
reg <name> = 1'b0;
|
|
</Template>
|
|
<Template label="2-bit" treetype="template">
|
|
reg [1:0] <name> = 2'b00;
|
|
</Template>
|
|
<Template label="3-bit" treetype="template">
|
|
reg [2:0] <name> = 3'b000;
|
|
</Template>
|
|
<Template label="4-bit" treetype="template">
|
|
reg [3:0] <name> = 4'h0;
|
|
</Template>
|
|
<Template label="8-bit" treetype="template">
|
|
reg [7:0] <name> = 8'h00;
|
|
</Template>
|
|
<Template label="16-bit" treetype="template">
|
|
reg [15:0] <name> = 16'h0000;
|
|
</Template>
|
|
<Template label="32-bit" treetype="template">
|
|
reg [31:0] <name> = 32'h00000000;
|
|
</Template>
|
|
<Template label="64-bit" treetype="template">
|
|
reg [63:0] <name> = 64'h0000000000000000;
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Signed Reg" treetype="folder">
|
|
<Template label="8-bit" treetype="template">
|
|
reg signed [7:0] <name> = 8'sh00;
|
|
</Template>
|
|
<Template label="9-bit" treetype="template">
|
|
reg signed [8:0] <name> = 9'sh000;
|
|
</Template>
|
|
<Template label="16-bit" treetype="template">
|
|
reg signed [15:0] <name> = 16'sh0000;
|
|
</Template>
|
|
<Template label="18-bit" treetype="template">
|
|
reg signed [17:0] <name> = 18'sh00000;
|
|
</Template>
|
|
<Template label="32-bit" treetype="template">
|
|
reg signed [31:0] <name> = 32'sh00000000;
|
|
</Template>
|
|
<Template label="64-bit" treetype="template">
|
|
reg signed [63:0] <name> = 64'sh0000000000000000;
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Keeper Reg" treetype="folder">
|
|
<Template label="1-bit" treetype="template">
|
|
// Stores last value when 3-stated
|
|
trireg <name> = 1'b0;
|
|
</Template>
|
|
<Template label="2-bit" treetype="template">
|
|
// Stores last value when 3-stated
|
|
trireg [1:0] <name> = 2'b00;
|
|
</Template>
|
|
<Template label="3-bit" treetype="template">
|
|
// Stores last value when 3-stated
|
|
trireg [2:0] <name> = 3'b000;
|
|
</Template>
|
|
<Template label="4-bit" treetype="template">
|
|
// Stores last value when 3-stated
|
|
trireg [3:0] <name> = 4'h0;
|
|
</Template>
|
|
<Template label="8-bit" treetype="template">
|
|
// Stores last value when 3-stated
|
|
trireg [7:0] <name> = 8'h00;
|
|
</Template>
|
|
<Template label="16-bit" treetype="template">
|
|
// Stores last value when 3-stated
|
|
trireg [15:0] <name> = 16'h0000;
|
|
</Template>
|
|
<Template label="32-bit" treetype="template">
|
|
// Stores last value when 3-stated
|
|
trireg [31:0] <name> = 32'h00000000;
|
|
</Template>
|
|
<Template label="64-bit" treetype="template">
|
|
// Stores last value when 3-stated
|
|
trireg [63:0] <name> = 64'h0000000000000000;
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Configuration" treetype="folder">
|
|
<Template label="Info (Configuration)" treetype="template">
|
|
// The Verilog-2001 Configuration Statement
|
|
// ========================================
|
|
//
|
|
// Verilog-2001 adds a new construct, the configuration or config statement,
|
|
// to the Verilog language to allow the modification of library binding rules.
|
|
// In general, it is still suggested to use the simulator to specify the library
|
|
// binding however at times more specific control is needed and this construct
|
|
// allows very specific binding rules for libraries. This is generally used
|
|
// for simulation where different models (i.e. behavioral, rtl or gate-level) can
|
|
// be used and inter-changed during simulation. for instance, a config can be
|
|
// used with the KEEP_HIERARCHY=TRUE and the MHF (Multiple Hierarchical Netlists)
|
|
// feature in the Xilinx tools to allow for a true mixed gate-level timing
|
|
// and behavioral/RTL simulation so that you can have speed in the parts of
|
|
// the simulation that is not currently being verified for gate-level function
|
|
// and/or timing and full timing gate-level netlists for the parts that are
|
|
// being verified for timing and end function.
|
|
//
|
|
// Example: The forllowing will change the default library binding rules for
|
|
// a design named ethernet_top located in the work library so that
|
|
// the library named gate_lib is used first and if not forund there,
|
|
// rtl_lib is used. The configuration is name mixed_gate_sim
|
|
|
|
config mixed_gate_sim;
|
|
design work.ethernet_top
|
|
default liblist gate_lib rtl_lib;
|
|
endconfig;
|
|
|
|
// Example: The forllowing will change the default library binding rules for
|
|
// any instantiation of a module named sram512 in the module named
|
|
// ethernet_top located in the work library so that the library named
|
|
// sim_lib is used for that model
|
|
|
|
config mixed_gate_sim;
|
|
design work.ethernet_top
|
|
default liblist gate_lib rtl_lib;
|
|
cell sram512 use sim_lib.sram512;
|
|
endconfig;
|
|
|
|
// Example: The forllowing will change the default library binding rules for
|
|
// the instance named sdram_ctrl_inst in the module named
|
|
// custom_cpu located in the work library so that the library named
|
|
// dave_lib is used for that model
|
|
|
|
config mixed_gate_sim;
|
|
design work.custom_cpu
|
|
default liblist gate_lib rtl_lib;
|
|
instance custom_cpu_top.sdram_ctrl_inst liblist dave_lib;
|
|
endconfig;
|
|
</Template>
|
|
<Template label="Default Library Clause" treetype="template">
|
|
// The forllowing overrides the default library search order
|
|
config <config_name>;
|
|
design <lib_name>.<design_name>
|
|
default liblist <library_1> <library_2>;
|
|
endconfig;
|
|
</Template>
|
|
<Template label="Cell Library Clause" treetype="template">
|
|
// The forllowing will specify which library to bind to a sub-module (cell) within the design
|
|
config <config_name>;
|
|
design <lib_name>.<design_name>
|
|
default liblist <new_library_1> <library_2>;
|
|
cell <sub-module_name> use <new_library>.<new_module_name>;
|
|
endconfig;
|
|
</Template>
|
|
<Template label="Instance Library Clause" treetype="template">
|
|
// The forllowing will specify which library to bind to an instance within the design
|
|
config <config_name>;
|
|
design <lib_name>.<design_name>
|
|
default liblist <new_library_1> <library_2>;
|
|
instance <instance_name> liblist <new_library>;
|
|
endconfig;
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Mnemonics" treetype="folder">
|
|
<Template label="Info (Mnemonics)" treetype="template">
|
|
// Mnemonics
|
|
//
|
|
// Most simulators have the ability to display ASCII text in the waveform and
|
|
// other debug windows as a means to allow for easier visual reference and
|
|
// understanding of a circuit operation. A useful debugging methodology is to
|
|
// assign text values to certain circuit values from within the testbench so
|
|
// that when added to the waveform and displayed as ASCII, would give more
|
|
// useful information about that current state of the circuit. Such methods are
|
|
// particularly useful in state-machine designs where each state value could be
|
|
// represented as a more easily identified text string. Other examples could
|
|
// include mapping OPMODEs, detecting certain data (i.e. packet starts, training
|
|
// sequences, etc.) or mapping address values/ranges. Below is an example of
|
|
// defining a mnemonic in a testbench to decode a simple state-machine states to
|
|
// something more intelligible.
|
|
//
|
|
|
|
// A reg must be declared with enough bits (8 times number of characters)
|
|
// to store the desired string. Add this vector to the waveform and set the
|
|
// radix to ASCII
|
|
|
|
reg [(8*12)-1:0] state_string = "??UNKNOWN??";
|
|
|
|
// There is a 4-bit register called "state" in the uart_inst sub-instance in
|
|
// the design file. This always statement looks at it to generate the
|
|
// mnemonics for the state-machine to the desired state_string reg.
|
|
|
|
always @(uut.uart_inst.state)
|
|
case (uut.uart_inst.state)
|
|
4'b0001 : begin
|
|
$display("%t: STATE is now: START", $realtime);
|
|
state_string = "START";
|
|
end
|
|
4'b0010 : begin
|
|
$display("%t: STATE is now: FIRST_MATCH", $realtime);
|
|
state_string = "FIRST_MATCH";
|
|
end
|
|
4'b0100 : begin
|
|
$display("%t: STATE is now: SECOND_MATCH", $realtime);
|
|
state_string = "SECOND_MATCH";
|
|
end
|
|
4'b1000 : begin
|
|
$display("%t: STATE is now: SUCCESS", $realtime);
|
|
state_string = "SUCCESS";
|
|
end
|
|
default : begin
|
|
$display("%t: ERROR: STATE is now: UNKNOWN !!!!", $realtime);
|
|
state_string = "??UNKNOWN??";
|
|
end
|
|
endcase
|
|
</Template>
|
|
</SubFolder>
|
|
</Folder>
|
|
<Folder label="Synthesis Constructs" treetype="folder">
|
|
<SubFolder label="Conditional" treetype="folder">
|
|
<Template label="Continuous Assignment (2-to-1 MUX)" treetype="template">
|
|
assign <output> = <1-bit_select> ? <input1> : <input0>;
|
|
</Template>
|
|
<Template label="If / Else If / Else Statement" treetype="template">
|
|
if (<condition>) begin
|
|
<statement>;
|
|
end
|
|
else if (<condition>) begin
|
|
<statement>;
|
|
end
|
|
else begin
|
|
<statement>;
|
|
end
|
|
</Template>
|
|
<SubFolder label="Case" treetype="folder">
|
|
<Template label="2-input Select" treetype="template">
|
|
case (<2-bit select>)
|
|
2'b00 : begin
|
|
<statement>;
|
|
end
|
|
2'b01 : begin
|
|
<statement>;
|
|
end
|
|
2'b10 : begin
|
|
<statement>;
|
|
end
|
|
2'b11 : begin
|
|
<statement>;
|
|
end
|
|
default: begin
|
|
<statement>;
|
|
end
|
|
endcase
|
|
</Template>
|
|
<Template label="3-input Select" treetype="template">
|
|
case (<3-bit select>)
|
|
3'b000 : begin
|
|
<statement>;
|
|
end
|
|
3'b001 : begin
|
|
<statement>;
|
|
end
|
|
3'b010 : begin
|
|
<statement>;
|
|
end
|
|
3'b011 : begin
|
|
<statement>;
|
|
end
|
|
3'b100 : begin
|
|
<statement>;
|
|
end
|
|
3'b101 : begin
|
|
<statement>;
|
|
end
|
|
3'b110 : begin
|
|
<statement>;
|
|
end
|
|
3'b111 : begin
|
|
<statement>;
|
|
end
|
|
default: begin
|
|
<statement>;
|
|
end
|
|
endcase
|
|
</Template>
|
|
<Template label="4-input Select" treetype="template">
|
|
case (<4-bit select>)
|
|
4'b0000: begin
|
|
<statement>;
|
|
end
|
|
4'b0001: begin
|
|
<statement>;
|
|
end
|
|
4'b0010: begin
|
|
<statement>;
|
|
end
|
|
4'b0011: begin
|
|
<statement>;
|
|
end
|
|
4'b0100: begin
|
|
<statement>;
|
|
end
|
|
4'b0101: begin
|
|
<statement>;
|
|
end
|
|
4'b0110: begin
|
|
<statement>;
|
|
end
|
|
4'b0111: begin
|
|
<statement>;
|
|
end
|
|
4'b1000: begin
|
|
<statement>;
|
|
end
|
|
4'b1001: begin
|
|
<statement>;
|
|
end
|
|
4'b1010: begin
|
|
<statement>;
|
|
end
|
|
4'b1011: begin
|
|
<statement>;
|
|
end
|
|
4'b1100: begin
|
|
<statement>;
|
|
end
|
|
4'b1101: begin
|
|
<statement>;
|
|
end
|
|
4'b1110: begin
|
|
<statement>;
|
|
end
|
|
4'b1111: begin
|
|
<statement>;
|
|
end
|
|
default: begin
|
|
<statement>;
|
|
end
|
|
endcase
|
|
</Template>
|
|
<Template label="5-input Select" treetype="template">
|
|
case (<5-bit select>)
|
|
5'b00000: begin
|
|
<statement>;
|
|
end
|
|
5'b00001: begin
|
|
<statement>;
|
|
end
|
|
5'b00010: begin
|
|
<statement>;
|
|
end
|
|
5'b00011: begin
|
|
<statement>;
|
|
end
|
|
5'b00100: begin
|
|
<statement>;
|
|
end
|
|
5'b00101: begin
|
|
<statement>;
|
|
end
|
|
5'b00110: begin
|
|
<statement>;
|
|
end
|
|
5'b00111: begin
|
|
<statement>;
|
|
end
|
|
5'b01000: begin
|
|
<statement>;
|
|
end
|
|
5'b01001: begin
|
|
<statement>;
|
|
end
|
|
5'b01010: begin
|
|
<statement>;
|
|
end
|
|
5'b01011: begin
|
|
<statement>;
|
|
end
|
|
5'b01100: begin
|
|
<statement>;
|
|
end
|
|
5'b01101: begin
|
|
<statement>;
|
|
end
|
|
5'b01110: begin
|
|
<statement>;
|
|
end
|
|
5'b01111: begin
|
|
<statement>;
|
|
end
|
|
5'b10000: begin
|
|
<statement>;
|
|
end
|
|
5'b10001: begin
|
|
<statement>;
|
|
end
|
|
5'b10010: begin
|
|
<statement>;
|
|
end
|
|
5'b10011: begin
|
|
<statement>;
|
|
end
|
|
5'b10100: begin
|
|
<statement>;
|
|
end
|
|
5'b10101: begin
|
|
<statement>;
|
|
end
|
|
5'b10110: begin
|
|
<statement>;
|
|
end
|
|
5'b10111: begin
|
|
<statement>;
|
|
end
|
|
5'b11000: begin
|
|
<statement>;
|
|
end
|
|
5'b11001: begin
|
|
<statement>;
|
|
end
|
|
5'b11010: begin
|
|
<statement>;
|
|
end
|
|
5'b11011: begin
|
|
<statement>;
|
|
end
|
|
5'b11100: begin
|
|
<statement>;
|
|
end
|
|
5'b11101: begin
|
|
<statement>;
|
|
end
|
|
5'b11110: begin
|
|
<statement>;
|
|
end
|
|
5'b11111: begin
|
|
<statement>;
|
|
end
|
|
default : begin
|
|
<statement>;
|
|
end
|
|
endcase
|
|
</Template>
|
|
<Template label="6-input Select" treetype="template">
|
|
case (<6-bit select>)
|
|
6'b000000: begin
|
|
<statement>;
|
|
end
|
|
6'b000001: begin
|
|
<statement>;
|
|
end
|
|
6'b000010: begin
|
|
<statement>;
|
|
end
|
|
6'b000011: begin
|
|
<statement>;
|
|
end
|
|
6'b000100: begin
|
|
<statement>;
|
|
end
|
|
6'b000101: begin
|
|
<statement>;
|
|
end
|
|
6'b000110: begin
|
|
<statement>;
|
|
end
|
|
6'b000111: begin
|
|
<statement>;
|
|
end
|
|
6'b001000: begin
|
|
<statement>;
|
|
end
|
|
6'b001001: begin
|
|
<statement>;
|
|
end
|
|
6'b001010: begin
|
|
<statement>;
|
|
end
|
|
6'b001011: begin
|
|
<statement>;
|
|
end
|
|
6'b001100: begin
|
|
<statement>;
|
|
end
|
|
6'b001101: begin
|
|
<statement>;
|
|
end
|
|
6'b001110: begin
|
|
<statement>;
|
|
end
|
|
6'b001111: begin
|
|
<statement>;
|
|
end
|
|
6'b010000: begin
|
|
<statement>;
|
|
end
|
|
6'b010001: begin
|
|
<statement>;
|
|
end
|
|
6'b010010: begin
|
|
<statement>;
|
|
end
|
|
6'b010011: begin
|
|
<statement>;
|
|
end
|
|
6'b010100: begin
|
|
<statement>;
|
|
end
|
|
6'b010101: begin
|
|
<statement>;
|
|
end
|
|
6'b010110: begin
|
|
<statement>;
|
|
end
|
|
6'b010111: begin
|
|
<statement>;
|
|
end
|
|
6'b011000: begin
|
|
<statement>;
|
|
end
|
|
6'b011001: begin
|
|
<statement>;
|
|
end
|
|
6'b011010: begin
|
|
<statement>;
|
|
end
|
|
6'b011011: begin
|
|
<statement>;
|
|
end
|
|
6'b011100: begin
|
|
<statement>;
|
|
end
|
|
6'b011101: begin
|
|
<statement>;
|
|
end
|
|
6'b011110: begin
|
|
<statement>;
|
|
end
|
|
6'b011111: begin
|
|
<statement>;
|
|
end
|
|
6'b100000: begin
|
|
<statement>;
|
|
end
|
|
6'b100001: begin
|
|
<statement>;
|
|
end
|
|
6'b100010: begin
|
|
<statement>;
|
|
end
|
|
6'b100011: begin
|
|
<statement>;
|
|
end
|
|
6'b100100: begin
|
|
<statement>;
|
|
end
|
|
6'b100101: begin
|
|
<statement>;
|
|
end
|
|
6'b100110: begin
|
|
<statement>;
|
|
end
|
|
6'b100111: begin
|
|
<statement>;
|
|
end
|
|
6'b101000: begin
|
|
<statement>;
|
|
end
|
|
6'b101001: begin
|
|
<statement>;
|
|
end
|
|
6'b101010: begin
|
|
<statement>;
|
|
end
|
|
6'b101011: begin
|
|
<statement>;
|
|
end
|
|
6'b101100: begin
|
|
<statement>;
|
|
end
|
|
6'b101101: begin
|
|
<statement>;
|
|
end
|
|
6'b101110: begin
|
|
<statement>;
|
|
end
|
|
6'b101111: begin
|
|
<statement>;
|
|
end
|
|
6'b110000: begin
|
|
<statement>;
|
|
end
|
|
6'b110001: begin
|
|
<statement>;
|
|
end
|
|
6'b110010: begin
|
|
<statement>;
|
|
end
|
|
6'b110011: begin
|
|
<statement>;
|
|
end
|
|
6'b110100: begin
|
|
<statement>;
|
|
end
|
|
6'b110101: begin
|
|
<statement>;
|
|
end
|
|
6'b110110: begin
|
|
<statement>;
|
|
end
|
|
6'b110111: begin
|
|
<statement>;
|
|
end
|
|
6'b111000: begin
|
|
<statement>;
|
|
end
|
|
6'b111001: begin
|
|
<statement>;
|
|
end
|
|
6'b111010: begin
|
|
<statement>;
|
|
end
|
|
6'b111011: begin
|
|
<statement>;
|
|
end
|
|
6'b111100: begin
|
|
<statement>;
|
|
end
|
|
6'b111101: begin
|
|
<statement>;
|
|
end
|
|
6'b111110: begin
|
|
<statement>;
|
|
end
|
|
6'b111111: begin
|
|
<statement>;
|
|
end
|
|
default : begin
|
|
<statement>;
|
|
end
|
|
endcase
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Always" treetype="folder">
|
|
<SubFolder label="Posedge Clocked" treetype="folder">
|
|
<Template label="Simple Flop" treetype="template">
|
|
always @(posedge <clock>) begin
|
|
<signal> <= <clocked_value>;
|
|
end
|
|
</Template>
|
|
<Template label="w/ Async Low Reset" treetype="template">
|
|
// Usage of asynchronous resets may negatively impact FPGA resources
|
|
// and timing. In general faster and smaller FPGA designs will
|
|
// result from not using asynchronous resets. Please refer to
|
|
// the Synthesis and Simulation Design Guide for more information.
|
|
|
|
always @(posedge <clock> or negedge <reset>)
|
|
if (!<reset>) begin
|
|
<signal> <= 0;
|
|
end else begin
|
|
<signal> <= <clocked_value>;
|
|
end
|
|
</Template>
|
|
<Template label="w/ Async High Reset" treetype="template">
|
|
// Usage of asynchronous resets may negatively impact FPGA resources
|
|
// and timing. In general faster and smaller FPGA designs will
|
|
// result from not using asynchronous resets. Please refer to
|
|
// the Synthesis and Simulation Design Guide for more information.
|
|
|
|
always @(posedge <clock> or posedge <reset>)
|
|
if (<reset>) begin
|
|
<signal> <= 0;
|
|
end else begin
|
|
<signal> <= <clocked_value>;
|
|
end
|
|
</Template>
|
|
<Template label="w/ Async Low Reset and CE" treetype="template">
|
|
// Usage of asynchronous resets may negatively impact FPGA resources
|
|
// and timing. In general faster and smaller FPGA designs will
|
|
// result from not using asynchronous resets. Please refer to
|
|
// the Synthesis and Simulation Design Guide for more information.
|
|
|
|
always @(posedge <clock> or negedge <reset>)
|
|
if (!<reset>) begin
|
|
<signal> <= 0;
|
|
end else if (<clock_enable>) begin
|
|
<signal> <= <clocked_value>;
|
|
end
|
|
</Template>
|
|
<Template label="w/ Async High Reset and CE" treetype="template">
|
|
// Usage of asynchronous resets may negatively impact FPGA resources
|
|
// and timing. In general faster and smaller FPGA designs will
|
|
// result from not using asynchronous resets. Please refer to
|
|
// the Synthesis and Simulation Design Guide for more information.
|
|
|
|
always @(posedge <clock> or posedge <reset>)
|
|
if (<reset>) begin
|
|
<signal> <= 0;
|
|
end else if (<clock_enable>) begin
|
|
<signal> <= <clocked_value>;
|
|
end
|
|
</Template>
|
|
<Template label="w/ Sync Low Reset" treetype="template">
|
|
always @(posedge <clock>)
|
|
if (!<reset>) begin
|
|
<signal> <= 0;
|
|
end else begin
|
|
<signal> <= <clocked_value>;
|
|
end
|
|
</Template>
|
|
<Template label="w/ Sync High Reset" treetype="template">
|
|
always @(posedge <clock>)
|
|
if (<reset>) begin
|
|
<signal> <= 0;
|
|
end else begin
|
|
<signal> <= <clocked_value>;
|
|
end
|
|
</Template>
|
|
<Template label="w/ Async & Sync Low Reset" treetype="template">
|
|
// Usage of asynchronous resets may negatively impact FPGA resources
|
|
// and timing. In general faster and smaller FPGA designs will
|
|
// result from not using asynchronous resets. Please refer to
|
|
// the Synthesis and Simulation Design Guide for more information.
|
|
|
|
always @(posedge <clock> or negedge <async_reset>)
|
|
if (!<async_reset>) begin
|
|
<signal> <= 0;
|
|
end else if (!<sync_reset>) begin
|
|
<signal> <= 0;
|
|
end else begin
|
|
<signal> <= <clocked_value>;
|
|
end
|
|
</Template>
|
|
<Template label="w/ Async & Sync High Reset" treetype="template">
|
|
// Usage of asynchronous resets may negatively impact FPGA resources
|
|
// and timing. In general faster and smaller FPGA designs will
|
|
// result from not using asynchronous resets. Please refer to
|
|
// the Synthesis and Simulation Design Guide for more information.
|
|
|
|
always @(posedge <clock> or posedge <async_reset>)
|
|
if (<async_reset>) begin
|
|
<signal> <= 0;
|
|
end else if (<sync_reset>) begin
|
|
<signal> <= 0;
|
|
end else begin
|
|
<signal> <= <clocked_value>;
|
|
end
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Negedge Clocked" treetype="folder">
|
|
<Template label="Simple Flop" treetype="template">
|
|
always @(negedge <clock>) begin
|
|
<signal> <= <clocked_value>;
|
|
end
|
|
</Template>
|
|
<Template label="w/ Async Low Reset" treetype="template">
|
|
// Usage of asynchronous resets may negatively impact FPGA resources
|
|
// and timing. In general faster and smaller FPGA designs will
|
|
// result from not using asynchronous resets. Please refer to
|
|
// the Synthesis and Simulation Design Guide for more information.
|
|
|
|
always @(negedge <clock> or negedge <reset>)
|
|
if (!<reset>) begin
|
|
<signal> <= 0;
|
|
end else begin
|
|
<signal> <= <clocked_value>;
|
|
end
|
|
</Template>
|
|
<Template label="w/ Async High Reset" treetype="template">
|
|
// Usage of asynchronous resets may negatively impact FPGA resources
|
|
// and timing. In general faster and smaller FPGA designs will
|
|
// result from not using asynchronous resets. Please refer to
|
|
// the Synthesis and Simulation Design Guide for more information.
|
|
|
|
always @(negedge <clock> or posedge <reset>)
|
|
if (<reset>) begin
|
|
<signal> <= 0;
|
|
end else begin
|
|
<signal> <= <clocked_value>;
|
|
end
|
|
</Template>
|
|
<Template label="w/ Async Low Reset and CE" treetype="template">
|
|
// Usage of asynchronous resets may negatively impact FPGA resources
|
|
// and timing. In general faster and smaller FPGA designs will
|
|
// result from not using asynchronous resets. Please refer to
|
|
// the Synthesis and Simulation Design Guide for more information.
|
|
|
|
always @(negedge <clock> or negedge <reset>)
|
|
if (!<reset>) begin
|
|
<signal> <= 0;
|
|
end else if (<clock_enable>) begin
|
|
<signal> <= <clocked_value>;
|
|
end
|
|
</Template>
|
|
<Template label="w/ Async High Reset and CE" treetype="template">
|
|
// Usage of asynchronous resets may negatively impact FPGA resources
|
|
// and timing. In general faster and smaller FPGA designs will
|
|
// result from not using asynchronous resets. Please refer to
|
|
// the Synthesis and Simulation Design Guide for more information.
|
|
|
|
always @(negedge <clock> or posedge <reset>)
|
|
if (<reset>) begin
|
|
<signal> <= 0;
|
|
end else if (<clock_enable>) begin
|
|
<signal> <= <clocked_value>;
|
|
end
|
|
</Template>
|
|
<Template label="w/ Sync Low Reset" treetype="template">
|
|
always @(negedge <clock>)
|
|
if (!<reset>) begin
|
|
<signal> <= 0;
|
|
end else begin
|
|
<signal> <= <clocked_value>;
|
|
end
|
|
</Template>
|
|
<Template label="w/ Sync High Reset" treetype="template">
|
|
always @(negedge <clock>)
|
|
if (<reset>) begin
|
|
<signal> <= 0;
|
|
end else begin
|
|
<signal> <= <clocked_value>;
|
|
end
|
|
</Template>
|
|
<Template label="w/ Async & Sync Low Reset" treetype="template">
|
|
// Usage of asynchronous resets may negatively impact FPGA resources
|
|
// and timing. In general faster and smaller FPGA designs will
|
|
// result from not using asynchronous resets. Please refer to
|
|
// the Synthesis and Simulation Design Guide for more information.
|
|
|
|
always @(negedge <clock> or negedge <async_reset>)
|
|
if (!<async_reset>) begin
|
|
<signal> <= 0;
|
|
end else if (!<sync_reset>) begin
|
|
<signal> <= 0;
|
|
end else begin
|
|
<signal> <= <clocked_value>;
|
|
end
|
|
</Template>
|
|
<Template label="w/ Async & Sync High Reset" treetype="template">
|
|
// Usage of asynchronous resets may negatively impact FPGA resources
|
|
// and timing. In general faster and smaller FPGA designs will
|
|
// result from not using asynchronous resets. Please refer to
|
|
// the Synthesis and Simulation Design Guide for more information.
|
|
|
|
always @(negedge <clock> or posedge <async_reset>)
|
|
if (<async_reset>) begin
|
|
<signal> <= 0;
|
|
end else if (<sync_reset>) begin
|
|
<signal> <= 0;
|
|
end else begin
|
|
<signal> <= <clocked_value>;
|
|
end
|
|
</Template>
|
|
</SubFolder>
|
|
<Template label="Combinatorial" treetype="template">
|
|
// Always specify an else statement with a combinatorial if statement in
|
|
// order to avoid the inference of a latch
|
|
always @*
|
|
if (<condition>) begin
|
|
<signal> = <value>;
|
|
else
|
|
<signal> = <value>;
|
|
end
|
|
</Template>
|
|
</SubFolder>
|
|
<Template label="Continuous Assignment" treetype="template">
|
|
assign <wire_name> = <siganl_or_value>;
|
|
</Template>
|
|
<SubFolder label="Generate" treetype="folder">
|
|
<Template label="Generate Multiple Instances" treetype="template">
|
|
genvar <var>;
|
|
generate
|
|
for (<var>=0; <var> < <limit>; <var>=<var>+1)
|
|
begin: <label>
|
|
<instantiation>
|
|
end
|
|
endgenerate
|
|
</Template>
|
|
<Template label="Nested Generates Multiple Instances" treetype="template">
|
|
genvar <var1>, <var2>;
|
|
generate
|
|
for (<var1>=0; <var1> < <limit>; <var1>=<var1>+1)
|
|
begin: <label_1>
|
|
for (<var2>=0; <var2> < <limit>; <var2>=<var2>+1)
|
|
begin: <label_2>
|
|
<code>
|
|
end
|
|
end
|
|
endgenerate
|
|
</Template>
|
|
<Template label="Conditional Instances (if)" treetype="template">
|
|
generate
|
|
if (<condition>) begin: <label_1>
|
|
<code>;
|
|
end else if (<condition>) begin: <label_2>
|
|
<code>;
|
|
end else begin: <label_3>
|
|
<code>;
|
|
end
|
|
endgenerate
|
|
</Template>
|
|
<Template label="Conditional Instances (case)" treetype="template">
|
|
generate
|
|
case (<constant_expression>)
|
|
<value>: begin: <label_1>
|
|
<code>
|
|
end
|
|
<value>: begin: <label_2>
|
|
<code>
|
|
end
|
|
default: begin: <label_3>
|
|
<code>
|
|
end
|
|
endcase
|
|
endgenerate
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Signal, Constant & Variable Declarations" treetype="folder">
|
|
<SubFolder label="Parameter" treetype="folder">
|
|
<SubFolder label="Local Parameter" treetype="folder">
|
|
<Template label="Un-typed, unranged local parameter" treetype="template">
|
|
localparam <name> = <value>;
|
|
</Template>
|
|
<Template label="Un-typed, ranged local parameter" treetype="template">
|
|
localparam [upper:lower] <name> = <value>;
|
|
</Template>
|
|
<Template label="Signed, unranged local parameter" treetype="template">
|
|
localparam signed <name> = <value>;
|
|
</Template>
|
|
<Template label="Signed, ranged local parameter" treetype="template">
|
|
localparam signed [upper:lower] <name> = <value>;
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Parameter" treetype="folder">
|
|
<Template label="Un-typed, unranged parameter" treetype="template">
|
|
parameter <name> = <value>;
|
|
</Template>
|
|
<Template label="Un-typed, ranged parameter" treetype="template">
|
|
parameter [upper:lower] <name> = <value>;
|
|
</Template>
|
|
<Template label="Signed, unranged parameter" treetype="template">
|
|
parameter signed <name> = <value>;
|
|
</Template>
|
|
<Template label="Signed, ranged parameter" treetype="template">
|
|
parameter signed [upper:lower] <name> = <value>;
|
|
</Template>
|
|
</SubFolder>
|
|
<Template label="Info (Parameter)" treetype="template">
|
|
// information on the Verilog Parameter, Local Parameter,
|
|
// Defparam and Named Parameter Value Assignment
|
|
// =======================================================
|
|
//
|
|
// Parameters are a method within Verilog in order to define constants
|
|
// within the code. They are very useful in order to define bus widths,
|
|
// memory depths, state-machine assignments, clock periods and other useful
|
|
// constants used throughout the design and testbench. Parameters can bring
|
|
// more meaning and documentation to the code or can be used to make the
|
|
// code more parameterizable and thus help enable re-use or help adjust to
|
|
// late changes in the design. There are two main types of parameters, the
|
|
// parameter and local parameter. A local parameter acts the same as a
|
|
// parameter however its contents cannot be modified via a defparam or a
|
|
// named parameter value assignment in the instantiation. A defparam allows
|
|
// the reassignment to the value of a parameter from a different level of
|
|
// hierarchy in the testbench or design. A named parameter value assignment
|
|
// allows a respecification of the parameter value within the instance
|
|
// declaration of the instantiation of the component. Both local parameters
|
|
// and parameters can be sized to a specified number of bits and/or can be typed
|
|
// to be either a signed value, an integer, a real number, a time (64-bit
|
|
// precision) or a realtime (double-precision floating point) value.
|
|
|
|
// Example declaring a parameter and local parameter
|
|
|
|
// Define pi as a local real number parameter since I do not want to ever change this
|
|
|
|
localparam real pi = 3.14;
|
|
|
|
// Define BUS_WIDTH as a parameter with a default value of 8
|
|
|
|
parameter BUS_WIDTH = 8;
|
|
|
|
// Use this parameter to define the width of a declared register
|
|
|
|
reg [BUS_WIDTH-1:0] my_reg;
|
|
|
|
// Use a defparam from my testbench to change BUS_WIDTH to 16 for the instantiated
|
|
// design instance UUT
|
|
|
|
defparam UUT.BUS_WIDTH = 16;
|
|
|
|
// Alternatively to the defparam, I could have done this using the named parameter value assignment when I instantiate UUT
|
|
|
|
my_design #(
|
|
.BUS_WIDTH(16)
|
|
) UUT (
|
|
.A(A),
|
|
.B(B),
|
|
.C(C)
|
|
);
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Wire" treetype="folder">
|
|
<SubFolder label="Wire Signal" treetype="folder">
|
|
<Template label="1-bit" treetype="template">
|
|
wire <name>;
|
|
</Template>
|
|
<Template label="2-bit" treetype="template">
|
|
wire [1:0] <name>;
|
|
</Template>
|
|
<Template label="3-bit" treetype="template">
|
|
wire [2:0] <name>;
|
|
</Template>
|
|
<Template label="4-bit" treetype="template">
|
|
wire [3:0] <name>;
|
|
</Template>
|
|
<Template label="8-bit" treetype="template">
|
|
wire [7:0] <name>;
|
|
</Template>
|
|
<Template label="16-bit" treetype="template">
|
|
wire [15:0] <name>;
|
|
</Template>
|
|
<Template label="32-bit" treetype="template">
|
|
wire [31:0] <name>;
|
|
</Template>
|
|
<Template label="64-bit" treetype="template">
|
|
wire [63:0] <name>;
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Signed Wire" treetype="folder">
|
|
<Template label="8-bit" treetype="template">
|
|
wire signed [7:0] <name>;
|
|
</Template>
|
|
<Template label="9-bit" treetype="template">
|
|
wire signed [8:0] <name>;
|
|
</Template>
|
|
<Template label="16-bit" treetype="template">
|
|
wire signed [15:0] <name>;
|
|
</Template>
|
|
<Template label="18-bit" treetype="template">
|
|
wire signed [17:0] <name>;
|
|
</Template>
|
|
<Template label="32-bit" treetype="template">
|
|
wire signed [31:0] <name>;
|
|
</Template>
|
|
<Template label="64-bit" treetype="template">
|
|
wire signed [63:0] <name>;
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Register" treetype="folder">
|
|
<SubFolder label="Uninitialized" treetype="folder">
|
|
<SubFolder label="Reg" treetype="folder">
|
|
<Template label="1-bit" treetype="template">
|
|
reg <name>;
|
|
</Template>
|
|
<Template label="2-bit" treetype="template">
|
|
reg [1:0] <name>;
|
|
</Template>
|
|
<Template label="3-bit" treetype="template">
|
|
reg [2:0] <name>;
|
|
</Template>
|
|
<Template label="4-bit" treetype="template">
|
|
reg [3:0] <name>;
|
|
</Template>
|
|
<Template label="8-bit" treetype="template">
|
|
reg [7:0] <name>;
|
|
</Template>
|
|
<Template label="16-bit" treetype="template">
|
|
reg [15:0] <name>;
|
|
</Template>
|
|
<Template label="32-bit" treetype="template">
|
|
reg [31:0] <name>;
|
|
</Template>
|
|
<Template label="64-bit" treetype="template">
|
|
reg [63:0] <name>;
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Signed Reg" treetype="folder">
|
|
<Template label="8-bit" treetype="template">
|
|
reg signed [7:0] <name>;
|
|
</Template>
|
|
<Template label="9-bit" treetype="template">
|
|
reg signed [8:0] <name>;
|
|
</Template>
|
|
<Template label="16-bit" treetype="template">
|
|
reg signed [15:0] <name>;
|
|
</Template>
|
|
<Template label="18-bit" treetype="template">
|
|
reg signed [17:0] <name>;
|
|
</Template>
|
|
<Template label="32-bit" treetype="template">
|
|
reg signed [31:0] <name>;
|
|
</Template>
|
|
<Template label="64-bit" treetype="template">
|
|
reg signed [63:0] <name>;
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="2-dimensional" treetype="folder">
|
|
<Template label="16 x 1" treetype="template">
|
|
reg <name> [3:0];
|
|
</Template>
|
|
<Template label="32 x 1" treetype="template">
|
|
reg <name> [4:0];
|
|
</Template>
|
|
<Template label="16k x 1" treetype="template">
|
|
reg <name> [16383:0];
|
|
</Template>
|
|
<Template label="8k x 2" treetype="template">
|
|
reg [1:0] <name> [8191:0];
|
|
</Template>
|
|
<Template label="4k x 4" treetype="template">
|
|
reg [3:0] <name> [4095:0];
|
|
</Template>
|
|
<Template label="2k x 9" treetype="template">
|
|
reg [8:0] <name> [2047:0];
|
|
</Template>
|
|
<Template label="1k x 18" treetype="template">
|
|
reg [17:0] <name> [1023:0];
|
|
</Template>
|
|
<Template label="512 x 36" treetype="template">
|
|
reg [35:0] <name> [511:0];
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Initialized" treetype="folder">
|
|
<SubFolder label="Reg" treetype="folder">
|
|
<Template label="1-bit" treetype="template">
|
|
reg <name> = 1'b0;
|
|
</Template>
|
|
<Template label="2-bit" treetype="template">
|
|
reg [1:0] <name> = 2'b00;
|
|
</Template>
|
|
<Template label="3-bit" treetype="template">
|
|
reg [2:0] <name> = 3'b000;
|
|
</Template>
|
|
<Template label="4-bit" treetype="template">
|
|
reg [3:0] <name> = 4'h0;
|
|
</Template>
|
|
<Template label="8-bit" treetype="template">
|
|
reg [7:0] <name> = 8'h00;
|
|
</Template>
|
|
<Template label="16-bit" treetype="template">
|
|
reg [15:0] <name> = 16'h0000;
|
|
</Template>
|
|
<Template label="32-bit" treetype="template">
|
|
reg [31:0] <name> = 32'h00000000;
|
|
</Template>
|
|
<Template label="64-bit" treetype="template">
|
|
reg [63:0] <name> = 64'h0000000000000000;
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Signed Reg" treetype="folder">
|
|
<Template label="8-bit" treetype="template">
|
|
reg signed [7:0] <name> = 8'sh00;
|
|
</Template>
|
|
<Template label="9-bit" treetype="template">
|
|
reg signed [8:0] <name> = 9'sh000;
|
|
</Template>
|
|
<Template label="16-bit" treetype="template">
|
|
reg signed [15:0] <name> = 16'sh0000;
|
|
</Template>
|
|
<Template label="18-bit" treetype="template">
|
|
reg signed [17:0] <name> = 18'sh00000;
|
|
</Template>
|
|
<Template label="32-bit" treetype="template">
|
|
reg signed [31:0] <name> = 32'sh00000000;
|
|
</Template>
|
|
<Template label="64-bit" treetype="template">
|
|
reg signed [63:0] <name> = 64'sh0000000000000000;
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Ports" treetype="folder">
|
|
<SubFolder label="Simple Declaration" treetype="folder">
|
|
<SubFolder label="Input" treetype="folder">
|
|
<Template label="1-bit" treetype="template">
|
|
input <name>;
|
|
</Template>
|
|
<Template label="2-bit" treetype="template">
|
|
input [1:0] <name>;
|
|
</Template>
|
|
<Template label="3-bit" treetype="template">
|
|
input [2:0] <name>;
|
|
</Template>
|
|
<Template label="4-bit" treetype="template">
|
|
input [3:0] <name>;
|
|
</Template>
|
|
<Template label="8-bit" treetype="template">
|
|
input [7:0] <name>;
|
|
</Template>
|
|
<Template label="16-bit" treetype="template">
|
|
input [15:0] <name>;
|
|
</Template>
|
|
<Template label="32-bit" treetype="template">
|
|
input [31:0] <name>;
|
|
</Template>
|
|
<Template label="64-bit" treetype="template">
|
|
input [63:0] <name>;
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Output" treetype="folder">
|
|
<Template label="1-bit" treetype="template">
|
|
output <name>;
|
|
</Template>
|
|
<Template label="2-bit" treetype="template">
|
|
output [1:0] <name>;
|
|
</Template>
|
|
<Template label="3-bit" treetype="template">
|
|
output [2:0] <name>;
|
|
</Template>
|
|
<Template label="4-bit" treetype="template">
|
|
output [3:0] <name>;
|
|
</Template>
|
|
<Template label="8-bit" treetype="template">
|
|
output [7:0] <name>;
|
|
</Template>
|
|
<Template label="16-bit" treetype="template">
|
|
output [15:0] <name>;
|
|
</Template>
|
|
<Template label="32-bit" treetype="template">
|
|
output [31:0] <name>;
|
|
</Template>
|
|
<Template label="64-bit" treetype="template">
|
|
output [63:0] <name>;
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Bidirectional (inout)" treetype="folder">
|
|
<Template label="1-bit" treetype="template">
|
|
inout <name>;
|
|
</Template>
|
|
<Template label="2-bit" treetype="template">
|
|
inout [1:0] <name>;
|
|
</Template>
|
|
<Template label="3-bit" treetype="template">
|
|
inout [2:0] <name>;
|
|
</Template>
|
|
<Template label="4-bit" treetype="template">
|
|
inout [3:0] <name>;
|
|
</Template>
|
|
<Template label="8-bit" treetype="template">
|
|
inout [7:0] <name>;
|
|
</Template>
|
|
<Template label="16-bit" treetype="template">
|
|
inout [15:0] <name>;
|
|
</Template>
|
|
<Template label="32-bit" treetype="template">
|
|
inout [31:0] <name>;
|
|
</Template>
|
|
<Template label="64-bit" treetype="template">
|
|
inout [63:0] <name>;
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Registered" treetype="folder">
|
|
<SubFolder label="Output" treetype="folder">
|
|
<Template label="1-bit" treetype="template">
|
|
output reg <name>;
|
|
</Template>
|
|
<Template label="2-bit" treetype="template">
|
|
output reg [1:0] <name>;
|
|
</Template>
|
|
<Template label="3-bit" treetype="template">
|
|
output reg [2:0] <name>;
|
|
</Template>
|
|
<Template label="4-bit" treetype="template">
|
|
output reg [3:0] <name>;
|
|
</Template>
|
|
<Template label="8-bit" treetype="template">
|
|
output reg [7:0] <name>;
|
|
</Template>
|
|
<Template label="16-bit" treetype="template">
|
|
output reg [15:0] <name>;
|
|
</Template>
|
|
<Template label="32-bit" treetype="template">
|
|
output reg [31:0] <name>;
|
|
</Template>
|
|
<Template label="64-bit" treetype="template">
|
|
output reg [63:0] <name>;
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<Template label="ANSI-style" treetype="template">
|
|
module <module_name> (
|
|
input <input_port_name>,
|
|
// ...<other_inputs>...
|
|
output <output_port_name>,
|
|
// ...<other_outputs>...
|
|
output reg <output_reg_name>,
|
|
// ...<other_registered_outputs>...
|
|
inout <inout_port_name>,
|
|
// ...<other_inouts>...
|
|
inout reg <inout_reg_name>
|
|
// ...<other_registered_inouts>...
|
|
);
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Coding Examples" treetype="folder">
|
|
<SubFolder label="Flip Flops" treetype="folder">
|
|
<SubFolder label="D Flip Flop" treetype="folder">
|
|
<SubFolder label="Posedge" treetype="folder">
|
|
<Template label="Simple Register" treetype="template">
|
|
always @(posedge <clock>) begin
|
|
<reg> <= <signal>;
|
|
end
|
|
</Template>
|
|
<Template label="w/ Asynchronous Active High Reset" treetype="template">
|
|
// Usage of asynchronous resets may negatively impact FPGA resources
|
|
// and timing. In general faster and smaller FPGA designs will
|
|
// result from not using asynchronous resets. Please refer to
|
|
// the Synthesis and Simulation Design Guide for more information.
|
|
|
|
always @(posedge <clock> or posedge <reset>)
|
|
if (<reset>) begin
|
|
<reg> <= 1'b0;
|
|
end else begin
|
|
<reg> <= <signal>;
|
|
end
|
|
</Template>
|
|
<Template label="w/ Asynchronous Active High Reset and CE" treetype="template">
|
|
// Usage of asynchronous resets may negatively impact FPGA resources
|
|
// and timing. In general faster and smaller FPGA designs will
|
|
// result from not using asynchronous resets. Please refer to
|
|
// the Synthesis and Simulation Design Guide for more information.
|
|
|
|
always @(posedge <clock> or posedge <reset>)
|
|
if (<reset>) begin
|
|
<reg> <= 1'b0;
|
|
end else if (<clock_enable>) begin
|
|
<reg> <= <signal>;
|
|
end
|
|
</Template>
|
|
<Template label="w/ Asynchronous Active Low Reset" treetype="template">
|
|
// Usage of asynchronous resets may negatively impact FPGA resources
|
|
// and timing. In general faster and smaller FPGA designs will
|
|
// result from not using asynchronous resets. Please refer to
|
|
// the Synthesis and Simulation Design Guide for more information.
|
|
|
|
always @(posedge <clock> or negedge <reset>)
|
|
if (!<reset>) begin
|
|
<reg> <= 1'b0;
|
|
end else begin
|
|
<reg> <= <signal>;
|
|
end
|
|
</Template>
|
|
<Template label="w/ Asynchronous Active Low Reset and CE" treetype="template">
|
|
// Usage of asynchronous resets may negatively impact FPGA resources
|
|
// and timing. In general faster and smaller FPGA designs will
|
|
// result from not using asynchronous resets. Please refer to
|
|
// the Synthesis and Simulation Design Guide for more information.
|
|
|
|
always @(posedge <clock> or negedge <reset>)
|
|
if (!<reset>) begin
|
|
<reg> <= 1'b0;
|
|
end else if (<clock_enable>) begin
|
|
<reg> <= <signal>;
|
|
end
|
|
</Template>
|
|
<Template label="w/ Synchronous Active High Reset" treetype="template">
|
|
always @(posedge <clock>)
|
|
if (<reset>) begin
|
|
<reg> <= 1'b0;
|
|
end else begin
|
|
<reg> <= <signal>;
|
|
end
|
|
</Template>
|
|
<Template label="w/ Synchronous Active High Reset and CE" treetype="template">
|
|
always @(posedge <clock>)
|
|
if (<reset>) begin
|
|
<reg> <= 1'b0;
|
|
end else if (<clock_enable>) begin
|
|
<reg> <= <signal>;
|
|
end
|
|
</Template>
|
|
<Template label="w/ Synchronous Active Low Reset" treetype="template">
|
|
always @(posedge <clock>)
|
|
if (!<reset>) begin
|
|
<reg> <= 1'b0;
|
|
end else begin
|
|
<reg> <= <signal>;
|
|
end
|
|
</Template>
|
|
<Template label="w/ Synchronous Active Low Reset and CE" treetype="template">
|
|
always @(posedge <clock> )
|
|
if (!<reset>) begin
|
|
<reg> <= 1'b0;
|
|
end else if (<clock_enable>) begin
|
|
<reg> <= <signal>;
|
|
end
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Negedge" treetype="folder">
|
|
<Template label="Simple Register" treetype="template">
|
|
always @(negedge <clock>) begin
|
|
<reg> <= <signal>;
|
|
end
|
|
</Template>
|
|
<Template label="w/ Asynchronous Active High Reset" treetype="template">
|
|
// Usage of asynchronous resets may negatively impact FPGA resources
|
|
// and timing. In general faster and smaller FPGA designs will
|
|
// result from not using asynchronous resets. Please refer to
|
|
// the Synthesis and Simulation Design Guide for more information.
|
|
|
|
always @(negedge <clock> or posedge <reset>)
|
|
if (<reset>) begin
|
|
<reg> <= 1'b0;
|
|
end else begin
|
|
<reg> <= <signal>;
|
|
end
|
|
</Template>
|
|
<Template label="w/ Asynchronous Active High Reset and CE" treetype="template">
|
|
// Usage of asynchronous resets may negatively impact FPGA resources
|
|
// and timing. In general faster and smaller FPGA designs will
|
|
// result from not using asynchronous resets. Please refer to
|
|
// the Synthesis and Simulation Design Guide for more information.
|
|
|
|
always @(negedge <clock> or posedge <reset>)
|
|
if (<reset>) begin
|
|
<reg> <= 1'b0;
|
|
end else if (<clock_enable>) begin
|
|
<reg> <= <signal>;
|
|
end
|
|
</Template>
|
|
<Template label="w/ Asynchronous Active Low Reset" treetype="template">
|
|
// Usage of asynchronous resets may negatively impact FPGA resources
|
|
// and timing. In general faster and smaller FPGA designs will
|
|
// result from not using asynchronous resets. Please refer to
|
|
// the Synthesis and Simulation Design Guide for more information.
|
|
|
|
always @(negedge <clock> or negedge <reset>)
|
|
if (!<reset>) begin
|
|
<reg> <= 1'b0;
|
|
end else begin
|
|
<reg> <= <signal>;
|
|
end
|
|
</Template>
|
|
<Template label="w/ Asynchronous Active Low Reset and CE" treetype="template">
|
|
// Usage of asynchronous resets may negatively impact FPGA resources
|
|
// and timing. In general faster and smaller FPGA designs will
|
|
// result from not using asynchronous resets. Please refer to
|
|
// the Synthesis and Simulation Design Guide for more information.
|
|
|
|
always @(negedge <clock> or negedge <reset>)
|
|
if (!<reset>) begin
|
|
<reg> <= 1'b0;
|
|
end else if (<clock_enable>) begin
|
|
<reg> <= <signal>;
|
|
end
|
|
</Template>
|
|
<Template label="w/ Synchronous Active High Reset" treetype="template">
|
|
always @(negedge <clock>)
|
|
if (<reset>) begin
|
|
<reg> <= 1'b0;
|
|
end else begin
|
|
<reg> <= <signal>;
|
|
end
|
|
</Template>
|
|
<Template label="w/ Synchronous Active High Reset and CE" treetype="template">
|
|
always @(negedge <clock>)
|
|
if (<reset>) begin
|
|
<reg> <= 1'b0;
|
|
end else if (<clock_enable>) begin
|
|
<reg> <= <signal>;
|
|
end
|
|
</Template>
|
|
<Template label="w/ Synchronous Active Low Reset" treetype="template">
|
|
always @(negedge <clock>)
|
|
if (!<reset>) begin
|
|
<reg> <= 1'b0;
|
|
end else begin
|
|
<reg> <= <signal>;
|
|
end
|
|
</Template>
|
|
<Template label="w/ Synchronous Active Low Reset and CE" treetype="template">
|
|
always @(negedge <clock> )
|
|
if (!<reset>) begin
|
|
<reg> <= 1'b0;
|
|
end else if (<clock_enable>) begin
|
|
<reg> <= <signal>;
|
|
end
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="T Flip Flop" treetype="folder">
|
|
<SubFolder label="Posedge" treetype="folder">
|
|
<Template label="Simple Register" treetype="template">
|
|
always @(posedge <clock>) begin
|
|
<reg> <= ~<reg>;
|
|
end
|
|
</Template>
|
|
<Template label="w/ Asynchronous Active High Reset" treetype="template">
|
|
// Usage of asynchronous resets may negatively impact FPGA resources
|
|
// and timing. In general faster and smaller FPGA designs will
|
|
// result from not using asynchronous resets. Please refer to
|
|
// the Synthesis and Simulation Design Guide for more information.
|
|
|
|
always @(posedge <clock> or posedge <reset>)
|
|
if (<reset>) begin
|
|
<reg> <= 1'b0;
|
|
end else begin
|
|
<reg> <= ~<reg>;
|
|
end
|
|
</Template>
|
|
<Template label="w/ Asynchronous Active High Reset and CE" treetype="template">
|
|
// Usage of asynchronous resets may negatively impact FPGA resources
|
|
// and timing. In general faster and smaller FPGA designs will
|
|
// result from not using asynchronous resets. Please refer to
|
|
// the Synthesis and Simulation Design Guide for more information.
|
|
|
|
always @(posedge <clock> or posedge <reset>)
|
|
if (<reset>) begin
|
|
<reg> <= 1'b0;
|
|
end else if (<clock_enable>) begin
|
|
<reg> <= ~<reg>;
|
|
end
|
|
</Template>
|
|
<Template label="w/ Asynchronous Active Low Reset" treetype="template">
|
|
// Usage of asynchronous resets may negatively impact FPGA resources
|
|
// and timing. In general faster and smaller FPGA designs will
|
|
// result from not using asynchronous resets. Please refer to
|
|
// the Synthesis and Simulation Design Guide for more information.
|
|
|
|
always @(posedge <clock> or negedge <reset>)
|
|
if (!<reset>) begin
|
|
<reg> <= 1'b0;
|
|
end else begin
|
|
<reg> <= ~<reg>;
|
|
end
|
|
</Template>
|
|
<Template label="w/ Asynchronous Active Low Reset and CE" treetype="template">
|
|
// Usage of asynchronous resets may negatively impact FPGA resources
|
|
// and timing. In general faster and smaller FPGA designs will
|
|
// result from not using asynchronous resets. Please refer to
|
|
// the Synthesis and Simulation Design Guide for more information.
|
|
|
|
always @(posedge <clock> or negedge <reset>)
|
|
if (!<reset>) begin
|
|
<reg> <= 1'b0;
|
|
end else if (<clock_enable>) begin
|
|
<reg> <= ~<reg>;
|
|
end
|
|
</Template>
|
|
<Template label="w/ Synchronous Active High Reset" treetype="template">
|
|
always @(posedge <clock>)
|
|
if (<reset>) begin
|
|
<reg> <= 1'b0;
|
|
end else begin
|
|
<reg> <= ~<reg>;
|
|
end
|
|
</Template>
|
|
<Template label="w/ Synchronous Active High Reset and CE" treetype="template">
|
|
always @(posedge <clock>)
|
|
if (<reset>) begin
|
|
<reg> <= 1'b0;
|
|
end else if (<clock_enable>) begin
|
|
<reg> <= ~<reg>;
|
|
end
|
|
</Template>
|
|
<Template label="w/ Synchronous Active Low Reset" treetype="template">
|
|
always @(posedge <clock>)
|
|
if (!<reset>) begin
|
|
<reg> <= 1'b0;
|
|
end else begin
|
|
<reg> <= ~<reg>;
|
|
end
|
|
</Template>
|
|
<Template label="w/ Synchronous Active Low Reset and CE" treetype="template">
|
|
always @(posedge <clock> )
|
|
if (!<reset>) begin
|
|
<reg> <= 1'b0;
|
|
end else if (<clock_enable>) begin
|
|
<reg> <= ~<reg>;
|
|
end
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Negedge" treetype="folder">
|
|
<Template label="Simple Register" treetype="template">
|
|
always @(negedge <clock>) begin
|
|
<reg> <= ~<reg>;
|
|
end
|
|
</Template>
|
|
<Template label="w/ Asynchronous Active High Reset" treetype="template">
|
|
// Usage of asynchronous resets may negatively impact FPGA resources
|
|
// and timing. In general faster and smaller FPGA designs will
|
|
// result from not using asynchronous resets. Please refer to
|
|
// the Synthesis and Simulation Design Guide for more information.
|
|
|
|
always @(negedge <clock> or posedge <reset>)
|
|
if (<reset>) begin
|
|
<reg> <= 1'b0;
|
|
end else begin
|
|
<reg> <= ~<reg>;
|
|
end
|
|
</Template>
|
|
<Template label="w/ Asynchronous Active High Reset and CE" treetype="template">
|
|
// Usage of asynchronous resets may negatively impact FPGA resources
|
|
// and timing. In general faster and smaller FPGA designs will
|
|
// result from not using asynchronous resets. Please refer to
|
|
// the Synthesis and Simulation Design Guide for more information.
|
|
|
|
always @(negedge <clock> or posedge <reset>)
|
|
if (<reset>) begin
|
|
<reg> <= 1'b0;
|
|
end else if (<clock_enable>) begin
|
|
<reg> <= ~<reg>;
|
|
end
|
|
</Template>
|
|
<Template label="w/ Asynchronous Active Low Reset" treetype="template">
|
|
// Usage of asynchronous resets may negatively impact FPGA resources
|
|
// and timing. In general faster and smaller FPGA designs will
|
|
// result from not using asynchronous resets. Please refer to
|
|
// the Synthesis and Simulation Design Guide for more information.
|
|
|
|
always @(negedge <clock> or negedge <reset>)
|
|
if (!<reset>) begin
|
|
<reg> <= 1'b0;
|
|
end else begin
|
|
<reg> <= ~<reg>;
|
|
end
|
|
</Template>
|
|
<Template label="w/ Asynchronous Active Low Reset and CE" treetype="template">
|
|
// Usage of asynchronous resets may negatively impact FPGA resources
|
|
// and timing. In general faster and smaller FPGA designs will
|
|
// result from not using asynchronous resets. Please refer to
|
|
// the Synthesis and Simulation Design Guide for more information.
|
|
|
|
always @(negedge <clock> or negedge <reset>)
|
|
if (!<reset>) begin
|
|
<reg> <= 1'b0;
|
|
end else if (<clock_enable>) begin
|
|
<reg> <= ~<reg>;
|
|
end
|
|
</Template>
|
|
<Template label="w/ Synchronous Active High Reset" treetype="template">
|
|
always @(negedge <clock>)
|
|
if (<reset>) begin
|
|
<reg> <= 1'b0;
|
|
end else begin
|
|
<reg> <= ~<reg>;
|
|
end
|
|
</Template>
|
|
<Template label="w/ Synchronous Active High Reset and CE" treetype="template">
|
|
always @(negedge <clock>)
|
|
if (<reset>) begin
|
|
<reg> <= 1'b0;
|
|
end else if (<clock_enable>) begin
|
|
<reg> <= ~<reg>;
|
|
end
|
|
</Template>
|
|
<Template label="w/ Synchronous Active Low Reset" treetype="template">
|
|
always @(negedge <clock>)
|
|
if (!<reset>) begin
|
|
<reg> <= 1'b0;
|
|
end else begin
|
|
<reg> <= ~<reg>;
|
|
end
|
|
</Template>
|
|
<Template label="w/ Synchronous Active Low Reset and CE" treetype="template">
|
|
always @(negedge <clock> )
|
|
if (!<reset>) begin
|
|
<reg> <= 1'b0;
|
|
end else if (<clock_enable>) begin
|
|
<reg> <= ~<reg>;
|
|
end
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Accumulators" treetype="folder">
|
|
<Template label="Async Reset, CE & Sync Load" treetype="template">
|
|
// Usage of asynchronous resets may negatively impact FPGA resources
|
|
// and timing. In general faster and smaller FPGA designs will
|
|
// result from not using asynchronous resets. Please refer to
|
|
// the Synthesis and Simulation Design Guide for more information.
|
|
|
|
parameter ACC_SIZE=<accumulator_width>;
|
|
reg [ACC_SIZE-1:0] <accumulate_out>;
|
|
|
|
always @ (posedge <clock> or posedge <reset>)
|
|
if (<reset>)
|
|
<accumulate_out> <= 0;
|
|
else if (<clock_enable>)
|
|
if (<load>)
|
|
<accumulate_out> <= <load_value>;
|
|
else
|
|
<accumulate_out> <= <accumulate_out> + <accumulate_in>;
|
|
</Template>
|
|
<Template label="Sync Reset, CE, & Sync Load" treetype="template">
|
|
parameter ACC_SIZE=<accumulator_width>;
|
|
reg [ACC_SIZE-1:0] <accumulate_out>;
|
|
|
|
always @ (posedge <clock>)
|
|
if (<reset>)
|
|
<accumulate_out> <= 0;
|
|
else if (<clock_enable>)
|
|
if (<load>)
|
|
<accumulate_out> <= <load_value>;
|
|
else
|
|
<accumulate_out> <= <accumulate_out> + <accumulate_in>;
|
|
</Template>
|
|
<Template label="Async Reset & CE" treetype="template">
|
|
// Usage of asynchronous resets may negatively impact FPGA resources
|
|
// and timing. In general faster and smaller FPGA designs will
|
|
// result from not using asynchronous resets. Please refer to
|
|
// the Synthesis and Simulation Design Guide for more information.
|
|
|
|
parameter ACC_SIZE=<accumulator_width>;
|
|
reg [ACC_SIZE-1:0] <accumulate_out>;
|
|
|
|
always @ (posedge <clock> or posedge <reset>)
|
|
if (<reset>)
|
|
<accumulate_out> <= 0;
|
|
else if (<clock_enable>)
|
|
<accumulate_out> <= <accumulate_out> + <accumulate_in>;
|
|
</Template>
|
|
<Template label="Sync Reset & CE" treetype="template">
|
|
parameter ACC_SIZE=<accumulator_width>;
|
|
reg [ACC_SIZE-1:0] <accumulate_out>;
|
|
|
|
always @ (posedge <clock>)
|
|
if (<reset>)
|
|
<accumulate_out> <= 0;
|
|
else if (<clock_enable>)
|
|
<accumulate_out> <= <accumulate_out> + <accumulate_in>;
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Multiplexers" treetype="folder">
|
|
<SubFolder label="Combinatorial" treetype="folder">
|
|
<Template label="2-to-1 (assign)" treetype="template">
|
|
assign <output_wire> = <1-bit_select> ? <input1> : <input0>;
|
|
</Template>
|
|
<Template label="4-to-1 (always)" treetype="template">
|
|
always @(<2-bit_select>, <input1>, <input2>, <input3>, <input4>)
|
|
case (<2-bit_select>)
|
|
2'b00: <output> = <input1>;
|
|
2'b01: <output> = <input2>;
|
|
2'b10: <output> = <input3>;
|
|
2'b11: <output> = <input4>;
|
|
endcase
|
|
</Template>
|
|
<Template label="8-to-1 (always)" treetype="template">
|
|
always @(<3-bit_select>, <input1>, <input2>, <input3>, <input4>, <input5>,
|
|
<input6>, <input7>, <input8>)
|
|
case (<3-bit_select>)
|
|
3'b000: <output> = <input1>;
|
|
3'b001: <output> = <input2>;
|
|
3'b010: <output> = <input3>;
|
|
3'b011: <output> = <input4>;
|
|
3'b100: <output> = <input5>;
|
|
3'b101: <output> = <input6>;
|
|
3'b110: <output> = <input7>;
|
|
3'b111: <output> = <input8>;
|
|
endcase
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Synchronous" treetype="folder">
|
|
<Template label="2-to-1" treetype="template">
|
|
always @(posedge <clock>)
|
|
if (<1-bit_select>)
|
|
<output_wire> <= <input1>;
|
|
else
|
|
<output_wire> <= <input0>;
|
|
</Template>
|
|
<Template label="4-to-1" treetype="template">
|
|
always @(posedge <clock>)
|
|
case (<2-bit_select>)
|
|
2'b00: <output> = <input1>;
|
|
2'b01: <output> = <input2>;
|
|
2'b10: <output> = <input3>;
|
|
2'b11: <output> = <input4>;
|
|
endcase
|
|
</Template>
|
|
<Template label="8-to-1" treetype="template">
|
|
always @(posedge <clock>)
|
|
case (<3-bit_select>)
|
|
3'b000: <output> = <input1>;
|
|
3'b001: <output> = <input2>;
|
|
3'b010: <output> = <input3>;
|
|
3'b011: <output> = <input4>;
|
|
3'b100: <output> = <input5>;
|
|
3'b101: <output> = <input6>;
|
|
3'b110: <output> = <input7>;
|
|
3'b111: <output> = <input8>;
|
|
endcase
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Shift Registers" treetype="folder">
|
|
<SubFolder label="Serial In, Serial Out" treetype="folder">
|
|
<Template label="Simple Shift Register" treetype="template">
|
|
parameter shift = <shift_length>;
|
|
|
|
reg [shift-1:0] <reg_name>;
|
|
|
|
always @(posedge <clock>)
|
|
<reg_name> <= {<input>, <reg_name>[shift-1:1]};
|
|
|
|
assign <output> = <reg_name>[0];
|
|
</Template>
|
|
<Template label="w/ CE" treetype="template">
|
|
parameter siso_shift = <shift_length>;
|
|
|
|
reg [siso_shift-1:0] <reg_name>;
|
|
|
|
always @(posedge <clock>)
|
|
if (<clock_enable>)
|
|
<reg_name> <= {<input>, <reg_name>[siso_shift-1:1]};
|
|
|
|
assign <output> = <reg_name>[0];
|
|
</Template>
|
|
<Template label="w/ CE and Async Active High Reset" treetype="template">
|
|
// Usage of asynchronous resets may negatively impact FPGA resources
|
|
// and timing. In general faster and smaller FPGA designs will
|
|
// result from not using asynchronous resets. Please refer to
|
|
// the Synthesis and Simulation Design Guide for more information.
|
|
|
|
// Note: By using a reset for this shift register, this cannot
|
|
// be placed in an SRL16 shift register LUT.
|
|
|
|
parameter siso_shift = <shift_length>;
|
|
|
|
reg [siso_shift-1:0] <reg_name>;
|
|
|
|
always @(posedge <clock> or posedge <reset>)
|
|
if (<reset>)
|
|
<reg_name> <= 0;
|
|
else if (<clock_enable>)
|
|
<reg_name> <= {<input>, <reg_name>[siso_shift-1:1]};
|
|
|
|
assign <output> = <reg_name>[0];
|
|
</Template>
|
|
<Template label="w/ CE and Async Active Low Reset" treetype="template">
|
|
// Usage of asynchronous resets may negatively impact FPGA resources
|
|
// and timing. In general faster and smaller FPGA designs will
|
|
// result from not using asynchronous resets. Please refer to
|
|
// the Synthesis and Simulation Design Guide for more information.
|
|
|
|
// Note: By using a reset for this shift register, this cannot
|
|
// be placed in an SRL16 shift register LUT.
|
|
|
|
parameter siso_shift = <shift_length>;
|
|
|
|
reg [siso_shift-1:0] <reg_name>;
|
|
|
|
always @(posedge <clock> or negedge <reset>)
|
|
if (!<reset>)
|
|
<reg_name> <= 0;
|
|
else if (<clock_enable>)
|
|
<reg_name> <= {<input>, <reg_name>[siso_shift-1:1]};
|
|
|
|
assign <output> = <reg_name>[0];
|
|
</Template>
|
|
<Template label="w/ CE and Sync Active High Reset" treetype="template">
|
|
// Note: By using a reset for this shift register, this cannot
|
|
// be placed in an SRL16 shift register LUT.
|
|
|
|
parameter siso_shift = <shift_length>;
|
|
|
|
reg [siso_shift-1:0] <reg_name>;
|
|
|
|
always @(posedge <clock>)
|
|
if (<reset>)
|
|
<reg_name> <= 0;
|
|
else if (<clock_enable>)
|
|
<reg_name> <= {<input>, <reg_name>[siso_shift-1:1]};
|
|
|
|
assign <output> = <reg_name>[0];
|
|
</Template>
|
|
<Template label="w/ CE and Sync Active Low Reset" treetype="template">
|
|
// Note: By using a reset for this shift register, this cannot
|
|
// be placed in an SRL16 shift register LUT.
|
|
|
|
parameter siso_shift = <shift_length>;
|
|
|
|
reg [siso_shift-1:0] <reg_name>;
|
|
|
|
always @(posedge <clock>)
|
|
if (!<reset>)
|
|
<reg_name> <= 0;
|
|
else if (<clock_enable>)
|
|
<reg_name> <= {<input>, <reg_name>[siso_shift-1:1]};
|
|
|
|
assign <output> = <reg_name>[0];
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Parallel In, Serial Out" treetype="folder">
|
|
<Template label="Simple Shift Register" treetype="template">
|
|
parameter piso_shift = <shift_width>;
|
|
|
|
reg [piso_shift-2:0] <reg_name>;
|
|
reg <output>;
|
|
|
|
always @(posedge <clock>)
|
|
if (<load_signal>) begin
|
|
<reg_name> <= <input>[piso_shift-1:1];
|
|
<output> <= <input>[0];
|
|
end
|
|
else begin
|
|
<reg_name> <= {1'b0, <reg_name>[piso_shift-2:1]};
|
|
<output> <= <reg_name>[0];
|
|
end
|
|
</Template>
|
|
<Template label="w/ CE" treetype="template">
|
|
parameter piso_shift = <shift_width>;
|
|
|
|
reg [piso_shift-2:0] <reg_name>;
|
|
reg <output>;
|
|
|
|
always @(posedge <clock>)
|
|
if (<load_signal>) begin
|
|
<reg_name> <= <input>[piso_shift-1:1];
|
|
<output> <= <input>[0];
|
|
end
|
|
else if (<clock_enable>) begin
|
|
<reg_name> <= {1'b0, <reg_name>[piso_shift-2:1]};
|
|
<output> <= <reg_name>[0];
|
|
end
|
|
</Template>
|
|
<Template label="w/ CE and Async Active High Reset" treetype="template">
|
|
// Usage of asynchronous resets may negatively impact FPGA resources
|
|
// and timing. In general faster and smaller FPGA designs will
|
|
// result from not using asynchronous resets. Please refer to
|
|
// the Synthesis and Simulation Design Guide for more information.
|
|
|
|
parameter piso_shift = <shift_width>;
|
|
|
|
reg [piso_shift-2:0] <reg_name>;
|
|
reg <output>;
|
|
|
|
always @(posedge <clock> or posedge <reset>)
|
|
if (<reset>) begin
|
|
<reg_name> <= 0;
|
|
<output> <= 1'b0;
|
|
end
|
|
else if (<load_signal>) begin
|
|
<reg_name> <= <input>[piso_shift-1:1];
|
|
<output> <= <input>[0];
|
|
end
|
|
else if (<clock_enable>) begin
|
|
<reg_name> <= {1'b0, <reg_name>[piso_shift-2:1]};
|
|
<output> <= <reg_name>[0];
|
|
end
|
|
</Template>
|
|
<Template label="w/ CE and Async Active Low Reset" treetype="template">
|
|
// Usage of asynchronous resets may negatively impact FPGA resources
|
|
// and timing. In general faster and smaller FPGA designs will
|
|
// result from not using asynchronous resets. Please refer to
|
|
// the Synthesis and Simulation Design Guide for more information.
|
|
|
|
parameter piso_shift = <shift_width>;
|
|
|
|
reg [piso_shift-2:0] <reg_name>;
|
|
reg <output>;
|
|
|
|
always @(posedge <clock> or negedge <reset>)
|
|
if (!<reset>) begin
|
|
<reg_name> <= 0;
|
|
<output> <= 1'b0;
|
|
end
|
|
else if (<load_signal>) begin
|
|
<reg_name> <= <input>[piso_shift-1:1];
|
|
<output> <= <input>[0];
|
|
end
|
|
else if (<clock_enable>) begin
|
|
<reg_name> <= {1'b0, <reg_name>[piso_shift-2:1]};
|
|
<output> <= <reg_name>[0];
|
|
end
|
|
</Template>
|
|
<Template label="w/ CE and Sync Active High Reset" treetype="template">
|
|
parameter piso_shift = <shift_width>;
|
|
|
|
reg [piso_shift-2:0] <reg_name>;
|
|
reg <output>;
|
|
|
|
always @(posedge <clock>)
|
|
if (<reset>) begin
|
|
<reg_name> <= 0;
|
|
<output> <= 1'b0;
|
|
end
|
|
else if (<load_signal>) begin
|
|
<reg_name> <= <input>[piso_shift-1:1];
|
|
<output> <= <input>[0];
|
|
end
|
|
else if (<clock_enable>) begin
|
|
<reg_name> <= {1'b0, <reg_name>[piso_shift-2:1]};
|
|
<output> <= <reg_name>[0];
|
|
end
|
|
</Template>
|
|
<Template label="w/ CE and Sync Active Low Reset" treetype="template">
|
|
parameter piso_shift = <shift_width>;
|
|
|
|
reg [piso_shift-2:0] <reg_name>;
|
|
reg <output>;
|
|
|
|
always @(posedge <clock>)
|
|
if (!<reset>) begin
|
|
<reg_name> <= 0;
|
|
<output> <= 1'b0;
|
|
end
|
|
else if (<load_signal>) begin
|
|
<reg_name> <= <input>[piso_shift-1:1];
|
|
<output> <= <input>[0];
|
|
end
|
|
else if (<clock_enable>) begin
|
|
<reg_name> <= {1'b0, <reg_name>[piso_shift-2:1]};
|
|
<output> <= <reg_name>[0];
|
|
end
|
|
</Template>
|
|
</SubFolder>
|
|
<Template label="Static Shift SRL16 (single)" treetype="template">
|
|
parameter clock_cycles = <number_of_clock_cycles>;
|
|
|
|
wire/reg <data_in>, <data_out>;
|
|
reg [clock_cycles-1:0] <shift_reg>;
|
|
|
|
always @(posedge <clock>)
|
|
if (<clock_enable>)
|
|
<shift_reg> <= {<shift_reg>[clock_cycles-2:0], <data_in>};
|
|
|
|
assign <data_out> = <shift_reg>[clock_cycles-1];
|
|
</Template>
|
|
<Template label="Static Shift SRL16 (bus)" treetype="template">
|
|
parameter clock_cycles = <number_of_clock_cycles>;
|
|
parameter data_width = <width_of_data>;
|
|
|
|
wire/reg [data_width-1:0] <data_in>, <data_out>;
|
|
reg [clock_cycles-1:0] <shift_reg> [data_width-1:0];
|
|
|
|
genvar i;
|
|
generate
|
|
for (i=0; i < data_width; i=i+1)
|
|
begin: <label>
|
|
always @(posedge <clock>)
|
|
if (<clock_enable>)
|
|
<shift_reg>[i] <= {<shift_reg>[i][clock_cycles-2:0], <data_in>[i]};
|
|
|
|
assign <data_out>[i] = <shift_reg>[i][clock_cycles-1];
|
|
end
|
|
endgenerate
|
|
</Template>
|
|
<Template label="Dynamic Shift SRL16 (single)" treetype="template">
|
|
// Shift register depth will be selectable from 1 (all zeroes) to 2**depth_select_bits (all ones) deep
|
|
parameter depth_select_bits = <number_of_depth_select_bits>;
|
|
|
|
wire/reg <data_in>, <data_out>;
|
|
wire/reg [depth_select_bits-1:0] <depth_select>;
|
|
reg [2**depth_select_bits-1:0] <shift_reg>;
|
|
|
|
always @(posedge <clock>)
|
|
if (<clock_enable>)
|
|
<shift_reg> <= {<shift_reg>[2**depth_select_bits-2:0], <data_in>};
|
|
|
|
assign <data_out> = <shift_reg>[<depth_select>];
|
|
</Template>
|
|
<Template label="Dynamic Shift SRL16 (bus)" treetype="template">
|
|
// Shift register depth will be selectable from 1 (all zeroes) to 2**depth_select_bits (all ones) deep
|
|
parameter depth_select_bits = <number_of_depth_select_bits>;
|
|
parameter data_width = <width_of_data>;
|
|
|
|
wire/reg [data_width-1:0] <data_in>, <data_out>;
|
|
wire/reg [depth_select_bits-1:0] <depth_select>;
|
|
reg [2**depth_select_bits-1:0] <shift_reg> [data_width-1:0];
|
|
|
|
genvar i;
|
|
generate
|
|
for (i=0; i < data_width; i=i+1)
|
|
begin: <label>
|
|
always @(posedge <clock>)
|
|
if (<clock_enable>)
|
|
<shift_reg>[i] <= {<shift_reg>[i][2**depth_select_bits-2:0], <data_in>[i]};
|
|
|
|
assign <data_out>[i] = <shift_reg>[i][<depth_select>];
|
|
end
|
|
endgenerate
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Logical Shifters" treetype="folder">
|
|
<Template label="2-bit select" treetype="template">
|
|
reg [3:0] <data_out>;
|
|
|
|
always @*
|
|
case (<2-bit_select>)
|
|
2'b00 : <data_out> = <data_in>;
|
|
2'b01 : <data_out> = <data_in> << 1;
|
|
2'b10 : <data_out> = <data_in> << 2;
|
|
default: <data_out> = <data_in> << 3;
|
|
endcase
|
|
</Template>
|
|
<Template label="3-bit select" treetype="template">
|
|
reg [7:0] <data_out>;
|
|
|
|
always @*
|
|
case (<3-bit_select>)
|
|
3'b000 : <data_out> = <data_in>;
|
|
3'b001 : <data_out> = <data_in> << 1;
|
|
3'b010 : <data_out> = <data_in> << 2;
|
|
3'b011 : <data_out> = <data_in> << 3;
|
|
3'b100 : <data_out> = <data_in> << 4;
|
|
3'b101 : <data_out> = <data_in> << 5;
|
|
3'b110 : <data_out> = <data_in> << 6;
|
|
default: <data_out> = <data_in> << 7;
|
|
endcase
|
|
</Template>
|
|
<Template label="4-bit select" treetype="template">
|
|
reg [15:0] <data_out>;
|
|
|
|
always @*
|
|
case (<4-bit_select>)
|
|
4'b0000: <data_out> = <data_in>;
|
|
4'b0001: <data_out> = <data_in> << 1;
|
|
4'b0010: <data_out> = <data_in> << 2;
|
|
4'b0011: <data_out> = <data_in> << 3;
|
|
4'b0100: <data_out> = <data_in> << 4;
|
|
4'b0101: <data_out> = <data_in> << 5;
|
|
4'b0110: <data_out> = <data_in> << 6;
|
|
4'b0111: <data_out> = <data_in> << 7;
|
|
4'b1000: <data_out> = <data_in> << 8;
|
|
4'b1001: <data_out> = <data_in> << 9;
|
|
4'b1010: <data_out> = <data_in> << 10;
|
|
4'b1011: <data_out> = <data_in> << 11;
|
|
4'b1100: <data_out> = <data_in> << 12;
|
|
4'b1101: <data_out> = <data_in> << 13;
|
|
4'b1110: <data_out> = <data_in> << 14;
|
|
default: <data_out> = <data_in> << 15;
|
|
endcase
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Arithmetic" treetype="folder">
|
|
<SubFolder label="Adder" treetype="folder">
|
|
<SubFolder label="Combinatorial" treetype="folder">
|
|
<Template label="Simple Unsigned Adder" treetype="template">
|
|
parameter ADDER_WIDTH = <adder_bit_width>;
|
|
|
|
wire [ADDER_WIDTH-1:0] <a_input>;
|
|
wire [ADDER_WIDTH-1:0] <b_input>;
|
|
wire [ADDER_WIDTH-1:0] <sum>;
|
|
|
|
assign <sum> = <a_input> + <b_input>;
|
|
</Template>
|
|
<Template label="Unsigned Adder w/ Carry-out" treetype="template">
|
|
parameter ADDER_WIDTH = <adder_bit_width>;
|
|
|
|
wire [ADDER_WIDTH-1:0] <a_input>;
|
|
wire [ADDER_WIDTH-1:0] <b_input>;
|
|
wire <carry_out>;
|
|
wire [ADDER_WIDTH-1:0] <sum>;
|
|
|
|
assign {<carry_out>, <sum>} = <a_input> + <b_input>;
|
|
</Template>
|
|
<Template label="Simple Signed Adder" treetype="template">
|
|
parameter ADDER_WIDTH = <adder_bit_width>;
|
|
|
|
wire signed [ADDER_WIDTH-1:0] <a_input>;
|
|
wire signed [ADDER_WIDTH-1:0] <b_input>;
|
|
wire signed [ADDER_WIDTH-1:0] <sum>;
|
|
|
|
assign <sum> = <a_input> + <b_input>;
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Sequential" treetype="folder">
|
|
<Template label="Simple Unsigned Adder" treetype="template">
|
|
parameter ADDER_WIDTH = <adder_bit_width>;
|
|
|
|
reg [ADDER_WIDTH-1:0] <sum>;
|
|
|
|
always @(posedge <CLK>)
|
|
<sum> <= <a_input> + <b_input>;
|
|
</Template>
|
|
<Template label="Unsigned Adder w/ Carry-out" treetype="template">
|
|
parameter ADDER_WIDTH = <adder_bit_width>;
|
|
|
|
reg [ADDER_WIDTH-1:0] <sum>;
|
|
reg <carry_out>;
|
|
|
|
always @(posedge <CLK>)
|
|
{<carry_out>, <sum>} <= <a_input> + <b_input>;
|
|
</Template>
|
|
<Template label="Simple Signed Adder" treetype="template">
|
|
parameter ADDER_WIDTH = <adder_bit_width>;
|
|
|
|
reg signed [ADDER_WIDTH-1:0] <sum>;
|
|
|
|
always @(posedge <CLK>)
|
|
<sum> <= <a_input> + <b_input>;
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Subtractor" treetype="folder">
|
|
<Template label="Simple Subtractor" treetype="template">
|
|
parameter SUB_WIDTH = <sub_bit_width>;
|
|
|
|
wire [SUB_WIDTH-1:0] <a_input>;
|
|
wire [SUB_WIDTH-1:0] <b_input>;
|
|
wire [SUB_WIDTH-1:0] <difference>;
|
|
|
|
assign <difference> = <a_input> - <b_input>;
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Add/Sub" treetype="folder">
|
|
<Template label="Simple Adder/Subtractor" treetype="template">
|
|
parameter ADDSUB_WIDTH = <addsub_bit_width>;
|
|
|
|
wire [ADDSUB_WIDTH-1:0] <a_input>;
|
|
wire [ADDSUB_WIDTH-1:0] <b_input>;
|
|
reg [ADDSUB_WIDTH-1:0] <addsub_output>;
|
|
|
|
always @*
|
|
if (<add_sub>)
|
|
<addsub_output> = <a_input> + <b_input>;
|
|
else
|
|
<addsub_output> = <a_input> - <b_input>;
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Divider" treetype="folder">
|
|
<Template label="Divide by 2" treetype="template">
|
|
parameter DIV_WIDTH = <div_bit_width>;
|
|
|
|
wire [DIV_WIDTH-1:0] <div_input>;
|
|
wire [DIV_WIDTH-1:0] <dividend>;
|
|
|
|
assign <dividend> = <div_input> / 2;
|
|
</Template>
|
|
<Template label="Divide by 4" treetype="template">
|
|
parameter DIV_WIDTH = <div_bit_width>;
|
|
|
|
wire [DIV_WIDTH-1:0] <div_input>;
|
|
wire [DIV_WIDTH-1:0] <dividend>;
|
|
|
|
assign <dividend> = <div_input> / 4;
|
|
</Template>
|
|
<Template label="Divide by 8" treetype="template">
|
|
parameter DIV_WIDTH = <div_bit_width>;
|
|
|
|
wire [DIV_WIDTH-1:0] <div_input>;
|
|
wire [DIV_WIDTH-1:0] <dividend>;
|
|
|
|
assign <dividend> = <div_input> / 8;
|
|
</Template>
|
|
<Template label="Divide by 16" treetype="template">
|
|
parameter DIV_WIDTH = <div_bit_width>;
|
|
|
|
wire [DIV_WIDTH-1:0] <div_input>;
|
|
wire [DIV_WIDTH-1:0] <dividend>;
|
|
|
|
assign <dividend> = <div_input> / 16;
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Multiplier" treetype="folder">
|
|
<Template label="Asynchronous Multiplier" treetype="template">
|
|
parameter MULT_INPUT_WIDTH = <mult_input_bit_width>;
|
|
|
|
wire [MULT_INPUT_WIDTH-1:0] <a_input>;
|
|
wire [MULT_INPUT_WIDTH-1:0] <b_input>;
|
|
wire [MULT_INPUT_WIDTH*2-1:0] <product>;
|
|
|
|
assign <product> = <a_input> * <b_input>;
|
|
</Template>
|
|
<Template label="18x18 Synchronous Multiplier" treetype="template">
|
|
wire [17:0] <a_input>;
|
|
wire [17:0] <b_input>;
|
|
reg [35:0] <product>;
|
|
|
|
always @(posedge <clock>)
|
|
<product> <= <a_input> * <b_input>;
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Comparators" treetype="folder">
|
|
<Template label="Equal" treetype="template">
|
|
reg <output>;
|
|
|
|
always @(posedge <clock>)
|
|
if (<input1> == <input2>)
|
|
<output> <= 1'b1;
|
|
else
|
|
<output> <= 1'b0;
|
|
</Template>
|
|
<Template label="Not Equal" treetype="template">
|
|
reg <output>;
|
|
|
|
always @(posedge <clock>)
|
|
if (<input1> != <input2>)
|
|
<output> <= 1'b1;
|
|
else
|
|
<output> <= 1'b0;
|
|
</Template>
|
|
<Template label="Greater-than" treetype="template">
|
|
reg <output>;
|
|
|
|
always @(posedge <clock>)
|
|
if (<input1> > <input2>)
|
|
<output> <= 1'b1;
|
|
else
|
|
<output> <= 1'b0;
|
|
</Template>
|
|
<Template label="Less-than" treetype="template">
|
|
reg <output>;
|
|
|
|
always @(posedge <clock>)
|
|
if (<input1> < <input2>)
|
|
<output> <= 1'b1;
|
|
else
|
|
<output> <= 1'b0;
|
|
</Template>
|
|
<Template label="Greater-than or Equal" treetype="template">
|
|
reg <output>;
|
|
|
|
always @(posedge <clock>)
|
|
if (<input1> >= <input2>)
|
|
<output> <= 1'b1;
|
|
else
|
|
<output> <= 1'b0;
|
|
</Template>
|
|
<Template label="Less-than or equal" treetype="template">
|
|
reg <output>;
|
|
|
|
always @(posedge <clock>)
|
|
if (<input1> <= <input2>)
|
|
<output> <= 1'b1;
|
|
else
|
|
<output> <= 1'b0;
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Tristate Buffers" treetype="folder">
|
|
<SubFolder label="Active High" treetype="folder">
|
|
<Template label="Using Always" treetype="template">
|
|
always @(<enable> or <data>)
|
|
if (<enable>)
|
|
<output_reg> = <data>;
|
|
else
|
|
<output_reg> = 1'bz;
|
|
</Template>
|
|
<Template label="Using Wire Assignment" treetype="template">
|
|
assign <output_wire> = <enable> ? <data> : 1'bz;
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Active Low" treetype="folder">
|
|
<Template label="Using Always" treetype="template">
|
|
always @(<enable> or <data>)
|
|
if (!<enable>)
|
|
<output_reg> = <data>;
|
|
else
|
|
<output_reg> = 1'bz;
|
|
</Template>
|
|
<Template label="Using Wire Assignment" treetype="template">
|
|
assign <output_wire> = <enable> ? 1'bz : <data>;
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Counters" treetype="folder">
|
|
<SubFolder label="Binary" treetype="folder">
|
|
<SubFolder label="Up Counters" treetype="folder">
|
|
<Template label="Simple Counter" treetype="template">
|
|
reg [<upper>:0] <reg_name>;
|
|
|
|
always @(posedge <clock>)
|
|
<reg_name> <= <reg_name> + 1;
|
|
</Template>
|
|
<Template label="w/ CE" treetype="template">
|
|
reg [<upper>:0] <reg_name>;
|
|
|
|
always @(posedge <clock>)
|
|
if (<clock_enable>)
|
|
<reg_name> <= <reg_name> + 1;
|
|
</Template>
|
|
<Template label="w/ CE and Async Active High Reset" treetype="template">
|
|
// Usage of asynchronous resets may negatively impact FPGA resources
|
|
// and timing. In general faster and smaller FPGA designs will
|
|
// result from not using asynchronous resets. Please refer to
|
|
// the Synthesis and Simulation Design Guide for more information.
|
|
|
|
reg [<upper>:0] <reg_name>;
|
|
|
|
always @(posedge <clock> or posedge <reset>)
|
|
if (<reset>)
|
|
<reg_name> <= 0;
|
|
else if (<clock_enable>)
|
|
<reg_name> <= <reg_name> + 1;
|
|
</Template>
|
|
<Template label="w/ CE and Async Active Low Reset" treetype="template">
|
|
// Usage of asynchronous resets may negatively impact FPGA resources
|
|
// and timing. In general faster and smaller FPGA designs will
|
|
// result from not using asynchronous resets. Please refer to
|
|
// the Synthesis and Simulation Design Guide for more information.
|
|
|
|
reg [<upper>:0] <reg_name>;
|
|
|
|
always @(posedge <clock> or negedge <reset>)
|
|
if (!<reset>)
|
|
<reg_name> <= 0;
|
|
else if (<clock_enable>)
|
|
<reg_name> <= <reg_name> + 1;
|
|
</Template>
|
|
<Template label="w/ Load, CE and Async Active High Reset" treetype="template">
|
|
// Usage of asynchronous resets may negatively impact FPGA resources
|
|
// and timing. In general faster and smaller FPGA designs will
|
|
// result from not using asynchronous resets. Please refer to
|
|
// the Synthesis and Simulation Design Guide for more information.
|
|
|
|
reg [<upper>:0] <reg_name>;
|
|
|
|
always @(posedge <clock> or posedge <reset>)
|
|
if (<reset>)
|
|
<reg_name> <= 0;
|
|
else if (<clock_enable>)
|
|
if (<load_enable>)
|
|
<reg_name> <= <load_signal_or_value>;
|
|
else
|
|
<reg_name> <= <reg_name> + 1;
|
|
</Template>
|
|
<Template label="w/ Load, CE and Async Active Low Reset" treetype="template">
|
|
// Usage of asynchronous resets may negatively impact FPGA resources
|
|
// and timing. In general faster and smaller FPGA designs will
|
|
// result from not using asynchronous resets. Please refer to
|
|
// the Synthesis and Simulation Design Guide for more information.
|
|
|
|
reg [<upper>:0] <reg_name>;
|
|
|
|
always @(posedge <clock> or negedge <reset>)
|
|
if (!<reset>)
|
|
<reg_name> <= 0;
|
|
else if (<clock_enable>)
|
|
if (<load_enable>)
|
|
<reg_name> <= <load_signal_or_value>;
|
|
else
|
|
<reg_name> <= <reg_name> + 1;
|
|
</Template>
|
|
<Template label="w/ CE and Sync Active High Reset" treetype="template">
|
|
reg [<upper>:0] <reg_name>;
|
|
|
|
always @(posedge <clock>)
|
|
if (<reset>)
|
|
<reg_name> <= 0;
|
|
else if (<clock_enable>)
|
|
<reg_name> <= <reg_name> + 1;
|
|
</Template>
|
|
<Template label="w/ CE and Sync Active Low Reset" treetype="template">
|
|
reg [<upper>:0] <reg_name>;
|
|
|
|
always @(posedge <clock>)
|
|
if (!<reset>)
|
|
<reg_name> <= 0;
|
|
else if (<clock_enable>)
|
|
<reg_name> <= <reg_name> + 1;
|
|
</Template>
|
|
<Template label="w/ Load, CE and Sync Active High Reset" treetype="template">
|
|
reg [<upper>:0] <reg_name>;
|
|
|
|
always @(posedge <clock>)
|
|
if (<reset>)
|
|
<reg_name> <= 0;
|
|
else if (<clock_enable>)
|
|
if (<load_enable>)
|
|
<reg_name> <= <load_signal_or_value>;
|
|
else
|
|
<reg_name> <= <reg_name> + 1;
|
|
</Template>
|
|
<Template label="w/ Load, CE and Sync Active Low Reset" treetype="template">
|
|
reg [<upper>:0] <reg_name>;
|
|
|
|
always @(posedge <clock>)
|
|
if (!<reset>)
|
|
<reg_name> <= 0;
|
|
else if (<clock_enable>)
|
|
if (<load_enable>)
|
|
<reg_name> <= <load_signal_or_value>;
|
|
else
|
|
<reg_name> <= <reg_name> + 1;
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Up/Down Counters" treetype="folder">
|
|
<Template label="Simple Counter" treetype="template">
|
|
reg [<upper>:0] <reg_name>;
|
|
|
|
always @(posedge <clock>)
|
|
if (<up_down>)
|
|
<reg_name> <= <reg_name> + 1;
|
|
else
|
|
<reg_name> <= <reg_name> - 1;
|
|
</Template>
|
|
<Template label="w/ CE" treetype="template">
|
|
reg [<upper>:0] <reg_name>;
|
|
|
|
always @(posedge <clock>)
|
|
if (<clock_enable>)
|
|
if (<up_down>)
|
|
<reg_name> <= <reg_name> + 1;
|
|
else
|
|
<reg_name> <= <reg_name> - 1;
|
|
</Template>
|
|
<Template label="w/ CE and Async Active High Reset" treetype="template">
|
|
// Usage of asynchronous resets may negatively impact FPGA resources
|
|
// and timing. In general faster and smaller FPGA designs will
|
|
// result from not using asynchronous resets. Please refer to
|
|
// the Synthesis and Simulation Design Guide for more information.
|
|
|
|
reg [<upper>:0] <reg_name>;
|
|
|
|
always @(posedge <clock> or posedge <reset>)
|
|
if (<reset>)
|
|
<reg_name> <= 0;
|
|
else if (<clock_enable>)
|
|
if (<up_down>)
|
|
<reg_name> <= <reg_name> + 1;
|
|
else
|
|
<reg_name> <= <reg_name> - 1;
|
|
</Template>
|
|
<Template label="w/ CE and Async Active Low Reset" treetype="template">
|
|
// Usage of asynchronous resets may negatively impact FPGA resources
|
|
// and timing. In general faster and smaller FPGA designs will
|
|
// result from not using asynchronous resets. Please refer to
|
|
// the Synthesis and Simulation Design Guide for more information.
|
|
|
|
reg [<upper>:0] <reg_name>;
|
|
|
|
always @(posedge <clock> or negedge <reset>)
|
|
if (!<reset>)
|
|
<reg_name> <= 0;
|
|
else if (<clock_enable>)
|
|
if (<up_down>)
|
|
<reg_name> <= <reg_name> + 1;
|
|
else
|
|
<reg_name> <= <reg_name> - 1;
|
|
</Template>
|
|
<Template label="w/ Load, CE and Async Active High Reset" treetype="template">
|
|
// Usage of asynchronous resets may negatively impact FPGA resources
|
|
// and timing. In general faster and smaller FPGA designs will
|
|
// result from not using asynchronous resets. Please refer to
|
|
// the Synthesis and Simulation Design Guide for more information.
|
|
|
|
reg [<upper>:0] <reg_name>;
|
|
|
|
always @(posedge <clock> or posedge <reset>)
|
|
if (<reset>)
|
|
<reg_name> <= 0;
|
|
else if (<clock_enable>)
|
|
if (<load_enable>)
|
|
<reg_name> <= <load_signal_or_value>;
|
|
else if (<up_down>)
|
|
<reg_name> <= <reg_name> + 1;
|
|
else
|
|
<reg_name> <= <reg_name> - 1;
|
|
</Template>
|
|
<Template label="w/ Load, CE and Async Active Low Reset" treetype="template">
|
|
// Usage of asynchronous resets may negatively impact FPGA resources
|
|
// and timing. In general faster and smaller FPGA designs will
|
|
// result from not using asynchronous resets. Please refer to
|
|
// the Synthesis and Simulation Design Guide for more information.
|
|
|
|
reg [<upper>:0] <reg_name>;
|
|
|
|
always @(posedge <clock> or negedge <reset>)
|
|
if (!<reset>)
|
|
<reg_name> <= 0;
|
|
else if (<clock_enable>)
|
|
if (<load_enable>)
|
|
<reg_name> <= <load_signal_or_value>;
|
|
else if (<up_down>)
|
|
<reg_name> <= <reg_name> + 1;
|
|
else
|
|
<reg_name> <= <reg_name> - 1;
|
|
</Template>
|
|
<Template label="w/ CE and Sync Active High Reset" treetype="template">
|
|
reg [<upper>:0] <reg_name>;
|
|
|
|
always @(posedge <clock>)
|
|
if (<reset>)
|
|
<reg_name> <= 0;
|
|
else if (<clock_enable>)
|
|
if (<up_down>)
|
|
<reg_name> <= <reg_name> + 1;
|
|
else
|
|
<reg_name> <= <reg_name> - 1;
|
|
</Template>
|
|
<Template label="w/ CE and Sync Active Low Reset" treetype="template">
|
|
reg [<upper>:0] <reg_name>;
|
|
|
|
always @(posedge <clock>)
|
|
if (!<reset>)
|
|
<reg_name> <= 0;
|
|
else if (<clock_enable>)
|
|
if (<up_down>)
|
|
<reg_name> <= <reg_name> + 1;
|
|
else
|
|
<reg_name> <= <reg_name> - 1;
|
|
</Template>
|
|
<Template label="w/ Load, CE and Sync Active High Reset" treetype="template">
|
|
reg [<upper>:0] <reg_name>;
|
|
|
|
always @(posedge <clock>)
|
|
if (<reset>)
|
|
<reg_name> <= 0;
|
|
else if (<clock_enable>)
|
|
if (<load_enable>)
|
|
<reg_name> <= <load_signal_or_value>;
|
|
else if (<up_down>)
|
|
<reg_name> <= <reg_name> + 1;
|
|
else
|
|
<reg_name> <= <reg_name> - 1;
|
|
</Template>
|
|
<Template label="w/ Load, CE and Sync Active Low Reset" treetype="template">
|
|
reg [<upper>:0] <reg_name>;
|
|
|
|
always @(posedge <clock>)
|
|
if (!<reset>)
|
|
<reg_name> <= 0;
|
|
else if (<clock_enable>)
|
|
if (<load_enable>)
|
|
<reg_name> <= <load_signal_or_value>;
|
|
else if (<up_down>)
|
|
<reg_name> <= <reg_name> + 1;
|
|
else
|
|
<reg_name> <= <reg_name> - 1;
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Down Counters" treetype="folder">
|
|
<Template label="Simple Counter" treetype="template">
|
|
reg [<upper>:0] <reg_name>;
|
|
|
|
always @(posedge <clock>)
|
|
<reg_name> <= <reg_name> - 1;
|
|
</Template>
|
|
<Template label="w/ CE" treetype="template">
|
|
reg [<upper>:0] <reg_name>;
|
|
|
|
always @(posedge <clock>)
|
|
if (<clock_enable>)
|
|
<reg_name> <= <reg_name> - 1;
|
|
</Template>
|
|
<Template label="w/ CE and Async Active High Reset" treetype="template">
|
|
// Usage of asynchronous resets may negatively impact FPGA resources
|
|
// and timing. In general faster and smaller FPGA designs will
|
|
// result from not using asynchronous resets. Please refer to
|
|
// the Synthesis and Simulation Design Guide for more information.
|
|
|
|
reg [<upper>:0] <reg_name>;
|
|
|
|
always @(posedge <clock> or posedge <reset>)
|
|
if (<reset>)
|
|
<reg_name> <= 0;
|
|
else if (<clock_enable>)
|
|
<reg_name> <= <reg_name> - 1;
|
|
</Template>
|
|
<Template label="w/ CE and Async Active Low Reset" treetype="template">
|
|
// Usage of asynchronous resets may negatively impact FPGA resources
|
|
// and timing. In general faster and smaller FPGA designs will
|
|
// result from not using asynchronous resets. Please refer to
|
|
// the Synthesis and Simulation Design Guide for more information.
|
|
|
|
reg [<upper>:0] <reg_name>;
|
|
|
|
always @(posedge <clock> or negedge <reset>)
|
|
if (!<reset>)
|
|
<reg_name> <= 0;
|
|
else if (<clock_enable>)
|
|
<reg_name> <= <reg_name> - 1;
|
|
</Template>
|
|
<Template label="w/ Load, CE and Async Active High Reset" treetype="template">
|
|
// Usage of asynchronous resets may negatively impact FPGA resources
|
|
// and timing. In general faster and smaller FPGA designs will
|
|
// result from not using asynchronous resets. Please refer to
|
|
// the Synthesis and Simulation Design Guide for more information.
|
|
|
|
reg [<upper>:0] <reg_name>;
|
|
|
|
always @(posedge <clock> or posedge <reset>)
|
|
if (<reset>)
|
|
<reg_name> <= 0;
|
|
else if (<clock_enable>)
|
|
if (<load_enable>)
|
|
<reg_name> <= <load_signal_or_value>;
|
|
else
|
|
<reg_name> <= <reg_name> - 1;
|
|
</Template>
|
|
<Template label="w/ Load, CE and Async Active Low Reset" treetype="template">
|
|
// Usage of asynchronous resets may negatively impact FPGA resources
|
|
// and timing. In general faster and smaller FPGA designs will
|
|
// result from not using asynchronous resets. Please refer to
|
|
// the Synthesis and Simulation Design Guide for more information.
|
|
|
|
reg [<upper>:0] <reg_name>;
|
|
|
|
always @(posedge <clock> or negedge <reset>)
|
|
if (!<reset>)
|
|
<reg_name> <= 0;
|
|
else if (<clock_enable>)
|
|
if (<load_enable>)
|
|
<reg_name> <= <load_signal_or_value>;
|
|
else
|
|
<reg_name> <= <reg_name> - 1;
|
|
</Template>
|
|
<Template label="w/ CE and Sync Active High Reset" treetype="template">
|
|
reg [<upper>:0] <reg_name>;
|
|
|
|
always @(posedge <clock>)
|
|
if (<reset>)
|
|
<reg_name> <= 0;
|
|
else if (<clock_enable>)
|
|
<reg_name> <= <reg_name> - 1;
|
|
</Template>
|
|
<Template label="w/ CE and Sync Active Low Reset" treetype="template">
|
|
reg [<upper>:0] <reg_name>;
|
|
|
|
always @(posedge <clock>)
|
|
if (!<reset>)
|
|
<reg_name> <= 0;
|
|
else if (<clock_enable>)
|
|
<reg_name> <= <reg_name> - 1;
|
|
</Template>
|
|
<Template label="w/ Load, CE and Sync Active High Reset" treetype="template">
|
|
reg [<upper>:0] <reg_name>;
|
|
|
|
always @(posedge <clock>)
|
|
if (<reset>)
|
|
<reg_name> <= 0;
|
|
else if (<clock_enable>)
|
|
if (<load_enable>)
|
|
<reg_name> <= <load_signal_or_value>;
|
|
else
|
|
<reg_name> <= <reg_name> - 1;
|
|
</Template>
|
|
<Template label="w/ Load, CE and Sync Active Low Reset" treetype="template">
|
|
reg [<upper>:0] <reg_name>;
|
|
|
|
always @(posedge <clock>)
|
|
if (!<reset>)
|
|
<reg_name> <= 0;
|
|
else if (<clock_enable>)
|
|
if (<load_enable>)
|
|
<reg_name> <= <load_signal_or_value>;
|
|
else
|
|
<reg_name> <= <reg_name> - 1;
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Gray Code" treetype="folder">
|
|
<Template label="w/ CE and Sync Active High Reset" treetype="template">
|
|
parameter gray_width = <gray_value_width>;
|
|
|
|
reg [gray_width-1:0] <binary_value>;
|
|
reg [gray_width-1:0] <gray_value>;
|
|
|
|
always @(posedge <clock>)
|
|
if (<reset>) begin
|
|
<binary_value> <= {{gray_width{1'b0}}, 1'b1};
|
|
<gray_value> <= {gray_width{1'b0}};
|
|
end
|
|
else if (<clock_enable>) begin
|
|
<binary_value> <= <binary_value> + 1;
|
|
<gray_value> <= (<binary_value> >> 1) ^ <binary_value>;
|
|
end
|
|
parameter gray_width = <gray_value_width>;
|
|
|
|
reg [gray_width-1:0] <binary_value>;
|
|
reg [gray_width-1:0] <gray_value>;
|
|
|
|
always @(posedge <clock>)
|
|
if (<reset>) begin
|
|
<binary_value> <= {{gray_width{1'b0}}, 1'b1};
|
|
<gray_value> <= {gray_width{1'b0}};
|
|
end
|
|
else if (<clock_enable>) begin
|
|
<binary_value> <= <binary_value> + 1;
|
|
<gray_value> <= (<binary_value> >> 1) ^ <binary_value>;
|
|
end
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="LFSR" treetype="folder">
|
|
<Template label="4-bit w/ CE and Sync Active High Reset" treetype="template">
|
|
reg [3:0] <reg_name>;
|
|
|
|
always @(posedge <clock>)
|
|
if (<reset>)
|
|
<reg_name> <= 4'h0;
|
|
else if (<clock_enable>) begin
|
|
<reg_name>[3:1] <= <reg_name>[2:0];
|
|
<reg_name>[0] <= ~^<reg_name>[3:2];
|
|
end
|
|
</Template>
|
|
<Template label="8-bit w/ CE and Sync Active High Reset" treetype="template">
|
|
reg [7:0] <reg_name>;
|
|
|
|
always @(posedge <clock>)
|
|
if (<reset>)
|
|
<reg_name> <= 8'h00;
|
|
else if (<clock_enable>) begin
|
|
<reg_name>[7:1] <= <reg_name>[6:0];
|
|
<reg_name>[0] <= ~^{<reg_name>[7], <reg_name>[5:3]};
|
|
end
|
|
</Template>
|
|
<Template label="16-bit w/ CE and Sync Active High Reset" treetype="template">
|
|
reg [15:0] <reg_name>;
|
|
|
|
always @(posedge <clock>)
|
|
if (<reset>)
|
|
<reg_name> <= 16'h0000;
|
|
else if (<clock_enable>) begin
|
|
<reg_name>[15:1] <= <reg_name>[14:0];
|
|
<reg_name>[0] <= ~^{<reg_name>[15:14], <reg_name>[12], <reg_name>[3]};
|
|
end
|
|
</Template>
|
|
<Template label="32-bit w/ CE and Sync Active High Reset" treetype="template">
|
|
reg [31:0] <reg_name>;
|
|
|
|
always @(posedge <clock>)
|
|
if (<reset>)
|
|
<reg_name> <= 32'h00000000;
|
|
else if (<clock_enable>) begin
|
|
<reg_name>[31:1] <= <reg_name>[30:0];
|
|
<reg_name>[0] <= ~^{<reg_name>[31], <reg_name>[21], <reg_name>[1:0]};
|
|
end
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="RAM" treetype="folder">
|
|
<SubFolder label="BlockRAM" treetype="folder">
|
|
<SubFolder label="Single Port" treetype="folder">
|
|
<Template label="Read First Mode" treetype="template">
|
|
parameter RAM_WIDTH = <ram_width>;
|
|
parameter RAM_ADDR_BITS = <ram_addr_bits>;
|
|
|
|
(* RAM_STYLE="{AUTO | BLOCK | BLOCK_POWER1 | BLOCK_POWER2}" *)
|
|
reg [RAM_WIDTH-1:0] <ram_name> [(2**RAM_ADDR_BITS)-1:0];
|
|
reg [RAM_WIDTH-1:0] <output_data>;
|
|
|
|
<reg_or_wire> [RAM_ADDR_BITS-1:0] <address>;
|
|
<reg_or_wire> [RAM_WIDTH-1:0] <input_data>;
|
|
|
|
// The forllowing code is only necessary if you wish to initialize the RAM
|
|
// contents via an external file (use $readmemb for binary data)
|
|
initial
|
|
$readmemh("<data_file_name>", <ram_name>, <begin_address>, <end_address>);
|
|
|
|
always @(posedge <clock>)
|
|
if (<ram_enable>) begin
|
|
if (<write_enable>)
|
|
<ram_name>[<address>] <= <input_data>;
|
|
<output_data> <= <ram_name>[<address>];
|
|
end
|
|
</Template>
|
|
<SubFolder label="Byte-wide Write Enable" treetype="folder">
|
|
<Template label="Read First Mode w/ 2-bit write enable (for device families older than Virtex-6 and Spartan-6)" treetype="template">
|
|
// Important!
|
|
// This is the mandatory coding style to describe byte-write enable functionality for device families older than Virtex-6 and
|
|
// Spartan-6. for Virtex-6, Spartan-6, and newer device families, please refer to the improved templates recommended for those
|
|
// families.
|
|
//
|
|
parameter DATA_WIDTH = 16;
|
|
parameter ADDR_WIDTH = <num_addr_bits>;
|
|
|
|
reg/wire [DATA_WIDTH-1:0] <data_in>;
|
|
reg/wire [ADDR_WIDTH-1:0] <address>;
|
|
reg/wire [1:0] <write_enable>;
|
|
reg/wire <clock>;
|
|
reg/wire <ram_enable>;
|
|
reg [DATA_WIDTH-1:0] <data_out>;
|
|
|
|
(* RAM_STYLE="{AUTO | BLOCK | BLOCK_POWER1 | BLOCK_POWER2}" *)
|
|
reg [DATA_WIDTH-1:0] <ram_name> [2**ADDR_WIDTH-1:0];
|
|
reg [(DATA_WIDTH/2)-1:0] di0, di1;
|
|
|
|
// The forllowing code is only necessary if you wish to initialize the RAM
|
|
// contents via an external file (use $readmemb for binary data)
|
|
initial
|
|
$readmemh("<data_file_name>", <ram_name>, <begin_address>, <end_address>);
|
|
|
|
always @(<write_enable>, <data_in>) begin
|
|
if (<write_enable>[0])
|
|
di0 = <data_in>[(DATA_WIDTH/2)-1:0];
|
|
else
|
|
di0 = <ram_name>[<address>][(DATA_WIDTH/2)-1:0];
|
|
if (<write_enable>[1])
|
|
di1 = <data_in>[DATA_WIDTH-1:DATA_WIDTH/2];
|
|
else
|
|
di1 = <ram_name>[<address>][DATA_WIDTH-1:DATA_WIDTH/2];
|
|
end
|
|
|
|
always @(posedge <clock>)
|
|
if (<ram_enable>) begin
|
|
<data_out> <= <ram_name>[<address>];
|
|
<ram_name>[<address>] <= {di1,di0};
|
|
end
|
|
</Template>
|
|
<Template label="Read First Mode w/ 4-bit write enable (for device families older than Virtex-6 and Spartan-6)" treetype="template">
|
|
// Important!
|
|
// This is the mandatory coding style to describe byte-write enable functionality for device families older than Virtex-6 and
|
|
// Spartan-6. for Virtex-6, Spartan-6, and newer device families, please refer to the improved templates recommended for those
|
|
// families.
|
|
//
|
|
parameter DATA_WIDTH = 32;
|
|
parameter ADDR_WIDTH = <num_addr_bits>;
|
|
|
|
reg/wire [DATA_WIDTH-1:0] <data_in>;
|
|
reg/wire [ADDR_WIDTH-1:0] <address>;
|
|
reg/wire [3:0] <write_enable>;
|
|
reg/wire <clock>;
|
|
reg/wire <ram_enable>;
|
|
reg [DATA_WIDTH-1:0] <data_out>;
|
|
|
|
(* RAM_STYLE="{AUTO | BLOCK | BLOCK_POWER1 | BLOCK_POWER2}" *)
|
|
reg [DATA_WIDTH-1:0] <ram_name> [2**ADDR_WIDTH-1:0];
|
|
reg [(DATA_WIDTH/4)-1:0] di0, di1, di2, di3;
|
|
|
|
// The forllowing code is only necessary if you wish to initialize the RAM
|
|
// contents via an external file (use $readmemb for binary data)
|
|
initial
|
|
$readmemh("<data_file_name>", <ram_name>, <begin_address>, <end_address>);
|
|
|
|
always @(<write_enable>, <data_in>) begin
|
|
if (<write_enable>[0])
|
|
di0 = <data_in>[(DATA_WIDTH/4)-1:0];
|
|
else
|
|
di0 = <ram_name>[<address>][(DATA_WIDTH/4)-1:0];
|
|
if (<write_enable>[1])
|
|
di1 = <data_in>[(DATA_WIDTH/2)-1:DATA_WIDTH/4];
|
|
else
|
|
di1 = <ram_name>[<address>][(DATA_WIDTH/2)-1:DATA_WIDTH/4];
|
|
if (<write_enable>[2])
|
|
di2 = <data_in>[(3*DATA_WIDTH/4)-1:DATA_WIDTH/2];
|
|
else
|
|
di2 = <ram_name>[<address>][(3*DATA_WIDTH/4)-1:DATA_WIDTH/2];
|
|
if (<write_enable>[3])
|
|
di3 = <data_in>[DATA_WIDTH-1:(3*DATA_WIDTH/4)];
|
|
else
|
|
di3 = <ram_name>[<address>][DATA_WIDTH-1:(3*DATA_WIDTH/4)];
|
|
end
|
|
|
|
always @(posedge <clock>)
|
|
if (<ram_enable>) begin
|
|
<data_out> <= <ram_name>[<address>];
|
|
<ram_name>[<address>] <= {di3,di2,di1,di0};
|
|
end
|
|
</Template>
|
|
<Template label="No Change Mode w/ 2-bit write enable (for device families older than Virtex-6 and Spartan-6)" treetype="template">
|
|
// Important!
|
|
// This is the mandatory coding style to describe byte-write enable functionality for device families older than Virtex-6 and
|
|
// Spartan-6. for Virtex-6, Spartan-6, and newer device families, please refer to the improved templates recommended for those
|
|
// families.
|
|
//
|
|
parameter DATA_WIDTH = 16;
|
|
parameter ADDR_WIDTH = <num_addr_bits>;
|
|
|
|
reg/wire [DATA_WIDTH-1:0] <data_in>;
|
|
reg/wire [ADDR_WIDTH-1:0] <address>;
|
|
reg/wire [1:0] <write_enable>;
|
|
reg/wire <clock>;
|
|
reg/wire <ram_enable>;
|
|
reg [DATA_WIDTH-1:0] <data_out>;
|
|
|
|
(* RAM_STYLE="{AUTO | BLOCK | BLOCK_POWER1 | BLOCK_POWER2}" *)
|
|
reg [DATA_WIDTH-1:0] <ram_name> [2**ADDR_WIDTH-1:0];
|
|
reg [(DATA_WIDTH/2)-1:0] di0, di1;
|
|
|
|
// The forllowing code is only necessary if you wish to initialize the RAM
|
|
// contents via an external file (use $readmemb for binary data)
|
|
initial
|
|
$readmemh("<data_file_name>", <ram_name>, <begin_address>, <end_address>);
|
|
|
|
always @(<write_enable>, <data_in>) begin
|
|
if (<write_enable>[0])
|
|
di0 = <data_in>[(DATA_WIDTH/2)-1:0];
|
|
else
|
|
di0 = <ram_name>[<address>][(DATA_WIDTH/2)-1:0];
|
|
if (<write_enable>[1])
|
|
di1 = <data_in>[DATA_WIDTH-1:DATA_WIDTH/2];
|
|
else
|
|
di1 = <ram_name>[<address>][DATA_WIDTH-1:DATA_WIDTH/2];
|
|
end
|
|
|
|
always @(posedge <clock>)
|
|
if (<ram_enable>) begin
|
|
<data_out> <= {di1,di0};
|
|
<ram_name>[<address>] <= {di1,di0};
|
|
end
|
|
</Template>
|
|
<Template label="No Change Mode w/ 4-bit write enable (for device families older than Virtex-6 and Spartan-6)" treetype="template">
|
|
// Important!
|
|
// This is the mandatory coding style to describe byte-write enable functionality for device families older than Virtex-6 and
|
|
// Spartan-6. for Virtex-6, Spartan-6, and newer device families, please refer to the improved templates recommended for those
|
|
// families.
|
|
//
|
|
parameter DATA_WIDTH = 32;
|
|
parameter ADDR_WIDTH = <num_addr_bits>;
|
|
|
|
reg/wire [DATA_WIDTH-1:0] <data_in>;
|
|
reg/wire [ADDR_WIDTH-1:0] <address>;
|
|
reg/wire [3:0] <write_enable>;
|
|
reg/wire <clock>;
|
|
reg/wire <ram_enable>;
|
|
reg [DATA_WIDTH-1:0] <data_out>;
|
|
|
|
(* RAM_STYLE="{AUTO | BLOCK | BLOCK_POWER1 | BLOCK_POWER2}" *)
|
|
reg [DATA_WIDTH-1:0] <ram_name> [2**ADDR_WIDTH-1:0];
|
|
reg [(DATA_WIDTH/4)-1:0] di0, di1, di2, di3;
|
|
|
|
// The forllowing code is only necessary if you wish to initialize the RAM
|
|
// contents via an external file (use $readmemb for binary data)
|
|
initial
|
|
$readmemh("<data_file_name>", <ram_name>, <begin_address>, <end_address>);
|
|
|
|
always @(<write_enable>, <data_in>) begin
|
|
if (<write_enable>[0])
|
|
di0 = <data_in>[(DATA_WIDTH/4)-1:0];
|
|
else
|
|
di0 = <ram_name>[<address>][(DATA_WIDTH/4)-1:0];
|
|
if (<write_enable>[1])
|
|
di1 = <data_in>[(DATA_WIDTH/2)-1:DATA_WIDTH/4];
|
|
else
|
|
di1 = <ram_name>[<address>][(DATA_WIDTH/2)-1:DATA_WIDTH/4];
|
|
if (<write_enable>[2])
|
|
di2 = <data_in>[(3*DATA_WIDTH/4)-1:DATA_WIDTH/2];
|
|
else
|
|
di2 = <ram_name>[<address>][(3*DATA_WIDTH/4)-1:DATA_WIDTH/2];
|
|
if (<write_enable>[3])
|
|
di3 = <data_in>[DATA_WIDTH-1:(3*DATA_WIDTH/4)];
|
|
else
|
|
di3 = <ram_name>[<address>][DATA_WIDTH-1:(3*DATA_WIDTH/4)];
|
|
end
|
|
|
|
always @(posedge <clock>)
|
|
if (<ram_enable>) begin
|
|
<data_out> <= {di3,di2,di1,di0};
|
|
<ram_name>[<address>] <= {di3,di2,di1,di0};
|
|
end
|
|
</Template>
|
|
<Template label="Read-First Mode w/ 2-bit or 4-bit write enable (recommended for Virtex-6, Spartan-6 and newer)" treetype="template">
|
|
// Important!
|
|
// This is the recommended coding style to describe read-first synchronized byte-write enable functionality for Virtex-6,
|
|
// Spartan-6 and newer device families. This coding style is not supported for older device families. In that case, please refer
|
|
// to the corresponding 2-bit and 4-bit write enable templates for device families before Virtex-6 and Spartan-6.
|
|
//
|
|
parameter ADDR_WIDTH = 10;
|
|
parameter NB_COL = 4; // Number of write columns
|
|
parameter COL_WIDTH = 9; // Width of each write column
|
|
|
|
input <clock>;
|
|
input [NB_COL-1:0] <write_enable>;
|
|
input [ADDR_WIDTH-1:0] <address>;
|
|
input [NB_COL*COL_WIDTH-1:0] <data_in>;
|
|
output reg [NB_COL*COL_WIDTH-1:0] <data_out>;
|
|
|
|
reg [NB_COL*COL_WIDTH-1:0] <ram_name> [0:2**ADDR_WIDTH-1];
|
|
|
|
// The forllowing code is only necessary if you wish to initialize the RAM
|
|
// contents via an external file (use $readmemb for binary data)
|
|
initial
|
|
$readmemh("<data_file_name>", <ram_name>, <begin_address>, <end_address>);
|
|
|
|
always @(posedge <clock>)
|
|
begin
|
|
<data_out> <= <ram_name>[<address>];
|
|
end
|
|
|
|
generate
|
|
genvar i;
|
|
for (i = 0; i < NB_COL; i = i+1)
|
|
begin
|
|
always @(posedge <clock>)
|
|
begin
|
|
if (<write_enable>[i])
|
|
<ram_name>[<address>][(i+1)*COL_WIDTH-1:i*COL_WIDTH]
|
|
<= <data_in>[(i+1)*COL_WIDTH-1:i*COL_WIDTH];
|
|
end
|
|
end
|
|
endgenerate
|
|
</Template>
|
|
<Template label="Write-First Mode w/ 2-bit or 4-bit write enable (recommended for Virtex-6, Spartan-6 and newer)" treetype="template">
|
|
// Important!
|
|
// This is the recommended coding style to describe write-first synchronized byte-write enable functionality for Virtex-6,
|
|
// Spartan-6 and newer device families. This coding style is not supported for older device families. In that case, please refer
|
|
// to the corresponding 2-bit and 4-bit write enable templates for device families before Virtex-6 and Spartan-6.
|
|
//
|
|
parameter ADDR_WIDTH = 10;
|
|
parameter NB_COL = 4; // Number of write columns
|
|
parameter COL_WIDTH = 9; // Width of each write column
|
|
|
|
input <clock>;
|
|
input [NB_COL-1:0] <write_enable>;
|
|
input [ADDR_WIDTH-1:0] <address>;
|
|
input [NB_COL*COL_WIDTH-1:0] <data_in>;
|
|
output reg [NB_COL*COL_WIDTH-1:0] <data_out>;
|
|
|
|
reg [NB_COL*COL_WIDTH-1:0] <ram_name> [0:2**ADDR_WIDTH-1];
|
|
|
|
// The forllowing code is only necessary if you wish to initialize the RAM
|
|
// contents via an external file (use $readmemb for binary data)
|
|
initial
|
|
$readmemh("<data_file_name>", <ram_name>, <begin_address>, <end_address>);
|
|
|
|
generate
|
|
genvar i;
|
|
for (i = 0; i < NB_COL; i = i+1)
|
|
begin
|
|
always @(posedge <clock>)
|
|
begin
|
|
if (<write_enable>[i])
|
|
begin
|
|
<ram_name>[<address>][(i+1)*COL_WIDTH-1:i*COL_WIDTH]
|
|
<= <data_in>[(i+1)*COL_WIDTH-1:i*COL_WIDTH];
|
|
<data_out>[(i+1)*COL_WIDTH-1:i*COL_WIDTH]
|
|
<= <data_in>[(i+1)*COL_WIDTH-1:i*COL_WIDTH];
|
|
end
|
|
else
|
|
<data_out>[(i+1)*COL_WIDTH-1:i*COL_WIDTH]
|
|
<= <ram_name>[<address>][(i+1)*COL_WIDTH-1:i*COL_WIDTH];
|
|
end
|
|
end
|
|
endgenerate
|
|
</Template>
|
|
<Template label="No-Change Mode w/ 2-bit or 4-bit write enable (recommended for Virtex-6, Spartan-6 and newer)" treetype="template">
|
|
// Important!
|
|
// This is the recommended coding style to describe no-change synchronized byte-write enable functionality for Virtex-6,
|
|
// Spartan-6 and newer device families. This coding style is not supported for older device families. In that case, please refer
|
|
// to the corresponding 2-bit and 4-bit write enable templates for device families before Virtex-6 and Spartan-6.
|
|
//
|
|
parameter ADDR_WIDTH = 10;
|
|
parameter NB_COL = 4; // Number of write columns
|
|
parameter COL_WIDTH = 9; // Width of each write column
|
|
|
|
input <clock>;
|
|
input [NB_COL-1:0] <write_enable>;
|
|
input [ADDR_WIDTH-1:0] <address>;
|
|
input [NB_COL*COL_WIDTH-1:0] <data_in>;
|
|
output reg [NB_COL*COL_WIDTH-1:0] <data_out>;
|
|
|
|
reg [NB_COL*COL_WIDTH-1:0] <ram_name> [0:2**ADDR_WIDTH-1];
|
|
|
|
// The forllowing code is only necessary if you wish to initialize the RAM
|
|
// contents via an external file (use $readmemb for binary data)
|
|
initial
|
|
$readmemh("<data_file_name>", <ram_name>, <begin_address>, <end_address>);
|
|
|
|
always @(posedge <clock>)
|
|
begin
|
|
if (~|<write_enable>)
|
|
<data_out> <= <ram_name>[<address>];
|
|
end
|
|
|
|
generate
|
|
genvar i;
|
|
for (i = 0; i < NB_COL; i = i+1)
|
|
begin
|
|
always @(posedge <clock>)
|
|
begin
|
|
if (<write_enable>[i])
|
|
<ram_name>[<address>][(i+1)*COL_WIDTH-1:i*COL_WIDTH]
|
|
<= <data_in>[(i+1)*COL_WIDTH-1:i*COL_WIDTH];
|
|
end
|
|
end
|
|
endgenerate
|
|
</Template>
|
|
</SubFolder>
|
|
<Template label="Write First Mode" treetype="template">
|
|
parameter RAM_WIDTH = <ram_width>;
|
|
parameter RAM_ADDR_BITS = <ram_addr_bits>;
|
|
|
|
(* RAM_STYLE="{AUTO | BLOCK | BLOCK_POWER1 | BLOCK_POWER2}" *)
|
|
reg [RAM_WIDTH-1:0] <ram_name> [(2**RAM_ADDR_BITS)-1:0];
|
|
reg [RAM_WIDTH-1:0] <output_data>;
|
|
|
|
<reg_or_wire> [RAM_ADDR_BITS-1:0] <address>;
|
|
<reg_or_wire> [RAM_WIDTH-1:0] <input_data>;
|
|
|
|
// The forllowing code is only necessary if you wish to initialize the RAM
|
|
// contents via an external file (use $readmemb for binary data)
|
|
initial
|
|
$readmemh("<data_file_name>", <rom_name>, <begin_address>, <end_address>);
|
|
|
|
always @(posedge <clock>)
|
|
if (<ram_enable>) begin
|
|
if (<write_enable>) begin
|
|
<ram_name>[<address>] <= <input_data>;
|
|
<output_data> <= <input_data>;
|
|
end
|
|
else
|
|
<output_data> <= <ram_name>[<address>];
|
|
end
|
|
</Template>
|
|
<Template label="No-Change Mode" treetype="template">
|
|
parameter RAM_WIDTH = <ram_width>;
|
|
parameter RAM_ADDR_BITS = <ram_addr_bits>;
|
|
|
|
(* RAM_STYLE="{AUTO | BLOCK | BLOCK_POWER1 | BLOCK_POWER2}" *)
|
|
reg [RAM_WIDTH-1:0] <ram_name> [(2**RAM_ADDR_BITS)-1:0];
|
|
reg [RAM_WIDTH-1:0] <output_data>;
|
|
|
|
<reg_or_wire> [RAM_ADDR_BITS-1:0] <address>;
|
|
<reg_or_wire> [RAM_WIDTH-1:0] <input_data>;
|
|
|
|
// The forllowing code is only necessary if you wish to initialize the RAM
|
|
// contents via an external file (use $readmemb for binary data)
|
|
initial
|
|
$readmemh("<data_file_name>", <rom_name>, <begin_address>, <end_address>);
|
|
|
|
always @(posedge <clock>)
|
|
if (<ram_enable>)
|
|
if (<write_enable>)
|
|
<ram_name>[<address>] <= <input_data>;
|
|
else
|
|
<output_data> <= <ram_name>[<address>];
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Dual Port" treetype="folder">
|
|
<Template label="1 Clock, 1 Write Port, 1 Read Port" treetype="template">
|
|
parameter RAM_WIDTH = <ram_width>;
|
|
parameter RAM_ADDR_BITS = <ram_addr_bits>;
|
|
|
|
(* RAM_STYLE="{AUTO | BLOCK | BLOCK_POWER1 | BLOCK_POWER2}" *)
|
|
reg [RAM_WIDTH-1:0] <ram_name> [(2**RAM_ADDR_BITS)-1:0];
|
|
reg [RAM_WIDTH-1:0] <output_data>;
|
|
|
|
<reg_or_wire> [RAM_ADDR_BITS-1:0] <read_address>, <write_address>;
|
|
<reg_or_wire> [RAM_WIDTH-1:0] <input_data>;
|
|
|
|
// The forllowing code is only necessary if you wish to initialize the RAM
|
|
// contents via an external file (use $readmemb for binary data)
|
|
initial
|
|
$readmemh("<data_file_name>", <ram_name>, <begin_address>, <end_address>);
|
|
|
|
always @(posedge <clock>) begin
|
|
if (<write_enable>)
|
|
<ram_name>[<write_address>] <= <input_data>;
|
|
<output_data> <= <ram_name>[<read_address>];
|
|
end
|
|
</Template>
|
|
<Template label="1 Clock, 1 Read/write Port, 1 Read Port" treetype="template">
|
|
parameter RAM_WIDTH = <ram_width>;
|
|
parameter RAM_ADDR_BITS = <ram_addr_bits>;
|
|
|
|
(* RAM_STYLE="{AUTO | BLOCK | BLOCK_POWER1 | BLOCK_POWER2}" *)
|
|
reg [RAM_WIDTH-1:0] <ram_name> [(2**RAM_ADDR_BITS)-1:0];
|
|
reg [RAM_WIDTH-1:0] <output_dataA>, <output_dataB>;
|
|
|
|
<reg_or_wire> [RAM_ADDR_BITS-1:0] <addressA>, <addressB>;
|
|
<reg_or_wire> [RAM_WIDTH-1:0] <input_dataA>;
|
|
|
|
// The forllowing code is only necessary if you wish to initialize the RAM
|
|
// contents via an external file (use $readmemb for binary data)
|
|
initial
|
|
$readmemh("<data_file_name>", <ram_name>, <begin_address>, <end_address>);
|
|
|
|
always @(posedge <clock>) begin
|
|
if (<enableA>) begin
|
|
if (<write_enableA>)
|
|
<ram_name>[<addressA>] <= <input_dataA>;
|
|
<output_dataA> <= <ram_name>[<addressA>];
|
|
end
|
|
if (<enableB>)
|
|
<output_dataB> <= <ram_name>[<addressB>];
|
|
end
|
|
</Template>
|
|
<Template label="2 Clocks, 1 Read/write Port, 1 Read Port" treetype="template">
|
|
parameter RAM_WIDTH = <ram_width>;
|
|
parameter RAM_ADDR_BITS = <ram_addr_bits>;
|
|
|
|
(* RAM_STYLE="{AUTO | BLOCK | BLOCK_POWER1 | BLOCK_POWER2}" *)
|
|
reg [RAM_WIDTH-1:0] <ram_name> [(2**RAM_ADDR_BITS)-1:0];
|
|
reg [RAM_WIDTH-1:0] <output_dataA>, <output_dataB>;
|
|
|
|
<reg_or_wire> [RAM_ADDR_BITS-1:0] <addressA>, <addressB>;
|
|
<reg_or_wire> [RAM_WIDTH-1:0] <input_dataA>;
|
|
|
|
// The forllowing code is only necessary if you wish to initialize the RAM
|
|
// contents via an external file (use $readmemb for binary data)
|
|
initial
|
|
$readmemh("<data_file_name>", <ram_name>, <begin_address>, <end_address>);
|
|
|
|
always @(posedge <clockA>)
|
|
if (<enableA>) begin
|
|
if (<write_enableA>)
|
|
<ram_name>[<addressA>] <= <input_dataA>;
|
|
<output_dataA> <= <ram_name>[<addressA>];
|
|
end
|
|
|
|
always @(posedge <clockB>)
|
|
if (<enableB>)
|
|
<output_dataB> <= <ram_name>[<addressB>];
|
|
</Template>
|
|
<Template label="2 Clocks, 1 Write Port, 1 Read Port" treetype="template">
|
|
parameter RAM_WIDTH = <ram_width>;
|
|
parameter RAM_ADDR_BITS = <ram_addr_bits>;
|
|
|
|
(* RAM_STYLE="{AUTO | BLOCK | BLOCK_POWER1 | BLOCK_POWER2}" *)
|
|
reg [RAM_WIDTH-1:0] <ram_name> [(2**RAM_ADDR_BITS)-1:0];
|
|
reg [RAM_WIDTH-1:0] <output_dataB>;
|
|
|
|
<reg_or_wire> [RAM_ADDR_BITS-1:0] <addressA>, <addressB>;
|
|
<reg_or_wire> [RAM_WIDTH-1:0] <input_dataA>;
|
|
|
|
// The forllowing code is only necessary if you wish to initialize the RAM
|
|
// contents via an external file (use $readmemb for binary data)
|
|
initial
|
|
$readmemh("<data_file_name>", <ram_name>, <begin_address>, <end_address>);
|
|
|
|
always @(posedge <clockA>)
|
|
if (<enableA>)
|
|
if (<write_enableA>)
|
|
<ram_name>[<addressA>] <= <input_dataA>;
|
|
|
|
always @(posedge <clockB>)
|
|
if (<enableB>)
|
|
<output_dataB> <= <ram_name>[<addressB>];
|
|
</Template>
|
|
<Template label="2 Clocks, 2 Read/write Ports" treetype="template">
|
|
parameter RAM_WIDTH = <ram_width>;
|
|
parameter RAM_ADDR_BITS = <ram_addr_bits>;
|
|
|
|
(* RAM_STYLE="{AUTO | BLOCK | BLOCK_POWER1 | BLOCK_POWER2}" *)
|
|
reg [RAM_WIDTH-1:0] <ram_name> [(2**RAM_ADDR_BITS)-1:0];
|
|
reg [RAM_WIDTH-1:0] <output_dataA>, <output_dataB>;
|
|
|
|
<reg_or_wire> [RAM_ADDR_BITS-1:0] <addressA>, <addressB>;
|
|
<reg_or_wire> [RAM_WIDTH-1:0] <input_dataA>;
|
|
|
|
// The forllowing code is only necessary if you wish to initialize the RAM
|
|
// contents via an external file (use $readmemb for binary data)
|
|
initial
|
|
$readmemh("<data_file_name>", <ram_name>, <begin_address>, <end_address>);
|
|
|
|
always @(posedge <clockA>)
|
|
if (<enableA>) begin
|
|
if (<write_enableA>)
|
|
<ram_name>[<addressA>] <= <input_dataA>;
|
|
<output_dataA> <= <ram_name>[<addressA>];
|
|
end
|
|
|
|
always @(posedge <clockB>)
|
|
if (<enableB>) begin
|
|
if (<write_enableB>)
|
|
<ram_name>[<addressB>] <= <input_dataB>;
|
|
<output_dataB> <= <ram_name>[<addressB>];
|
|
end
|
|
</Template>
|
|
<SubFolder label="Asymmetric Ports" treetype="folder">
|
|
<Template label="Read-First Mode" treetype="template">
|
|
parameter WIDTHA = 8;
|
|
parameter SIZEA = 256;
|
|
parameter ADDRWIDTHA = 8;
|
|
parameter WIDTHB = 32;
|
|
parameter SIZEB = 64;
|
|
parameter ADDRWIDTHB = 6;
|
|
|
|
<input/wire> <clkA>;
|
|
<input/wire> <clkB>;
|
|
<input/wire> <enA>;
|
|
<input/wire> <enB>;
|
|
<input/wire> <weA>;
|
|
<input/wire> <weB>;
|
|
<input/wire> [ADDRWIDTHA-1:0] <addrA>;
|
|
<input/wire> [ADDRWIDTHB-1:0] <addrB>;
|
|
<input/wire> [WIDTHA-1:0] <diA>;
|
|
<input/wire> [WIDTHB-1:0] <diB>;
|
|
<output reg/reg> [WIDTHA-1:0] <doA>;
|
|
<output reg/reg> [WIDTHB-1:0] <doB>;
|
|
|
|
`define max(a,b) {(a) > (b) ? (a) : (b)}
|
|
`define min(a,b) {(a) < (b) ? (a) : (b)}
|
|
|
|
function integer log2;
|
|
input integer value;
|
|
reg [31:0] shifted;
|
|
integer res;
|
|
begin
|
|
if (value < 2)
|
|
log2 = value;
|
|
else
|
|
begin
|
|
shifted = value-1;
|
|
for (res=0; shifted>0; res=res+1)
|
|
shifted = shifted>>1;
|
|
log2 = res;
|
|
end
|
|
end
|
|
endfunction
|
|
|
|
localparam maxSIZE = `max(SIZEA, SIZEB);
|
|
localparam maxWIDTH = `max(WIDTHA, WIDTHB);
|
|
localparam minWIDTH = `min(WIDTHA, WIDTHB);
|
|
localparam RATIO = maxWIDTH / minWIDTH;
|
|
localparam log2RATIO = log2(RATIO);
|
|
|
|
// An asymmetric RAM is modeled in a similar way as a symmetric RAM, with an
|
|
// array of array reg. Its aspect ratio corresponds to the port with the
|
|
// lower data width (larger depth)
|
|
reg [minWIDTH-1:0] <RAM> [0:maxSIZE-1];
|
|
|
|
genvar i;
|
|
|
|
// Describe the port with the smaller data width exactly as you are used to
|
|
// for symmetric block RAMs
|
|
always @(posedge <clkA>)
|
|
if (<enA>) begin
|
|
<doA> <= <RAM>[<addrA>];
|
|
if (<weA>)
|
|
<RAM>[<addrA>] <= <diA>;
|
|
end
|
|
|
|
// A generate-for is used to describe the port with the larger data width in a
|
|
// generic and compact way
|
|
generate for (i = 0; i < RATIO; i = i+1)
|
|
begin: portB
|
|
localparam [log2RATIO-1:0] lsbaddr = i;
|
|
always @(posedge <clkB>)
|
|
if (<enB>) begin
|
|
<doB>[(i+1)*minWIDTH-1:i*minWIDTH] <= <RAM>[{<addrB>, lsbaddr}];
|
|
if (<weB>)
|
|
<RAM>[{<addrB>, lsbaddr}] <= <diB>[(i+1)*minWIDTH-1:i*minWIDTH];
|
|
end
|
|
end
|
|
endgenerate
|
|
</Template>
|
|
<Template label="Write-First Mode" treetype="template">
|
|
parameter WIDTHA = 8;
|
|
parameter SIZEA = 256;
|
|
parameter ADDRWIDTHA = 8;
|
|
parameter WIDTHB = 32;
|
|
parameter SIZEB = 64;
|
|
parameter ADDRWIDTHB = 6;
|
|
|
|
<input/wire> <clkA>;
|
|
<input/wire> <clkB>;
|
|
<input/wire> <enA>;
|
|
<input/wire> <enB>;
|
|
<input/wire> <weA>;
|
|
<input/wire> <weB>;
|
|
<input/wire> [ADDRWIDTHA-1:0] <addrA>;
|
|
<input/wire> [ADDRWIDTHB-1:0] <addrB>;
|
|
<input/wire> [WIDTHA-1:0] <diA>;
|
|
<input/wire> [WIDTHB-1:0] <diB>;
|
|
<output reg/reg> [WIDTHA-1:0] <doA>;
|
|
<output reg/reg> [WIDTHB-1:0] <doB>;
|
|
|
|
`define max(a,b) {(a) > (b) ? (a) : (b)}
|
|
`define min(a,b) {(a) < (b) ? (a) : (b)}
|
|
|
|
function integer log2;
|
|
input integer value;
|
|
reg [31:0] shifted;
|
|
integer res;
|
|
begin
|
|
if (value < 2)
|
|
log2 = value;
|
|
else
|
|
begin
|
|
shifted = value-1;
|
|
for (res=0; shifted>0; res=res+1)
|
|
shifted = shifted>>1;
|
|
log2 = res;
|
|
end
|
|
end
|
|
endfunction
|
|
|
|
localparam maxSIZE = `max(SIZEA, SIZEB);
|
|
localparam maxWIDTH = `max(WIDTHA, WIDTHB);
|
|
localparam minWIDTH = `min(WIDTHA, WIDTHB);
|
|
localparam RATIO = maxWIDTH / minWIDTH;
|
|
localparam log2RATIO = log2(RATIO);
|
|
|
|
// An asymmetric RAM is modeled in a similar way as a symmetric RAM, with an
|
|
// array of array reg. Its aspect ratio corresponds to the port with the
|
|
// lower data width (larger depth)
|
|
reg [minWIDTH-1:0] <RAM> [0:maxSIZE-1];
|
|
|
|
genvar i;
|
|
|
|
// Describe the port with the smaller data width exactly as you are used to
|
|
// for symmetric block RAMs
|
|
always @(posedge <clkA>)
|
|
begin
|
|
if (<enA>)
|
|
if (<weA>) begin
|
|
<RAM>[<addrA>] <= <diA>;
|
|
<doA> <= <diA>;
|
|
end else
|
|
<doA> <= <RAM>[<addrA>];
|
|
end
|
|
|
|
// A generate-for is used to describe the port with the larger data width in a
|
|
// generic and compact way
|
|
generate for (i = 0; i < RATIO; i = i+1)
|
|
begin: portB
|
|
localparam [log2RATIO-1:0] lsbaddr = i;
|
|
always @(posedge <clkB>)
|
|
if (<enB>)
|
|
if (<weB>) begin
|
|
<RAM>[{<addrB>, lsbaddr}] <= <diB>[(i+1)*minWIDTH-1:i*minWIDTH];
|
|
<doB>[(i+1)*minWIDTH-1:i*minWIDTH] <= <diB>[(i+1)*minWIDTH-1:i*minWIDTH];
|
|
end else
|
|
<doB>[(i+1)*minWIDTH-1:i*minWIDTH] <= <RAM>[{<addrB>, lsbaddr}];
|
|
end
|
|
endgenerate
|
|
</Template>
|
|
<Template label="No-Change Mode" treetype="template">
|
|
parameter WIDTHA = 8;
|
|
parameter SIZEA = 256;
|
|
parameter ADDRWIDTHA = 8;
|
|
parameter WIDTHB = 32;
|
|
parameter SIZEB = 64;
|
|
parameter ADDRWIDTHB = 6;
|
|
|
|
<input/wire> <clkA>;
|
|
<input/wire> <clkB>;
|
|
<input/wire> <enA>;
|
|
<input/wire> <enB>;
|
|
<input/wire> <weA>;
|
|
<input/wire> <weB>;
|
|
<input/wire> [ADDRWIDTHA-1:0] <addrA>;
|
|
<input/wire> [ADDRWIDTHB-1:0] <addrB>;
|
|
<input/wire> [WIDTHA-1:0] <diA>;
|
|
<input/wire> [WIDTHB-1:0] <diB>;
|
|
<output reg/reg> [WIDTHA-1:0] <doA>;
|
|
<output reg/reg> [WIDTHB-1:0] <doB>;
|
|
|
|
`define max(a,b) {(a) > (b) ? (a) : (b)}
|
|
`define min(a,b) {(a) < (b) ? (a) : (b)}
|
|
|
|
function integer log2;
|
|
input integer value;
|
|
reg [31:0] shifted;
|
|
integer res;
|
|
begin
|
|
if (value < 2)
|
|
log2 = value;
|
|
else
|
|
begin
|
|
shifted = value-1;
|
|
for (res=0; shifted>0; res=res+1)
|
|
shifted = shifted>>1;
|
|
log2 = res;
|
|
end
|
|
end
|
|
endfunction
|
|
|
|
localparam maxSIZE = `max(SIZEA, SIZEB);
|
|
localparam maxWIDTH = `max(WIDTHA, WIDTHB);
|
|
localparam minWIDTH = `min(WIDTHA, WIDTHB);
|
|
localparam RATIO = maxWIDTH / minWIDTH;
|
|
localparam log2RATIO = log2(RATIO);
|
|
|
|
// An asymmetric RAM is modeled in a similar way as a symmetric RAM, with an
|
|
// array of array reg. Its aspect ratio corresponds to the port with the
|
|
// lower data width (larger depth)
|
|
reg [minWIDTH-1:0] <RAM> [0:maxSIZE-1];
|
|
|
|
genvar i;
|
|
|
|
// Describe the port with the smaller data width exactly as you are used to
|
|
// for symmetric block RAMs
|
|
always @(posedge <clkA>)
|
|
if (<enA>)
|
|
if (<weA>)
|
|
<RAM>[<addrA>] <= <diA>;
|
|
else
|
|
<doA> <= <RAM>[<addrA>];
|
|
|
|
// A generate-for is used to describe the port with the larger data width in a
|
|
// generic and compact way
|
|
generate for (i = 0; i < RATIO; i = i+1)
|
|
begin: portB
|
|
localparam [log2RATIO-1:0] lsbaddr = i;
|
|
always @(posedge <clkB>)
|
|
if (<enB>)
|
|
if (<weB>)
|
|
<RAM>[{<addrB>, lsbaddr}] <= <diB>[(i+1)*minWIDTH-1:i*minWIDTH];
|
|
else
|
|
<doB>[(i+1)*minWIDTH-1:i*minWIDTH] <= <RAM>[{<addrB>, lsbaddr}];
|
|
end
|
|
endgenerate
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Distributed RAM" treetype="folder">
|
|
<Template label="Single Port, Async Read" treetype="template">
|
|
parameter RAM_WIDTH = <ram_width>;
|
|
parameter RAM_ADDR_BITS = <ram_addr_bits>;
|
|
|
|
(* RAM_STYLE="{AUTO | DISTRIBUTED | PIPE_DISTRIBUTED}" *)
|
|
reg [RAM_WIDTH-1:0] <ram_name> [(2**RAM_ADDR_BITS)-1:0];
|
|
|
|
wire [RAM_WIDTH-1:0] <output_data>;
|
|
|
|
<reg_or_wire> [RAM_ADDR_BITS-1:0] <address>;
|
|
<reg_or_wire> [RAM_WIDTH-1:0] <input_data>;
|
|
|
|
always @(posedge <clock>)
|
|
if (<write_enable>)
|
|
<ram_name>[<address>] <= <input_data>;
|
|
|
|
assign <output_data> = <ram_name>[<address>];
|
|
</Template>
|
|
<Template label="Dual Port, Async Read" treetype="template">
|
|
parameter RAM_WIDTH = <ram_width>;
|
|
parameter RAM_ADDR_BITS = <ram_addr_bits>;
|
|
|
|
(* RAM_STYLE="{AUTO | DISTRIBUTED | PIPE_DISTRIBUTED}" *)
|
|
reg [RAM_WIDTH-1:0] <ram_name> [(2**RAM_ADDR_BITS)-1:0];
|
|
|
|
wire [RAM_WIDTH-1:0] <output_data>;
|
|
|
|
<reg_or_wire> [RAM_ADDR_BITS-1:0] <read_address>, <write_address>;
|
|
<reg_or_wire> [RAM_WIDTH-1:0] <input_data>;
|
|
|
|
always @(posedge <clock>)
|
|
if (<write_enable>)
|
|
<ram_name>[<write_address>] <= <input_data>;
|
|
|
|
assign <output_data> = <ram_name>[<read_address>];
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="ROM/Lookup Table" treetype="folder">
|
|
<Template label="Using 4-bit Case Statement" treetype="template">
|
|
parameter ROM_WIDTH = <rom_width>;
|
|
|
|
reg [ROM_WIDTH-1:0] <output_data>;
|
|
<reg_or_wire> [3:0] <address>;
|
|
|
|
always @(posedge <clock>)
|
|
if (<enable>)
|
|
case (<address>)
|
|
4'b0000: <output_data> <= <value>;
|
|
4'b0001: <output_data> <= <value>;
|
|
4'b0010: <output_data> <= <value>;
|
|
4'b0011: <output_data> <= <value>;
|
|
4'b0100: <output_data> <= <value>;
|
|
4'b0101: <output_data> <= <value>;
|
|
4'b0110: <output_data> <= <value>;
|
|
4'b0111: <output_data> <= <value>;
|
|
4'b1000: <output_data> <= <value>;
|
|
4'b1001: <output_data> <= <value>;
|
|
4'b1010: <output_data> <= <value>;
|
|
4'b1011: <output_data> <= <value>;
|
|
4'b1100: <output_data> <= <value>;
|
|
4'b1101: <output_data> <= <value>;
|
|
4'b1110: <output_data> <= <value>;
|
|
4'b1111: <output_data> <= <value>;
|
|
default: <output_data> <= <value>;
|
|
endcase
|
|
</Template>
|
|
<Template label="Using 5-bit Case Statement" treetype="template">
|
|
parameter ROM_WIDTH = <rom_width>;
|
|
|
|
reg [ROM_WIDTH-1:0] <output_data>;
|
|
<reg_or_wire> [4:0] <address>;
|
|
|
|
always @(posedge <clock>)
|
|
if (<enable>)
|
|
case (<address>)
|
|
5'b00000: <output_data> <= <value>;
|
|
5'b00001: <output_data> <= <value>;
|
|
5'b00010: <output_data> <= <value>;
|
|
5'b00011: <output_data> <= <value>;
|
|
5'b00100: <output_data> <= <value>;
|
|
5'b00101: <output_data> <= <value>;
|
|
5'b00110: <output_data> <= <value>;
|
|
5'b00111: <output_data> <= <value>;
|
|
5'b01000: <output_data> <= <value>;
|
|
5'b01001: <output_data> <= <value>;
|
|
5'b01010: <output_data> <= <value>;
|
|
5'b01011: <output_data> <= <value>;
|
|
5'b01100: <output_data> <= <value>;
|
|
5'b01101: <output_data> <= <value>;
|
|
5'b01110: <output_data> <= <value>;
|
|
5'b01111: <output_data> <= <value>;
|
|
5'b10000: <output_data> <= <value>;
|
|
5'b10001: <output_data> <= <value>;
|
|
5'b10010: <output_data> <= <value>;
|
|
5'b10011: <output_data> <= <value>;
|
|
5'b10100: <output_data> <= <value>;
|
|
5'b10101: <output_data> <= <value>;
|
|
5'b10110: <output_data> <= <value>;
|
|
5'b10111: <output_data> <= <value>;
|
|
5'b11000: <output_data> <= <value>;
|
|
5'b11001: <output_data> <= <value>;
|
|
5'b11010: <output_data> <= <value>;
|
|
5'b11011: <output_data> <= <value>;
|
|
5'b11100: <output_data> <= <value>;
|
|
5'b11101: <output_data> <= <value>;
|
|
5'b11110: <output_data> <= <value>;
|
|
5'b11111: <output_data> <= <value>;
|
|
default: <output_data> <= <value>;
|
|
endcase
|
|
</Template>
|
|
<Template label="Using 6-bit Case Statement" treetype="template">
|
|
parameter ROM_WIDTH = <rom_width>;
|
|
|
|
reg [ROM_WIDTH-1:0] <output_data>;
|
|
<reg_or_wire> [5:0] <address>;
|
|
|
|
always @(posedge <clock>)
|
|
if (<enable>)
|
|
case (<address>)
|
|
6'b000000: <output_data> <= <value>;
|
|
6'b000001: <output_data> <= <value>;
|
|
6'b000010: <output_data> <= <value>;
|
|
6'b000011: <output_data> <= <value>;
|
|
6'b000100: <output_data> <= <value>;
|
|
6'b000101: <output_data> <= <value>;
|
|
6'b000110: <output_data> <= <value>;
|
|
6'b000111: <output_data> <= <value>;
|
|
6'b001000: <output_data> <= <value>;
|
|
6'b001001: <output_data> <= <value>;
|
|
6'b001010: <output_data> <= <value>;
|
|
6'b001011: <output_data> <= <value>;
|
|
6'b001100: <output_data> <= <value>;
|
|
6'b001101: <output_data> <= <value>;
|
|
6'b001110: <output_data> <= <value>;
|
|
6'b001111: <output_data> <= <value>;
|
|
6'b010000: <output_data> <= <value>;
|
|
6'b010001: <output_data> <= <value>;
|
|
6'b010010: <output_data> <= <value>;
|
|
6'b010011: <output_data> <= <value>;
|
|
6'b010100: <output_data> <= <value>;
|
|
6'b010101: <output_data> <= <value>;
|
|
6'b010110: <output_data> <= <value>;
|
|
6'b010111: <output_data> <= <value>;
|
|
6'b011000: <output_data> <= <value>;
|
|
6'b011001: <output_data> <= <value>;
|
|
6'b011010: <output_data> <= <value>;
|
|
6'b011011: <output_data> <= <value>;
|
|
6'b011100: <output_data> <= <value>;
|
|
6'b011101: <output_data> <= <value>;
|
|
6'b011110: <output_data> <= <value>;
|
|
6'b011111: <output_data> <= <value>;
|
|
6'b100000: <output_data> <= <value>;
|
|
6'b100001: <output_data> <= <value>;
|
|
6'b100010: <output_data> <= <value>;
|
|
6'b100011: <output_data> <= <value>;
|
|
6'b100100: <output_data> <= <value>;
|
|
6'b100101: <output_data> <= <value>;
|
|
6'b100110: <output_data> <= <value>;
|
|
6'b100111: <output_data> <= <value>;
|
|
6'b101000: <output_data> <= <value>;
|
|
6'b101001: <output_data> <= <value>;
|
|
6'b101010: <output_data> <= <value>;
|
|
6'b101011: <output_data> <= <value>;
|
|
6'b101100: <output_data> <= <value>;
|
|
6'b101101: <output_data> <= <value>;
|
|
6'b101110: <output_data> <= <value>;
|
|
6'b101111: <output_data> <= <value>;
|
|
6'b110000: <output_data> <= <value>;
|
|
6'b110001: <output_data> <= <value>;
|
|
6'b110010: <output_data> <= <value>;
|
|
6'b110011: <output_data> <= <value>;
|
|
6'b110100: <output_data> <= <value>;
|
|
6'b110101: <output_data> <= <value>;
|
|
6'b110110: <output_data> <= <value>;
|
|
6'b110111: <output_data> <= <value>;
|
|
6'b111000: <output_data> <= <value>;
|
|
6'b111001: <output_data> <= <value>;
|
|
6'b111010: <output_data> <= <value>;
|
|
6'b111011: <output_data> <= <value>;
|
|
6'b111100: <output_data> <= <value>;
|
|
6'b111101: <output_data> <= <value>;
|
|
6'b111110: <output_data> <= <value>;
|
|
6'b111111: <output_data> <= <value>;
|
|
default: <output_data> <= <value>;
|
|
endcase
|
|
</Template>
|
|
<Template label="Using $readmemb" treetype="template">
|
|
parameter ROM_WIDTH = <rom_width>;
|
|
parameter ROM_ADDR_BITS = <rom_addr_bits>;
|
|
|
|
(* ROM_STYLE="{AUTO | DISTRIBUTED | BLOCK}" *)
|
|
reg [ROM_WIDTH-1:0] <rom_name> [(2**ROM_ADDR_BITS)-1:0];
|
|
reg [ROM_WIDTH-1:0] <output_data>;
|
|
|
|
<reg_or_wire> [ROM_ADDR_BITS-1:0] <address>;
|
|
|
|
initial
|
|
$readmemb("<data_file_name>", <rom_name>, <begin_address>, <end_address>);
|
|
|
|
always @(posedge <clock>)
|
|
if (<enable>)
|
|
<output_data> <= <rom_name>[<address>];
|
|
</Template>
|
|
<Template label="Using $readmemh" treetype="template">
|
|
parameter ROM_WIDTH = <rom_width>;
|
|
parameter ROM_ADDR_BITS = <rom_addr_bits>;
|
|
|
|
reg [ROM_WIDTH-1:0] <rom_name> [(2**ROM_ADDR_BITS)-1:0];
|
|
reg [ROM_WIDTH-1:0] <output_data>;
|
|
|
|
<reg_or_wire> [ROM_ADDR_BITS-1:0] <address>;
|
|
|
|
initial
|
|
$readmemh("<data_file_name>", <rom_name>, <begin_address>, <end_address>);
|
|
|
|
always @(posedge <clock>)
|
|
if (<enable>)
|
|
<output_data> <= <rom_name>[<address>];
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="State-Machines" treetype="folder">
|
|
<Template label="Info (State-machine)" treetype="template">
|
|
// Finite State-machines
|
|
//
|
|
// There are several methods to code state-machines however forllowing certain
|
|
// coding styles ensures the synthesis tool FSM (Finite State-Machine)
|
|
// extraction algorithms properly identify and optimize the state-machine as
|
|
// well as possibly improving the simulation, timing and debug of the circuit.
|
|
// The forllowing examples are broken down into Mealy vs. Moore, One-hot vs.
|
|
// Binary and Safe vs. Fast implementations. The basic trade-offs for each
|
|
// implementation is explained below. The general recommendation for the
|
|
// choice of state-machine depends on the target architecture and specifics of
|
|
// the state-machine size and behavior however typically, Moore style, one-hot
|
|
// state-machines implement better for FPGAs and Mealy, binary state-machines
|
|
// implement best for CPLDs.
|
|
//
|
|
// Mealy vs. Moore Styles
|
|
//
|
|
// There are two well known implementation styles for state-machines, Mealy
|
|
// and Moore. The main difference between Mealy and Moore styles is the Mealy
|
|
// state-machine determines the output values based on both the current state
|
|
// as well as the inputs to the state-machine where Moore determines its
|
|
// outputs solely on the state. In general, Moore type of state-machines
|
|
// implement best in FPGAs due to the fact that most often one-hot
|
|
// state-machines is the chosen encoding method and there is little or no
|
|
// decode and thus logic necessary for output values. If a binary encoding is
|
|
// used, it is possible that a more compact and sometimes faster state-machine
|
|
// can be built using the Mealy method however this is not always true and not
|
|
// easy to determine without knowing more specifics of the state-machine.
|
|
//
|
|
// One-hot vs. Binary Encoding
|
|
//
|
|
// There are several encoding methods for state-machine design however the two
|
|
// most popular for FPGA or CPLD design are binary and one-hot. for most FPGA
|
|
// architectures, one-hot is the better encoding method due the abundance
|
|
// of FF resources and the lesser fan-in requirements for the next
|
|
// state-equation (maps better into LUTs). When targeting CPLDs, binary can
|
|
// many times work better due to the logic structure of the CPLD and fewer
|
|
// register resources. In any case, most modern synthesis tools contain FSM
|
|
// extraction algorithms that can identify state-machine code and choose the
|
|
// best encoding method for the size, type and target architecture. Even though
|
|
// this facility exists, many times it can be most advantageous to manually code
|
|
// and control the best encoding scheme for the design to allow better control
|
|
// and possibly ease debug of the implemented design. It is suggested to
|
|
// consult the synthesis tool documentation for details about the state-machine
|
|
// extraction capabilities of the synthesis tool you are using.
|
|
//
|
|
// Safe vs. Fast
|
|
//
|
|
// When coding a state-machine, there are two generally conflicting goals that
|
|
// must be understood, safe vs. fast. A safe state-machine implementation
|
|
// refers to the case where if a state-machine should get an unknown input or
|
|
// into an unknown state that it can recover into a known state the next clock
|
|
// cycle and resume from that recovery state. On the other hand, if this
|
|
// requirement is discarded (no recovery state) many times the state-machine
|
|
// can be implemented with less logic and more speed than if state-machine
|
|
// recovery is necessary. How to design a safe state-machine generally
|
|
// involves coding in a default state into the state-machine next-state case
|
|
// clause and/or specifying to the synthesis tool to implement the
|
|
// state-machine encoding in a "safe" mode. If a safe state-machine is desired
|
|
// many time binary encoding works best due to the fact there are generally fewer
|
|
// unassigned states with that encoding method. Again it is suggested to consult
|
|
// the synthesis tool documentation for details about implementing a safe
|
|
// state-machine.
|
|
</Template>
|
|
<SubFolder label="Mealy" treetype="folder">
|
|
<SubFolder label="One-Hot" treetype="folder">
|
|
<SubFolder label="Safe" treetype="folder">
|
|
<Template label="4 States" treetype="template">
|
|
parameter <state1> = 4'b0001;
|
|
parameter <state2> = 4'b0010;
|
|
parameter <state3> = 4'b0100;
|
|
parameter <state4> = 4'b1000;
|
|
|
|
(* FSM_ENCODING="ONE-HOT", SAFE_IMPLEMENTATION="YES", SAFE_RECOVERY_STATE="<recovery_state_value>" *) reg [3:0] state = <state1>;
|
|
|
|
always@(posedge <clock>)
|
|
if (<reset>) begin
|
|
state <= <state1>;
|
|
end
|
|
else
|
|
(* PARALLEL_CASE *) case (state)
|
|
<state1> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state2> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state3> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state4> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
default : begin // Fault Recovery
|
|
state <= <state1>;
|
|
end
|
|
endcase
|
|
|
|
assign <output1> = <logic_equation_based_on_states_and_inputs>;
|
|
assign <output2> = <logic_equation_based_on_states_and_inputs>;
|
|
// Add other output equations as necessary
|
|
</Template>
|
|
<Template label="8 States" treetype="template">
|
|
parameter <state1> = 8'b00000001;
|
|
parameter <state2> = 8'b00000010;
|
|
parameter <state3> = 8'b00000100;
|
|
parameter <state4> = 8'b00001000;
|
|
parameter <state5> = 8'b00010000;
|
|
parameter <state6> = 8'b00100000;
|
|
parameter <state7> = 8'b01000000;
|
|
parameter <state8> = 8'b10000000;
|
|
|
|
(* FSM_ENCODING="ONE-HOT", SAFE_IMPLEMENTATION="YES", SAFE_RECOVERY_STATE="<recovery_state_value>" *) reg [7:0] state = <state1>;
|
|
|
|
always@(posedge <clock>)
|
|
if (<reset>) begin
|
|
state <= <state1>;
|
|
end
|
|
else
|
|
(* PARALLEL_CASE *) case (state)
|
|
<state1> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state2> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state3> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state4> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state5> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state6> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state7> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state8> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
default : begin // Fault Recovery
|
|
state <= <state1>;
|
|
end
|
|
endcase
|
|
|
|
assign <output1> = <logic_equation_based_on_states_and_inputs>;
|
|
assign <output2> = <logic_equation_based_on_states_and_inputs>;
|
|
// Add other output equations as necessary
|
|
</Template>
|
|
<Template label="16 States" treetype="template">
|
|
parameter <state1> = 16'b0000000000000001;
|
|
parameter <state2> = 16'b0000000000000010;
|
|
parameter <state3> = 16'b0000000000000100;
|
|
parameter <state4> = 16'b0000000000001000;
|
|
parameter <state5> = 16'b0000000000010000;
|
|
parameter <state6> = 16'b0000000000100000;
|
|
parameter <state7> = 16'b0000000001000000;
|
|
parameter <state8> = 16'b0000000010000000;
|
|
parameter <state9> = 16'b0000000100000000;
|
|
parameter <state10> = 16'b0000001000000000;
|
|
parameter <state11> = 16'b0000010000000000;
|
|
parameter <state12> = 16'b0000100000000000;
|
|
parameter <state13> = 16'b0001000000000000;
|
|
parameter <state14> = 16'b0010000000000000;
|
|
parameter <state15> = 16'b0100000000000000;
|
|
parameter <state16> = 16'b1000000000000000;
|
|
|
|
(* FSM_ENCODING="ONE-HOT", SAFE_IMPLEMENTATION="YES", SAFE_RECOVERY_STATE="<recovery_state_value>" *) reg [15:0] state = <state1>;
|
|
|
|
always@(posedge <clock>)
|
|
if (<reset>) begin
|
|
state <= <state1>;
|
|
end
|
|
else
|
|
(* PARALLEL_CASE *) case (state)
|
|
<state1> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state2> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state3> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state4> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state5> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state6> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state7> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state8> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state9> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state10> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state11> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state12> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state13> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state14> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state15> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state16> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
default : begin // Fault Recovery
|
|
state <= <state1>;
|
|
end
|
|
endcase
|
|
|
|
assign <output1> = <logic_equation_based_on_states_and_inputs>;
|
|
assign <output2> = <logic_equation_based_on_states_and_inputs>;
|
|
// Add other output equations as necessary
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Fast" treetype="folder">
|
|
<Template label="4 States" treetype="template">
|
|
parameter <state1> = 4'b0001;
|
|
parameter <state2> = 4'b0010;
|
|
parameter <state3> = 4'b0100;
|
|
parameter <state4> = 4'b1000;
|
|
|
|
(* FSM_ENCODING="ONE-HOT", SAFE_IMPLEMENTATION="NO" *) reg [3:0] state = <state1>;
|
|
|
|
always@(posedge <clock>)
|
|
if (<reset>) begin
|
|
state <= <state1>;
|
|
end
|
|
else
|
|
(* FULL_CASE, PARALLEL_CASE *)case (state)
|
|
<state1> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state2> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state3> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state4> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
endcase
|
|
|
|
assign <output1> = <logic_equation_based_on_states_and_inputs>;
|
|
assign <output2> = <logic_equation_based_on_states_and_inputs>;
|
|
// Add other output equations as necessary
|
|
</Template>
|
|
<Template label="8 States" treetype="template">
|
|
parameter <state1> = 8'b00000001;
|
|
parameter <state2> = 8'b00000010;
|
|
parameter <state3> = 8'b00000100;
|
|
parameter <state4> = 8'b00001000;
|
|
parameter <state5> = 8'b00010000;
|
|
parameter <state6> = 8'b00100000;
|
|
parameter <state7> = 8'b01000000;
|
|
parameter <state8> = 8'b10000000;
|
|
|
|
(* FSM_ENCODING="ONE-HOT", SAFE_IMPLEMENTATION="NO" *) reg [7:0] state = <state1>;
|
|
|
|
always@(posedge <clock>)
|
|
if (<reset>) begin
|
|
state <= <state1>;
|
|
end
|
|
else
|
|
(* FULL_CASE, PARALLEL_CASE *) case (state)
|
|
<state1> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state2> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state3> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state4> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state5> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state6> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state7> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state8> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
endcase
|
|
|
|
assign <output1> = <logic_equation_based_on_states_and_inputs>;
|
|
assign <output2> = <logic_equation_based_on_states_and_inputs>;
|
|
// Add other output equations as necessary
|
|
</Template>
|
|
<Template label="16 States" treetype="template">
|
|
parameter <state1> = 16'b0000000000000001;
|
|
parameter <state2> = 16'b0000000000000010;
|
|
parameter <state3> = 16'b0000000000000100;
|
|
parameter <state4> = 16'b0000000000001000;
|
|
parameter <state5> = 16'b0000000000010000;
|
|
parameter <state6> = 16'b0000000000100000;
|
|
parameter <state7> = 16'b0000000001000000;
|
|
parameter <state8> = 16'b0000000010000000;
|
|
parameter <state9> = 16'b0000000100000000;
|
|
parameter <state10> = 16'b0000001000000000;
|
|
parameter <state11> = 16'b0000010000000000;
|
|
parameter <state12> = 16'b0000100000000000;
|
|
parameter <state13> = 16'b0001000000000000;
|
|
parameter <state14> = 16'b0010000000000000;
|
|
parameter <state15> = 16'b0100000000000000;
|
|
parameter <state16> = 16'b1000000000000000;
|
|
|
|
(* FSM_ENCODING="ONE-HOT", SAFE_IMPLEMENTATION="NO" *) reg [15:0] state = <state1>;
|
|
|
|
always@(posedge <clock>)
|
|
if (<reset>) begin
|
|
state <= <state1>;
|
|
end
|
|
else
|
|
(* FULL_CASE, PARALLEL_CASE *) case (state)
|
|
<state1> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state2> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state3> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state4> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state5> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state6> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state7> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state8> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state9> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state10> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state11> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state12> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state13> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state14> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state15> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state16> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
endcase
|
|
|
|
assign <output1> = <logic_equation_based_on_states_and_inputs>;
|
|
assign <output2> = <logic_equation_based_on_states_and_inputs>;
|
|
// Add other output equations as necessary
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Binary" treetype="folder">
|
|
<SubFolder label="Safe" treetype="folder">
|
|
<Template label="4 States" treetype="template">
|
|
parameter <state1> = 2'b00;
|
|
parameter <state2> = 2'b01;
|
|
parameter <state3> = 2'b10;
|
|
parameter <state4> = 2'b11;
|
|
|
|
(* FSM_ENCODING="SEQUNTIAL", SAFE_IMPLEMENTATION="YES", SAFE_RECOVERY_STATE="<recovery_state_value>" *) reg [1:0] state = <state1>;
|
|
|
|
always@(posedge <clock>)
|
|
if (<reset>) begin
|
|
state <= <state1>;
|
|
end
|
|
else
|
|
(* PARALLEL_CASE *) case (state)
|
|
<state1> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state2> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state3> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state4> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
default : begin // Fault Recovery
|
|
state <= <state1>;
|
|
end
|
|
endcase
|
|
|
|
assign <output1> = <logic_equation_based_on_states_and_inputs>;
|
|
assign <output2> = <logic_equation_based_on_states_and_inputs>;
|
|
// Add other output equations as necessary
|
|
</Template>
|
|
<Template label="8 States" treetype="template">
|
|
parameter <state1> = 3'b000;
|
|
parameter <state2> = 3'b001;
|
|
parameter <state3> = 3'b010;
|
|
parameter <state4> = 3'b011;
|
|
parameter <state5> = 3'b100;
|
|
parameter <state6> = 3'b101;
|
|
parameter <state7> = 3'b110;
|
|
parameter <state8> = 3'b111;
|
|
|
|
(* FSM_ENCODING="SEQUNTIAL", SAFE_IMPLEMENTATION="YES", SAFE_RECOVERY_STATE="<recovery_state_value>" *) reg [2:0] state = <state1>;
|
|
|
|
always@(posedge <clock>)
|
|
if (<reset>) begin
|
|
state <= <state1>;
|
|
end
|
|
else
|
|
(* PARALLEL_CASE *) case (state)
|
|
<state1> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state2> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state3> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state4> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state5> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state6> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state7> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state8> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
default : begin // Fault Recovery
|
|
state <= <state1>;
|
|
end
|
|
endcase
|
|
|
|
assign <output1> = <logic_equation_based_on_states_and_inputs>;
|
|
assign <output2> = <logic_equation_based_on_states_and_inputs>;
|
|
// Add other output equations as necessary
|
|
</Template>
|
|
<Template label="16 States" treetype="template">
|
|
parameter <state1> = 4'b0000;
|
|
parameter <state2> = 4'b0001;
|
|
parameter <state3> = 4'b0010;
|
|
parameter <state4> = 4'b0011;
|
|
parameter <state5> = 4'b0100;
|
|
parameter <state6> = 4'b0101;
|
|
parameter <state7> = 4'b0110;
|
|
parameter <state8> = 4'b0111;
|
|
parameter <state9> = 4'b1000;
|
|
parameter <state10> = 4'b1001;
|
|
parameter <state11> = 4'b1010;
|
|
parameter <state12> = 4'b1011;
|
|
parameter <state13> = 4'b1100;
|
|
parameter <state14> = 4'b1101;
|
|
parameter <state15> = 4'b1110;
|
|
parameter <state16> = 4'b1111;
|
|
|
|
(* FSM_ENCODING="SEQUNTIAL", SAFE_IMPLEMENTATION="YES", SAFE_RECOVERY_STATE="<recovery_state_value>" *) reg [3:0] state = <state1>;
|
|
|
|
always@(posedge <clock>)
|
|
if (<reset>) begin
|
|
state <= <state1>;
|
|
end
|
|
else
|
|
(* PARALLEL_CASE *) case (state)
|
|
<state1> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state2> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state3> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state4> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state5> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state6> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state7> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state8> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state9> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state10> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state11> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state12> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state13> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state14> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state15> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state16> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
default : begin // Fault Recovery
|
|
state <= <state1>;
|
|
end
|
|
endcase
|
|
|
|
assign <output1> = <logic_equation_based_on_states_and_inputs>;
|
|
assign <output2> = <logic_equation_based_on_states_and_inputs>;
|
|
// Add other output equations as necessary
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Fast" treetype="folder">
|
|
<Template label="4 States" treetype="template">
|
|
parameter <state1> = 2'b00;
|
|
parameter <state2> = 2'b01;
|
|
parameter <state3> = 2'b10;
|
|
parameter <state4> = 2'b11;
|
|
|
|
(* FSM_ENCODING="SEQUNTIAL", SAFE_IMPLEMENTATION="NO" *) reg [1:0] state = <state1>;
|
|
|
|
always@(posedge <clock>)
|
|
if (<reset>) begin
|
|
state <= <state1>;
|
|
end
|
|
else
|
|
(* FULL_CASE, PARALLEL_CASE *) case (state)
|
|
<state1> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state2> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state3> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state4> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
endcase
|
|
|
|
assign <output1> = <logic_equation_based_on_states_and_inputs>;
|
|
assign <output2> = <logic_equation_based_on_states_and_inputs>;
|
|
// Add other output equations as necessary
|
|
</Template>
|
|
<Template label="8 States" treetype="template">
|
|
parameter <state1> = 3'b000;
|
|
parameter <state2> = 3'b001;
|
|
parameter <state3> = 3'b010;
|
|
parameter <state4> = 3'b011;
|
|
parameter <state5> = 3'b100;
|
|
parameter <state6> = 3'b101;
|
|
parameter <state7> = 3'b110;
|
|
parameter <state8> = 3'b111;
|
|
|
|
(* FSM_ENCODING="SEQUNTIAL", SAFE_IMPLEMENTATION="NO" *) reg [2:0] state = <state1>;
|
|
|
|
always@(posedge <clock>)
|
|
if (<reset>) begin
|
|
state <= <state1>;
|
|
end
|
|
else
|
|
(* FULL_CASE, PARALLEL_CASE *) case (state)
|
|
<state1> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state2> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state3> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state4> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state5> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state6> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state7> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state8> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
endcase
|
|
|
|
assign <output1> = <logic_equation_based_on_states_and_inputs>;
|
|
assign <output2> = <logic_equation_based_on_states_and_inputs>;
|
|
// Add other output equations as necessary
|
|
</Template>
|
|
<Template label="16 States" treetype="template">
|
|
parameter <state1> = 4'b0000;
|
|
parameter <state2> = 4'b0001;
|
|
parameter <state3> = 4'b0010;
|
|
parameter <state4> = 4'b0011;
|
|
parameter <state5> = 4'b0100;
|
|
parameter <state6> = 4'b0101;
|
|
parameter <state7> = 4'b0110;
|
|
parameter <state8> = 4'b0111;
|
|
parameter <state9> = 4'b1000;
|
|
parameter <state10> = 4'b1001;
|
|
parameter <state11> = 4'b1010;
|
|
parameter <state12> = 4'b1011;
|
|
parameter <state13> = 4'b1100;
|
|
parameter <state14> = 4'b1101;
|
|
parameter <state15> = 4'b1110;
|
|
parameter <state16> = 4'b1111;
|
|
|
|
(* FSM_ENCODING="SEQUNTIAL", SAFE_IMPLEMENTATION="NO" *) reg [3:0] state = <state1>;
|
|
|
|
always@(posedge <clock>)
|
|
if (<reset>) begin
|
|
state <= <state1>;
|
|
end
|
|
else
|
|
(* FULL_CASE, PARALLEL_CASE *) case (state)
|
|
<state1> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state2> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state3> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state4> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state5> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state6> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state7> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state8> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state9> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state10> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state11> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state12> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state13> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state14> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state15> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
<state16> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
end
|
|
endcase
|
|
|
|
assign <output1> = <logic_equation_based_on_states_and_inputs>;
|
|
assign <output2> = <logic_equation_based_on_states_and_inputs>;
|
|
// Add other output equations as necessary
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Moore" treetype="folder">
|
|
<SubFolder label="One-Hot" treetype="folder">
|
|
<SubFolder label="Safe" treetype="folder">
|
|
<Template label="4 States" treetype="template">
|
|
parameter <state1> = 4'b0001;
|
|
parameter <state2> = 4'b0010;
|
|
parameter <state3> = 4'b0100;
|
|
parameter <state4> = 4'b1000;
|
|
|
|
(* FSM_ENCODING="ONE-HOT", SAFE_IMPLEMENTATION="YES", SAFE_RECOVERY_STATE="<recovery_state_value>" *) reg [3:0] state = <state1>;
|
|
|
|
always@(posedge <clock>)
|
|
if (<reset>) begin
|
|
state <= <state1>;
|
|
<outputs> <= <initial_values>;
|
|
end
|
|
else
|
|
(* PARALLEL_CASE *) case (state)
|
|
<state1> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state2> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state3> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state4> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
default: begin // Fault Recovery
|
|
state <= <state1>;
|
|
<outputs> <= <values>;
|
|
end
|
|
endcase
|
|
</Template>
|
|
<Template label="8 States" treetype="template">
|
|
parameter <state1> = 8'b00000001;
|
|
parameter <state2> = 8'b00000010;
|
|
parameter <state3> = 8'b00000100;
|
|
parameter <state4> = 8'b00001000;
|
|
parameter <state5> = 8'b00010000;
|
|
parameter <state6> = 8'b00100000;
|
|
parameter <state7> = 8'b01000000;
|
|
parameter <state8> = 8'b10000000;
|
|
|
|
(* FSM_ENCODING="ONE-HOT", SAFE_IMPLEMENTATION="YES", SAFE_RECOVERY_STATE="<recovery_state_value>" *) reg [7:0] state = <state1>;
|
|
|
|
always@(posedge <clock>)
|
|
if (<reset>) begin
|
|
state <= <state1>;
|
|
<outputs> <= <initial_values>;
|
|
end
|
|
else
|
|
(* PARALLEL_CASE *) case (state)
|
|
<state1> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state2> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state3> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state4> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state5> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state6> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state7> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state8> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
default: begin // Fault Recovery
|
|
state <= <state1>;
|
|
<outputs> <= <values>;
|
|
end
|
|
endcase
|
|
</Template>
|
|
<Template label="16 States" treetype="template">
|
|
parameter <state1> = 16'b0000000000000001;
|
|
parameter <state2> = 16'b0000000000000010;
|
|
parameter <state3> = 16'b0000000000000100;
|
|
parameter <state4> = 16'b0000000000001000;
|
|
parameter <state5> = 16'b0000000000010000;
|
|
parameter <state6> = 16'b0000000000100000;
|
|
parameter <state7> = 16'b0000000001000000;
|
|
parameter <state8> = 16'b0000000010000000;
|
|
parameter <state9> = 16'b0000000100000000;
|
|
parameter <state10> = 16'b0000001000000000;
|
|
parameter <state11> = 16'b0000010000000000;
|
|
parameter <state12> = 16'b0000100000000000;
|
|
parameter <state13> = 16'b0001000000000000;
|
|
parameter <state14> = 16'b0010000000000000;
|
|
parameter <state15> = 16'b0100000000000000;
|
|
parameter <state16> = 16'b1000000000000000;
|
|
|
|
(* FSM_ENCODING="ONE-HOT", SAFE_IMPLEMENTATION="YES", SAFE_RECOVERY_STATE="<recovery_state_value>" *) reg [15:0] state = <state1>;
|
|
|
|
always@(posedge <clock>)
|
|
if (<reset>) begin
|
|
state <= <state1>;
|
|
<outputs> <= <initial_values>;
|
|
end
|
|
else
|
|
(* PARALLEL_CASE *) case (state)
|
|
<state1> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state2> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state3> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state4> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state5> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state6> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state7> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state8> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state9> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state10> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state11> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state12> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state13> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state14> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state15> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state16> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
default: begin // Fault Recovery
|
|
state <= <state1>;
|
|
<outputs> <= <values>;
|
|
end
|
|
endcase
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Fast" treetype="folder">
|
|
<Template label="4 States" treetype="template">
|
|
parameter <state1> = 4'b0001;
|
|
parameter <state2> = 4'b0010;
|
|
parameter <state3> = 4'b0100;
|
|
parameter <state4> = 4'b1000;
|
|
|
|
(* FSM_ENCODING="ONE-HOT", SAFE_IMPLEMENTATION="NO" *) reg [3:0] state = <state1>;
|
|
|
|
always@(posedge <clock>)
|
|
if (<reset>) begin
|
|
state <= <state1>;
|
|
<outputs> <= <initial_values>;
|
|
end
|
|
else
|
|
(* FULL_CASE, PARALLEL_CASE *) case (state)
|
|
<state1> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state2> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state3> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state4> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
endcase
|
|
</Template>
|
|
<Template label="8 States" treetype="template">
|
|
parameter <state1> = 8'b00000001;
|
|
parameter <state2> = 8'b00000010;
|
|
parameter <state3> = 8'b00000100;
|
|
parameter <state4> = 8'b00001000;
|
|
parameter <state5> = 8'b00010000;
|
|
parameter <state6> = 8'b00100000;
|
|
parameter <state7> = 8'b01000000;
|
|
parameter <state8> = 8'b10000000;
|
|
|
|
(* FSM_ENCODING="ONE-HOT", SAFE_IMPLEMENTATION="NO" *) reg [7:0] state = <state1>;
|
|
|
|
always@(posedge <clock>)
|
|
if (<reset>) begin
|
|
state <= <state1>;
|
|
<outputs> <= <initial_values>;
|
|
end
|
|
else
|
|
(* FULL_CASE, PARALLEL_CASE *) case (state)
|
|
<state1> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state2> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state3> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state4> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state5> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state6> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state7> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state8> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
endcase
|
|
</Template>
|
|
<Template label="16 States" treetype="template">
|
|
parameter <state1> = 16'b0000000000000001;
|
|
parameter <state2> = 16'b0000000000000010;
|
|
parameter <state3> = 16'b0000000000000100;
|
|
parameter <state4> = 16'b0000000000001000;
|
|
parameter <state5> = 16'b0000000000010000;
|
|
parameter <state6> = 16'b0000000000100000;
|
|
parameter <state7> = 16'b0000000001000000;
|
|
parameter <state8> = 16'b0000000010000000;
|
|
parameter <state9> = 16'b0000000100000000;
|
|
parameter <state10> = 16'b0000001000000000;
|
|
parameter <state11> = 16'b0000010000000000;
|
|
parameter <state12> = 16'b0000100000000000;
|
|
parameter <state13> = 16'b0001000000000000;
|
|
parameter <state14> = 16'b0010000000000000;
|
|
parameter <state15> = 16'b0100000000000000;
|
|
parameter <state16> = 16'b1000000000000000;
|
|
|
|
(* FSM_ENCODING="ONE-HOT", SAFE_IMPLEMENTATION="NO" *) reg [15:0] state = <state1>;
|
|
|
|
always@(posedge <clock>)
|
|
if (<reset>) begin
|
|
state <= <state1>;
|
|
<outputs> <= <initial_values>;
|
|
end
|
|
else
|
|
(* FULL_CASE, PARALLEL_CASE *) case (state)
|
|
<state1> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state2> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state3> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state4> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state5> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state6> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state7> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state8> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state9> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state10> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state11> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state12> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state13> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state14> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state15> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state16> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
endcase
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Binary" treetype="folder">
|
|
<SubFolder label="Safe" treetype="folder">
|
|
<Template label="4 States" treetype="template">
|
|
parameter <state1> = 2'b00;
|
|
parameter <state2> = 2'b01;
|
|
parameter <state3> = 2'b10;
|
|
parameter <state4> = 2'b11;
|
|
|
|
(* FSM_ENCODING="SEQUENTIAL", SAFE_IMPLEMENTATION="YES", SAFE_RECOVERY_STATE="<recovery_state_value>" *) reg [1:0] state = <state1>;
|
|
|
|
always@(posedge <clock>)
|
|
if (<reset>) begin
|
|
state <= <state1>;
|
|
<outputs> <= <initial_values>;
|
|
end
|
|
else
|
|
(* PARALLEL_CASE, FULL_CASE *) case (state)
|
|
<state1> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state2> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state3> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state4> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
default : begin // Fault Recovery
|
|
state <= <state1>;
|
|
<outputs> <= <values>;
|
|
end
|
|
endcase
|
|
</Template>
|
|
<Template label="8 States" treetype="template">
|
|
parameter <state1> = 3'b000;
|
|
parameter <state2> = 3'b001;
|
|
parameter <state3> = 3'b010;
|
|
parameter <state4> = 3'b011;
|
|
parameter <state5> = 3'b100;
|
|
parameter <state6> = 3'b101;
|
|
parameter <state7> = 3'b110;
|
|
parameter <state8> = 3'b111;
|
|
|
|
(* FSM_ENCODING="SEQUENTIAL", SAFE_IMPLEMENTATION="YES", SAFE_RECOVERY_STATE="<recovery_state_value>" *) reg [2:0] state = <state1>;
|
|
|
|
always@(posedge <clock>)
|
|
if (<reset>) begin
|
|
state <= <state1>;
|
|
<outputs> <= <initial_values>;
|
|
end
|
|
else
|
|
(* PARALLEL_CASE, FULL_CASE *) case (state)
|
|
<state1> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state2> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state3> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state4> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state5> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state6> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state7> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state8> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
default : begin // Fault Recovery
|
|
state <= <state1>;
|
|
<outputs> <= <values>;
|
|
end
|
|
endcase
|
|
</Template>
|
|
<Template label="16 States" treetype="template">
|
|
parameter <state1> = 4'b0000;
|
|
parameter <state2> = 4'b0001;
|
|
parameter <state3> = 4'b0010;
|
|
parameter <state4> = 4'b0011;
|
|
parameter <state5> = 4'b0100;
|
|
parameter <state6> = 4'b0101;
|
|
parameter <state7> = 4'b0110;
|
|
parameter <state8> = 4'b0111;
|
|
parameter <state9> = 4'b1000;
|
|
parameter <state10> = 4'b1001;
|
|
parameter <state11> = 4'b1010;
|
|
parameter <state12> = 4'b1011;
|
|
parameter <state13> = 4'b1100;
|
|
parameter <state14> = 4'b1101;
|
|
parameter <state15> = 4'b1110;
|
|
parameter <state16> = 4'b1111;
|
|
|
|
(* FSM_ENCODING="SEQUENTIAL", SAFE_IMPLEMENTATION="YES", SAFE_RECOVERY_STATE="<recovery_state_value>" *) reg [3:0] state = <state1>;
|
|
|
|
always@(posedge <clock>)
|
|
if (<reset>) begin
|
|
state <= <state1>;
|
|
<outputs> <= <initial_values>;
|
|
end
|
|
else
|
|
(* PARALLEL_CASE, FULL_CASE *) case (state)
|
|
<state1> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state2> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state3> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state4> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state5> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state6> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state7> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state8> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state9> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state10> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state11> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state12> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state13> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state14> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state15> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state16> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
default : begin // Fault Recovery
|
|
state <= <state1>;
|
|
<outputs> <= <values>;
|
|
end
|
|
endcase
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Fast" treetype="folder">
|
|
<Template label="4 States" treetype="template">
|
|
parameter <state1> = 2'b00;
|
|
parameter <state2> = 2'b01;
|
|
parameter <state3> = 2'b10;
|
|
parameter <state4> = 2'b11;
|
|
|
|
(* FSM_ENCODING="SEQUENTIAL", SAFE_IMPLEMENTATION="NO" *) reg [1:0] state = <state1>;
|
|
|
|
always@(posedge <clock>)
|
|
if (<reset>) begin
|
|
state <= <state1>;
|
|
<outputs> <= <initial_values>;
|
|
end
|
|
else
|
|
(* FULL_CASE, PARALLEL_CASE *) case (state)
|
|
<state1> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state2> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state3> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state4> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
endcase
|
|
</Template>
|
|
<Template label="8 States" treetype="template">
|
|
parameter <state1> = 3'b000;
|
|
parameter <state2> = 3'b001;
|
|
parameter <state3> = 3'b010;
|
|
parameter <state4> = 3'b011;
|
|
parameter <state5> = 3'b100;
|
|
parameter <state6> = 3'b101;
|
|
parameter <state7> = 3'b110;
|
|
parameter <state8> = 3'b111;
|
|
|
|
(* FSM_ENCODING="SEQUENTIAL", SAFE_IMPLEMENTATION="NO" *) reg [2:0] state = <state1>;
|
|
|
|
always@(posedge <clock>)
|
|
if (<reset>) begin
|
|
state <= <state1>;
|
|
<outputs> <= <initial_values>;
|
|
end
|
|
else
|
|
(* FULL_CASE, PARALLEL_CASE *) case (state)
|
|
<state1> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state2> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state3> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state4> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state5> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state6> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state7> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state8> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
endcase
|
|
</Template>
|
|
<Template label="16 States" treetype="template">
|
|
parameter <state1> = 4'b0000;
|
|
parameter <state2> = 4'b0001;
|
|
parameter <state3> = 4'b0010;
|
|
parameter <state4> = 4'b0011;
|
|
parameter <state5> = 4'b0100;
|
|
parameter <state6> = 4'b0101;
|
|
parameter <state7> = 4'b0110;
|
|
parameter <state8> = 4'b0111;
|
|
parameter <state9> = 4'b1000;
|
|
parameter <state10> = 4'b1001;
|
|
parameter <state11> = 4'b1010;
|
|
parameter <state12> = 4'b1011;
|
|
parameter <state13> = 4'b1100;
|
|
parameter <state14> = 4'b1101;
|
|
parameter <state15> = 4'b1110;
|
|
parameter <state16> = 4'b1111;
|
|
|
|
(* FSM_ENCODING="SEQUENTIAL", SAFE_IMPLEMENTATION="NO" *) reg [3:0] state = <state1>;
|
|
|
|
always@(posedge <clock>)
|
|
if (<reset>) begin
|
|
state <= <state1>;
|
|
<outputs> <= <initial_values>;
|
|
end
|
|
else
|
|
(* FULL_CASE, PARALLEL_CASE *) case (state)
|
|
<state1> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state2> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state3> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state4> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state5> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state6> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state7> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state8> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state9> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state10> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state11> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state12> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state13> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state14> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state15> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
<state16> : begin
|
|
if (<condition>)
|
|
state <= <next_state>;
|
|
else if (<condition>)
|
|
state <= <next_state>;
|
|
else
|
|
state <= <next_state>;
|
|
<outputs> <= <values>;
|
|
end
|
|
endcase
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Encoders" treetype="folder">
|
|
<Template label="4-bit Registered Output" treetype="template">
|
|
reg [1:0] <output>;
|
|
|
|
<reg_or_wire> [3:0] <input>;
|
|
|
|
always @(posedge <clock>)
|
|
if (<reset>)
|
|
<output> <= 2'b00;
|
|
else
|
|
case (<input>)
|
|
4'b0001 : <output> <= 2'b00;
|
|
4'b0010 : <output> <= 2'b01;
|
|
4'b0100 : <output> <= 2'b10;
|
|
4'b1000 : <output> <= 2'b11;
|
|
default : <output> <= 2'b00;
|
|
endcase
|
|
</Template>
|
|
<Template label="8-bit Registered Output" treetype="template">
|
|
reg [2:0] <output>;
|
|
|
|
<reg_or_wire> [7:0] <input>;
|
|
|
|
always @(posedge <clock>)
|
|
if (<reset>)
|
|
<output> <= 3'b000;
|
|
else
|
|
case (<input>)
|
|
8'b00000001 : <output> <= 3'b000;
|
|
8'b00000010 : <output> <= 3'b001;
|
|
8'b00000100 : <output> <= 3'b010;
|
|
8'b00001000 : <output> <= 3'b011;
|
|
8'b00010000 : <output> <= 3'b100;
|
|
8'b00100000 : <output> <= 3'b101;
|
|
8'b01000000 : <output> <= 3'b110;
|
|
8'b10000000 : <output> <= 3'b111;
|
|
default : <output> <= 3'b000;
|
|
endcase
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Decoders" treetype="folder">
|
|
<Template label="4-bit Registered Output" treetype="template">
|
|
reg [3:0] <output>;
|
|
|
|
<reg_or_wire> [1:0] <input>;
|
|
|
|
always @(posedge <clock>)
|
|
if (<reset>)
|
|
<output> <= 4'h0;
|
|
else
|
|
case (<input>)
|
|
2'b00 : <output> <= 4'b0001;
|
|
2'b01 : <output> <= 4'b0010;
|
|
2'b10 : <output> <= 4'b0100;
|
|
2'b11 : <output> <= 4'b1000;
|
|
default : <output> <= 4'b0000;
|
|
endcase
|
|
</Template>
|
|
<Template label="8-bit Registered Output" treetype="template">
|
|
reg [7:0] <output>;
|
|
|
|
<reg_or_wire> [2:0] <input>;
|
|
|
|
always @(posedge <clock>)
|
|
if (<reset>)
|
|
<output> <= 8'h00;
|
|
else
|
|
case (<input>)
|
|
3'b000 : <output> <= 8'b00000001;
|
|
3'b001 : <output> <= 8'b00000010;
|
|
3'b010 : <output> <= 8'b00000100;
|
|
3'b011 : <output> <= 8'b00001000;
|
|
3'b100 : <output> <= 8'b00010000;
|
|
3'b101 : <output> <= 8'b00100000;
|
|
3'b110 : <output> <= 8'b01000000;
|
|
3'b111 : <output> <= 8'b10000000;
|
|
default : <output> <= 8'b00000000;
|
|
endcase
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Misc" treetype="folder">
|
|
<Template label="7-Segment Display Hex Conversion" treetype="template">
|
|
// 7-segment encoding
|
|
// 0
|
|
// ---
|
|
// 5 | | 1
|
|
// --- <--6
|
|
// 4 | | 2
|
|
// ---
|
|
// 3
|
|
|
|
always @(<4-bit_hex_input>)
|
|
case (<4-bit_hex_input>)
|
|
4'b0001 : <7-seg_output> = 7'b1111001; // 1
|
|
4'b0010 : <7-seg_output> = 7'b0100100; // 2
|
|
4'b0011 : <7-seg_output> = 7'b0110000; // 3
|
|
4'b0100 : <7-seg_output> = 7'b0011001; // 4
|
|
4'b0101 : <7-seg_output> = 7'b0010010; // 5
|
|
4'b0110 : <7-seg_output> = 7'b0000010; // 6
|
|
4'b0111 : <7-seg_output> = 7'b1111000; // 7
|
|
4'b1000 : <7-seg_output> = 7'b0000000; // 8
|
|
4'b1001 : <7-seg_output> = 7'b0010000; // 9
|
|
4'b1010 : <7-seg_output> = 7'b0001000; // A
|
|
4'b1011 : <7-seg_output> = 7'b0000011; // b
|
|
4'b1100 : <7-seg_output> = 7'b1000110; // C
|
|
4'b1101 : <7-seg_output> = 7'b0100001; // d
|
|
4'b1110 : <7-seg_output> = 7'b0000110; // E
|
|
4'b1111 : <7-seg_output> = 7'b0001110; // F
|
|
default : <7-seg_output> = 7'b1000000; // 0
|
|
endcase
|
|
</Template>
|
|
<Template label="One-shot, Debounce Circuit" treetype="template">
|
|
reg [2:0] <reg_name>;
|
|
|
|
always @ (posedge <clock>)
|
|
if (reset == 1)
|
|
<reg_name> <= 3'b000;
|
|
else
|
|
<reg_name> <= {<reg_name>[1:0], <input>};
|
|
|
|
assign <output> = <reg_name>[0] & <reg_name>[1] & !<reg_name>[2];
|
|
</Template>
|
|
<Template label="Pulse Width Modulation Circuit" treetype="template">
|
|
parameter PWM_PRECISION_WIDTH = <value>;
|
|
|
|
reg <pwm_output>;
|
|
reg [PWM_PRECISION_WIDTH-1:0] <duty_cycle_reg>, <temp_reg>;
|
|
|
|
always @ (posedge <clock>)
|
|
if (<reset>)
|
|
<duty_cycle_reg> <= 0;
|
|
else if (<new_duty_cycle>)
|
|
<duty_cycle_reg> <= <new_duty_cycle>;
|
|
|
|
always @ (posedge <clock>)
|
|
if (<reset>)
|
|
<temp_reg> <= 0;
|
|
else if (&<temp_reg>)
|
|
<temp_reg> <= <duty_cycle_reg>;
|
|
else if (<pwm_output>)
|
|
<temp_reg> <= <temp_reg> + 1;
|
|
else
|
|
<temp_reg> <= <temp_reg> - 1;
|
|
|
|
always @ (posedge <clock>)
|
|
if (<reset>)
|
|
<pwm_output> <= 1'b0;
|
|
else if (&<temp_reg>)
|
|
<pwm_output> <= ~<pwm_output>;
|
|
</Template>
|
|
<Template label="Open Drain Output (single signal)" treetype="template">
|
|
assign <output> = <internal_out> ? 1'bz : 1'b0;
|
|
</Template>
|
|
<Template label="Open Drain Output (bused reg)" treetype="template">
|
|
integer i;
|
|
|
|
always @*
|
|
for (i = 0; i <= <upper_val>; i=i+1)
|
|
<output>[i] = <internal_out>[i] ? 1'bz : 1'b0;
|
|
</Template>
|
|
<Template label="Asynchronous Input Synchronization (Reduces Issues w/ Metastability)" treetype="template">
|
|
// The forllowing code is an example of double registering an asynchronous input
|
|
// of a design to reduce the probability of metastability affecting a circuit.
|
|
// Several synthesis and implementation attributes are added to the code in
|
|
// order improve the characteristics of the implementation:
|
|
//
|
|
// ASYNC_REG="TRUE" - Specifies registers will be receiving asynchronous data
|
|
// input to allow for better timing simulation
|
|
// characteristics
|
|
|
|
module async_input_sync(
|
|
input clk,
|
|
input async_in,
|
|
output reg sync_out
|
|
);
|
|
|
|
(* ASYNC_REG="TRUE" *) reg [1:0] sreg;
|
|
always @(posedge clk) begin
|
|
sync_out <= sreg[1];
|
|
sreg <= {sreg[0], async_in};
|
|
end
|
|
|
|
endmodule
|
|
</Template>
|
|
<SubFolder label="Output Clock forwarding Using DDR" treetype="folder">
|
|
<Template label="Info (Clock forwarding)" treetype="template">
|
|
// A common method for supplying an external clock from the FPGA to drive
|
|
// other devices on the PCB board is to use clock forwarding via a double
|
|
// data-rate register. This provides an external clock with a relatively
|
|
// small offset delay and does not consume any additional DLL/DCM/PLL/MMCM, clock
|
|
// buffers or input pins. The basic technique is to supply the input clock
|
|
// to an output DDR register where one value is tied to a logic 0 and the
|
|
// other is tied to a logic 1. A clock can be made with the same phase
|
|
// relationship (plus the added offset delay) or 180 degrees out of phase by
|
|
// changing the 1 and 0 values to the inputs to the DDR register. Set SRTYPE
|
|
// to "SYNC" to avoid possible glitches on the clock if the set/reset signals
|
|
// are used. for FPGA architectures which use two separate clocks into the
|
|
// DDR register, you may use a simple inversion of duty-cycle is not important
|
|
// however for output clocks that you wish to retain the duty-cycle as much as
|
|
// possible, it is suggested to supply a 0 degree and 180 degree clock from a
|
|
// DLL/DCM/PLL/MMCM to the input clocks to the output DDR component.
|
|
</Template>
|
|
<Template label="Virtex-4/5/6" treetype="template">
|
|
// Clock forwarding circuit using the double data-rate register
|
|
// Virtex-4/5/6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ODDR #(
|
|
.DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE"
|
|
.INIT(1'b0), // Initial value of Q: 1'b0 or 1'b1
|
|
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
|
|
) clock_forward_inst (
|
|
.Q(<output_clock>), // 1-bit DDR output
|
|
.C(<internal_clock>), // 1-bit clock input
|
|
.CE(<stop_clock>), // 1-bit clock enable input
|
|
.D1(1'b0), // 1-bit data input (positive edge)
|
|
.D2(1'b1), // 1-bit data input (negative edge)
|
|
.R(<hold_clock_low>), // 1-bit reset
|
|
.S(<hold_clock_high>) // 1-bit set
|
|
);
|
|
|
|
// End of clock_forward_inst instantiation
|
|
</Template>
|
|
<Template label="Spartan-3E/3A/6" treetype="template">
|
|
// Clock forwarding circuit using the double data-rate register
|
|
// Spartan-3E/3A/6
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
ODDR2 #(
|
|
.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
|
|
.INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1
|
|
.SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
|
|
) clock_forward_inst (
|
|
.Q(<output_clock>), // 1-bit DDR output data
|
|
.C0(<internal_clock>), // 1-bit clock input
|
|
.C1(~<internal_clock>), // 1-bit clock input
|
|
.CE(<stop_clock>), // 1-bit clock enable input
|
|
.D0(1'b0), // 1-bit data input (associated with C0)
|
|
.D1(1'b1), // 1-bit data input (associated with C1)
|
|
.R(<hold_clock_low>), // 1-bit reset input
|
|
.S(<hold_clock_high>) // 1-bit set input
|
|
);
|
|
|
|
// End of clock_forward_inst instantiation
|
|
</Template>
|
|
<Template label="Spartan-3" treetype="template">
|
|
// Clock forwarding circuit using the double data-rate register
|
|
// Spartan-3
|
|
// Xilinx HDL Language Template, version 14.7
|
|
|
|
OFDDRRSE OFDDRRSE_inst (
|
|
.Q(<output_clock>), // Data output (connect directly to top-level port)
|
|
.C0(<internal_clock>), // 0 degree clock input
|
|
.C1(~<internal_clock>), // 180 degree clock input
|
|
.CE(<stop_clock>), // Clock enable input
|
|
.D0(1'b0), // Posedge data input
|
|
.D1(1'b1), // Negedge data input
|
|
.R(<hold_clock_low>), // Synchronous reset input
|
|
.S(<hold_clock_high>) // Synchronous preset input
|
|
);
|
|
|
|
// End of clock_forward_inst instantiation
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Bi-directional I/O" treetype="folder">
|
|
<SubFolder label="Registered Input, Output and OE" treetype="folder">
|
|
<Template label="1-bit Registered" treetype="template">
|
|
inout <top_level_port>;
|
|
|
|
reg <input_reg>, <output_reg>, <output_enable_reg>;
|
|
|
|
assign <top_level_port> = <output_enable_reg> ? <output_reg> : 1'bz;
|
|
|
|
always @(posedge <clock>)
|
|
if (<reset>) begin
|
|
<input_reg> <= 1'b0;
|
|
<output_reg> <= 1'b0;
|
|
<output_enable_reg> <= 1'b0;
|
|
end else begin
|
|
<input_reg> <= <top_level_port>;
|
|
<output_reg> <= <output_signal>;
|
|
<output_enable_reg> <= <output_enable_signal>;
|
|
end
|
|
</Template>
|
|
<Template label="2-bit" treetype="template">
|
|
inout [1:0] <top_level_port>;
|
|
|
|
reg [1:0] <input_reg>, <output_reg>, <output_enable_reg>;
|
|
|
|
assign <top_level_port>[0] = <output_enable_reg>[0] ? <output_reg>[0] : 1'bz;
|
|
assign <top_level_port>[1] = <output_enable_reg>[1] ? <output_reg>[1] : 1'bz;
|
|
|
|
always @(posedge <clock>)
|
|
if (<reset>) begin
|
|
<input_reg> <= 2'b00;
|
|
<output_reg> <= 2'b00;
|
|
<output_enable_reg> <= 2'b00;
|
|
end else begin
|
|
<input_reg> <= <top_level_port>;
|
|
<output_reg> <= <output_signal>;
|
|
<output_enable_reg> <= {2{<output_enable_signal>}};
|
|
end
|
|
</Template>
|
|
<Template label="4-bit" treetype="template">
|
|
inout [3:0] <top_level_port>;
|
|
|
|
reg [3:0] <input_reg>, <output_reg>, <output_enable_reg>;
|
|
|
|
assign <top_level_port>[0] = <output_enable_reg>[0] ? <output_reg>[0] : 1'bz;
|
|
assign <top_level_port>[1] = <output_enable_reg>[1] ? <output_reg>[1] : 1'bz;
|
|
assign <top_level_port>[2] = <output_enable_reg>[2] ? <output_reg>[2] : 1'bz;
|
|
assign <top_level_port>[3] = <output_enable_reg>[3] ? <output_reg>[3] : 1'bz;
|
|
|
|
always @(posedge <clock>)
|
|
if (<reset>) begin
|
|
<input_reg> <= 4'h0;
|
|
<output_reg> <= 4'h0;
|
|
<output_enable_reg> <= 4'h0;
|
|
end else begin
|
|
<input_reg> <= <top_level_port>;
|
|
<output_reg> <= <output_signal>;
|
|
<output_enable_reg> <= {4{<output_enable_signal>}};
|
|
end
|
|
</Template>
|
|
<Template label="8-bit" treetype="template">
|
|
inout [7:0] <top_level_port>;
|
|
|
|
reg [7:0] <input_reg>, <output_reg>, <output_enable_reg>;
|
|
|
|
assign <top_level_port>[0] = <output_enable_reg>[0] ? <output_reg>[0] : 1'bz;
|
|
assign <top_level_port>[1] = <output_enable_reg>[1] ? <output_reg>[1] : 1'bz;
|
|
assign <top_level_port>[2] = <output_enable_reg>[2] ? <output_reg>[2] : 1'bz;
|
|
assign <top_level_port>[3] = <output_enable_reg>[3] ? <output_reg>[3] : 1'bz;
|
|
assign <top_level_port>[4] = <output_enable_reg>[4] ? <output_reg>[4] : 1'bz;
|
|
assign <top_level_port>[5] = <output_enable_reg>[5] ? <output_reg>[5] : 1'bz;
|
|
assign <top_level_port>[6] = <output_enable_reg>[6] ? <output_reg>[6] : 1'bz;
|
|
assign <top_level_port>[7] = <output_enable_reg>[7] ? <output_reg>[7] : 1'bz;
|
|
|
|
always @(posedge <clock>)
|
|
if (<reset>) begin
|
|
<input_reg> <= 8'h00;
|
|
<output_reg> <= 8'h00;
|
|
<output_enable_reg> <= 8'h00;
|
|
end else begin
|
|
<input_reg> <= <top_level_port>;
|
|
<output_reg> <= <output_signal>;
|
|
<output_enable_reg> <= {8{<output_enable_signal>}};
|
|
end
|
|
</Template>
|
|
<Template label="16-bit" treetype="template">
|
|
inout [15:0] <top_level_port>;
|
|
|
|
reg [15:0] <input_reg>, <output_reg>, <output_enable_reg>;
|
|
|
|
assign <top_level_port>[0] = <output_enable_reg>[0] ? <output_reg>[0] : 1'bz;
|
|
assign <top_level_port>[1] = <output_enable_reg>[1] ? <output_reg>[1] : 1'bz;
|
|
assign <top_level_port>[2] = <output_enable_reg>[2] ? <output_reg>[2] : 1'bz;
|
|
assign <top_level_port>[3] = <output_enable_reg>[3] ? <output_reg>[3] : 1'bz;
|
|
assign <top_level_port>[4] = <output_enable_reg>[4] ? <output_reg>[4] : 1'bz;
|
|
assign <top_level_port>[5] = <output_enable_reg>[5] ? <output_reg>[5] : 1'bz;
|
|
assign <top_level_port>[6] = <output_enable_reg>[6] ? <output_reg>[6] : 1'bz;
|
|
assign <top_level_port>[7] = <output_enable_reg>[7] ? <output_reg>[7] : 1'bz;
|
|
assign <top_level_port>[8] = <output_enable_reg>[8] ? <output_reg>[8] : 1'bz;
|
|
assign <top_level_port>[9] = <output_enable_reg>[9] ? <output_reg>[9] : 1'bz;
|
|
assign <top_level_port>[10] = <output_enable_reg>[10] ? <output_reg>[10] : 1'bz;
|
|
assign <top_level_port>[11] = <output_enable_reg>[11] ? <output_reg>[11] : 1'bz;
|
|
assign <top_level_port>[12] = <output_enable_reg>[12] ? <output_reg>[12] : 1'bz;
|
|
assign <top_level_port>[13] = <output_enable_reg>[13] ? <output_reg>[13] : 1'bz;
|
|
assign <top_level_port>[14] = <output_enable_reg>[14] ? <output_reg>[14] : 1'bz;
|
|
assign <top_level_port>[15] = <output_enable_reg>[15] ? <output_reg>[15] : 1'bz;
|
|
|
|
always @(posedge <clock>)
|
|
if (<reset>) begin
|
|
<input_reg> <= 16'h0000;
|
|
<output_reg> <= 16'h0000;
|
|
<output_enable_reg> <= 16'h0000;
|
|
end else begin
|
|
<input_reg> <= <top_level_port>;
|
|
<output_reg> <= <output_signal>;
|
|
<output_enable_reg> <= {16{<output_enable_signal>}};
|
|
end
|
|
</Template>
|
|
<Template label="32-bit" treetype="template">
|
|
inout [31:0] <top_level_port>;
|
|
|
|
reg [31:0] <input_reg>, <output_reg>, <output_enable_reg>;
|
|
|
|
assign <top_level_port>[0] = <output_enable_reg>[0] ? <output_reg>[0] : 1'bz;
|
|
assign <top_level_port>[1] = <output_enable_reg>[1] ? <output_reg>[1] : 1'bz;
|
|
assign <top_level_port>[2] = <output_enable_reg>[2] ? <output_reg>[2] : 1'bz;
|
|
assign <top_level_port>[3] = <output_enable_reg>[3] ? <output_reg>[3] : 1'bz;
|
|
assign <top_level_port>[4] = <output_enable_reg>[4] ? <output_reg>[4] : 1'bz;
|
|
assign <top_level_port>[5] = <output_enable_reg>[5] ? <output_reg>[5] : 1'bz;
|
|
assign <top_level_port>[6] = <output_enable_reg>[6] ? <output_reg>[6] : 1'bz;
|
|
assign <top_level_port>[7] = <output_enable_reg>[7] ? <output_reg>[7] : 1'bz;
|
|
assign <top_level_port>[8] = <output_enable_reg>[8] ? <output_reg>[8] : 1'bz;
|
|
assign <top_level_port>[9] = <output_enable_reg>[9] ? <output_reg>[9] : 1'bz;
|
|
assign <top_level_port>[10] = <output_enable_reg>[10] ? <output_reg>[10] : 1'bz;
|
|
assign <top_level_port>[11] = <output_enable_reg>[11] ? <output_reg>[11] : 1'bz;
|
|
assign <top_level_port>[12] = <output_enable_reg>[12] ? <output_reg>[12] : 1'bz;
|
|
assign <top_level_port>[13] = <output_enable_reg>[13] ? <output_reg>[13] : 1'bz;
|
|
assign <top_level_port>[14] = <output_enable_reg>[14] ? <output_reg>[14] : 1'bz;
|
|
assign <top_level_port>[15] = <output_enable_reg>[15] ? <output_reg>[15] : 1'bz;
|
|
assign <top_level_port>[16] = <output_enable_reg>[16] ? <output_reg>[16] : 1'bz;
|
|
assign <top_level_port>[17] = <output_enable_reg>[17] ? <output_reg>[17] : 1'bz;
|
|
assign <top_level_port>[18] = <output_enable_reg>[18] ? <output_reg>[18] : 1'bz;
|
|
assign <top_level_port>[19] = <output_enable_reg>[19] ? <output_reg>[19] : 1'bz;
|
|
assign <top_level_port>[20] = <output_enable_reg>[20] ? <output_reg>[20] : 1'bz;
|
|
assign <top_level_port>[21] = <output_enable_reg>[21] ? <output_reg>[21] : 1'bz;
|
|
assign <top_level_port>[22] = <output_enable_reg>[22] ? <output_reg>[22] : 1'bz;
|
|
assign <top_level_port>[23] = <output_enable_reg>[23] ? <output_reg>[23] : 1'bz;
|
|
assign <top_level_port>[24] = <output_enable_reg>[24] ? <output_reg>[24] : 1'bz;
|
|
assign <top_level_port>[25] = <output_enable_reg>[25] ? <output_reg>[25] : 1'bz;
|
|
assign <top_level_port>[26] = <output_enable_reg>[26] ? <output_reg>[26] : 1'bz;
|
|
assign <top_level_port>[27] = <output_enable_reg>[27] ? <output_reg>[27] : 1'bz;
|
|
assign <top_level_port>[28] = <output_enable_reg>[28] ? <output_reg>[28] : 1'bz;
|
|
assign <top_level_port>[29] = <output_enable_reg>[29] ? <output_reg>[29] : 1'bz;
|
|
assign <top_level_port>[30] = <output_enable_reg>[30] ? <output_reg>[30] : 1'bz;
|
|
assign <top_level_port>[31] = <output_enable_reg>[31] ? <output_reg>[31] : 1'bz;
|
|
|
|
always @(posedge <clock>)
|
|
if (<reset>) begin
|
|
<input_reg> <= 32'h00000000;
|
|
<output_reg> <= 32'h00000000;
|
|
<output_enable_reg> <= 32'h00000000;
|
|
end else begin
|
|
<input_reg> <= <top_level_port>;
|
|
<output_reg> <= <output_signal>;
|
|
<output_enable_reg> <= {32{<output_enable_signal>}};
|
|
end
|
|
</Template>
|
|
</SubFolder>
|
|
<Template label="Info" treetype="template">
|
|
|
|
// The forllowing represents the connectivity of the registered
|
|
// bi-directional I/O example
|
|
//
|
|
// ______
|
|
// | |
|
|
// |----------|D |
|
|
// | | Q|-----in_reg
|
|
// | clock___|\ |
|
|
// ________________ | |/ |
|
|
// / top_level_port \______| |_____|
|
|
// \________________/ |
|
|
// |
|
|
// | /|
|
|
// |____/ |________________________
|
|
// \ | _____ |
|
|
// _____ |\| | | |
|
|
// | | | out_sig-|D Q|----|
|
|
// out_en-----|D Q|____| | |
|
|
// | | clock___|\ |
|
|
// clock_|\ | |/ |
|
|
// |/ | |_____|
|
|
// |_____|
|
|
//
|
|
//
|
|
//
|
|
// The forllowing represents the connectivity of the unregistered
|
|
// bi-directional I/O example
|
|
//
|
|
// |----------input_signal
|
|
// |
|
|
// |
|
|
// ________________ |
|
|
// / top_level_port \______|
|
|
// \________________/ |
|
|
// |
|
|
// | /|
|
|
// |____/ |______output_signal
|
|
// \ |
|
|
// |\|
|
|
// |
|
|
// |---output_enable_signal
|
|
//
|
|
</Template>
|
|
<SubFolder label="Unregistered" treetype="folder">
|
|
<Template label="1-bit" treetype="template">
|
|
inout <top_level_port>;
|
|
|
|
wire <output_enable_signal>, <output_signal>, <input_signal>;
|
|
|
|
assign <top_level_port> = <output_enable_signal> ? <output_signal> : 1'bz;
|
|
|
|
assign <input_signal> = <top_level_port>;
|
|
</Template>
|
|
<Template label="2-bit" treetype="template">
|
|
inout [1:0] <top_level_port>;
|
|
|
|
wire [1:0] <output_signal>, <input_signal>;
|
|
wire <output_enable_signal>;
|
|
|
|
assign <top_level_port> = <output_enable_signal> ? <output_signal> : 2'bzz;
|
|
|
|
assign <input_signal> = <top_level_port>;
|
|
</Template>
|
|
<Template label="4-bit" treetype="template">
|
|
inout [3:0] <top_level_port>;
|
|
|
|
wire [3:0] <output_signal>, <input_signal>;
|
|
wire <output_enable_signal>;
|
|
|
|
assign <top_level_port> = <output_enable_signal> ? <output_signal> : 4'hz;
|
|
|
|
assign <input_signal> = <top_level_port>;
|
|
</Template>
|
|
<Template label="8-bit" treetype="template">
|
|
inout [7:0] <top_level_port>;
|
|
|
|
wire [7:0] <output_signal>, <input_signal>;
|
|
wire <output_enable_signal>;
|
|
|
|
assign <top_level_port> = <output_enable_signal> ? <output_signal> : 8'hzz;
|
|
|
|
assign <input_signal> = <top_level_port>;
|
|
</Template>
|
|
<Template label="16-bit" treetype="template">
|
|
inout [15:0] <top_level_port>;
|
|
|
|
wire [15:0] <output_signal>, <input_signal>;
|
|
wire <output_enable_signal>;
|
|
|
|
assign <top_level_port> = <output_enable_signal> ? <output_signal> : 16'hzzzz;
|
|
|
|
assign <input_signal> = <top_level_port>;
|
|
</Template>
|
|
<Template label="32-bit" treetype="template">
|
|
inout [31:0] <top_level_port>;
|
|
|
|
wire [31:0] <output_signal>, <input_signal>;
|
|
wire <output_enable_signal>;
|
|
|
|
assign <top_level_port> = <output_enable_signal> ? <output_signal> : 32'hzzzzzzzz;
|
|
|
|
assign <input_signal> = <top_level_port>;
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Registered Input only" treetype="folder">
|
|
<Template label="1-bit" treetype="template">
|
|
inout <top_level_port>;
|
|
|
|
wire <output_enable_signal>, <output_signal>;
|
|
reg <input_reg>;
|
|
|
|
assign <top_level_port> = <output_enable_signal> ? <output_signal> : 1'bz;
|
|
|
|
always @(posedge <clock>)
|
|
if (<reset>)
|
|
<input_reg> <= 1'b0;
|
|
else
|
|
<input_reg> <= <top_level_port>;
|
|
</Template>
|
|
<Template label="2-bit" treetype="template">
|
|
inout [1:0] <top_level_port>;
|
|
|
|
wire [1:0] <output_signal>;
|
|
wire <output_enable_signal>;
|
|
reg [1:0] <input_reg>;
|
|
|
|
assign <top_level_port> = <output_enable_signal> ? <output_signal> : 2'bzz;
|
|
|
|
always @(posedge <clock>)
|
|
if (<reset>)
|
|
<input_reg> <= 2'b00;
|
|
else
|
|
<input_reg> <= <top_level_port>;
|
|
</Template>
|
|
<Template label="4-bit" treetype="template">
|
|
inout [3:0] <top_level_port>;
|
|
|
|
wire [3:0] <output_signal>;
|
|
wire <output_enable_signal>;
|
|
reg [3:0] <input_reg>;
|
|
|
|
assign <top_level_port> = <output_enable_signal> ? <output_signal> : 4'hz;
|
|
|
|
always @(posedge <clock>)
|
|
if (<reset>)
|
|
<input_reg> <= 4'h0;
|
|
else
|
|
<input_reg> <= <top_level_port>;
|
|
</Template>
|
|
<Template label="8-bit" treetype="template">
|
|
inout [7:0] <top_level_port>;
|
|
|
|
wire [7:0] <output_signal>;
|
|
wire <output_enable_signal>;
|
|
reg [7:0] <input_reg>;
|
|
|
|
assign <top_level_port> = <output_enable_signal> ? <output_signal> : 8'hzz;
|
|
|
|
always @(posedge <clock>)
|
|
if (<reset>)
|
|
<input_reg> <= 8'h00;
|
|
else
|
|
<input_reg> <= <top_level_port>;
|
|
</Template>
|
|
<Template label="16-bit" treetype="template">
|
|
inout [15:0] <top_level_port>;
|
|
|
|
wire [15:0] <output_signal>;
|
|
wire <output_enable_signal>;
|
|
reg [15:0] <input_reg>;
|
|
|
|
assign <top_level_port> = <output_enable_signal> ? <output_signal> : 16'hzzzz;
|
|
|
|
always @(posedge <clock>)
|
|
if (<reset>)
|
|
<input_reg> <= 16'h0000;
|
|
else
|
|
<input_reg> <= <top_level_port>;
|
|
</Template>
|
|
<Template label="32-bit" treetype="template">
|
|
inout [31:0] <top_level_port>;
|
|
|
|
wire [31:0] <output_signal>;
|
|
wire <output_enable_signal>;
|
|
reg [31:0] <input_reg>;
|
|
|
|
assign <top_level_port> = <output_enable_signal> ? <output_signal> : 32'hzzzzzzzz;
|
|
|
|
always @(posedge <clock>)
|
|
if (<reset>)
|
|
<input_reg> <= 32'h00000000;
|
|
else
|
|
<input_reg> <= <top_level_port>;
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Registered Output and Output Enable only" treetype="folder">
|
|
<Template label="1-bit" treetype="template">
|
|
inout <top_level_port>;
|
|
|
|
reg <output_reg>, <output_enable_reg>;
|
|
wire <input_signal>, <output_enable_wire>, <output_signal>;
|
|
|
|
assign <input_signal> = <top_level_port>;
|
|
|
|
assign <top_level_port> = <output_enable_reg> ? <output_reg> : 1'bz;
|
|
|
|
always @(posedge <clock>)
|
|
if (<reset>) begin
|
|
<output_reg> <= 1'b0;
|
|
<output_enable_reg> <= 1'b0;
|
|
end
|
|
else begin
|
|
<output_reg> <= <output_signal>;
|
|
<output_enable_reg> <= <output_enable_signal>;
|
|
end
|
|
</Template>
|
|
<Template label="2-bit" treetype="template">
|
|
inout [1:0] <top_level_port>;
|
|
|
|
reg [1:0] <output_reg>, <output_enable_reg>;
|
|
wire [1:0] <input_signal>, <output_signal>;
|
|
wire <output_enable_wire>;
|
|
|
|
assign <input_signal> = <top_level_port>;
|
|
|
|
assign <top_level_port>[0] = <output_enable_reg>[0] ? <output_reg>[0] : 1'bz;
|
|
assign <top_level_port>[1] = <output_enable_reg>[1] ? <output_reg>[1] : 1'bz;
|
|
|
|
always @(posedge <clock>)
|
|
if (<reset>) begin
|
|
<output_reg> <= 2'b00;
|
|
<output_enable_reg> <= 2'b00;
|
|
end
|
|
else begin
|
|
<output_reg> <= <output_signal>;
|
|
<output_enable_reg> <= {2{<output_enable_signal>}};
|
|
end
|
|
</Template>
|
|
<Template label="4-bit" treetype="template">
|
|
inout [3:0] <top_level_port>;
|
|
|
|
reg [3:0] <output_reg>, <output_enable_reg>;
|
|
wire [3:0] <input_signal>, <output_signal>;
|
|
wire <output_enable_wire>;
|
|
|
|
assign <input_signal> = <top_level_port>;
|
|
|
|
assign <top_level_port>[0] = <output_enable_reg>[0] ? <output_reg>[0] : 1'bz;
|
|
assign <top_level_port>[1] = <output_enable_reg>[1] ? <output_reg>[1] : 1'bz;
|
|
assign <top_level_port>[2] = <output_enable_reg>[2] ? <output_reg>[2] : 1'bz;
|
|
assign <top_level_port>[3] = <output_enable_reg>[3] ? <output_reg>[3] : 1'bz;
|
|
|
|
always @(posedge <clock>)
|
|
if (<reset>) begin
|
|
<output_reg> <= 4'h0;
|
|
<output_enable_reg> <= 4'h0;
|
|
end
|
|
else begin
|
|
<output_reg> <= <output_signal>;
|
|
<output_enable_reg> <= {4{<output_enable_signal>}};
|
|
end
|
|
</Template>
|
|
<Template label="8-bit" treetype="template">
|
|
inout [7:0] <top_level_port>;
|
|
|
|
reg [7:0] <output_reg>, <output_enable_reg>;
|
|
wire [7:0] <input_signal>, <output_signal>;
|
|
wire <output_enable_wire>;
|
|
|
|
assign <input_signal> = <top_level_port>;
|
|
|
|
assign <top_level_port>[0] = <output_enable_reg>[0] ? <output_reg>[0] : 1'bz;
|
|
assign <top_level_port>[1] = <output_enable_reg>[1] ? <output_reg>[1] : 1'bz;
|
|
assign <top_level_port>[2] = <output_enable_reg>[2] ? <output_reg>[2] : 1'bz;
|
|
assign <top_level_port>[3] = <output_enable_reg>[3] ? <output_reg>[3] : 1'bz;
|
|
assign <top_level_port>[4] = <output_enable_reg>[4] ? <output_reg>[4] : 1'bz;
|
|
assign <top_level_port>[5] = <output_enable_reg>[5] ? <output_reg>[5] : 1'bz;
|
|
assign <top_level_port>[6] = <output_enable_reg>[6] ? <output_reg>[6] : 1'bz;
|
|
assign <top_level_port>[7] = <output_enable_reg>[7] ? <output_reg>[7] : 1'bz;
|
|
|
|
always @(posedge <clock>)
|
|
if (<reset>) begin
|
|
<output_reg> <= 8'h00;
|
|
<output_enable_reg> <= 8'h00;
|
|
end
|
|
else begin
|
|
<output_reg> <= <output_signal>;
|
|
<output_enable_reg> <= {8{<output_enable_signal>}};
|
|
end
|
|
</Template>
|
|
<Template label="16-bit" treetype="template">
|
|
inout [15:0] <top_level_port>;
|
|
|
|
reg [15:0] <output_reg>, <output_enable_reg>;
|
|
wire [15:0] <input_signal>, <output_signal>;
|
|
wire <output_enable_wire>;
|
|
|
|
assign <input_signal> = <top_level_port>;
|
|
|
|
assign <top_level_port>[0] = <output_enable_reg>[0] ? <output_reg>[0] : 1'bz;
|
|
assign <top_level_port>[1] = <output_enable_reg>[1] ? <output_reg>[1] : 1'bz;
|
|
assign <top_level_port>[2] = <output_enable_reg>[2] ? <output_reg>[2] : 1'bz;
|
|
assign <top_level_port>[3] = <output_enable_reg>[3] ? <output_reg>[3] : 1'bz;
|
|
assign <top_level_port>[4] = <output_enable_reg>[4] ? <output_reg>[4] : 1'bz;
|
|
assign <top_level_port>[5] = <output_enable_reg>[5] ? <output_reg>[5] : 1'bz;
|
|
assign <top_level_port>[6] = <output_enable_reg>[6] ? <output_reg>[6] : 1'bz;
|
|
assign <top_level_port>[7] = <output_enable_reg>[7] ? <output_reg>[7] : 1'bz;
|
|
assign <top_level_port>[8] = <output_enable_reg>[8] ? <output_reg>[8] : 1'bz;
|
|
assign <top_level_port>[9] = <output_enable_reg>[9] ? <output_reg>[9] : 1'bz;
|
|
assign <top_level_port>[10] = <output_enable_reg>[10] ? <output_reg>[10] : 1'bz;
|
|
assign <top_level_port>[11] = <output_enable_reg>[11] ? <output_reg>[11] : 1'bz;
|
|
assign <top_level_port>[12] = <output_enable_reg>[12] ? <output_reg>[12] : 1'bz;
|
|
assign <top_level_port>[13] = <output_enable_reg>[13] ? <output_reg>[13] : 1'bz;
|
|
assign <top_level_port>[14] = <output_enable_reg>[14] ? <output_reg>[14] : 1'bz;
|
|
assign <top_level_port>[15] = <output_enable_reg>[15] ? <output_reg>[15] : 1'bz;
|
|
|
|
always @(posedge <clock>)
|
|
if (<reset>) begin
|
|
<output_reg> <= 16'h0000;
|
|
<output_enable_reg> <= 16'h0000;
|
|
end
|
|
else begin
|
|
<output_reg> <= <output_signal>;
|
|
<output_enable_reg> <= {16{<output_enable_signal>}};
|
|
end
|
|
</Template>
|
|
<Template label="32-bit" treetype="template">
|
|
inout [31:0] <top_level_port>;
|
|
|
|
reg [31:0] <output_reg>, <output_enable_reg>;
|
|
wire [31:0] <input_signal>, <output_signal>;
|
|
wire <output_enable_wire>;
|
|
|
|
assign <input_signal> = <top_level_port>;
|
|
|
|
assign <top_level_port>[0] = <output_enable_reg>[0] ? <output_reg>[0] : 1'bz;
|
|
assign <top_level_port>[1] = <output_enable_reg>[1] ? <output_reg>[1] : 1'bz;
|
|
assign <top_level_port>[2] = <output_enable_reg>[2] ? <output_reg>[2] : 1'bz;
|
|
assign <top_level_port>[3] = <output_enable_reg>[3] ? <output_reg>[3] : 1'bz;
|
|
assign <top_level_port>[4] = <output_enable_reg>[4] ? <output_reg>[4] : 1'bz;
|
|
assign <top_level_port>[5] = <output_enable_reg>[5] ? <output_reg>[5] : 1'bz;
|
|
assign <top_level_port>[6] = <output_enable_reg>[6] ? <output_reg>[6] : 1'bz;
|
|
assign <top_level_port>[7] = <output_enable_reg>[7] ? <output_reg>[7] : 1'bz;
|
|
assign <top_level_port>[8] = <output_enable_reg>[8] ? <output_reg>[8] : 1'bz;
|
|
assign <top_level_port>[9] = <output_enable_reg>[9] ? <output_reg>[9] : 1'bz;
|
|
assign <top_level_port>[10] = <output_enable_reg>[10] ? <output_reg>[10] : 1'bz;
|
|
assign <top_level_port>[11] = <output_enable_reg>[11] ? <output_reg>[11] : 1'bz;
|
|
assign <top_level_port>[12] = <output_enable_reg>[12] ? <output_reg>[12] : 1'bz;
|
|
assign <top_level_port>[13] = <output_enable_reg>[13] ? <output_reg>[13] : 1'bz;
|
|
assign <top_level_port>[14] = <output_enable_reg>[14] ? <output_reg>[14] : 1'bz;
|
|
assign <top_level_port>[15] = <output_enable_reg>[15] ? <output_reg>[15] : 1'bz;
|
|
assign <top_level_port>[16] = <output_enable_reg>[16] ? <output_reg>[16] : 1'bz;
|
|
assign <top_level_port>[17] = <output_enable_reg>[17] ? <output_reg>[17] : 1'bz;
|
|
assign <top_level_port>[18] = <output_enable_reg>[18] ? <output_reg>[18] : 1'bz;
|
|
assign <top_level_port>[19] = <output_enable_reg>[19] ? <output_reg>[19] : 1'bz;
|
|
assign <top_level_port>[20] = <output_enable_reg>[20] ? <output_reg>[20] : 1'bz;
|
|
assign <top_level_port>[21] = <output_enable_reg>[21] ? <output_reg>[21] : 1'bz;
|
|
assign <top_level_port>[22] = <output_enable_reg>[22] ? <output_reg>[22] : 1'bz;
|
|
assign <top_level_port>[23] = <output_enable_reg>[23] ? <output_reg>[23] : 1'bz;
|
|
assign <top_level_port>[24] = <output_enable_reg>[24] ? <output_reg>[24] : 1'bz;
|
|
assign <top_level_port>[25] = <output_enable_reg>[25] ? <output_reg>[25] : 1'bz;
|
|
assign <top_level_port>[26] = <output_enable_reg>[26] ? <output_reg>[26] : 1'bz;
|
|
assign <top_level_port>[27] = <output_enable_reg>[27] ? <output_reg>[27] : 1'bz;
|
|
assign <top_level_port>[28] = <output_enable_reg>[28] ? <output_reg>[28] : 1'bz;
|
|
assign <top_level_port>[29] = <output_enable_reg>[29] ? <output_reg>[29] : 1'bz;
|
|
assign <top_level_port>[30] = <output_enable_reg>[30] ? <output_reg>[30] : 1'bz;
|
|
assign <top_level_port>[31] = <output_enable_reg>[31] ? <output_reg>[31] : 1'bz;
|
|
|
|
always @(posedge <clock>)
|
|
if (<reset>) begin
|
|
<output_reg> <= 32'h00000000;
|
|
<output_enable_reg> <= 32'h00000000;
|
|
end
|
|
else begin
|
|
<output_reg> <= <output_signal>;
|
|
<output_enable_reg> <= {32{<output_enable_signal>}};
|
|
end
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Basic Gates" treetype="folder">
|
|
<SubFolder label="AND" treetype="folder">
|
|
<Template label="2-Input AND Gate" treetype="template">
|
|
<1-bit_wire> = <signal1> & <signal2>;
|
|
</Template>
|
|
<Template label="3-Input AND Gate" treetype="template">
|
|
<1-bit_wire> = <signal1> & <signal2> & <signal3>;
|
|
</Template>
|
|
<Template label="4-Input AND Gate" treetype="template">
|
|
<1-bit_wire> = <signal1> & <signal2> & <signal3> & <signal4>;
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="OR" treetype="folder">
|
|
<Template label="2-Input OR Gate" treetype="template">
|
|
<1-bit_wire> = <signal1> | <signal2>;
|
|
</Template>
|
|
<Template label="3-Input OR Gate" treetype="template">
|
|
<1-bit_wire> = <signal1> | <signal2> | <signal3>;
|
|
</Template>
|
|
<Template label="4-Input OR Gate" treetype="template">
|
|
<1-bit_wire> = <signal1> | <signal2> | <signal3> | <signal4>;
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="XOR" treetype="folder">
|
|
<Template label="2-Input XOR Gate" treetype="template">
|
|
<1-bit_wire> = <signal1> ^ <signal2>;
|
|
</Template>
|
|
<Template label="3-Input XOR Gate" treetype="template">
|
|
<1-bit_wire> = <signal1> ^ <signal2> ^ <signal3>;
|
|
</Template>
|
|
<Template label="4-Input XOR Gate" treetype="template">
|
|
<1-bit_wire> = <signal1> ^ <signal2> ^ <signal3> ^ <signal4>;
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="NOR" treetype="folder">
|
|
<Template label="2-Input NOR Gate" treetype="template">
|
|
<1-bit_wire> = ~(<signal1> | <signal2>);
|
|
</Template>
|
|
<Template label="3-Input NOR Gate" treetype="template">
|
|
<1-bit_wire> = ~(<signal1> | <signal2> | <signal3>);
|
|
</Template>
|
|
<Template label="4-Input NOR Gate" treetype="template">
|
|
<1-bit_wire> = ~(<signal1> | <signal2> | <signal3> | <signal4>);
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="NAND" treetype="folder">
|
|
<Template label="2-Input NAND Gate" treetype="template">
|
|
<1-bit_wire> = ~(<signal1> & <signal2>);
|
|
</Template>
|
|
<Template label="3-Input NAND Gate" treetype="template">
|
|
<1-bit_wire> = ~(<signal1> & <signal2> & <signal3>);
|
|
</Template>
|
|
<Template label="4-Input NAND Gate" treetype="template">
|
|
<1-bit_wire> = ~(<signal1> & <signal2> & <signal3> & <signal4>);
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="XNOR" treetype="folder">
|
|
<Template label="2-Input XNOR Gate" treetype="template">
|
|
<1-bit_wire> = <signal1> ~^ <signal2>;
|
|
</Template>
|
|
<Template label="3-Input XNOR Gate" treetype="template">
|
|
<1-bit_wire> = <signal1> ~^ <signal2> ~^ <signal3>;
|
|
</Template>
|
|
<Template label="4-Input XNOR Gate" treetype="template">
|
|
<1-bit_wire> = <signal1> ~^ <signal2> ~^ <signal3> ~^ <signal4>;
|
|
</Template>
|
|
</SubFolder>
|
|
<Template label="Inverter" treetype="template">
|
|
<1-bit_wire> = ~<signal>;
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Attributes" treetype="folder">
|
|
<Template label="Info (Synthesis Attributes)" treetype="template">
|
|
// information on Synthesis Attributes
|
|
// ===================================
|
|
//
|
|
// The forllowing templates for synthesis attributes use the Verilog-2001 attribute
|
|
// syntax for passing these constraints to the synthesis and back-end Xilinx tools.
|
|
// Since these are synthesis attributes, they are ignored for the purpose of
|
|
// simulation and thus generally should be used for passing attributes that do not
|
|
// effect design or component functionality such as placement or hierarchy
|
|
// constraints. These can also be used to guide synthesis implementation such as in
|
|
// the case of the state-machine extraction algorithms and parallel and full case
|
|
// specifications. To properly specify these constraints, they must be placed
|
|
// in-line with the declaring function or signal. Multiple attributes can be
|
|
// specified by comma separating them in the parenthesis-star brackets.
|
|
|
|
// Example of placing a LOC attribute on an input port declaration:
|
|
|
|
(* LOC="K1" *) input A;
|
|
|
|
// Example of placing an ASYNC_REG constraint on an inferred register:
|
|
|
|
(* ASYNC_REG="TRUE" *) reg empty_reg;
|
|
|
|
// Example of placing a KEEP_HIERARCHY constraint on an instantiated module:
|
|
|
|
// Instantiation of the DECODER module
|
|
(* KEEP_HIERARCHY="TRUE" *) DECODER DECODER_inst (
|
|
.DATA_IN(DATA_IN),
|
|
.CLK(CLK),
|
|
.RST(RST),
|
|
.DATA_OUT(DATA_OUT)
|
|
);
|
|
// End of DECODER_inst instantiation
|
|
|
|
// Example of PARALLEL_CASE / FULL_CASE:
|
|
|
|
always @(A, B, C, current_state) begin (* PARALLEL_CASE, FULL_CASE *)
|
|
case (current_state)
|
|
RESET: begin
|
|
...
|
|
</Template>
|
|
<SubFolder label="Misc" treetype="folder">
|
|
<Template label="Asynchronous Register Specification (ASYNC_REG)" treetype="template">
|
|
(* ASYNC_REG="TRUE" *)
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="I/O" treetype="folder">
|
|
<SubFolder label="IOB Delay" treetype="folder">
|
|
<SubFolder label="Spartan-3" treetype="folder">
|
|
<Template label="No Delay (NODELAY)" treetype="template">
|
|
(* NODELAY="TRUE" *)
|
|
</Template>
|
|
<Template label="None (IOBDELAY)" treetype="template">
|
|
(* IOBDELAY="NONE" *)
|
|
</Template>
|
|
<Template label="Both (IOBDELAY)" treetype="template">
|
|
(* IOBDELAY="BOTH" *)
|
|
</Template>
|
|
<Template label="IBUF (IOBDELAY)" treetype="template">
|
|
(* IOBDELAY="IBUF" *)
|
|
</Template>
|
|
<Template label="IFD (IOBDELAY)" treetype="template">
|
|
(* IOBDELAY="IFD" *)
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Spartan-3E" treetype="folder">
|
|
<Template label="Non-registered path (IBUF_DELAY_VALUE)" treetype="template">
|
|
(* IBUF_DELAY_VALUE="<number_from_0_to_12>" *)
|
|
</Template>
|
|
<Template label="Registered path (IFD_DELAY_VALUE)" treetype="template">
|
|
(* IFD_DELAY_VALUE="<number_from_0_to_6>" *)
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Spartan-3A" treetype="folder">
|
|
<Template label="Non-registered path (IBUF_DELAY_VALUE)" treetype="template">
|
|
(* IBUF_DELAY_VALUE="<number_from_0_to_16>" *)
|
|
</Template>
|
|
<Template label="Registered path (IFD_DELAY_VALUE)" treetype="template">
|
|
(* IFD_DELAY_VALUE="<number_from_0_to_8>" *)
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<Template label="I/O Standard (IOSTANDARD)" treetype="template">
|
|
(* IOSTANDARD="<standard>" *)
|
|
</Template>
|
|
<Template label="Don't Place Register into IOB (IOB)" treetype="template">
|
|
(* IOB="FALSE" *)
|
|
</Template>
|
|
<Template label="Place Register into IOB (IOB)" treetype="template">
|
|
(* IOB="TRUE" *)
|
|
</Template>
|
|
<SubFolder label="Buffer Type" treetype="folder">
|
|
<Template label="BUFGDLL (BUFFER_TYPE)" treetype="template">
|
|
(* BUFFER_TYPE="BUFGDLL" *)
|
|
</Template>
|
|
<Template label="IBUFG (BUFFER_TYPE)" treetype="template">
|
|
(* BUFFER_TYPE="IBUFG" *)
|
|
</Template>
|
|
<Template label="IBUF (BUFFER_TYPE)" treetype="template">
|
|
(* BUFFER_TYPE="IBUF" *)
|
|
</Template>
|
|
<Template label="BUFR (BUFFER_TYPE)" treetype="template">
|
|
(* BUFFER_TYPE="BUFR" *)
|
|
</Template>
|
|
<Template label="NONE (BUFFER_TYPE)" treetype="template">
|
|
(* BUFFER_TYPE="NONE" *)
|
|
</Template>
|
|
<Template label="AUTO (BUFFER_TYPE)" treetype="template">
|
|
(* BUFFER_TYPE="AUTO" *)
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Location / Packing" treetype="folder">
|
|
<Template label="Absolute Location Constraint (LOC)" treetype="template">
|
|
(* LOC="<value>" *)
|
|
</Template>
|
|
<Template label="Relative Location Constraint (RLOC)" treetype="template">
|
|
(* RLOC="<value>" *)
|
|
</Template>
|
|
<Template label="LUT Packing Constraint (LUTNM)" treetype="template">
|
|
// Specifies LUT packing of two LUT5s into the same LUT6 for Virtex-5
|
|
(* LUTNM="<value>" *)
|
|
</Template>
|
|
<Template label="Hierarchical LUT Packing Constraint (HLUTNM)" treetype="template">
|
|
// Specifies LUT packing of two LUT5s into the same LUT6 for Virtex-5 uniquified by hierarchy
|
|
(* HLUTNM="<value>" *)
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Synthesis" treetype="folder">
|
|
<Template label="Keep Hierarchy (KEEP_HIERARCHY)" treetype="template">
|
|
(* KEEP_HIERARCHY="TRUE" *)
|
|
</Template>
|
|
<SubFolder label="Case Statement" treetype="folder">
|
|
<Template label="Full Case Statement" treetype="template">
|
|
(* FULL_CASE *)
|
|
</Template>
|
|
<Template label="Parallel Case Statement" treetype="template">
|
|
(* PARALLEL_CASE *)
|
|
</Template>
|
|
<Template label="Full Case, Parallel Case Statement" treetype="template">
|
|
(* FULL_CASE, PARALLEL_CASE *)
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Finite State-Machine" treetype="folder">
|
|
<SubFolder label="FSM Encoding" treetype="folder">
|
|
<Template label="One-hot (FSM_ENCODING)" treetype="template">
|
|
(* FSM_ENCODING="ONE-HOT" *)
|
|
</Template>
|
|
<Template label="Compact (FSM_ENCODING)" treetype="template">
|
|
(* FSM_ENCODING="COMPACT" *)
|
|
</Template>
|
|
<Template label="Gray (FSM_ENCODING)" treetype="template">
|
|
(* FSM_ENCODING="GRAY" *)
|
|
</Template>
|
|
<Template label="Sequential (FSM_ENCODING)" treetype="template">
|
|
(* FSM_ENCODING="SEQUENTIAL" *)
|
|
</Template>
|
|
<Template label="Johnson (FSM_ENCODING)" treetype="template">
|
|
(* FSM_ENCODING="JOHNSON" *)
|
|
</Template>
|
|
<Template label="User (FSM_ENCODING)" treetype="template">
|
|
(* FSM_ENCODING="USER" *)
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="FSM Extraction" treetype="folder">
|
|
<Template label="Extract Finite State-Machine (FSM_EXTRACT)" treetype="template">
|
|
(* FSM_EXTRACT="YES" *)
|
|
</Template>
|
|
<Template label="Do Not Extract Finite State-Machine (FSM_EXTRACT)" treetype="template">
|
|
(* FSM_EXTRACT="NO" *)
|
|
</Template>
|
|
</SubFolder>
|
|
<Template label="State Recovery (SAFE_IMPLEMENTATION and SAFE_RECOVERY_STATE)" treetype="template">
|
|
// Specify FSM State Recovery
|
|
(* SAFE_IMPLEMENTATION="YES", SAFE_RECOVERY_STATE="<recovery_state_value>" *)
|
|
</Template>
|
|
<Template label="No State Recovery (SAFE_IMPLEMENTATION)" treetype="template">
|
|
// Specify FSM State Recovery
|
|
(* SAFE_IMPLEMENTATION="NO" *)
|
|
</Template>
|
|
</SubFolder>
|
|
<Template label="Keep/Preserve a Signal (KEEP)" treetype="template">
|
|
(* KEEP="TRUE" *)
|
|
</Template>
|
|
<SubFolder label="RAM Inference Styles" treetype="folder">
|
|
<Template label="Automatic RAM Implementation (RAM_STYLE=AUTO)" treetype="template">
|
|
(* RAM_STYLE="AUTO" *)
|
|
</Template>
|
|
<Template label="BlockRAM Implementation (RAM_STYLE=BLOCK)" treetype="template">
|
|
(* RAM_STYLE="BLOCK" *)
|
|
</Template>
|
|
<Template label="Distributed RAM Implementation (RAM_STYLE=DISTRIBUTED)" treetype="template">
|
|
(* RAM_STYLE="DISTRIBUTED" *)
|
|
</Template>
|
|
<Template label="Pipelined Distributed RAM Implementation (RAM_STYLE=PIPE_DISTRIBUTED)" treetype="template">
|
|
(* RAM_STYLE="PIPE_DISTRIBUTED" *)
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Equivalent Register Removal" treetype="folder">
|
|
<Template label="Yes (EQUIVALENT_REGISTER_REMOVAL)" treetype="template">
|
|
(* EQUIVALENT_REGISTER_REMOVAL="YES" *)
|
|
</Template>
|
|
<Template label="No (EQUIVALENT_REGISTER_REMOVAL)" treetype="template">
|
|
(* EQUIVALENT_REGISTER_REMOVAL="NO" *)
|
|
</Template>
|
|
</SubFolder>
|
|
<Template label="Shift Register Macro Detection (SHREG_EXTRACT) Disable" treetype="template">
|
|
(* SHREG_EXTRACT="NO" *)
|
|
</Template>
|
|
<SubFolder label="Buffer Type" treetype="folder">
|
|
<Template label="BUFGDLL (BUFFER_TYPE)" treetype="template">
|
|
(* BUFFER_TYPE="BUFGDLL" *)
|
|
</Template>
|
|
<Template label="IBUFG (BUFFER_TYPE)" treetype="template">
|
|
(* BUFFER_TYPE="IBUFG" *)
|
|
</Template>
|
|
<Template label="IBUF (BUFFER_TYPE)" treetype="template">
|
|
(* BUFFER_TYPE="IBUF" *)
|
|
</Template>
|
|
<Template label="BUFR (BUFFER_TYPE)" treetype="template">
|
|
(* BUFFER_TYPE="BUFR" *)
|
|
</Template>
|
|
<Template label="NONE (BUFFER_TYPE)" treetype="template">
|
|
(* BUFFER_TYPE="NONE" *)
|
|
</Template>
|
|
<Template label="AUTO (BUFFER_TYPE)" treetype="template">
|
|
(* BUFFER_TYPE="AUTO" *)
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Multiplier Inference" treetype="folder">
|
|
<Template label="Automatic Multiplier Implementation (MULT_STYLE=AUTO)" treetype="template">
|
|
(* MULT_STYLE="AUTO" *)
|
|
</Template>
|
|
<Template label="LUT Multiplier Implementation (MULT_STYLE=LUT)" treetype="template">
|
|
(* MULT_STYLE="LUT" *)
|
|
</Template>
|
|
<Template label="Pipelined LUT Multiplier Implementation (MULT_STYLE=PIPE_LUT)" treetype="template">
|
|
(* MULT_STYLE="PIPE_LUT" *)
|
|
</Template>
|
|
<Template label="Block Multiplier Implementation (MULT_STYLE=BLOCK)" treetype="template">
|
|
(* MULT_STYLE="BLOCK" *)
|
|
</Template>
|
|
<Template label="Pipelined Block Multiplier Implementation (MULT_STYLE=PIPE_BLOCK)" treetype="template">
|
|
(* MULT_STYLE="PIPE_BLOCK" *)
|
|
</Template>
|
|
<Template label="Constant Coefficient Multiplier Implementation (MULT_STYLE=KCM)" treetype="template">
|
|
(* MULT_STYLE="KCM" *)
|
|
</Template>
|
|
</SubFolder>
|
|
<Template label="Use DSP48 (USE_DSP48)" treetype="template">
|
|
(* USE_DSP48="YES" *)
|
|
</Template>
|
|
<Template label="Register Duplication (REGISTER_DUPLICATION)" treetype="template">
|
|
(* REGISTER_DUPLICATION="YES" *)
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Timing" treetype="folder">
|
|
<Template label="Period constraint MHz (PERIOD)" treetype="template">
|
|
// Add PERIOD constraint prior to the clock port definition
|
|
(* PERIOD="<value> MHz" *)
|
|
</Template>
|
|
<Template label="Period constraint ns (PERIOD)" treetype="template">
|
|
// Add PERIOD constraint prior to the clock port definition
|
|
(* PERIOD="<value> ns" *)
|
|
</Template>
|
|
<Template label="Timing ignore a net (TIG)" treetype="template">
|
|
// Add TIG constraint prior to the signal or port definition
|
|
(* TIG="TRUE" *)
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="System Tasks & Functions" treetype="folder">
|
|
<Template label="$display and $finish (info)" treetype="template">
|
|
// information for $display and $finish for synthesis
|
|
// ==================================================
|
|
//
|
|
// $display will display a string to the console and log file of the
|
|
// synthesis tool. This can be useful for adding specific notes to the
|
|
// log file for documentation or future reference as well as for debug of
|
|
// parameterizable code. Variables may be added to the string to indicate
|
|
// constant values such as those for a particular parameter to further
|
|
// enhance debug capabilities.
|
|
//
|
|
// When using $display, variables can be specified to the output in a
|
|
// variety of formats. Also, special escape characters can be used to
|
|
// specify special characters or formatting. These formats are
|
|
// listed below.
|
|
//
|
|
// Variables
|
|
// ---------
|
|
// %b .... Binary Value
|
|
// %h .... Hexadecimal Value
|
|
// %d .... Decimal Value
|
|
// %s .... String
|
|
// %c .... ASCII
|
|
// %o .... Octal Value
|
|
//
|
|
// Escape Characters
|
|
// -----------------
|
|
// \t ........ Tab
|
|
// \n ........ Newline
|
|
// \\ ........ Backslash
|
|
// %% ........ Percent
|
|
// \" ........ Quote
|
|
// \<octal> .. ASCII representation
|
|
//
|
|
// The $finish system function can be used to halt synthesis in case a
|
|
// situation is detected in which you would no longer want to process
|
|
// the design. for instance, if a parameter is set to what is determined
|
|
// to be an incorrect value. Another possible use is to place a $finish
|
|
// in simulation-only files to ensure they are not accidentally synthesized.
|
|
//
|
|
//
|
|
// Assume the forllowing piece of code is run in the XST synthesis tool:
|
|
|
|
generate
|
|
if (bus_width<65) begin: bus_width_under_65
|
|
initial
|
|
$display("\n\nInfo: Parameter bus_width = %d\n", bus_width);
|
|
end else begin: bus_width_over_64
|
|
initial begin
|
|
$display ("\n\nError: The parameter bus_with in module display_and_finish is set to %d.\n\tThis parameter cannot exceed 64.\n", bus_width);
|
|
$finish;
|
|
end
|
|
end
|
|
endgenerate
|
|
|
|
// If the parameter bus_width in that module was set to 64, the
|
|
// forllowing note would appear in the log file and console and
|
|
// the code would continue processing normally:
|
|
//
|
|
//
|
|
// Analyzing top module <display_and_finish>.
|
|
// bus_width = 32'sb00000000000000000000000001000000
|
|
// "display_and_finish.v" line 31: $display :
|
|
//
|
|
// Info: Parameter bus_width = 64
|
|
//
|
|
// Module <display_and_finish> is correct for synthesis.
|
|
//
|
|
//
|
|
// If that same code was run with the bus_width parameter set to
|
|
// 65, the forllowing would result and processing would stop:
|
|
//
|
|
//
|
|
// Analyzing top module <display_and_finish>.
|
|
// bus_width = 32'sb00000000000000000000000001000001
|
|
// "display_and_finish.v" line 34: $display :
|
|
//
|
|
// Error: The parameter bus_with in module display_and_finish is set to 65.
|
|
// This parameter cannot exceed 64.
|
|
//
|
|
//
|
|
// "display_and_finish.v" line 35: $finish forund. Closing session.
|
|
// -->
|
|
</Template>
|
|
<Template label="Display information to screen/log file ($display)" treetype="template">
|
|
// Note: $display must appear after an initial declaration
|
|
$display ("Text to display");
|
|
</Template>
|
|
<Template label="Halt synthesis of the design ($finish)" treetype="template">
|
|
// Note: $finish must appear after an initial declaration
|
|
$finish;
|
|
</Template>
|
|
<SubFolder label="Read Memory File" treetype="folder">
|
|
<Template label="Info ($readmemb/h)" treetype="template">
|
|
// information on the $readmemb and $readmemh system functions
|
|
// ===========================================================
|
|
//
|
|
// $readmemb is a system function which will read binary data from a
|
|
// specified file and place it in an array. The syntax is the forllowing:
|
|
// $readmemb ("<file_name>", <reg_name>, <start_address>, <end_address>);
|
|
// where the <file_name> is the name and location of the file containing
|
|
// the binary data, the <reg_name> is a 2-D register array in which the
|
|
// memory data is stored, and the last two comma separated numbers
|
|
// specify the beginning and ending address of the data. The data file
|
|
// may only contain binary data, white spaces and comments. This function
|
|
// must be executed within an initial block.
|
|
//
|
|
// $readmemh is the same as $readmemb with the exception that it
|
|
// inputs hex data as the read values.
|
|
//
|
|
// In the past, these functions could only be used for simulation
|
|
// purposes however synthesis tools now has the ability to initialize RAM
|
|
// and ROM arrays using this construct.
|
|
//
|
|
// Example of reading binary data from a file:
|
|
|
|
reg [31:0] rom_data[1023:0];
|
|
|
|
initial
|
|
$readmemb("../data/mem_file.dat", rom_data, 0, 7);
|
|
|
|
// The initialization file may only contain white spaces, address
|
|
// labels (denoted by @<address>), comments and the actual binary
|
|
// or hexadecimal data.
|
|
// The forllowing is a small example of a binary memory file data:
|
|
|
|
// This is a comment
|
|
|
|
1111000011110000 // This specifies these 16-bits to the first address
|
|
1010_0101_1010_0101 // This is for the second address with underscores
|
|
// to make this more readable
|
|
<more entries like above to fill up the array>
|
|
|
|
// Optionally, we can change addresses
|
|
@025 // Now at address 025
|
|
11111111_00000000
|
|
|
|
// Addresses can also be specified in-line
|
|
@035 00000000_11111111
|
|
|
|
// It is highly suggested to fill all memory contents with a known value
|
|
// when initializing memories.
|
|
</Template>
|
|
<Template label="Binary Data ($readmemb)" treetype="template">
|
|
reg [<memory_width>] <reg_name> [<memory_depth>];
|
|
|
|
initial
|
|
$readmemb ("<file_name>", <reg_name>, <start_address>, <end_address>);
|
|
</Template>
|
|
<Template label="Hex Data ($readmemh)" treetype="template">
|
|
reg [<memory_width>] <reg_name> [<memory_depth>];
|
|
|
|
initial
|
|
$readmemh ("<file_name>", <reg_name>, <start_address>, <end_address>);
|
|
</Template>
|
|
</SubFolder>
|
|
<Template label="Signed Conversion ($signed)" treetype="template">
|
|
$signed(<argument>);
|
|
</Template>
|
|
<Template label="Unsigned Conversion ($unsigned)" treetype="template">
|
|
$unsigned(<argument>);
|
|
</Template>
|
|
</SubFolder>
|
|
</Folder>
|
|
<Folder label="Common Constructs" treetype="folder">
|
|
<SubFolder label="Compiler directives" treetype="folder">
|
|
<SubFolder label="`timescale" treetype="folder">
|
|
<Template label="Info (`timescale)" treetype="template">
|
|
// The `timescale compile directive information
|
|
// ============================================
|
|
//
|
|
// `timescale is a compiler directive that indicates to the simulator the time units
|
|
// and precision to be used during simulation. The format is the forllowing:
|
|
//
|
|
// `timescale <units> / <precision>
|
|
//
|
|
// The units should be set to the base value in which time will be communicated to
|
|
// the simulator for that module.
|
|
// The precision is the minimum time units you wish the simulator to resolve. The
|
|
// smallest resolution value in all files and models compiled for simulation dictates
|
|
// the overall simulation resolution. In general for Xilinx FPGAs, a simulator
|
|
// resolution of 1ps is recommended since some components like the DCM require this
|
|
// resolution for proper operation and 1 ps is the resolution used for timing simulation.
|
|
//
|
|
// In general, this directive should appear at the top of the testbench, simulation models
|
|
// and all design files for a Verilog project.
|
|
//
|
|
// Example:
|
|
|
|
`timescale 1 ns / 1ps
|
|
|
|
#1; // Delays for 1 ns
|
|
#1.111; // Delays for 1111 ps
|
|
#1.111111111; // Delays for 1111 ps since the resolution is more course than
|
|
// what is specified, the delay amount is truncated
|
|
</Template>
|
|
<Template label="1ns / 1ps" treetype="template">
|
|
`timescale 1 ns / 1 ps
|
|
</Template>
|
|
<Template label="1ps / 1ps" treetype="template">
|
|
`timescale 1 ps / 1 ps
|
|
</Template>
|
|
<Template label="1ns / 100ps" treetype="template">
|
|
`timescale 1 ns / 100 ps
|
|
</Template>
|
|
<Template label="100ps / 1ps" treetype="template">
|
|
`timescale 100 ps / 1 ps
|
|
</Template>
|
|
<Template label="1ns / 1ns" treetype="template">
|
|
`timescale 1 ns / 1 ns
|
|
</Template>
|
|
<Template label="1ns / 10ps" treetype="template">
|
|
`timescale 1 ns / 10 ps
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="`include" treetype="folder">
|
|
<Template label="Info (`include)" treetype="template">
|
|
// The `include complier directive
|
|
// ===============================
|
|
//
|
|
// `include can be used to insert the contents of a separate file into a module.
|
|
// This is often used to communicate common functions, compiler directives, parameters
|
|
// and `defines to multiple files in a project. The file and path name must be
|
|
// specified in quotes and can consist of just the file name (looks in the current
|
|
// working directory for the file), a relative path to the file or an absolute path
|
|
// to the file. This directive can be specified both before the module declaration
|
|
// as well as within the module directive.
|
|
//
|
|
// Example:
|
|
|
|
// Include the contents of the parameters.vh file located in the current working directory.
|
|
// Many simulator and synthesis tools also offer a switch/option to allow specification
|
|
// of a search directory other than the working directory for files specified in this manner.
|
|
`include "parameters.vh"
|
|
|
|
// Include the contents of the ram_data.vh file in the relative directory ../data
|
|
`include "../data/ram_data.vh"
|
|
|
|
// Include the contents of master.vh in the absolute directory /export/vol1/sim_data
|
|
`include "/export/vol1/sim_data/master.vh"
|
|
|
|
</Template>
|
|
<Template label="`include" treetype="template">
|
|
`include "<file_name>"
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Define" treetype="folder">
|
|
<Template label="Info (`define)" treetype="template">
|
|
// The `define, `ifdef, `elsif, `else, `ifndef and the `endif compiler directives
|
|
// ==============================================================================
|
|
//
|
|
// `define is a compiler directive that defines a value to a variable. That variable
|
|
// can then be called upon in the code by referencing the `name of the specified variable.
|
|
//
|
|
// `ifdef is a compiler directive that checks for the existence of a specified `define
|
|
// and then conditionally includes a section of code during compilation if it exists.
|
|
//
|
|
// `ifndef is the opposite of `ifdef in that if a `define was not declared, it includes
|
|
// a section of code.
|
|
//
|
|
// `elsif can be used in conjunction with a `ifdef to find the existence of another
|
|
// `define and conditionally compile a different section of code if the previous
|
|
// conditions were not met and this condition is met.
|
|
//
|
|
// `else also can be used in conjunction with a `ifdef where it will compile a section
|
|
// of code if all previous `ifdef and `elsif conditions were not met.
|
|
//
|
|
// `endif is used at the end of a `ifdef or `ifndef statement to signify the end of
|
|
// the included code.
|
|
//
|
|
// Example:
|
|
|
|
`define DATA_WIDTH 16
|
|
`define DATA_WIDTH16
|
|
|
|
reg [`DATA_WIDTH-1:0] data;
|
|
|
|
`ifdef DATA_WIDTH8
|
|
// If DATA_WIDTH8 was set, this would get compiled
|
|
`elsif DATA_WIDTH16
|
|
// Since DATA_WIDTH16 is set, this does get compiled
|
|
`else
|
|
// If DATA_WIDTH8 and DATA_WIDTH16 was not defined, this would be compiled
|
|
`endif
|
|
</Template>
|
|
<Template label="`define" treetype="template">
|
|
`define <name> <string>
|
|
</Template>
|
|
<Template label="`ifdef & `elsif & `else" treetype="template">
|
|
`ifdef <define_name>
|
|
<statements>;
|
|
`elsif <define_name>
|
|
<statements>;
|
|
`else
|
|
<statements>;
|
|
`endif
|
|
</Template>
|
|
<Template label="`ifndef" treetype="template">
|
|
`ifndef <define_name>
|
|
<statements>;
|
|
`endif
|
|
</Template>
|
|
</SubFolder>
|
|
</SubFolder>
|
|
<SubFolder label="Comments" treetype="folder">
|
|
<Template label="Single Line (//)" treetype="template">
|
|
// Comment here
|
|
</Template>
|
|
<Template label="Multiple Lines (/*---*/)" treetype="template">
|
|
/* Comment here
|
|
Comment here
|
|
Comment here */
|
|
</Template>
|
|
<Template label="Sample File Header" treetype="template">
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
// Company: <Company Name>
|
|
// Engineer: <Engineer Name>
|
|
//
|
|
// Create Date: <date>
|
|
// Design Name: <name_of_top-level_design>
|
|
// Module Name: <name_of_this_module>
|
|
// Target Device: <target device>
|
|
// Tool versions: <tool_versions>
|
|
// Description:
|
|
// <Description here>
|
|
// Dependencies:
|
|
// <Dependencies here>
|
|
// Revision:
|
|
// <Code_revision_information>
|
|
// Additional Comments:
|
|
// <Additional_comments>
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="User Defined Functions & Tasks" treetype="folder">
|
|
<Template label="Info (Functions and Tasks)" treetype="template">
|
|
// User defined function and task information
|
|
// ==========================================
|
|
//
|
|
// A user defined function is a set of Verilog statements that
|
|
// can be called from elsewhere within the body of the code by
|
|
// an assignment. A function can have multiple inputs however
|
|
// can return only a single output. No timing information can
|
|
// be specified within a function.
|
|
//
|
|
// A user defined task is a subroutine that can be executed by
|
|
// a single call from elsewhere within the body of the code.
|
|
// A task can have any number of inputs, outputs and inouts as
|
|
// well as contain timing information.
|
|
//
|
|
// Example of a function declaration:
|
|
|
|
function [9:0] gray_encode;
|
|
input [9:0] binary_input;
|
|
begin
|
|
gray_encode[9] = binary_input[9];
|
|
for (k=8; k>=0; k=k-1) begin
|
|
gray_encode[k] = binary_input[k+1] ^ binary_input[k];
|
|
end
|
|
end
|
|
endfunction
|
|
|
|
// Example of calling a function:
|
|
|
|
// write_count is the binary input being passed to the function gray_encode.
|
|
// The output of the function gray_encode is then passed to the signal FIFO_ADDR
|
|
FIFO_ADDR = gray_encode(write_count);
|
|
|
|
// Example of a task declaration:
|
|
|
|
task error_action;
|
|
input read_write;
|
|
input correct_value;
|
|
input actual_value;
|
|
input [8*11:0] output_string;
|
|
begin
|
|
if (ERROR_CHECK) begin
|
|
if (read_write)
|
|
$display("Error: %s value incorrect during write %d at time %t\nExpecting %b, got %b",
|
|
output_string, write_attempt, $realtime, correct_value, actual_value);
|
|
else
|
|
$display("Error: %s value incorrect during read %d at time %t\nExpecting %b, got %b",
|
|
output_string, read_attempt, $realtime, correct_value, actual_value);
|
|
if (ON_ERROR=="FINISH")
|
|
$finish;
|
|
else if (ON_ERROR=="STOP")
|
|
$stop;
|
|
end
|
|
end
|
|
endtask
|
|
|
|
// Example of calling a task:
|
|
|
|
// The task error_action is called by name and passed the four input values
|
|
// in the order they are declared in the task
|
|
error_action(1'b1, wr_ready_value, WR_READY, "WR_READY");
|
|
</Template>
|
|
<Template label="Function Declaration" treetype="template">
|
|
function [<lower>:<upper>] <output_name> ;
|
|
input <name>;
|
|
begin
|
|
<statements>
|
|
end
|
|
endfunction
|
|
</Template>
|
|
<Template label="Calling a Function" treetype="template">
|
|
<signal> = <function_name>(<comma_separated _inputs>);
|
|
</Template>
|
|
<Template label="Task Declaration" treetype="template">
|
|
// A task is a subroutine with any number of input, output or inout
|
|
// arguments and may contain timing controls
|
|
|
|
task <task_name>;
|
|
input <input_name>;
|
|
<more_inputs>
|
|
|
|
output <output_name>;
|
|
<more_outputs>
|
|
|
|
begin
|
|
<statements>;
|
|
end
|
|
endtask
|
|
</Template>
|
|
<Template label="Calling a Task" treetype="template">
|
|
<task_name>(<comma_separated _inputs>, <comma_separated _outputs>);
|
|
</Template>
|
|
</SubFolder>
|
|
<SubFolder label="Operators" treetype="folder">
|
|
<Template label="Arithmetic" treetype="template">
|
|
// The forllowing are the arithmetic operators as defined by the Verilog language.
|
|
//
|
|
// + .... Addition
|
|
// - .... Subtraction
|
|
// * .... Multiplication
|
|
// / .... Divide
|
|
// % .... Modulus
|
|
// ** ... Power Operator (i.e. 2**8 returns 256)
|
|
</Template>
|
|
<Template label="Bitwise" treetype="template">
|
|
// The forllowing operators can be used on two single bits to produce a single bit
|
|
// output or two equivalent sized bused signals where the operations are performed
|
|
// on each bit of the bus. In the case of the Invert, only one signal or bus is
|
|
// provided and the operation occurs on each bit of the signal.
|
|
//
|
|
// ~ .... Invert a single-bit signal or each bit in a bus
|
|
// & .... AND two single bits or each bit between two buses
|
|
// | .... OR two single bits or each bit between two buses
|
|
// ^ .... XOR two single bits or each bit between two buses
|
|
// ~^ ... XNOR two single bits or each bit between two buses
|
|
</Template>
|
|
<Template label="Unary Reduction" treetype="template">
|
|
// The forllowing operators can be used on a bussed signal where all bits in the bus
|
|
// are used to perform the operation and a single bit output is resolved.
|
|
//
|
|
// & .... AND all bits together to make single bit output
|
|
// ~& ... NAND all bits together to make single bit output
|
|
// | .... OR all bits together to make single bit output
|
|
// ~| ... NOR all bits together to make single bit output
|
|
// ^ .... XOR all bits together to make single bit output
|
|
// ~^ ... XNOR all bits together to make single bit output
|
|
</Template>
|
|
<Template label="Logical" treetype="template">
|
|
// The forllowing logical operators are used in conditional TRUE/FALSE statements
|
|
// such as an if statement in order to specify the condition for the operation.
|
|
//
|
|
// ! .... Not True
|
|
// && ... Both Inputs True
|
|
// || ... Either Input True
|
|
// == ... Inputs Equal
|
|
// === .. Inputs Equal including X and Z (simulation only)
|
|
// != ... Inputs Not Equal
|
|
// !== .. Inputs Not Equal including X and Z (simulation only)
|
|
// < .... Less-than
|
|
// <= ... Less-than or Equal
|
|
// > .... Greater-than
|
|
// >= ... Greater-than or Equal
|
|
</Template>
|
|
<Template label="Replicate/Concatenate" treetype="template">
|
|
// The forllowing operators either concatenates several bits into a bus or replicate
|
|
// a bit or combination of bits multiple times.
|
|
//
|
|
// {a, b, c} .... Concatenate a, b and c into a bus
|
|
// {3{a}} ....... Replicate a, 3 times
|
|
// {{5{a}}, b} .. Replicate a, 5 times and concatenate to b
|
|
//
|
|
</Template>
|
|
<Template label="Shift" treetype="template">
|
|
// The forllowing operators will shift a bus right or left a number of bits.
|
|
//
|
|
// << .... Left shift (i.e. a << 2 shifts a two bits to the left)
|
|
// <<< ... Left shift and maintain sign bit
|
|
// >> .... Right shift (i.e. b << 1 shifts b one bits to the right)
|
|
// >>> ... Right shift and maintain sign bit
|
|
</Template>
|
|
</SubFolder>
|
|
</Folder>
|
|
<Folder label="User Templates" language="Verilog" treetype="folder" utallowed="true">
|
|
</Folder>
|
|
</RootFolder>
|