17 lines
228 B
Verilog
17 lines
228 B
Verilog
module testModule();
|
|
reg clk, rst;
|
|
reg port_1;
|
|
|
|
|
|
always @(posedge clk or negedge rst) begin
|
|
|
|
end
|
|
|
|
|
|
|
|
always @(posedge clk or negedge rst) begin
|
|
|
|
end
|
|
|
|
endmodule //testModule
|