83 lines
1.6 KiB
Systemverilog
83 lines
1.6 KiB
Systemverilog
// Test Scenario to validate correct translation
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// Refer: https://github.com/Nic30/hdlConvertor/issues/173
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`define ADD 64
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module dummy #(
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parameter reg ADDR_WIDTH = 4,
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parameter interger ADDER_OOO = 25,
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parameter [63:0] ADDER_OOO_1 = (1 << ADDER_OOO) + 1,
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parameter logic [63:0] ADD_OTHER = `ADD'hff1
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) (c, a, b, d, f);
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output reg c;
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output logic [61:0] f;
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input [ADDR_WIDTH_ANSI - 1:0] d;
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input a, b;
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and a1(c, a, b);
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endmodule
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module d2(y, a);
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output [3:0] y;
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input reg [2:0] a;
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not n1 (y, a);
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endmodule
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module example (a, b, c, d);
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input a, b, c;
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output d;
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wire tmp;
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wire tmp2;
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wire tmp3;
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and a1 (tmp, a, b);
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dummy du(
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.c(tmp2), .a(b), .b(c));
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dummy #(
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.ADDR_WIDTH(8)
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) duu(tmp3, b, c);
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or o1 (d, tmp, tmp2);
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endmodule
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// test dummy comment
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module dummy_ansi #(
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parameter ADDR_WIDTH = 4,
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parameter interger ADDER_OOO = 25,
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parameter [63:0] ADDER_OOO_1 = (1 << ADDER_OOO) + 1,
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parameter logic [63:0] ADD_OTHER = `ADD'hff1
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) (
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output [ADDR_WIDTH_ANSI - 1:0] c,
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input [ADDR_WIDTH_ANSI-1: 0] a,
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input [ADDR_WIDTH_ANSI-1:0] b
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);
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and a1(c, a, b);
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assign c = a & b;
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endmodule
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module d2_ansi(
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output [3:0] y,
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input reg [2:0] a
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);
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not n1 (y, a);
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endmodule
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module example_ansi (
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input a, b, c,
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output d
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);
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wire tmp;
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wire tmp2;
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wire tmp3;
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and a1 (tmp, a, b);
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dummy_ansi du_ansi(
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.c(tmp2), .b(b), .a(c));
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dummy_ansi #(
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.ADDR_WIDTH_ANSI(8)
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) duu_ansi(
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tmp3,
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b,
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c
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);
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or o1 (d, tmp, tmp2);
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endmodule
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