96 lines
5.6 KiB
Plaintext
Executable File
96 lines
5.6 KiB
Plaintext
Executable File
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Warning-[DEBUG_DEP] Option will be deprecated
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The option '-debug_all' will be deprecated in a future release. Please use
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'-debug_acc+all+dmptf -debug_region+cell+encrypt' instead.
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Error-[DBG_UCLI_DEP] Option -ucli/-gui is deprecated
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The option '-ucli/-gui' can only be used in conjunction with '-R' and
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'-debug*'.
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Warning-[DBGACC_DBG] Multiple debug options being used
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The debug switches '-debug_access' and '-debug_all' are being used together.
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For better performance, consider using only '-debug_access'.
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Command: vcs -f /home/icer/Project/ASICs/virtual_project/sync_fifo_flow/user/sim/file_list/asic_fun_sim.f \
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-o simv -l ./vcs.log +v2k +libext+.v+.V+.sv+.svh -sverilog -debug_access -timescale=1ns/1ps \
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-P /home/kumon/Synopsys/verdi/T-2022.06/share/PLI/VCS/LINUX64/novas.tab /home/kumon/Synopsys/verdi/T-2022.06/share/PLI/VCS/LINUX64/pli.a \
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-top Tb_Sync_FIFO -full64 -debug_all +vcs+initreg+random +notimingcheck -Mupdate \
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-ucli -error=IWNF +lint=TFIPC-L
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Chronologic VCS (TM)
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Version T-2022.06_Full64 -- Tue Nov 26 20:49:42 2024
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Copyright (c) 1991 - 2022 Synopsys, Inc.
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This software and the associated documentation are proprietary to Synopsys,
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Inc. This software may only be used in accordance with the terms and conditions
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of a written license agreement with Synopsys, Inc. All other use, reproduction,
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or distribution of this software is strictly prohibited. Licensed Products
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communicate with Synopsys servers for the purpose of providing software
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updates, detecting software piracy and verifying that customers are using
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Licensed Products in conformity with the applicable License Key for such
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Licensed Products. Synopsys will use information gathered in connection with
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this process to deliver software updates and pursue software pirates and
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infringers.
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Inclusivity & Diversity - Visit SolvNetPlus to read the "Synopsys Statement on
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Inclusivity and Diversity" (Refer to article 000036315 at
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https://solvnetplus.synopsys.com)
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Warning-[DEBUG_DEP] Option will be deprecated
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The option '-debug_all' will be deprecated in a future release. Please use
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'-debug_acc+all -debug_region+cell+encrypt' instead.
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Parsing design file '/home/icer/Project/ASICs/virtual_project/sync_fifo_flow/user/sim/Tb_Sync_FIFO.sv'
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Parsing design file '/home/icer/Project/ASICs/virtual_project/sync_fifo_flow/user/src/Sync_FIFO.sv'
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Parsing design file '/home/icer/Project/ASICs/virtual_project/sync_fifo_flow/user/src/tem5n28hpcplvta64x20m4swbso_110a_tt0p9v25c.v'
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Top Level Modules:
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Tb_Sync_FIFO
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TimeScale is 1 ns / 1 ps
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Warning-[PCWM-W] Port connection width mismatch
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/home/icer/Project/ASICs/virtual_project/sync_fifo_flow/user/sim/Tb_Sync_FIFO.sv, 132
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"Sync_FIFO #(P_DATA_WIDTH, P_FIFO_DEPTH, ) u_Sync_FIFO( .i_clk (clk), .i_rst_n (rst_n), .i_wren (wren), .i_rden (rden), .i_wdata (wdata), .o_rdata (rdata), .o_rddata_valid (rddata_valid), .o_fifo_full (fifo_full), .o_fifo_empty (fifo_empty), .i_cfg_almost_full (3), .i_cfg_almost_empty (3), .o_fifo_almost_full (fifo_almost_full), .o_fifo_almost_empty (fifo_almost_empty), .o_fifo_space (fifo_space));"
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The following 32-bit expression is connected to 6-bit port
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"i_cfg_almost_full" of module "Sync_FIFO", instance "u_Sync_FIFO".
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Expression: 3
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Instantiated module defined at:
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"/home/icer/Project/ASICs/virtual_project/sync_fifo_flow/user/src/Sync_FIFO.sv",
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3
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Use +lint=PCWM for more details.
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Warning-[PCWM-W] Port connection width mismatch
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/home/icer/Project/ASICs/virtual_project/sync_fifo_flow/user/sim/Tb_Sync_FIFO.sv, 132
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"Sync_FIFO #(P_DATA_WIDTH, P_FIFO_DEPTH, ) u_Sync_FIFO( .i_clk (clk), .i_rst_n (rst_n), .i_wren (wren), .i_rden (rden), .i_wdata (wdata), .o_rdata (rdata), .o_rddata_valid (rddata_valid), .o_fifo_full (fifo_full), .o_fifo_empty (fifo_empty), .i_cfg_almost_full (3), .i_cfg_almost_empty (3), .o_fifo_almost_full (fifo_almost_full), .o_fifo_almost_empty (fifo_almost_empty), .o_fifo_space (fifo_space));"
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The following 32-bit expression is connected to 6-bit port
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"i_cfg_almost_empty" of module "Sync_FIFO", instance "u_Sync_FIFO".
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Expression: 3
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Instantiated module defined at:
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"/home/icer/Project/ASICs/virtual_project/sync_fifo_flow/user/src/Sync_FIFO.sv",
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3
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Use +lint=PCWM for more details.
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Starting vcs inline pass...
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1 module and 0 UDP read.
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recompiling module Tb_Sync_FIFO
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make[1]: Entering directory '/home/icer/Project/ASICs/virtual_project/sync_fifo_flow/prj/SIMv0.1/csrc' \
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rm -f _cuarc*.so _csrc*.so pre_vcsobj_*.so share_vcsobj_*.so
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if [ -x ../simv ]; then chmod a-x ../simv; fi
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g++ -o ../simv -rdynamic -Wl,-rpath='$ORIGIN'/simv.daidir -Wl,-rpath=./simv.daidir \
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-Wl,-rpath=/home/kumon/Synopsys/vcs/T-2022.06/linux64/lib -L/home/kumon/Synopsys/vcs/T-2022.06/linux64/lib \
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-Wl,-rpath-link=./ objs/amcQw_d.o _7567_archive_1.so SIM_l.o rmapats_mop.o \
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rmapats.o rmar.o rmar_nd.o rmar_llvm_0_1.o rmar_llvm_0_0.o -lnuma -lvirsim \
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-lerrorinf -lsnpsmalloc -lvfs /home/kumon/Synopsys/verdi/T-2022.06/share/PLI/VCS/LINUX64/pli.a \
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-lvcsnew -lsimprofile -luclinative /home/kumon/Synopsys/vcs/T-2022.06/linux64/lib/vcs_tls.o \
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-Wl,-whole-archive -lvcsucli -Wl,-no-whole-archive _vcs_pli_stub_.o /home/kumon/Synopsys/vcs/T-2022.06/linux64/lib/vcs_save_restore_new.o \
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/home/kumon/Synopsys/verdi/T-2022.06/share/PLI/VCS/LINUX64/pli.a -ldl -lm -lc -lpthread \
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-ldl
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../simv up to date
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make[1]: Leaving directory '/home/icer/Project/ASICs/virtual_project/sync_fifo_flow/prj/SIMv0.1/csrc' \
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CPU time: .366 seconds to compile + .172 seconds to elab + .123 seconds to link
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