diff --git a/public/iconfont.css b/public/iconfont.css
index dbf27c4..ec9df89 100644
--- a/public/iconfont.css
+++ b/public/iconfont.css
@@ -1,8 +1,8 @@
 @font-face {
   font-family: "iconfont"; /* Project id 4440655 */
-  src: url('iconfont.woff2?t=1709106897565') format('woff2'),
-       url('iconfont.woff?t=1709106897565') format('woff'),
-       url('iconfont.ttf?t=1709106897565') format('truetype');
+  src: url('iconfont.woff2?t=1709378049768') format('woff2'),
+       url('iconfont.woff?t=1709378049768') format('woff'),
+       url('iconfont.ttf?t=1709378049768') format('truetype');
 }
 
 .iconfont {
@@ -13,6 +13,42 @@
   -moz-osx-font-smoothing: grayscale;
 }
 
+.icon-parameter:before {
+  content: "\e6be";
+}
+
+.icon-task-:before {
+  content: "\e602";
+}
+
+.icon-fork:before {
+  content: "\e735";
+}
+
+.icon-prevent:before {
+  content: "\e69d";
+}
+
+.icon-Function:before {
+  content: "\e90e";
+}
+
+.icon-R:before {
+  content: "\e6ec";
+}
+
+.icon-integer:before {
+  content: "\e603";
+}
+
+.icon-String:before {
+  content: "\e614";
+}
+
+.icon-brackets:before {
+  content: "\e613";
+}
+
 .icon-register:before {
   content: "\e611";
 }
diff --git a/public/iconfont.woff2 b/public/iconfont.woff2
index fc91393..98fed9a 100644
Binary files a/public/iconfont.woff2 and b/public/iconfont.woff2 differ
diff --git a/public/test.vcd b/public/test.vcd
new file mode 100644
index 0000000..502135d
--- /dev/null
+++ b/public/test.vcd
@@ -0,0 +1,9529 @@
+$date
+	Thu Jul 22 22:29:56 2021
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1ps
+$end
+$scope module friscv_rv32i_testbench $end
+$var wire 1 ! inst_rready $end
+$var wire 2 " inst_rresp [1:0] $end
+$var wire 1 # uart_cts $end
+$var wire 1 $ uart_rx $end
+$var wire 1 % uart_tx $end
+$var wire 1 & uart_rts $end
+$var wire 1 ' mem_wr $end
+$var wire 32 ( mem_wdata [31:0] $end
+$var wire 4 ) mem_strb [3:0] $end
+$var wire 1 * mem_ready $end
+$var wire 32 + mem_rdata [31:0] $end
+$var wire 1 , mem_en $end
+$var wire 16 - mem_addr [15:0] $end
+$var wire 1 . inst_rvalid $end
+$var wire 8 / inst_rid [7:0] $end
+$var wire 128 0 inst_rdata [127:0] $end
+$var wire 1 1 inst_bvalid $end
+$var wire 2 2 inst_bresp [1:0] $end
+$var wire 1 3 inst_awready $end
+$var wire 1 4 inst_arvalid $end
+$var wire 1 5 inst_arready $end
+$var wire 3 6 inst_arprot [2:0] $end
+$var wire 8 7 inst_arid [7:0] $end
+$var wire 16 8 inst_araddr [15:0] $end
+$var wire 32 9 gpio_out [31:0] $end
+$var wire 1 : ebreak $end
+$var reg 1 ; aclk $end
+$var reg 1 < aresetn $end
+$var reg 1 = enable $end
+$var reg 32 > gpio_in [31:0] $end
+$var reg 16 ? inst_awaddr [15:0] $end
+$var reg 8 @ inst_awid [7:0] $end
+$var reg 3 A inst_awprot [2:0] $end
+$var reg 1 B inst_awvalid $end
+$var reg 1 C inst_bready $end
+$var reg 128 D inst_wdata [127:0] $end
+$var reg 8 E inst_wid [7:0] $end
+$var reg 1 F inst_wready $end
+$var reg 1 G inst_wvalid $end
+$var reg 1 H srst $end
+$var integer 32 I inst_counter [31:0] $end
+$var integer 32 J svut_critical [31:0] $end
+$var integer 32 K svut_error [31:0] $end
+$var integer 32 L svut_error_total [31:0] $end
+$var integer 32 M svut_nb_test [31:0] $end
+$var integer 32 N svut_nb_test_success [31:0] $end
+$var integer 32 O svut_status [31:0] $end
+$var integer 32 P svut_test_number [31:0] $end
+$var integer 32 Q svut_warning [31:0] $end
+$var integer 32 R timer [31:0] $end
+$scope module data_ram $end
+$var wire 1 ; aclk $end
+$var wire 1 < aresetn $end
+$var wire 16 S p2_addr [15:0] $end
+$var wire 1 T p2_en $end
+$var wire 4 U p2_strb [3:0] $end
+$var wire 32 V p2_wdata [31:0] $end
+$var wire 1 W p2_wr $end
+$var wire 1 H srst $end
+$var wire 32 X p2_rdata [31:0] $end
+$var wire 1 ' p1_wr $end
+$var wire 32 Y p1_wdata [31:0] $end
+$var wire 4 Z p1_strb [3:0] $end
+$var wire 32 [ p1_rdata [31:0] $end
+$var wire 1 , p1_en $end
+$var wire 16 \ p1_addr [15:0] $end
+$var reg 1 * p1_ready $end
+$var reg 1 ] p2_ready $end
+$scope begin LATENCY1 $end
+$upscope $end
+$scope module ram $end
+$var wire 1 ; aclk $end
+$var wire 1 < aresetn $end
+$var wire 16 ^ p2_addr [15:0] $end
+$var wire 1 T p2_en $end
+$var wire 4 _ p2_strb [3:0] $end
+$var wire 32 ` p2_wdata [31:0] $end
+$var wire 1 W p2_wr $end
+$var wire 1 H srst $end
+$var wire 1 ' p1_wr $end
+$var wire 32 a p1_wdata [31:0] $end
+$var wire 4 b p1_strb [3:0] $end
+$var wire 1 , p1_en $end
+$var wire 16 c p1_addr [15:0] $end
+$var reg 32 d p1_rdata [31:0] $end
+$var reg 32 e p2_rdata [31:0] $end
+$scope begin $ivl_for_loop0 $end
+$var integer 32 f i [31:0] $end
+$upscope $end
+$scope begin $ivl_for_loop1 $end
+$var integer 32 g i [31:0] $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope module dut $end
+$var wire 1 ; aclk $end
+$var wire 1 < aresetn $end
+$var wire 1 = enable $end
+$var wire 32 h gpio_in [31:0] $end
+$var wire 3 i inst_arprot_s [2:0] $end
+$var wire 1 ! inst_rready $end
+$var wire 2 j inst_rresp [1:0] $end
+$var wire 2 k inst_rresp_s [1:0] $end
+$var wire 32 l mem_rdata [31:0] $end
+$var wire 1 * mem_ready $end
+$var wire 4 m proc_fenceinfo [3:0] $end
+$var wire 1 H srst $end
+$var wire 1 # uart_cts $end
+$var wire 1 $ uart_rx $end
+$var wire 1 % uart_tx $end
+$var wire 1 & uart_rts $end
+$var wire 1 n proc_ready $end
+$var wire 87 o proc_instbus [86:0] $end
+$var wire 1 p proc_en $end
+$var wire 1 q proc_empty $end
+$var wire 1 r mst_wr $end
+$var wire 32 s mst_wdata [31:0] $end
+$var wire 4 t mst_strb [3:0] $end
+$var wire 1 u mst_ready $end
+$var wire 32 v mst_rdata [31:0] $end
+$var wire 1 w mst_en $end
+$var wire 16 x mst_addr [15:0] $end
+$var wire 32 y memfy_rs2_val [31:0] $end
+$var wire 5 z memfy_rs2_addr [4:0] $end
+$var wire 32 { memfy_rs1_val [31:0] $end
+$var wire 5 | memfy_rs1_addr [4:0] $end
+$var wire 1 } memfy_rd_wr $end
+$var wire 32 ~ memfy_rd_val [31:0] $end
+$var wire 4 !" memfy_rd_strb [3:0] $end
+$var wire 5 "" memfy_rd_addr [4:0] $end
+$var wire 1 ' mem_wr $end
+$var wire 32 #" mem_wdata [31:0] $end
+$var wire 4 $" mem_strb [3:0] $end
+$var wire 1 , mem_en $end
+$var wire 16 %" mem_addr [15:0] $end
+$var wire 1 &" inst_rvalid_s $end
+$var wire 1 . inst_rvalid $end
+$var wire 1 '" inst_rready_s $end
+$var wire 8 (" inst_rid_s [7:0] $end
+$var wire 8 )" inst_rid [7:0] $end
+$var wire 32 *" inst_rdata_s [31:0] $end
+$var wire 128 +" inst_rdata [127:0] $end
+$var wire 1 ," inst_arvalid_s $end
+$var wire 1 4 inst_arvalid $end
+$var wire 1 -" inst_arready_s $end
+$var wire 1 5 inst_arready $end
+$var wire 3 ." inst_arprot [2:0] $end
+$var wire 8 /" inst_arid_s [7:0] $end
+$var wire 8 0" inst_arid [7:0] $end
+$var wire 16 1" inst_araddr_s [15:0] $end
+$var wire 16 2" inst_araddr [15:0] $end
+$var wire 1 3" gpio_wr $end
+$var wire 32 4" gpio_wdata [31:0] $end
+$var wire 4 5" gpio_strb [3:0] $end
+$var wire 1 6" gpio_ready $end
+$var wire 32 7" gpio_rdata [31:0] $end
+$var wire 32 8" gpio_out [31:0] $end
+$var wire 1 9" gpio_en $end
+$var wire 16 :" gpio_addr [15:0] $end
+$var wire 1 ;" flush_req $end
+$var wire 1 <" flush_ack $end
+$var wire 1 : ebreak $end
+$var wire 32 =" ctrl_rs2_val [31:0] $end
+$var wire 5 >" ctrl_rs2_addr [4:0] $end
+$var wire 32 ?" ctrl_rs1_val [31:0] $end
+$var wire 5 @" ctrl_rs1_addr [4:0] $end
+$var wire 1 A" ctrl_rd_wr $end
+$var wire 32 B" ctrl_rd_val [31:0] $end
+$var wire 5 C" ctrl_rd_addr [4:0] $end
+$var wire 32 D" csr_rs1_val [31:0] $end
+$var wire 5 E" csr_rs1_addr [4:0] $end
+$var wire 1 F" csr_ready $end
+$var wire 1 G" csr_rd_wr $end
+$var wire 32 H" csr_rd_val [31:0] $end
+$var wire 5 I" csr_rd_addr [4:0] $end
+$var wire 87 J" csr_instbus [86:0] $end
+$var wire 1 K" csr_en $end
+$var wire 32 L" alu_rs2_val [31:0] $end
+$var wire 5 M" alu_rs2_addr [4:0] $end
+$var wire 32 N" alu_rs1_val [31:0] $end
+$var wire 5 O" alu_rs1_addr [4:0] $end
+$var wire 1 P" alu_rd_wr $end
+$var wire 32 Q" alu_rd_val [31:0] $end
+$var wire 4 R" alu_rd_strb [3:0] $end
+$var wire 5 S" alu_rd_addr [4:0] $end
+$scope begin USE_ICACHE $end
+$scope module icache $end
+$var wire 1 ; aclk $end
+$var wire 1 < aresetn $end
+$var wire 3 T" ctrl_arprot [2:0] $end
+$var wire 2 U" ctrl_rresp [1:0] $end
+$var wire 1 <" flush_ack $end
+$var wire 2 V" icache_arburst [1:0] $end
+$var wire 4 W" icache_arcache [3:0] $end
+$var wire 8 X" icache_arlen [7:0] $end
+$var wire 2 Y" icache_arlock [1:0] $end
+$var wire 4 Z" icache_arqos [3:0] $end
+$var wire 4 [" icache_arregion [3:0] $end
+$var wire 3 \" icache_arsize [2:0] $end
+$var wire 1 ]" icache_rlast $end
+$var wire 1 ! icache_rready $end
+$var wire 2 ^" icache_rresp [1:0] $end
+$var wire 1 H srst $end
+$var wire 1 _" memctrl_arvalid $end
+$var wire 1 `" memctrl_arready $end
+$var wire 3 a" memctrl_arprot [2:0] $end
+$var wire 8 b" memctrl_arid [7:0] $end
+$var wire 16 c" memctrl_araddr [15:0] $end
+$var wire 1 d" is_flushing $end
+$var wire 1 . icache_rvalid $end
+$var wire 8 e" icache_rid [7:0] $end
+$var wire 128 f" icache_rdata [127:0] $end
+$var wire 1 4 icache_arvalid $end
+$var wire 1 5 icache_arready $end
+$var wire 3 g" icache_arprot [2:0] $end
+$var wire 8 h" icache_arid [7:0] $end
+$var wire 16 i" icache_araddr [15:0] $end
+$var wire 1 ;" flush_req $end
+$var wire 1 j" flush_ack_memctrl $end
+$var wire 1 k" flush_ack_fetcher $end
+$var wire 1 &" ctrl_rvalid $end
+$var wire 1 '" ctrl_rready $end
+$var wire 8 l" ctrl_rid [7:0] $end
+$var wire 32 m" ctrl_rdata [31:0] $end
+$var wire 1 ," ctrl_arvalid $end
+$var wire 1 -" ctrl_arready $end
+$var wire 8 n" ctrl_arid [7:0] $end
+$var wire 16 o" ctrl_araddr [15:0] $end
+$var wire 1 p" cache_wen $end
+$var wire 128 q" cache_wdata [127:0] $end
+$var wire 16 r" cache_waddr [15:0] $end
+$var wire 1 s" cache_ren $end
+$var wire 32 t" cache_rdata [31:0] $end
+$var wire 16 u" cache_raddr [15:0] $end
+$var wire 1 v" cache_miss $end
+$var wire 1 w" cache_hit $end
+$scope module cache_lines $end
+$var wire 1 ; aclk $end
+$var wire 1 < aresetn $end
+$var wire 1 H srst $end
+$var wire 3 x" wtag [2:0] $end
+$var wire 132 y" wline [131:0] $end
+$var wire 9 z" windex [8:0] $end
+$var wire 1 p" wen $end
+$var wire 128 {" wdata [127:0] $end
+$var wire 16 |" waddr [15:0] $end
+$var wire 3 }" rtag [2:0] $end
+$var wire 1 ~" rset $end
+$var wire 2 !# roffset [1:0] $end
+$var wire 128 "# rline [127:0] $end
+$var wire 9 ## rindex [8:0] $end
+$var wire 1 s" ren $end
+$var wire 16 $# raddr [15:0] $end
+$var wire 1 d" flush $end
+$var reg 1 w" hit $end
+$var reg 1 v" miss $end
+$var reg 32 %# rdata [31:0] $end
+$scope begin $ivl_for_loop3 $end
+$var integer 32 &# i [31:0] $end
+$upscope $end
+$upscope $end
+$scope module fetcher $end
+$var wire 1 ; aclk $end
+$var wire 1 < aresetn $end
+$var wire 1 w" cache_hit $end
+$var wire 1 v" cache_miss $end
+$var wire 32 '# cache_rdata [31:0] $end
+$var wire 3 (# ctrl_arprot [2:0] $end
+$var wire 32 )# ctrl_rdata [31:0] $end
+$var wire 8 *# ctrl_rid [7:0] $end
+$var wire 2 +# ctrl_rresp [1:0] $end
+$var wire 1 &" ctrl_rvalid $end
+$var wire 3 ,# memctrl_arprot [2:0] $end
+$var wire 1 H srst $end
+$var wire 1 -# reboot $end
+$var wire 1 `" memctrl_arready $end
+$var wire 1 ;" flush_req $end
+$var wire 1 .# fifo_full_mf $end
+$var wire 1 /# fifo_full_if $end
+$var wire 1 0# fifo_empty_mf $end
+$var wire 1 1# fifo_empty_if $end
+$var wire 1 '" ctrl_rready $end
+$var wire 1 ," ctrl_arvalid $end
+$var wire 1 -" ctrl_arready $end
+$var wire 8 2# ctrl_arid [7:0] $end
+$var wire 16 3# ctrl_araddr [15:0] $end
+$var wire 1 p" cache_writing $end
+$var wire 8 4# cache_rid [7:0] $end
+$var wire 1 s" cache_ren $end
+$var wire 16 5# cache_raddr [15:0] $end
+$var wire 8 6# arid_mf [7:0] $end
+$var wire 8 7# arid_if [7:0] $end
+$var wire 16 8# araddr_mf [15:0] $end
+$var wire 16 9# araddr_if [15:0] $end
+$var reg 16 :# araddr_ffd [15:0] $end
+$var reg 8 ;# arid_ffd [7:0] $end
+$var reg 8 <# arid_reboot [7:0] $end
+$var reg 1 k" flush_ack $end
+$var reg 1 =# flush_fifo $end
+$var reg 16 ># memctrl_araddr [15:0] $end
+$var reg 8 ?# memctrl_arid [7:0] $end
+$var reg 1 _" memctrl_arvalid $end
+$var reg 1 @# pull_addr_if $end
+$var reg 1 A# pull_addr_mf $end
+$var reg 3 B# seq [2:0] $end
+$scope module if_fifo $end
+$var wire 1 ; aclk $end
+$var wire 1 < aresetn $end
+$var wire 24 C# data_in [23:0] $end
+$var wire 1 D# flush $end
+$var wire 1 @# pull $end
+$var wire 1 H srst $end
+$var wire 1 E# wr_en $end
+$var wire 1 ," push $end
+$var wire 1 F# pass_thru $end
+$var wire 1 G# full_flag $end
+$var wire 1 /# full $end
+$var wire 1 H# empty_flag $end
+$var wire 1 1# empty $end
+$var wire 24 I# data_out [23:0] $end
+$var wire 24 J# data_fifo [23:0] $end
+$var reg 4 K# rdptr [3:0] $end
+$var reg 4 L# wrptr [3:0] $end
+$scope begin PASS_THRU_MODE $end
+$upscope $end
+$scope module fifo_ram $end
+$var wire 1 ; aclk $end
+$var wire 3 M# addr_in [2:0] $end
+$var wire 3 N# addr_out [2:0] $end
+$var wire 24 O# data_in [23:0] $end
+$var wire 1 E# wr_en $end
+$var wire 24 P# data_out [23:0] $end
+$scope begin genblk2 $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope module mf_fifo $end
+$var wire 1 ; aclk $end
+$var wire 1 < aresetn $end
+$var wire 24 Q# data_in [23:0] $end
+$var wire 1 R# flush $end
+$var wire 1 A# pull $end
+$var wire 1 v" push $end
+$var wire 1 H srst $end
+$var wire 1 S# wr_en $end
+$var wire 1 T# pass_thru $end
+$var wire 1 U# full_flag $end
+$var wire 1 .# full $end
+$var wire 1 V# empty_flag $end
+$var wire 1 0# empty $end
+$var wire 24 W# data_out [23:0] $end
+$var wire 24 X# data_fifo [23:0] $end
+$var reg 2 Y# rdptr [1:0] $end
+$var reg 2 Z# wrptr [1:0] $end
+$scope begin PASS_THRU_MODE $end
+$upscope $end
+$scope module fifo_ram $end
+$var wire 1 ; aclk $end
+$var wire 1 [# addr_in $end
+$var wire 1 \# addr_out $end
+$var wire 24 ]# data_in [23:0] $end
+$var wire 1 S# wr_en $end
+$var wire 24 ^# data_out [23:0] $end
+$scope begin genblk2 $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope module mem_ctrl $end
+$var wire 1 ; aclk $end
+$var wire 1 < aresetn $end
+$var wire 128 _# cache_wdata [127:0] $end
+$var wire 16 `# ctrl_araddr [15:0] $end
+$var wire 8 a# ctrl_arid [7:0] $end
+$var wire 3 b# ctrl_arprot [2:0] $end
+$var wire 1 `" ctrl_arready $end
+$var wire 1 _" ctrl_arvalid $end
+$var wire 16 c# mem_araddr [15:0] $end
+$var wire 2 d# mem_arburst [1:0] $end
+$var wire 4 e# mem_arcache [3:0] $end
+$var wire 8 f# mem_arid [7:0] $end
+$var wire 8 g# mem_arlen [7:0] $end
+$var wire 2 h# mem_arlock [1:0] $end
+$var wire 3 i# mem_arprot [2:0] $end
+$var wire 4 j# mem_arqos [3:0] $end
+$var wire 4 k# mem_arregion [3:0] $end
+$var wire 3 l# mem_arsize [2:0] $end
+$var wire 1 4 mem_arvalid $end
+$var wire 1 ]" mem_rlast $end
+$var wire 1 ! mem_rready $end
+$var wire 2 m# mem_rresp [1:0] $end
+$var wire 1 H srst $end
+$var wire 1 . mem_rvalid $end
+$var wire 8 n# mem_rid [7:0] $end
+$var wire 128 o# mem_rdata [127:0] $end
+$var wire 1 5 mem_arready $end
+$var wire 1 ;" flush_req $end
+$var wire 1 p" cache_wen $end
+$var wire 16 p# cache_waddr [15:0] $end
+$var reg 2 q# cfsm [1:0] $end
+$var reg 17 r# erase_addr [16:0] $end
+$var reg 1 s# erase_wen $end
+$var reg 1 d" flush $end
+$var reg 1 j" flush_ack $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope module control $end
+$var wire 1 ; aclk $end
+$var wire 1 < aresetn $end
+$var wire 3 t# arprot [2:0] $end
+$var wire 1 -" arready $end
+$var wire 1 K" csr_en $end
+$var wire 87 u# csr_instbus [86:0] $end
+$var wire 5 v# ctrl_rd_addr [4:0] $end
+$var wire 5 w# ctrl_rs1_addr [4:0] $end
+$var wire 5 x# ctrl_rs2_addr [4:0] $end
+$var wire 1 <" flush_ack $end
+$var wire 1 y# jump_branch $end
+$var wire 1 p proc_en $end
+$var wire 4 z# proc_fenceinfo [3:0] $end
+$var wire 1 {# push_inst $end
+$var wire 32 |# rdata [31:0] $end
+$var wire 8 }# rid [7:0] $end
+$var wire 1 '" rready $end
+$var wire 2 ~# rresp [1:0] $end
+$var wire 1 &" rvalid $end
+$var wire 1 H srst $end
+$var wire 5 !$ zimm [4:0] $end
+$var wire 4 "$ succ [3:0] $end
+$var wire 6 #$ shamt [5:0] $end
+$var wire 5 $$ rs2 [4:0] $end
+$var wire 5 %$ rs1 [4:0] $end
+$var wire 5 &$ rd [4:0] $end
+$var wire 1 '$ pull_inst $end
+$var wire 1 ($ processing $end
+$var wire 1 n proc_ready $end
+$var wire 87 )$ proc_instbus [86:0] $end
+$var wire 1 q proc_empty $end
+$var wire 4 *$ pred [3:0] $end
+$var wire 32 +$ pc_plus4 [31:0] $end
+$var wire 32 ,$ pc_jalr [31:0] $end
+$var wire 32 -$ pc_jal [31:0] $end
+$var wire 32 .$ pc_branching [31:0] $end
+$var wire 32 /$ pc_auipc [31:0] $end
+$var wire 32 0$ pc [31:0] $end
+$var wire 7 1$ opcode [6:0] $end
+$var wire 1 2$ lui $end
+$var wire 1 3$ jalr $end
+$var wire 1 4$ jal $end
+$var wire 32 5$ instruction [31:0] $end
+$var wire 1 6$ inst_error $end
+$var wire 20 7$ imm20 [19:0] $end
+$var wire 12 8$ imm12 [11:0] $end
+$var wire 1 9$ goto_branch $end
+$var wire 7 :$ funct7 [6:0] $end
+$var wire 3 ;$ funct3 [2:0] $end
+$var wire 1 <$ fifo_full $end
+$var wire 1 =$ fifo_empty $end
+$var wire 2 >$ fence [1:0] $end
+$var wire 3 ?$ env [2:0] $end
+$var wire 32 @$ ctrl_rs2_val [31:0] $end
+$var wire 32 A$ ctrl_rs1_val [31:0] $end
+$var wire 1 A" ctrl_rd_wr $end
+$var wire 32 B$ ctrl_rd_val [31:0] $end
+$var wire 1 F" csr_ready $end
+$var wire 12 C$ csr [11:0] $end
+$var wire 1 D$ cant_process_now $end
+$var wire 1 E$ cant_branch_now $end
+$var wire 1 F$ branching $end
+$var wire 1 G$ bne $end
+$var wire 1 H$ bltu $end
+$var wire 1 I$ blt $end
+$var wire 1 J$ bgeu $end
+$var wire 1 K$ bge $end
+$var wire 1 L$ beq $end
+$var wire 1 M$ auipc $end
+$var reg 16 N$ araddr [15:0] $end
+$var reg 8 O$ arid [7:0] $end
+$var reg 1 ," arvalid $end
+$var reg 4 P$ cfsm [3:0] $end
+$var reg 1 : ebreak $end
+$var reg 1 Q$ flush_fifo $end
+$var reg 1 ;" flush_req $end
+$var reg 32 R$ pc_auipc_saved [31:0] $end
+$var reg 32 S$ pc_jal_saved [31:0] $end
+$var reg 32 T$ pc_reg [31:0] $end
+$scope module decoder $end
+$var wire 32 U$ instruction [31:0] $end
+$var reg 1 M$ auipc $end
+$var reg 1 F$ branching $end
+$var reg 12 V$ csr [11:0] $end
+$var reg 3 W$ env [2:0] $end
+$var reg 2 X$ fence [1:0] $end
+$var reg 3 Y$ funct3 [2:0] $end
+$var reg 7 Z$ funct7 [6:0] $end
+$var reg 12 [$ imm12 [11:0] $end
+$var reg 20 \$ imm20 [19:0] $end
+$var reg 1 6$ inst_error $end
+$var reg 1 4$ jal $end
+$var reg 1 3$ jalr $end
+$var reg 1 2$ lui $end
+$var reg 7 ]$ opcode [6:0] $end
+$var reg 4 ^$ pred [3:0] $end
+$var reg 1 ($ processing $end
+$var reg 5 _$ rd [4:0] $end
+$var reg 5 `$ rs1 [4:0] $end
+$var reg 5 a$ rs2 [4:0] $end
+$var reg 6 b$ shamt [5:0] $end
+$var reg 4 c$ succ [3:0] $end
+$var reg 5 d$ zimm [4:0] $end
+$upscope $end
+$scope module inst_fifo $end
+$var wire 1 ; aclk $end
+$var wire 1 < aresetn $end
+$var wire 32 e$ data_in [31:0] $end
+$var wire 1 Q$ flush $end
+$var wire 1 f$ pass_thru $end
+$var wire 1 '$ pull $end
+$var wire 1 {# push $end
+$var wire 1 H srst $end
+$var wire 1 g$ wr_en $end
+$var wire 1 h$ full_flag $end
+$var wire 1 <$ full $end
+$var wire 1 i$ empty_flag $end
+$var wire 1 =$ empty $end
+$var wire 32 j$ data_out [31:0] $end
+$var wire 32 k$ data_fifo [31:0] $end
+$var reg 4 l$ rdptr [3:0] $end
+$var reg 4 m$ wrptr [3:0] $end
+$scope begin STORE_MODE $end
+$upscope $end
+$scope module fifo_ram $end
+$var wire 1 ; aclk $end
+$var wire 3 n$ addr_in [2:0] $end
+$var wire 3 o$ addr_out [2:0] $end
+$var wire 32 p$ data_in [31:0] $end
+$var wire 1 g$ wr_en $end
+$var wire 32 q$ data_out [31:0] $end
+$scope begin genblk2 $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope module csrs $end
+$var wire 1 ; aclk $end
+$var wire 1 < aresetn $end
+$var wire 87 r$ instbus [86:0] $end
+$var wire 5 s$ rs1_addr [4:0] $end
+$var wire 1 H srst $end
+$var wire 1 K" valid $end
+$var wire 5 t$ zimm [4:0] $end
+$var wire 6 u$ shamt [5:0] $end
+$var wire 5 v$ rs2 [4:0] $end
+$var wire 32 w$ rs1_val [31:0] $end
+$var wire 5 x$ rs1 [4:0] $end
+$var wire 5 y$ rd [4:0] $end
+$var wire 7 z$ opcode [6:0] $end
+$var wire 20 {$ imm20 [19:0] $end
+$var wire 12 |$ imm12 [11:0] $end
+$var wire 7 }$ funct7 [6:0] $end
+$var wire 3 ~$ funct3 [2:0] $end
+$var wire 1 !% csr_rd $end
+$var wire 12 "% csr [11:0] $end
+$var reg 2 #% cfsm [1:0] $end
+$var reg 12 $% csr_r [11:0] $end
+$var reg 1 %% csr_wr $end
+$var reg 3 &% funct3_r [2:0] $end
+$var reg 32 '% newval [31:0] $end
+$var reg 32 (% oldval [31:0] $end
+$var reg 5 )% rd_wr_addr [4:0] $end
+$var reg 1 G" rd_wr_en $end
+$var reg 32 *% rd_wr_val [31:0] $end
+$var reg 1 F" ready $end
+$var reg 5 +% rs1_addr_r [4:0] $end
+$var reg 32 ,% rs1_val_r [31:0] $end
+$var reg 5 -% zimm_r [4:0] $end
+$scope begin $ivl_for_loop2 $end
+$var integer 32 .% i [31:0] $end
+$upscope $end
+$upscope $end
+$scope module ios $end
+$var wire 1 ; aclk $end
+$var wire 1 < aresetn $end
+$var wire 32 /% gpio_in [31:0] $end
+$var wire 1 H srst $end
+$var wire 1 # uart_cts $end
+$var wire 1 $ uart_rx $end
+$var wire 1 % uart_tx $end
+$var wire 1 & uart_rts $end
+$var wire 1 0% slv1_wr $end
+$var wire 32 1% slv1_wdata [31:0] $end
+$var wire 4 2% slv1_strb [3:0] $end
+$var wire 1 3% slv1_ready $end
+$var wire 32 4% slv1_rdata [31:0] $end
+$var wire 1 5% slv1_en $end
+$var wire 16 6% slv1_addr [15:0] $end
+$var wire 1 7% slv0_wr $end
+$var wire 32 8% slv0_wdata [31:0] $end
+$var wire 4 9% slv0_strb [3:0] $end
+$var wire 1 :% slv0_ready $end
+$var wire 32 ;% slv0_rdata [31:0] $end
+$var wire 1 <% slv0_en $end
+$var wire 16 =% slv0_addr [15:0] $end
+$var wire 1 3" mst_wr $end
+$var wire 32 >% mst_wdata [31:0] $end
+$var wire 4 ?% mst_strb [3:0] $end
+$var wire 1 6" mst_ready $end
+$var wire 32 @% mst_rdata [31:0] $end
+$var wire 1 w mst_en $end
+$var wire 16 A% mst_addr [15:0] $end
+$var wire 32 B% gpio_out [31:0] $end
+$scope module apb_interconnect $end
+$var wire 1 ; aclk $end
+$var wire 1 < aresetn $end
+$var wire 1 H srst $end
+$var wire 1 3% slv1_ready $end
+$var wire 32 C% slv1_rdata [31:0] $end
+$var wire 1 :% slv0_ready $end
+$var wire 32 D% slv0_rdata [31:0] $end
+$var wire 1 3" mst_wr $end
+$var wire 32 E% mst_wdata [31:0] $end
+$var wire 4 F% mst_strb [3:0] $end
+$var wire 1 w mst_en $end
+$var wire 16 G% mst_addr [15:0] $end
+$var reg 32 H% mst_rdata [31:0] $end
+$var reg 1 6" mst_ready $end
+$var reg 16 I% slv0_addr [15:0] $end
+$var reg 1 <% slv0_en $end
+$var reg 4 J% slv0_strb [3:0] $end
+$var reg 32 K% slv0_wdata [31:0] $end
+$var reg 1 7% slv0_wr $end
+$var reg 16 L% slv1_addr [15:0] $end
+$var reg 1 5% slv1_en $end
+$var reg 4 M% slv1_strb [3:0] $end
+$var reg 32 N% slv1_wdata [31:0] $end
+$var reg 1 0% slv1_wr $end
+$upscope $end
+$scope module gpios $end
+$var wire 1 ; aclk $end
+$var wire 1 < aresetn $end
+$var wire 32 O% gpio_in [31:0] $end
+$var wire 32 P% gpio_out [31:0] $end
+$var wire 16 Q% mst_addr [15:0] $end
+$var wire 1 <% mst_en $end
+$var wire 4 R% mst_strb [3:0] $end
+$var wire 32 S% mst_wdata [31:0] $end
+$var wire 1 7% mst_wr $end
+$var wire 32 T% register1 [31:0] $end
+$var wire 1 H srst $end
+$var reg 32 U% mst_rdata [31:0] $end
+$var reg 1 :% mst_ready $end
+$var reg 32 V% register0 [31:0] $end
+$upscope $end
+$scope module uart $end
+$var wire 1 ; aclk $end
+$var wire 1 < aresetn $end
+$var wire 1 W% busy $end
+$var wire 16 X% mst_addr [15:0] $end
+$var wire 1 5% mst_en $end
+$var wire 4 Y% mst_strb [3:0] $end
+$var wire 32 Z% mst_wdata [31:0] $end
+$var wire 1 0% mst_wr $end
+$var wire 1 H srst $end
+$var wire 1 # uart_cts $end
+$var wire 1 & uart_rts $end
+$var wire 1 $ uart_rx $end
+$var wire 1 [% uart_rx_sync $end
+$var wire 1 \% tx_full $end
+$var wire 1 ]% tx_empty $end
+$var wire 8 ^% tx_data [7:0] $end
+$var wire 1 _% rx_full $end
+$var wire 1 `% rx_empty $end
+$var wire 8 a% register3 [7:0] $end
+$var wire 32 b% register0 [31:0] $end
+$var reg 16 c% clock_divider [15:0] $end
+$var reg 1 d% enable $end
+$var reg 1 e% loopback_mode $end
+$var reg 32 f% mst_rdata [31:0] $end
+$var reg 1 3% mst_ready $end
+$var reg 1 g% parity_en $end
+$var reg 1 h% parity_mode $end
+$var reg 8 i% register2 [7:0] $end
+$var reg 16 j% rx_baud_cnt [15:0] $end
+$var reg 4 k% rx_bit_cnt [3:0] $end
+$var reg 8 l% rx_data [7:0] $end
+$var reg 1 m% rx_pull $end
+$var reg 1 n% rx_push $end
+$var reg 4 o% rxfsm [3:0] $end
+$var reg 1 p% stop_mode $end
+$var reg 16 q% tx_baud_cnt [15:0] $end
+$var reg 4 r% tx_bit_cnt [3:0] $end
+$var reg 8 s% tx_data_srr [7:0] $end
+$var reg 1 t% tx_pull $end
+$var reg 1 u% tx_push $end
+$var reg 4 v% txfsm [3:0] $end
+$var reg 2 w% uart_rx_cdc [1:0] $end
+$var reg 1 % uart_tx $end
+$scope module rx_fifo $end
+$var wire 1 ; aclk $end
+$var wire 1 < aresetn $end
+$var wire 8 x% data_in [7:0] $end
+$var wire 1 y% flush $end
+$var wire 1 z% pass_thru $end
+$var wire 1 m% pull $end
+$var wire 1 n% push $end
+$var wire 1 H srst $end
+$var wire 1 {% wr_en $end
+$var wire 1 |% full_flag $end
+$var wire 1 _% full $end
+$var wire 1 }% empty_flag $end
+$var wire 1 `% empty $end
+$var wire 8 ~% data_out [7:0] $end
+$var wire 8 !& data_fifo [7:0] $end
+$var reg 3 "& rdptr [2:0] $end
+$var reg 3 #& wrptr [2:0] $end
+$scope begin STORE_MODE $end
+$upscope $end
+$scope module fifo_ram $end
+$var wire 1 ; aclk $end
+$var wire 2 $& addr_in [1:0] $end
+$var wire 2 %& addr_out [1:0] $end
+$var wire 8 && data_in [7:0] $end
+$var wire 1 {% wr_en $end
+$var wire 8 '& data_out [7:0] $end
+$scope begin genblk2 $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope module tx_fifo $end
+$var wire 1 ; aclk $end
+$var wire 1 < aresetn $end
+$var wire 8 (& data_in [7:0] $end
+$var wire 1 )& flush $end
+$var wire 1 *& pass_thru $end
+$var wire 1 t% pull $end
+$var wire 1 u% push $end
+$var wire 1 H srst $end
+$var wire 1 +& wr_en $end
+$var wire 1 ,& full_flag $end
+$var wire 1 \% full $end
+$var wire 1 -& empty_flag $end
+$var wire 1 ]% empty $end
+$var wire 8 .& data_out [7:0] $end
+$var wire 8 /& data_fifo [7:0] $end
+$var reg 3 0& rdptr [2:0] $end
+$var reg 3 1& wrptr [2:0] $end
+$scope begin STORE_MODE $end
+$upscope $end
+$scope module fifo_ram $end
+$var wire 1 ; aclk $end
+$var wire 2 2& addr_in [1:0] $end
+$var wire 2 3& addr_out [1:0] $end
+$var wire 8 4& data_in [7:0] $end
+$var wire 1 +& wr_en $end
+$var wire 8 5& data_out [7:0] $end
+$scope begin genblk2 $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope module isa_registers $end
+$var wire 1 ; aclk $end
+$var wire 32 6& alu_rs1_val [31:0] $end
+$var wire 32 7& alu_rs2_val [31:0] $end
+$var wire 1 < aresetn $end
+$var wire 5 8& csr_rd_addr [4:0] $end
+$var wire 32 9& csr_rd_val [31:0] $end
+$var wire 1 G" csr_rd_wr $end
+$var wire 5 :& csr_rs1_addr [4:0] $end
+$var wire 32 ;& csr_rs1_val [31:0] $end
+$var wire 5 <& ctrl_rd_addr [4:0] $end
+$var wire 32 =& ctrl_rd_val [31:0] $end
+$var wire 1 A" ctrl_rd_wr $end
+$var wire 5 >& ctrl_rs1_addr [4:0] $end
+$var wire 32 ?& ctrl_rs1_val [31:0] $end
+$var wire 5 @& ctrl_rs2_addr [4:0] $end
+$var wire 32 A& ctrl_rs2_val [31:0] $end
+$var wire 32 B& memfy_rs1_val [31:0] $end
+$var wire 32 C& memfy_rs2_val [31:0] $end
+$var wire 1 H srst $end
+$var wire 32 D& x0 [31:0] $end
+$var wire 32 E& x1 [31:0] $end
+$var wire 32 F& x10 [31:0] $end
+$var wire 32 G& x11 [31:0] $end
+$var wire 32 H& x12 [31:0] $end
+$var wire 32 I& x13 [31:0] $end
+$var wire 32 J& x14 [31:0] $end
+$var wire 32 K& x15 [31:0] $end
+$var wire 32 L& x16 [31:0] $end
+$var wire 32 M& x17 [31:0] $end
+$var wire 32 N& x18 [31:0] $end
+$var wire 32 O& x19 [31:0] $end
+$var wire 32 P& x2 [31:0] $end
+$var wire 32 Q& x20 [31:0] $end
+$var wire 32 R& x21 [31:0] $end
+$var wire 32 S& x22 [31:0] $end
+$var wire 32 T& x23 [31:0] $end
+$var wire 32 U& x24 [31:0] $end
+$var wire 32 V& x25 [31:0] $end
+$var wire 32 W& x26 [31:0] $end
+$var wire 32 X& x27 [31:0] $end
+$var wire 32 Y& x28 [31:0] $end
+$var wire 32 Z& x29 [31:0] $end
+$var wire 32 [& x3 [31:0] $end
+$var wire 32 \& x30 [31:0] $end
+$var wire 32 ]& x31 [31:0] $end
+$var wire 32 ^& x4 [31:0] $end
+$var wire 32 _& x5 [31:0] $end
+$var wire 32 `& x6 [31:0] $end
+$var wire 32 a& x7 [31:0] $end
+$var wire 32 b& x8 [31:0] $end
+$var wire 32 c& x9 [31:0] $end
+$var wire 5 d& memfy_rs2_addr [4:0] $end
+$var wire 5 e& memfy_rs1_addr [4:0] $end
+$var wire 1 } memfy_rd_wr $end
+$var wire 32 f& memfy_rd_val [31:0] $end
+$var wire 4 g& memfy_rd_strb [3:0] $end
+$var wire 5 h& memfy_rd_addr [4:0] $end
+$var wire 5 i& alu_rs2_addr [4:0] $end
+$var wire 5 j& alu_rs1_addr [4:0] $end
+$var wire 1 P" alu_rd_wr $end
+$var wire 32 k& alu_rd_val [31:0] $end
+$var wire 4 l& alu_rd_strb [3:0] $end
+$var wire 5 m& alu_rd_addr [4:0] $end
+$var integer 32 n& s [31:0] $end
+$scope begin RegisterGeneration[0] $end
+$upscope $end
+$scope begin RegisterGeneration[1] $end
+$upscope $end
+$scope begin RegisterGeneration[2] $end
+$upscope $end
+$scope begin RegisterGeneration[3] $end
+$upscope $end
+$scope begin RegisterGeneration[4] $end
+$upscope $end
+$scope begin RegisterGeneration[5] $end
+$upscope $end
+$scope begin RegisterGeneration[6] $end
+$upscope $end
+$scope begin RegisterGeneration[7] $end
+$upscope $end
+$scope begin RegisterGeneration[8] $end
+$upscope $end
+$scope begin RegisterGeneration[9] $end
+$upscope $end
+$scope begin RegisterGeneration[10] $end
+$upscope $end
+$scope begin RegisterGeneration[11] $end
+$upscope $end
+$scope begin RegisterGeneration[12] $end
+$upscope $end
+$scope begin RegisterGeneration[13] $end
+$upscope $end
+$scope begin RegisterGeneration[14] $end
+$upscope $end
+$scope begin RegisterGeneration[15] $end
+$upscope $end
+$scope begin RegisterGeneration[16] $end
+$upscope $end
+$scope begin RegisterGeneration[17] $end
+$upscope $end
+$scope begin RegisterGeneration[18] $end
+$upscope $end
+$scope begin RegisterGeneration[19] $end
+$upscope $end
+$scope begin RegisterGeneration[20] $end
+$upscope $end
+$scope begin RegisterGeneration[21] $end
+$upscope $end
+$scope begin RegisterGeneration[22] $end
+$upscope $end
+$scope begin RegisterGeneration[23] $end
+$upscope $end
+$scope begin RegisterGeneration[24] $end
+$upscope $end
+$scope begin RegisterGeneration[25] $end
+$upscope $end
+$scope begin RegisterGeneration[26] $end
+$upscope $end
+$scope begin RegisterGeneration[27] $end
+$upscope $end
+$scope begin RegisterGeneration[28] $end
+$upscope $end
+$scope begin RegisterGeneration[29] $end
+$upscope $end
+$scope begin RegisterGeneration[30] $end
+$upscope $end
+$scope begin RegisterGeneration[31] $end
+$upscope $end
+$upscope $end
+$scope module mem_router $end
+$var wire 1 ; aclk $end
+$var wire 1 < aresetn $end
+$var wire 32 o& data_mem_rdata [31:0] $end
+$var wire 1 * data_mem_ready $end
+$var wire 32 p& gpio_rdata [31:0] $end
+$var wire 1 6" gpio_ready $end
+$var wire 1 H srst $end
+$var wire 1 r mst_wr $end
+$var wire 32 q& mst_wdata [31:0] $end
+$var wire 4 r& mst_strb [3:0] $end
+$var wire 1 w mst_en $end
+$var wire 16 s& mst_addr [15:0] $end
+$var reg 16 t& data_mem_addr [15:0] $end
+$var reg 1 , data_mem_en $end
+$var reg 4 u& data_mem_strb [3:0] $end
+$var reg 32 v& data_mem_wdata [31:0] $end
+$var reg 1 ' data_mem_wr $end
+$var reg 16 w& gpio_addr [15:0] $end
+$var reg 1 9" gpio_en $end
+$var reg 4 x& gpio_strb [3:0] $end
+$var reg 32 y& gpio_wdata [31:0] $end
+$var reg 1 3" gpio_wr $end
+$var reg 32 z& mst_rdata [31:0] $end
+$var reg 1 u mst_ready $end
+$upscope $end
+$scope module processing $end
+$var wire 1 ; aclk $end
+$var wire 1 {& alu_empty $end
+$var wire 1 |& alu_en $end
+$var wire 1 }& alu_ready $end
+$var wire 32 ~& alu_rs1_val [31:0] $end
+$var wire 32 !' alu_rs2_val [31:0] $end
+$var wire 1 < aresetn $end
+$var wire 32 "' mem_rdata [31:0] $end
+$var wire 1 u mem_ready $end
+$var wire 1 #' memfy_empty $end
+$var wire 1 $' memfy_en $end
+$var wire 32 %' memfy_rs1_val [31:0] $end
+$var wire 32 &' memfy_rs2_val [31:0] $end
+$var wire 1 q proc_empty $end
+$var wire 1 p proc_en $end
+$var wire 4 '' proc_fenceinfo [3:0] $end
+$var wire 87 (' proc_instbus [86:0] $end
+$var wire 1 n proc_ready $end
+$var wire 1 H srst $end
+$var wire 5 )' memfy_rs2_addr [4:0] $end
+$var wire 5 *' memfy_rs1_addr [4:0] $end
+$var wire 1 +' memfy_ready $end
+$var wire 1 } memfy_rd_wr $end
+$var wire 32 ,' memfy_rd_val [31:0] $end
+$var wire 4 -' memfy_rd_strb [3:0] $end
+$var wire 5 .' memfy_rd_addr [4:0] $end
+$var wire 1 r mem_wr $end
+$var wire 32 /' mem_wdata [31:0] $end
+$var wire 4 0' mem_strb [3:0] $end
+$var wire 1 w mem_en $end
+$var wire 16 1' mem_addr [15:0] $end
+$var wire 5 2' alu_rs2_addr [4:0] $end
+$var wire 5 3' alu_rs1_addr [4:0] $end
+$var wire 1 P" alu_rd_wr $end
+$var wire 32 4' alu_rd_val [31:0] $end
+$var wire 4 5' alu_rd_strb [3:0] $end
+$var wire 5 6' alu_rd_addr [4:0] $end
+$scope module alu $end
+$var wire 32 7' _and [31:0] $end
+$var wire 32 8' _andi [31:0] $end
+$var wire 32 9' _or [31:0] $end
+$var wire 32 :' _ori [31:0] $end
+$var wire 32 ;' _xor [31:0] $end
+$var wire 32 <' _xori [31:0] $end
+$var wire 1 ; aclk $end
+$var wire 1 {& alu_empty $end
+$var wire 1 |& alu_en $end
+$var wire 87 =' alu_instbus [86:0] $end
+$var wire 5 >' alu_rd_addr [4:0] $end
+$var wire 1 P" alu_rd_wr $end
+$var wire 1 }& alu_ready $end
+$var wire 5 ?' alu_rs1_addr [4:0] $end
+$var wire 32 @' alu_rs1_val [31:0] $end
+$var wire 5 A' alu_rs2_addr [4:0] $end
+$var wire 32 B' alu_rs2_val [31:0] $end
+$var wire 1 < aresetn $end
+$var wire 1 H srst $end
+$var wire 5 C' zimm [4:0] $end
+$var wire 6 D' shamt [5:0] $end
+$var wire 5 E' rs2 [4:0] $end
+$var wire 5 F' rs1 [4:0] $end
+$var wire 5 G' rd [4:0] $end
+$var wire 1 H' r_i_opcode $end
+$var wire 7 I' opcode [6:0] $end
+$var wire 20 J' imm20 [19:0] $end
+$var wire 12 K' imm12 [11:0] $end
+$var wire 7 L' funct7 [6:0] $end
+$var wire 3 M' funct3 [2:0] $end
+$var wire 12 N' csr [11:0] $end
+$var wire 32 O' alu_rd_val [31:0] $end
+$var wire 4 P' alu_rd_strb [3:0] $end
+$var wire 32 Q' _sub [31:0] $end
+$var wire 32 R' _srli [31:0] $end
+$var wire 32 S' _srl [31:0] $end
+$var wire 32 T' _srai [31:0] $end
+$var wire 32 U' _sra [31:0] $end
+$var wire 32 V' _sltu [31:0] $end
+$var wire 32 W' _sltiu [31:0] $end
+$var wire 32 X' _slti [31:0] $end
+$var wire 32 Y' _slt [31:0] $end
+$var wire 32 Z' _slli [31:0] $end
+$var wire 32 [' _sll [31:0] $end
+$var wire 32 \' _addi [31:0] $end
+$var wire 32 ]' _add [31:0] $end
+$upscope $end
+$scope module memfy $end
+$var wire 1 ; aclk $end
+$var wire 1 < aresetn $end
+$var wire 32 ^' mem_rdata [31:0] $end
+$var wire 1 u mem_ready $end
+$var wire 1 #' memfy_empty $end
+$var wire 1 $' memfy_en $end
+$var wire 4 _' memfy_fenceinfo [3:0] $end
+$var wire 87 `' memfy_instbus [86:0] $end
+$var wire 5 a' memfy_rd_addr [4:0] $end
+$var wire 5 b' memfy_rs1_addr [4:0] $end
+$var wire 32 c' memfy_rs1_val [31:0] $end
+$var wire 5 d' memfy_rs2_addr [4:0] $end
+$var wire 32 e' memfy_rs2_val [31:0] $end
+$var wire 1 H srst $end
+$var wire 5 f' zimm [4:0] $end
+$var wire 6 g' shamt [5:0] $end
+$var wire 5 h' rs2 [4:0] $end
+$var wire 5 i' rs1 [4:0] $end
+$var wire 5 j' rd [4:0] $end
+$var wire 7 k' opcode [6:0] $end
+$var wire 1 } memfy_rd_wr $end
+$var wire 32 l' memfy_rd_val [31:0] $end
+$var wire 4 m' memfy_rd_strb [3:0] $end
+$var wire 1 n' mem_access $end
+$var wire 1 o' is_unaligned $end
+$var wire 20 p' imm20 [19:0] $end
+$var wire 12 q' imm12 [11:0] $end
+$var wire 7 r' funct7 [6:0] $end
+$var wire 3 s' funct3 [2:0] $end
+$var wire 12 t' csr [11:0] $end
+$var wire 32 u' addr [31:0] $end
+$var reg 3 v' funct3_r [2:0] $end
+$var reg 16 w' mem_addr [15:0] $end
+$var reg 1 w mem_en $end
+$var reg 4 x' mem_strb [3:0] $end
+$var reg 32 y' mem_wdata [31:0] $end
+$var reg 1 r mem_wr $end
+$var reg 1 +' memfy_ready $end
+$var reg 4 z' next_strb [3:0] $end
+$var reg 2 {' offset [1:0] $end
+$var reg 7 |' opcode_r [6:0] $end
+$var reg 5 }' rd_r [4:0] $end
+$var reg 1 ~' two_phases $end
+$scope function aligned_strb $end
+$upscope $end
+$scope function get_aligned_mem_data $end
+$upscope $end
+$scope function get_aligned_rd_data $end
+$upscope $end
+$scope function get_mem_strb $end
+$upscope $end
+$scope function get_rd_strb $end
+$upscope $end
+$scope function get_rd_val $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope module statistic $end
+$var wire 1 ; aclk $end
+$var wire 1 < aresetn $end
+$var wire 1 !( debug $end
+$var wire 1 = enable $end
+$var wire 1 4 inst_en $end
+$var wire 1 H srst $end
+$var wire 1 5 inst_ready $end
+$var reg 32 "( inst_served [31:0] $end
+$var reg 32 #( inst_wait [31:0] $end
+$var reg 32 $( uptime [31:0] $end
+$upscope $end
+$upscope $end
+$scope module inst_axi4l_ram $end
+$var wire 1 ; aclk $end
+$var wire 16 %( araddr [15:0] $end
+$var wire 1 < aresetn $end
+$var wire 8 &( arid [7:0] $end
+$var wire 3 '( arprot [2:0] $end
+$var wire 1 5 arready $end
+$var wire 1 4 arvalid $end
+$var wire 16 (( awaddr [15:0] $end
+$var wire 8 )( awid [7:0] $end
+$var wire 3 *( awprot [2:0] $end
+$var wire 1 B awvalid $end
+$var wire 1 C bready $end
+$var wire 1 +( raddr_pull $end
+$var wire 8 ,( rid [7:0] $end
+$var wire 1 ! rready $end
+$var wire 2 -( rresp [1:0] $end
+$var wire 1 H srst $end
+$var wire 128 .( wdata [127:0] $end
+$var wire 8 /( wid [7:0] $end
+$var wire 1 F wready $end
+$var wire 1 G wvalid $end
+$var wire 128 0( rdata [127:0] $end
+$var wire 1 1( raddr_full $end
+$var wire 1 2( raddr_empty $end
+$var wire 8 3( arid_s [7:0] $end
+$var wire 16 4( araddr_s [15:0] $end
+$var reg 1 3 awready $end
+$var reg 2 5( bresp [1:0] $end
+$var reg 1 1 bvalid $end
+$var reg 1 . rvalid $end
+$var integer 32 6( random [31:0] $end
+$var integer 32 7( rcounter [31:0] $end
+$scope module arch_fifo $end
+$var wire 1 ; aclk $end
+$var wire 1 < aresetn $end
+$var wire 24 8( data_in [23:0] $end
+$var wire 1 9( flush $end
+$var wire 1 :( pass_thru $end
+$var wire 1 +( pull $end
+$var wire 1 4 push $end
+$var wire 1 H srst $end
+$var wire 1 ;( wr_en $end
+$var wire 1 <( full_flag $end
+$var wire 1 1( full $end
+$var wire 1 =( empty_flag $end
+$var wire 1 2( empty $end
+$var wire 24 >( data_out [23:0] $end
+$var wire 24 ?( data_fifo [23:0] $end
+$var reg 4 @( rdptr [3:0] $end
+$var reg 4 A( wrptr [3:0] $end
+$scope begin STORE_MODE $end
+$upscope $end
+$scope module fifo_ram $end
+$var wire 1 ; aclk $end
+$var wire 3 B( addr_in [2:0] $end
+$var wire 3 C( addr_out [2:0] $end
+$var wire 24 D( data_in [23:0] $end
+$var wire 1 ;( wr_en $end
+$var wire 24 E( data_out [23:0] $end
+$scope begin genblk2 $end
+$upscope $end
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+$var reg 1 F( msg $end
+$upscope $end
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+$var reg 1 G( msg $end
+$upscope $end
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+$var reg 1 H( msg $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
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+0H(
+1;
diff --git a/public/vcd.css b/public/vcd.css
index 941f614..a36f3af 100644
--- a/public/vcd.css
+++ b/public/vcd.css
@@ -2,11 +2,15 @@
     --display-signal-info-height: 50px;
     --signal-default-color: #4CAF50;
     --main-color: #CB81DA;
+    --sidebar-width: 280px;
+    --right-nav-width: 60px;
+    --time-scale-height: 50px;
 }
 
 html, body {
     background-color: var(--background);
     color: var(--foreground);
+    overflow: hidden;
 }
 
 body::-webkit-scrollbar {
@@ -75,4 +79,12 @@ body::-webkit-scrollbar {
 
 .el-checkbox-button__inner {
     font-size: 16px !important;
+}
+
+.el-select {
+    width: fit-content !important;
+}
+
+a {
+    color: var(--main-color);
 }
\ No newline at end of file
diff --git a/src/App.vue b/src/App.vue
index f4a38e4..137d0fb 100644
--- a/src/App.vue
+++ b/src/App.vue
@@ -1,13 +1,12 @@
 <template>
-    <div class="vcd-render-wrapper" @mousemove="getMousemove">
-    </div>
+    <!-- 主渲染区 -->
+    <MainRender></MainRender>
 
     <!-- 左上角的 sidebar，用于显示 -->
     <Sidebar></Sidebar>
 
     <!-- 工具栏 -->
     <div class="vcd-toolbar">
-
     </div>
 
     <!-- 显示当前信号树形关系 -->
@@ -18,15 +17,17 @@
 <script>
 import { onMounted, reactive } from 'vue';
 import { getVcdStream, readVcdFile } from '@/hook/utils';
-import { emitter, globalLookup, globalSetting } from '@/hook/global';
+import { emitter, globalLookup, globalSetting, signalValues } from '@/hook/global';
 
 import Sidebar from '@/components/sidebar.vue';
 import RightNav from '@/components/right-nav.vue';
+import MainRender from '@/components/render';
 
 export default {
     components: {
         RightNav,
-        Sidebar
+        Sidebar,
+        MainRender
     },
     setup() {
 
@@ -50,6 +51,10 @@ export default {
             document.body.style.setProperty('--el-border-color-light', 'var(--sidebar)');
             document.body.style.setProperty('--el-border-color-lighter', 'var(--sidebar)');
             document.body.style.setProperty('--el-bg-color-overlay', 'transplant');
+            document.body.style.setProperty('--el-color-info-light-9', 'var(--vscode-focusBorder)');
+            document.body.style.setProperty('--el-color-info', 'var(--foreground)');
+            document.body.style.setProperty('--el-color-info-light-8', 'var(--vscode-focusBorder)');
+            document.body.style.setProperty('--el-bg-color-overlay', 'transplant');
 
             
             // signal height
@@ -58,21 +63,34 @@ export default {
 
             const uint8array = await readVcdFile();
             const vcdstream = await getVcdStream();
+
+            vcdstream.change.any((id, time, cmd, value, mask) => {
+                if (signalValues[id] === undefined) {
+                    signalValues[id] = [];
+                }
+
+                signalValues[id].push({time, cmd, value, mask});
+            });
+
             const maxChunkLength = 1 << 17;
             for (let i = 0; i < uint8array.length; i += maxChunkLength) {
                 const piece = uint8array.slice(i, i + maxChunkLength);
                 vcdstream.write(piece);
             }
+
             for (const topModule of vcdstream.info.wires.body) {
                 VcdInfo.topModules.push(topModule);
             }
 
+
             globalLookup.status = vcdstream.info.status;
             globalLookup.version = vcdstream.info.version;
             globalLookup.timescale = vcdstream.info.timescale;
             globalLookup.date = vcdstream.info.date;
             globalLookup.t0 = vcdstream.info.t0;
 
+            emitter.emit('meta-ready', null);
+
             // 这一步时，已经加载完成
             // 默认第一个模块被选中
             if (VcdInfo.topModules.length > 0) {
@@ -86,13 +104,8 @@ export default {
             }
         });
 
-        function getMousemove(event) {
-            console.log(event);
-        }
-
         return {
-            VcdInfo,
-            getMousemove
+            VcdInfo
         }
     }
 }
@@ -107,9 +120,4 @@ export default {
     -moz-osx-font-smoothing: grayscale;
 }
 
-.vcd-render-wrapper {
-    height: 98vh;
-    width: 98vw;
-}
-
 </style>
diff --git a/src/components/render/cursor.vue b/src/components/render/cursor.vue
new file mode 100644
index 0000000..64eb533
--- /dev/null
+++ b/src/components/render/cursor.vue
@@ -0,0 +1,181 @@
+<template>
+    <div class="vertical-cursor-wrapper"
+        @click="makeCursor"
+        :style="`left: ${currentX}px`">
+        <div class="current-display-cursor-up">
+            <div class="current-time-value">{{ currentX }} px</div>
+            <div class="cursor-down-arrow"></div>
+        </div>
+        <div class="vertical-line"></div>
+        <div class="current-display-cursor-down">
+            <div class="current-time-value">{{ currentX }} px</div>
+            <div class="cursor-up-arrow"></div>
+        </div>
+    </div>
+
+    <div v-show="showFixedOne" 
+        class="vertical-cursor-wrapper"
+        @click="makeCursor"
+        :style="`left: ${fixedLeft}px`">
+        <div class="fix-current-display-cursor-up">
+            {{ globalLookup.view.currentX }} px
+        </div>
+        <div class="fix-vertical-line"></div>
+        <div class="fix-current-display-cursor-down">
+            {{ globalLookup.view.currentX }} px
+        </div>
+    </div>
+</template>
+
+<script>
+import { reactive, ref } from 'vue';
+import { globalLookup } from '../../hook/global';
+
+export default {
+    name: 'vertical-cursor',
+    setup() {        
+        // see --sidebar-width
+        const left = 280 + 20;
+
+        // see --right-nav-width
+        const right = document.body.clientWidth - 60;
+
+        const showFixedOne = ref(false);
+        const fixedLeft = ref(0);
+        const currentX = ref(left);
+        const boxShift = 25;
+        
+        document.onmousemove = event => {
+            const x = event.x;
+            if (x < left || x > right) {
+                return;
+            }
+            currentX.value = x - boxShift;
+        }
+
+        /**
+         * @param { PointerEvent } event
+         */
+        function makeCursor(event) {
+            console.log(event.x);
+            showFixedOne.value = true;
+            fixedLeft.value = event.x - boxShift;
+            globalLookup.view.currentX = event.x - boxShift;
+        }
+
+        return {
+            makeCursor,
+            fixedLeft,
+            showFixedOne,
+            boxShift,
+            globalLookup,
+            currentX
+        }
+    }
+}
+</script>
+
+<style>
+.vertical-cursor-wrapper {
+    position: absolute;
+    height: 100vh;
+    padding: 0;
+    top: 0;
+    cursor: crosshair;
+    z-index: 55;
+    display: flex;  
+    flex-direction: column;  
+    align-items: center; /* 沿着横轴（水平方向）对齐 */  
+    justify-content: center; /* 沿着纵轴（垂直方向）对齐 */
+}
+
+.current-display-cursor-up {
+    height: var(--time-scale-height);
+    width: 50px;
+    display: flex;
+    align-items: center;
+    justify-content: space-around;
+    color: var(--sidebar-item-text);
+    font-size: 14px;
+    position: relative;
+}
+
+.current-display-cursor-down {
+    height: var(--time-scale-height);
+    width: 50px;
+    display: flex;
+    align-items: center;
+    justify-content: space-around;
+    color: var(--sidebar-item-text);
+    font-size: 14px;
+    position: relative;
+}
+
+.current-time-value {
+    border-radius: .4em;
+    background-color: var(--color-deepPurple);
+    color: var(--sidebar-item-text);
+    padding: 5px;
+    width: fit-content;
+    white-space: nowrap;
+}
+
+.cursor-down-arrow {
+    border-left: 5px solid var(--color-deepPurple);
+    border-top: 5px solid var(--color-deepPurple);
+    transform: rotate(225deg);
+    position: absolute;
+    width: 10px;
+    height: 10px;
+    /* 25px - 10 * 2 / \sqrt{2} */
+    left: 17.93px;
+    bottom: 0;
+}
+
+.cursor-up-arrow {
+    border-left: 5px solid var(--color-deepPurple);
+    border-top: 5px solid var(--color-deepPurple);
+    transform: rotate(45deg);
+    position: absolute;
+    width: 10px;
+    height: 10px;
+    left: 17.93px;
+    top: 0;
+}
+
+.vertical-line {
+    width: 1px;
+    height: calc(100vh - 2 * var(--time-scale-height));
+}
+
+.fix-vertical-line {
+    width: 1px;
+    height: calc(100vh - 2 * var(--time-scale-height));
+    background-color: var(--color-deepPurple);
+}
+
+.fix-current-display-cursor-up {
+    height: var(--time-scale-height);
+    width: 50px;
+    background-color: var(--color-deepPurple);
+    border-radius: .5em .5em .5em .5em;
+    display: flex;
+    align-items: center;
+    justify-content: space-around;
+    color: var(--sidebar-item-text);
+    font-size: 14px;
+}
+
+.fix-current-display-cursor-down {
+    height: var(--time-scale-height);
+    width: 50px;
+    background-color: var(--color-deepPurple);
+    border-radius: .5em .5em .5em .5em;
+    display: flex;
+    align-items: center;
+    justify-content: space-around;
+    color: var(--sidebar-item-text);
+    font-size: 14px;
+}
+
+</style>
\ No newline at end of file
diff --git a/src/components/render/index.vue b/src/components/render/index.vue
new file mode 100644
index 0000000..3ae889c
--- /dev/null
+++ b/src/components/render/index.vue
@@ -0,0 +1,48 @@
+<template>
+    <VerticalCursor></VerticalCursor>
+    <TimeScale></TimeScale>
+    
+    <div class="vcd-render-wrapper" >
+        <div style="height: var(--time-scale-height);"></div>
+    </div>
+</template>
+
+
+<script>
+import { reactive, ref } from 'vue';
+import { emitter, globalLookup, globalSetting } from '@/hook/global';
+
+import VerticalCursor from '@/components/render/cursor.vue';
+import TimeScale from '@/components/render/time-scale.vue';
+
+export default {
+    name: 'main-render',
+    components: {
+        VerticalCursor,
+        TimeScale
+    },
+    setup() {
+        const cursorX = ref(0);
+
+        return {
+            cursorX
+        }
+    }
+}
+
+</script>
+
+<style>
+.vcd-render-wrapper {
+    height: 98vh;
+    width: 98vw;
+    cursor: crosshair;
+    padding: 10px;
+
+}
+
+.render-canvas {
+    
+}
+
+</style>
\ No newline at end of file
diff --git a/src/components/render/time-scale.vue b/src/components/render/time-scale.vue
new file mode 100644
index 0000000..6f5a14f
--- /dev/null
+++ b/src/components/render/time-scale.vue
@@ -0,0 +1,144 @@
+<template>
+    <div class="time-scale-up-wrapper">
+
+    </div>
+
+    <div class="time-scale-wrapper" :style="`left: ${currentX}px; width: ${300}px;`">
+        <div class="current-display-cursor-up">
+            <div class="time-scale-value">{{ currentX }} {{ timeScaleManage.unit }}</div>
+            <div class="time-scale-down"></div>
+        </div>
+        <div class="time-scale-line"></div>
+        <div class="current-display-cursor-down">
+            <div class="time-scale-value">{{ currentX }} {{ timeScaleManage.unit }}</div>
+            <div class="time-scale-up"></div>
+        </div>
+    </div>
+
+    <div class="time-scale-down-wrapper">
+
+    </div>
+</template>
+
+<script>
+import { onMounted, reactive } from 'vue';
+import { globalLookup, emitter } from '@/hook/global';
+import { handleTimeScale } from '@/hook/utils';
+
+export default {
+    name: 'time-scale',
+
+    setup() {
+        // see --sidebar-width
+        const left = 280 + 20;
+
+        // see --right-nav-width
+        const right = document.body.clientWidth - 60;
+
+        const timeScaleManage = reactive({
+            scale: 1,
+            unit: 'ns'
+        });
+
+        // 此时有关波形的元信息已经加载完毕
+        emitter.on('meta-ready', () => {
+            const { scale, unit } = handleTimeScale(globalLookup.timescale);
+            timeScaleManage.scale = scale;
+            timeScaleManage.unit = unit;
+
+            console.log(timeScaleManage.unit);
+
+            const viewInfo = globalLookup.view;
+        });
+
+        document.addEventListener('wheel', event => {
+            if ((event.wheelDelta && event.ctrlKey) || event.detail) {
+                event.preventDefault();
+            }
+            
+            if (event.ctrlKey) {
+                // console.log(event.wheelDelta);
+                console.log('deltaX', event.deltaX);
+                console.log('deltaY', event.deltaY);
+            } else if (event.shiftKey) {
+                // console.log(event.wheelDelta);
+                console.log('deltaX', event.deltaX);
+                console.log('deltaY', event.deltaY);
+            }
+        }, { capture: false, passive: false });
+
+
+        const currentX = 300;
+
+        return {
+            currentX,
+            timeScaleManage
+        }
+    }
+}
+</script>
+
+<style>
+.time-scale-up-wrapper {
+    position: absolute;
+    top: 0;
+    left: calc(var(--sidebar-width) + 20px);
+    width: calc(100vw - var(--sidebar-width) - var(--right-nav-width) - 20px);
+    height: var(--time-scale-height);
+    background-color: var(--sidebar);
+    z-index: 50;
+    cursor: crosshair;
+}
+
+.time-scale-down-wrapper {
+    position: absolute;
+    bottom: 0;
+    left: 0;
+    width: calc(100vw - var(--right-nav-width));
+    height: var(--time-scale-height);
+    background-color: var(--sidebar);
+    z-index: 50;
+    cursor: crosshair;
+}
+
+.time-scale-down {
+    position: absolute;
+    bottom: 0;
+    width: 1px;
+    height: 10px;
+    border: 1px solid var(--scrollbar-hover);
+    background-color: var(--scrollbar-hover);
+}
+
+.time-scale-up {
+    position: absolute;
+    top: 0;
+    width: 1px;
+    height: 10px;
+    border: 1px solid var(--scrollbar-hover);
+    background-color: var(--scrollbar-hover);
+}
+
+.time-scale-wrapper {
+    position: absolute;
+    height: 100vh;
+    padding: 0;
+    top: 0;
+    cursor: crosshair;
+    z-index: 55;
+    display: flex;
+    flex-direction: column;
+    align-items: center;
+    /* 沿着横轴（水平方向）对齐 */
+    justify-content: center;
+    /* 沿着纵轴（垂直方向）对齐 */
+}
+
+.time-scale-value {}
+
+.time-scale-line {
+    width: 1px;
+    background-color: var(--scrollbar-hover);
+    height: calc(100vh - 2 * var(--time-scale-height));
+}
+</style>
\ No newline at end of file
diff --git a/src/components/right-nav.vue b/src/components/right-nav.vue
index ab67c66..cfcd1a3 100644
--- a/src/components/right-nav.vue
+++ b/src/components/right-nav.vue
@@ -95,6 +95,7 @@ export default {
     position: fixed;
     top: 0;
     right: 0;
+    z-index: 60;
 }
 
 .vcd-function-panel {
@@ -107,12 +108,13 @@ export default {
 .vcd-function-option {
     width: fit-content;
     height: 100vh;
+    background-color: var(--sidebar);
     box-shadow: 0 0 15px 1px rgb(16, 16, 16);
 }
 
 .vcd-control-panel-wrapper {
-    width: 60px;
-    height: 60px;
+    width: var(--right-nav-width);
+    height: var(--right-nav-width);
     display: flex;
     align-items: center;
     justify-content: space-around;
diff --git a/src/components/setting/index.vue b/src/components/setting/index.vue
index 71f094d..f6a2ce6 100644
--- a/src/components/setting/index.vue
+++ b/src/components/setting/index.vue
@@ -18,11 +18,18 @@
 
             <div class="setting-option">
                 <span class="option-title">{{ t('search-scope') }}</span>
-                <el-checkbox-group v-model="globalSetting.searchScope" size="default">
-                    <el-checkbox-button label="wire"   border>wire  </el-checkbox-button>
-                    <el-checkbox-button label="reg"    border>reg   </el-checkbox-button>
-                    <el-checkbox-button label="module" border>module</el-checkbox-button>
-                </el-checkbox-group>
+                <el-select
+                    v-model="globalSetting.searchScope"
+                    multiple
+                    collapse-tags
+                    collapse-tags-tooltip
+                    placeholder="Select"
+                >
+                    <el-option v-for="name in scopes" :key="name"
+                        :label="name" :value="name" />
+                    <el-option v-for="name in variables" :key="name"
+                        :label="name" :value="name" />
+                </el-select>
             </div>
 
         </div>
@@ -69,7 +76,7 @@
 import { reactive } from 'vue';
 import { useI18n } from 'vue-i18n';
 import { globalSetting } from '@/hook/global';
-import { debounceWrapper } from '@/hook/utils';
+import { debounceWrapper, scopes, variables } from '@/hook/utils';
 
 export default {
     name: 'dide-setting',
@@ -101,7 +108,9 @@ export default {
             languageSetting,
             globalSetting,
             safeModifySignalTrackHeight,
-            locale
+            locale,
+            scopes,
+            variables
         }
     }
 }
diff --git a/src/components/sidebar.vue b/src/components/sidebar.vue
index 1ff4bcc..d1ce596 100644
--- a/src/components/sidebar.vue
+++ b/src/components/sidebar.vue
@@ -1,6 +1,7 @@
 <template>
     <div class="vcd-sidebar-wrapper">
         <div class="display-signal-wrapper">
+            <div style="height: var(--time-scale-height);"></div>
             <div class="display-signal-item"
                 v-for="(signal, index) in globalLookup.currentWires" :key="index">
                 <div class="signal-color-vendor">
@@ -25,6 +26,7 @@
 import { reactive } from 'vue';
 import { useI18n } from 'vue-i18n';
 import { emitter, globalLookup, globalSetting } from '@/hook/global';
+import { makeIconClass } from '@/hook/utils';
 
 export default {
     name: 'sidebar',
@@ -36,22 +38,9 @@ export default {
         }
 
         function makeSignalIconClass(signal) {
-            if (signal.type === 'wire') {
-                return 'iconfont icon-wave-square';
-            } else if (signal.type === 'reg') {
-                return 'iconfont icon-register';
-            } else {
-                return 'iconfont icon-wave-square';
-            }
+            return 'iconfont ' + makeIconClass(signal);
         }
 
-        function makeSignalInfo(signal) {
-            let htmlString = '';
-            
-        }
-
-
-
         return {
             t,
             globalLookup,
@@ -67,10 +56,11 @@ export default {
     position: absolute;
     top: 0px;
     left: 0px;
+    z-index: 60;
 }
 
 .add-signal-button {
-    margin: 10px;
+    margin-top: 10px;
     padding: 10px 25px;
     background-color: var(--color-deepPurple);
     border-radius: 0 0 .8em .8em;
@@ -85,12 +75,11 @@ export default {
 }
 
 .display-signal-wrapper {
-    margin: 10px;
     padding: 10px;
     background-color: var(--sidebar);
     border: solid 1px var(--sidebar-border);
-    min-width: var(--sidebar-min-width);
-    min-height: 50vh;
+    min-width: var(--sidebar-width);
+    height: calc(100vh - 90px);
     box-shadow: 0 0 15px 1px rgb(16, 16, 16);
 }
 
diff --git a/src/components/treeview/index.vue b/src/components/treeview/index.vue
index a0f0954..4704f9b 100644
--- a/src/components/treeview/index.vue
+++ b/src/components/treeview/index.vue
@@ -55,7 +55,7 @@ export default {
 
 <style>
 .vcd-module-info {
-    width: 300px;
+    width: fit-content;
     padding-right: 5px;
 }
 
@@ -64,8 +64,8 @@ export default {
 }
 
 .vcd-module-display-wrapper {
-    height: 80vh;
-    overflow-x: scroll;
+    height: 90vh;
+    overflow: scroll;
 }
 
 .vcd-treeview {
@@ -82,7 +82,7 @@ export default {
     flex: 1;
     display: flex;
     z-index: 5;
-    max-height: 98vh;
+    max-height: 99vh;
     /* overflow: scroll; */
     transition: flex .5s ease-in-out;
 }
diff --git a/src/components/treeview/modules.vue b/src/components/treeview/modules.vue
index 3132ca0..33c6590 100644
--- a/src/components/treeview/modules.vue
+++ b/src/components/treeview/modules.vue
@@ -5,7 +5,7 @@
             <span class="module-tag-status" @click.stop="expandManage.click">
                 <div :class="expandManage.expandTagClass"></div>
             </span>
-            <span class="iconfont icon-memory-chip"></span>
+            <span :class="`iconfont ${makeIconClass(module)}`"></span>
             &ensp;{{ module.name }}
         </div>
 
@@ -26,6 +26,7 @@
 /* eslint-disable */
 import { reactive, onMounted } from 'vue';
 import { emitter, globalLookup } from '@/hook/global';
+import { isScope, isVariable, makeIconClass } from '@/hook/utils';
 
 export default {
     name: "modules",
@@ -40,9 +41,9 @@ export default {
         const mods = [];
 
         for (const wire of module.body) {
-            if (wire.body) {
+            if (isScope(wire)) {
                 mods.push(wire);
-            } else {
+            } else if (isVariable(wire)) {
                 signals.push(wire);
             }
         }
@@ -51,7 +52,7 @@ export default {
             emitter.emit('tree-view', signals);
             // color change into selected
             globalLookup.currentModule = module;
-
+            console.log(module);
         }
 
         const expandManage = reactive({
@@ -68,10 +69,10 @@ export default {
         return {
             module,
             mods,
-            signals,
             clickItem,
             expandManage,
-            globalLookup
+            globalLookup,
+            makeIconClass
         }
     }
 };
@@ -97,6 +98,8 @@ export default {
     height: 27px;
     display: flex;
     align-items: center;
+    white-space: nowrap;
+    text-overflow: ellipsis;
 }
 
 .vcd-treeview-item::selection {
diff --git a/src/components/treeview/search.vue b/src/components/treeview/search.vue
index 0a6566e..3d2c174 100644
--- a/src/components/treeview/search.vue
+++ b/src/components/treeview/search.vue
@@ -12,13 +12,13 @@
         <div class="search-result-wrapper" v-if="searchManage.content.trim().length > 0">
             <div class="search-result">
                 <div v-if="searchManage.searchResult.length > 0">
-                    <div class="search-result-item" 
-                        v-for="(searchResult, index) in searchManage.searchResult"
-                        :key="index"
-                        :class="globalLookup.currentWires.has(searchResult.module) ? 'vcd-treeview-selected' : ''"
-                        v-html="searchResult.htmlString"
-                        @click="clickItem(searchResult.module)">
-                    </div>
+                        <div v-for="(searchResult, index) in searchManage.searchResult"
+                             :key="index"
+                             :class="globalLookup.currentWires.has(searchResult.module) ? 'vcd-treeview-selected' : ''"
+                             @click="clickItem(searchResult.module)">
+                                <div v-html="searchResult.htmlString" class="search-result-item"></div>                             
+                        </div>
+    
                 </div>
                 <div v-else>
                     {{ t('search-nothing') }}
@@ -76,6 +76,7 @@ export default {
         });
 
         function clickItem(signal) {
+            console.log(signal);
             if (!signal.link) {
                 return;
             }
@@ -108,6 +109,7 @@ export default {
 }
 
 .search-result-wrapper {
+    position: absolute;
     padding: 10px;
     margin: 10px;
     background-color: var(--sidebar);
@@ -115,7 +117,6 @@ export default {
     color: var(--sidebar-item-text);
     border-radius: .5em;
     min-width: 500px;
-    position: absolute;
     z-index: 10;
 }
 
@@ -123,6 +124,8 @@ export default {
     overflow-x: scroll;
     overflow-y: scroll;
     max-height: 80vh;
+    max-width: 600px;
+
     padding-right: 5px;
 }
 
@@ -131,6 +134,7 @@ export default {
     align-items: center;
     height: 25px;
     margin: 3px;
+    width: 800px;
     padding-left: 3px;
     cursor: pointer;
 }
diff --git a/src/components/treeview/signals.vue b/src/components/treeview/signals.vue
index d35d2e0..4e3eb4e 100644
--- a/src/components/treeview/signals.vue
+++ b/src/components/treeview/signals.vue
@@ -7,7 +7,7 @@
                 @click="clickItem(signal)"
                 class="vcd-signal-signal-item"
                 :class="globalLookup.currentWires.has(signal) ? 'vcd-treeview-selected' : ''">
-                <div><span class="iconfont icon-wave-square"></span>&ensp;{{ signal.name }}</div>
+                <div><span :class="`iconfont ${makeIconClass(signal)}`"></span>&ensp;{{ signal.name }}</div>
                 <div>
                     <div :class="signal.size > 1 ? 'vcd-signal-signal-caption' : ''">
                         {{ makeSignalCaption(signal) }}
@@ -23,6 +23,8 @@ import { reactive } from 'vue';
 import { useI18n } from 'vue-i18n';
 
 import { emitter, globalLookup } from '@/hook/global';
+import { makeIconClass } from '@/hook/utils';
+import { makeWaveCanvas, removeWaveCanvas } from '@/hook/render';
 
 /* eslint-disable */
 export default {
@@ -37,7 +39,7 @@ export default {
         });
 
         emitter.on('tree-view', sendWires => {
-            signals.content.length = 0;
+            signals.content = [];
             signals.content = sendWires;
         });
 
@@ -48,8 +50,10 @@ export default {
         function clickItem(signal) {
             if (globalLookup.currentWires.has(signal)) {
                 globalLookup.currentWires.delete(signal);
+                removeWaveCanvas(signal);
             } else {
                 globalLookup.currentWires.add(signal);
+                makeWaveCanvas(signal);
             }
         }
 
@@ -58,7 +62,8 @@ export default {
             clickItem,
             globalLookup,
             makeSignalCaption,
-            t
+            t,
+            makeIconClass
         }
     }
 }
@@ -73,10 +78,34 @@ export default {
     color: var(--signal-default-color);
 }
 
+.icon-brackets {
+    color: #75BEDF;
+}
+
+.icon-register {
+    color:#885dff;
+}
+
+.icon-integer {
+    color: #C76B3C;
+}
+
+.icon-String {
+    color: #8CC265;
+}
+
+.icon-R {
+    color: #5fb4d8;
+}
+
+.icon-task- {
+    color: orange;
+}
+
 .vcd-signal-signals-display {
     color: var(--sidebar-item-text);
     padding: 0px 8px;
-    height: 80vh;
+    height: 90vh;
     overflow-x: scroll;
 }
 
diff --git a/src/hook/global.js b/src/hook/global.js
index 8640570..b1fbd6b 100644
--- a/src/hook/global.js
+++ b/src/hook/global.js
@@ -23,6 +23,16 @@ const globalLookup = reactive({
     // 初始时间，一般都是 0
     t0: 0,
 
+    // 当前视图的左上角的坐标
+    view : {
+        x: 0,
+        y: 0,
+        gridGap: 300,
+        currentBaseUnit: 100,
+        currentX: 0,
+        currentScale: 1
+    },    
+
     initcurrentModule(module) {
         if (this.currentModule === undefined && module) {
             this.currentModule = module;
@@ -41,12 +51,17 @@ const globalSetting = reactive({
     displayParentOnly: false,
     displaySignalHeight: 50,
     searchMode: 'so',        // so, mo, sm
-    searchScope: ['wire', 'reg'],
+    searchScope: ['wire', 'reg', 'integer'],
     displaySignalInfoScope: ['width', 'parent'],
-})
+    
+    minGridWidth: 300
+});
+
+const signalValues = {};
 
 export {
     emitter,
     globalLookup,
-    globalSetting
+    globalSetting,
+    signalValues
 };
\ No newline at end of file
diff --git a/src/hook/render.js b/src/hook/render.js
new file mode 100644
index 0000000..bc62be0
--- /dev/null
+++ b/src/hook/render.js
@@ -0,0 +1,146 @@
+import { globalLookup, globalSetting, signalValues } from "./global";
+
+let mainRenderEl = null;
+const canvasMap = {};
+
+/**
+ * 
+ * @returns {Element}
+ */
+function getMainRenderEl() {
+    if (!mainRenderEl) {
+        const el = document.querySelectorAll('.vcd-render-wrapper')[0];
+        if (el) {
+            mainRenderEl = el;
+        }
+    }
+    return mainRenderEl;
+}
+
+/**
+ * 
+ * @param {{
+ *  time: BigInt,
+ *  cmd: number,
+ *  value?: BigInt,
+ *  mask?: BigInt
+ * }} dataItem 
+ * @returns 
+ */
+function isBlocked(dataItem) {
+    const mask = dataItem.mask;
+    if (mask && mask === 1n) {
+        return true;
+    }
+    if (mask && mask === 0n) {
+        return false;
+    }
+    if (mask === undefined && dataItem.cmd > 15) {
+        return true;
+    }
+    return false;
+}
+
+/**
+ * @param {{
+ * kind: 'var' | 'scope',
+ * type: 'wire' | 'reg' | 'module',
+ * name: string,
+ * size: number,
+ * link: string
+ * }} signal 
+ */
+function makeWaveCanvas(signal) {
+    const mainRender = getMainRenderEl();
+    const canvas = document.createElement('canvas');
+    canvas.id = 'wave-' + signal.link;
+    canvas.className = 'render-canvas';
+    canvas.width = document.body.clientWidth;
+    canvas.height = globalSetting.displaySignalHeight;
+    
+    mainRender.appendChild(canvas);
+    canvasMap[signal] = canvas;
+
+    const ctx = canvas.getContext('2d');
+    const datas = signalValues[signal.link];
+
+    if (signal.size === 1) {
+        drawSimpleSignal(ctx, datas);
+    } else {
+        // adwa
+    }
+}
+
+/**
+ * @param {{
+* kind: 'var' | 'scope',
+* type: 'wire' | 'reg' | 'module',
+* name: string,
+* size: number,
+* link: string
+* }} signal
+*/
+function removeWaveCanvas(signal) {
+    const canvas = canvasMap[signal];
+    if (canvas instanceof HTMLCanvasElement) {
+        canvas.parentNode.removeChild(canvas);
+    }
+}
+
+
+/**
+ * 
+ * @param {CanvasRenderingContext2D} ctx 
+ * @param {Array<{
+ *  time: BigInt,
+ *  cmd: number,
+ *  value?: BigInt,
+ *  mask?: BigInt
+ * }>} signals 
+ */
+function drawSimpleSignal(ctx, signals) {
+    let last_data = null;
+    let last_x = 300;
+    ctx.lineWidth = 3;
+    ctx.lineJoin = 'round';
+    
+    ctx.beginPath();
+    for (const data of signals) {
+        console.log(data);
+        if (last_data === null) {
+            last_data = data;
+            last_x = 300;
+            let last_y = Math.max((15 - last_data.cmd) * 30, 0) + 10;
+            ctx.moveTo(last_x, last_y);
+        } else {
+            // 高阻态
+            const start = last_data.time;
+            const end = data.time;
+            ctx.strokeStyle = isBlocked(last_data) ? 'rgb(224,108,117)' : 'rgb(10, 200, 10)';
+
+            let last_y = Math.max((15 - last_data.cmd) * 30, 0) + 10;
+
+            const duration = parseInt(end - start);
+            const current_x = last_x + 100;
+
+            console.log(current_x, last_y, duration);
+            ctx.lineTo(current_x, last_y);
+
+            if (last_data.cmd !== data.cmd) {
+                ctx.strokeStyle = isBlocked(data) ? 'rgb(224,108,117)' : 'rgb(10, 200, 10)';
+                let current_y = Math.max((15 - data.cmd) * 30, 0) + 10;
+                ctx.lineTo(current_x, current_y);
+            }
+
+            last_data = data;
+            last_x = current_x;
+        }
+    }
+    ctx.stroke();
+}
+
+export {
+    getMainRenderEl,
+    makeWaveCanvas,
+    removeWaveCanvas
+}
\ No newline at end of file
diff --git a/src/hook/utils.js b/src/hook/utils.js
index c2e09f2..13a69ad 100644
--- a/src/hook/utils.js
+++ b/src/hook/utils.js
@@ -15,7 +15,7 @@ async function getVcdStream() {
  * @returns {Promise<Uint8Array>}
  */
 async function readVcdFile() {
-    const response = await fetch('cpu.vcd');
+    const response = await fetch('test.vcd');
     const blob = await response.blob();
     const reader = new FileReader();
     return new Promise((resolve, reject) => {
@@ -40,6 +40,40 @@ function debounceWrapper(fn, delay) {
     }
 }
 
+
+function makeIconClass(mod) {
+    switch (mod.type) {
+        case 'module':      return 'icon-memory-chip';
+        case 'begin':       return 'icon-brackets';
+        case 'fork':        return 'icon-fork';
+        case 'function':    return 'icon-Function';
+        case 'task':        return 'icon-task-';
+
+        case 'event':       return 'icon-prevent';
+        case 'integer':     return 'icon-integer';
+        case 'parameter':   return 'icon-parameter';
+        case 'real':        return 'icon-R';
+        case 'realtime':    return 'icon-wave-square';
+        case 'reg':         return 'icon-register';
+        case 'supply0':     return 'icon-wave-square';
+        case 'supply1':     return 'icon-wave-square';
+        case 'time':        return 'icon-wave-square';
+        case 'tri':         return 'icon-wave-square';
+        case 'triand':      return 'icon-wave-square';
+        case 'trior':       return 'icon-wave-square';
+        case 'trireg':      return 'icon-wave-square';
+        case 'tri0':        return 'icon-wave-square';
+        case 'tri1':        return 'icon-wave-square';
+        case 'wand':        return 'icon-wave-square';
+        case 'wire':        return 'icon-wave-square';
+        case 'wor':         return 'icon-wave-square';
+        case 'string':      return 'icon-String';
+        default:
+            break;
+    }
+}
+
+
 /**
  * @param { string } searchString
  * @param {{
@@ -76,20 +110,27 @@ function makeSearchResultItem(searchString, module, searchScope, caseSensitivity
             }
 
             let htmlString = '';
+            let depString = '';
+            let currentCounts = 0;
             for (let i = deps.length - 1; i >= 0; -- i) {
                 const mod = deps[i];
-                if (mod.type === 'module') {
-                    htmlString += '<span class="iconfont icon-memory-chip"></span>&ensp;' + mod.name;
-                } else {
-                    htmlString += '<span class="iconfont icon-wave-square"></span>&ensp;' + mod.name;
-                }
+                // const displayName = mod.name.length > 6 ? mod.name.substring(0, 6) + '...' : mod.name;
+                const iconClass = makeIconClass(mod);
+                const iconText = `<span class="iconfont ${iconClass}"></span>&ensp;${mod.name}`;
+                
+                depString += iconText;
+                htmlString += iconText;
+
                 if (i > 0) {
+                    depString += '<br>';
                     htmlString += '<div class="dep-arrow"></div>';
                 }
             }
+
             return {
                 htmlString,
-                module
+                module,
+                depString
             };
         } 
     }
@@ -97,10 +138,49 @@ function makeSearchResultItem(searchString, module, searchScope, caseSensitivity
     return null;
 }
 
+/**
+ * 
+ * @param {string} timescale 
+ * @return {{
+ *  scale: number,
+ *  unit: string
+ * }}
+ */
+function handleTimeScale(timescale) {
+    const match = timescale.match(/^(\d+)(.*)$/);
+    if (match.length === 3) {
+        const scale = parseInt(match[1]);
+        const unit = match[2];
+        return { scale, unit };
+    } else {
+        console.log('Error: fail to parse timescale ' + timescale);
+        return { scale: null, unit: null };
+    }
+}
+
+const scopes = new Set(['begin', 'fork', 'function', 'module', 'task']);
+const variables = new Set(['event', 'integer', 'parameter', 'real', 'realtime', 'reg', 'supply0',
+                           'supply1', 'time', 'tri', 'triand', 'trior', 'trireg', 'tri0', 'tri1',
+                           'wand', 'wire', 'wor', 'string']);
+
+function isScope(wire) {
+    return scopes.has(wire.type);
+}
+
+function isVariable(wire) {
+    return variables.has(wire.type);
+}
+
 
 export {
     getVcdStream,
     readVcdFile,
     debounceWrapper,
-    makeSearchResultItem
+    makeSearchResultItem,
+    handleTimeScale,
+    isScope,
+    isVariable,
+    makeIconClass,
+    scopes,
+    variables
 };
\ No newline at end of file