Update README
This commit is contained in:
parent
6f9fe68c08
commit
4ba38f42db
@ -8,6 +8,7 @@ SystemVerilog parser library fully complient with [IEEE 1800-2017](https://stand
|
|||||||
## Tools using sv-parser
|
## Tools using sv-parser
|
||||||
|
|
||||||
* [svlint](https://github.com/dalance/svlint): SystemVerilog linter
|
* [svlint](https://github.com/dalance/svlint): SystemVerilog linter
|
||||||
|
* [svls](https://github.com/dalance/svls): SystemVerilog language server
|
||||||
|
|
||||||
## Usage
|
## Usage
|
||||||
|
|
||||||
|
Loading…
x
Reference in New Issue
Block a user