ppTests IEEE1800-2017_keyword_*

sv-parser-pp/src/preprocess.rs

@@ -964,6 +964,57 @@ mod tests {
         );
     } // }}}
 
+    #[test]
+    #[allow(non_snake_case)]
+    fn IEEE18002017_keywords_if2_13642005() { // {{{
+        let (ret, _) = preprocess(
+            testfile_path("IEEE18002017_keywords_if2_13642005.sv"),
+            &HashMap::new(),
+            &[] as &[String],
+            false,
+            false,
+        )
+        .unwrap();
+        assert_eq!(
+            ret.text(),
+            testfile_contents("expected/IEEE18002017_keywords_if2_13642005.sv")
+        );
+    } // }}}
+
+    #[test]
+    #[allow(non_snake_case)]
+    fn IEEE18002017_keywords_m2_13642001() { // {{{
+        let (ret, _) = preprocess(
+            testfile_path("IEEE18002017_keywords_m2_13642001.sv"),
+            &HashMap::new(),
+            &[] as &[String],
+            false,
+            false,
+        )
+        .unwrap();
+        assert_eq!(
+            ret.text(),
+            testfile_contents("expected/IEEE18002017_keywords_m2_13642001.sv")
+        );
+    } // }}}
+
+    #[test]
+    #[allow(non_snake_case)]
+    fn IEEE18002017_keywords_m2_18002005() { // {{{
+        let (ret, _) = preprocess(
+            testfile_path("IEEE18002017_keywords_m2_18002005.sv"),
+            &HashMap::new(),
+            &[] as &[String],
+            false,
+            false,
+        )
+        .unwrap();
+        assert_eq!(
+            ret.text(),
+            testfile_contents("expected/IEEE18002017_keywords_m2_18002005.sv")
+        );
+    } // }}}
+
     #[test]
     #[allow(non_snake_case)]
     fn IEEE18002017_macro_argument_expansion() { // {{{

sv-parser-pp/testcases/IEEE18002017_keywords_if2_13642005.sv

@@ -0,0 +1,8 @@
+
+`begin_keywords "1364-2005" // use IEEE Std 1364-2005 Verilog keywords
+interface if2 (); // ERROR: "interface" is not a keyword in 1364-2005
+  // This interface should pass the preprocessor, but not the main parser
+  // because the identifiers `interface` and `endinterface` are not reserved
+  // keywords in IEEE1364-2005.
+endinterface // ERROR: "endinterface" is not a keyword in 1364-2005
+`end_keywords

sv-parser-pp/testcases/IEEE18002017_keywords_m2_13642001.sv

@@ -0,0 +1,8 @@
+
+`begin_keywords "1364-2001"
+module m2 ();
+  // "logic" is NOT a reserved keyword in IEEE1364-2001.
+  // This module should pass both the preprocessor, AND the main parser.
+  reg [63:0] logic;
+endmodule
+`end_keywords

sv-parser-pp/testcases/IEEE18002017_keywords_m2_18002005.sv

@@ -0,0 +1,8 @@
+
+`begin_keywords "1800-2005"
+module m2 ();
+  // "logic" IS a reserved keyword in IEEE1800-2005.
+  // This module should pass both the preprocessor, but NOT the main parser.
+  reg [63:0] logic;
+endmodule
+`end_keywords

sv-parser-pp/testcases/expected/IEEE18002017_keywords_if2_13642005.sv

@@ -0,0 +1,8 @@
+
+`begin_keywords "1364-2005" // use IEEE Std 1364-2005 Verilog keywords
+interface if2 (); // ERROR: "interface" is not a keyword in 1364-2005
+  // This interface should pass the preprocessor, but not the main parser
+  // because the identifiers `interface` and `endinterface` are not reserved
+  // keywords in IEEE1364-2005.
+endinterface // ERROR: "endinterface" is not a keyword in 1364-2005
+`end_keywords

sv-parser-pp/testcases/expected/IEEE18002017_keywords_m2_13642001.sv

@@ -0,0 +1,8 @@
+
+`begin_keywords "1364-2001"
+module m2 ();
+  // "logic" is NOT a reserved keyword in IEEE1364-2001.
+  // This module should pass both the preprocessor, AND the main parser.
+  reg [63:0] logic;
+endmodule
+`end_keywords

sv-parser-pp/testcases/expected/IEEE18002017_keywords_m2_18002005.sv

@@ -0,0 +1,8 @@
+
+`begin_keywords "1800-2005"
+module m2 ();
+  // "logic" IS a reserved keyword in IEEE1800-2005.
+  // This module should pass both the preprocessor, but NOT the main parser.
+  reg [63:0] logic;
+endmodule
+`end_keywords