Add example
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README.md
71
README.md
@ -13,3 +13,74 @@ sv-parser = "0.1.0"
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```
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```
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## Example
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## Example
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```rust
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use std::collections::HashMap;
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use std::convert::TryInto;
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use std::env;
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use std::path::PathBuf;
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use sv_parser::{parse_sv, Locate, RefNode};
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fn main() {
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let args: Vec<String> = env::args().collect();
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// The path of SystemVerilog source file
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let path = PathBuf::from(&args[1]);
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// The list of defined macros
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let defines = HashMap::new();
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// The list of include paths
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let includes: Vec<PathBuf> = Vec::new();
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// Do parse
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let result = parse_sv(&path, &defines, &includes);
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if let Ok((syntax_tree, _)) = result {
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// SyntexTree is iterable
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for node in &syntax_tree {
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// The type of Each node is RefNode
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match node {
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RefNode::ModuleDeclarationNonansi(x) => {
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// The type of header is ModuleNonansiHeader
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let (ref header, _, _, _, _) = x.nodes;
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// The type of name is ModuleIdentifier
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let (_, _, _, ref name, _, _, _, _) = header.nodes;
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// Any type included in SyntaxTree can be convert RefNode by into()
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let id = get_identifier(name.into()).unwrap();
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// Original string can be got by SyntexTree::get_str(self, locate: &Locate)
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let id = syntax_tree.get_str(&id);
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println!("module: {}", id);
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}
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RefNode::ModuleDeclarationAnsi(x) => {
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let (ref header, _, _, _, _) = x.nodes;
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let (_, _, _, ref name, _, _, _, _) = header.nodes;
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let id = get_identifier(name.into()).unwrap();
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let id = syntax_tree.get_str(&id);
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println!("module: {}", id);
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}
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_ => (),
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}
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}
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} else {
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println!("Parse failed");
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}
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}
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fn get_identifier(node: RefNode) -> Option<Locate> {
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for n in node {
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match n {
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RefNode::SimpleIdentifier(x) => {
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let x: Locate = x.nodes.0.try_into().unwrap();
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return Some(x);
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}
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RefNode::EscapedIdentifier(x) => {
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let x: Locate = x.nodes.0.try_into().unwrap();
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return Some(x);
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}
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_ => (),
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}
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}
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None
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}
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```
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68
sv-parser/examples/module_list.rs
Normal file
68
sv-parser/examples/module_list.rs
Normal file
@ -0,0 +1,68 @@
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use std::collections::HashMap;
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use std::convert::TryInto;
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use std::env;
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use std::path::PathBuf;
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use sv_parser::{parse_sv, Locate, RefNode};
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fn main() {
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let args: Vec<String> = env::args().collect();
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// The path of SystemVerilog source file
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let path = PathBuf::from(&args[1]);
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// The list of defined macros
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let defines = HashMap::new();
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// The list of include paths
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let includes: Vec<PathBuf> = Vec::new();
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// Do parse
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let result = parse_sv(&path, &defines, &includes);
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if let Ok((syntax_tree, _)) = result {
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// SyntexTree is iterable
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for node in &syntax_tree {
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// The type of Each node is RefNode
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match node {
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RefNode::ModuleDeclarationNonansi(x) => {
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// The type of header is ModuleNonansiHeader
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let (ref header, _, _, _, _) = x.nodes;
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// The type of name is ModuleIdentifier
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let (_, _, _, ref name, _, _, _, _) = header.nodes;
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// Any type included in SyntaxTree can be convert RefNode by into()
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let id = get_identifier(name.into()).unwrap();
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// Original string can be got by SyntexTree::get_str(self, locate: &Locate)
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let id = syntax_tree.get_str(&id);
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println!("module: {}", id);
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}
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RefNode::ModuleDeclarationAnsi(x) => {
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let (ref header, _, _, _, _) = x.nodes;
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let (_, _, _, ref name, _, _, _, _) = header.nodes;
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let id = get_identifier(name.into()).unwrap();
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let id = syntax_tree.get_str(&id);
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println!("module: {}", id);
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}
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_ => (),
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}
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}
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} else {
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println!("Parse failed");
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}
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}
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fn get_identifier(node: RefNode) -> Option<Locate> {
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for n in node {
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match n {
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RefNode::SimpleIdentifier(x) => {
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let x: Locate = x.nodes.0.try_into().unwrap();
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return Some(x);
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}
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RefNode::EscapedIdentifier(x) => {
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let x: Locate = x.nodes.0.try_into().unwrap();
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return Some(x);
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}
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_ => (),
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}
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}
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None
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}
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