diff --git a/sv-parser-parser/src/source_text/system_verilog_source_text.rs b/sv-parser-parser/src/source_text/system_verilog_source_text.rs
index d8a4d97..c1b6c29 100644
--- a/sv-parser-parser/src/source_text/system_verilog_source_text.rs
+++ b/sv-parser-parser/src/source_text/system_verilog_source_text.rs
@@ -50,6 +50,9 @@ pub(crate) fn description(s: Span) -> IResult<Span, Description> {
         map(config_declaration, |x| {
             Description::ConfigDeclaration(Box::new(x))
         }),
+        map(class_declaration, |x| {
+            Description::ClassDeclaration(Box::new(x))
+        }),
     ))(s)
 }
 
diff --git a/sv-parser-pp/src/preprocess.rs b/sv-parser-pp/src/preprocess.rs
index 849527f..3545535 100644
--- a/sv-parser-pp/src/preprocess.rs
+++ b/sv-parser-pp/src/preprocess.rs
@@ -1339,4 +1339,36 @@ endmodule
         );
         assert_eq!(ret.origin(80).unwrap().1, 60);
     }
+
+
+    #[test]
+    fn test21() {
+        let include_paths = [get_testcase("")];
+        let (ret, _) = preprocess(
+            get_testcase("test21.sv"),
+            &HashMap::new(),
+            &include_paths,
+            false,
+            false,
+        )
+        .unwrap();
+    }
+
+    #[test]
+    fn test22() {
+        let include_paths = [get_testcase("")];
+        let (ret, _) = preprocess(
+            get_testcase("test22.sv"),
+            &HashMap::new(),
+            &include_paths,
+            false,
+            false,
+        )
+        .unwrap();
+    }
+
+
+
+
+
 }
diff --git a/sv-parser-pp/testcases/test21.sv b/sv-parser-pp/testcases/test21.sv
new file mode 100644
index 0000000..cfa2032
--- /dev/null
+++ b/sv-parser-pp/testcases/test21.sv
@@ -0,0 +1,7 @@
+class test21 extends base_class /* base class*/;
+	int a;
+	int b;
+	function int funcname();
+		return 2;
+	endfunction : funcname
+endclass : test21
\ No newline at end of file
diff --git a/sv-parser-pp/testcases/test22.sv b/sv-parser-pp/testcases/test22.sv
new file mode 100644
index 0000000..34266de
--- /dev/null
+++ b/sv-parser-pp/testcases/test22.sv
@@ -0,0 +1,18 @@
+// it's for test
+
+`ifndef ABCD
+`define ABCD
+
+package my_package;
+
+	import uvm_pkg::*;
+	import internal_pkg::*;
+
+	// include 
+	`include "test21.sv"
+
+	
+endpackage : my_package
+
+
+`endif
\ No newline at end of file
diff --git a/sv-parser-syntaxtree/src/source_text/system_verilog_source_text.rs b/sv-parser-syntaxtree/src/source_text/system_verilog_source_text.rs
index e66a47f..9af92ef 100644
--- a/sv-parser-syntaxtree/src/source_text/system_verilog_source_text.rs
+++ b/sv-parser-syntaxtree/src/source_text/system_verilog_source_text.rs
@@ -23,6 +23,7 @@ pub enum Description {
     PackageItem(Box<DescriptionPackageItem>),
     BindDirective(Box<DescriptionBindDirective>),
     ConfigDeclaration(Box<ConfigDeclaration>),
+    ClassDeclaration(Box<ClassDeclaration>),
 }
 
 #[derive(Clone, Debug, PartialEq, Node)]