ppTest Move expected pp output to separate files.

This commit is contained in:
damc 2022-07-20 13:28:58 +02:00
parent 1a77bbb75b
commit 9a254105c6
20 changed files with 176 additions and 165 deletions

View File

@ -860,6 +860,17 @@ mod tests {
) )
} }
fn testfile_contents(s: &str) -> String {
let path: String = testfile_path(s);
let file = File::open(path).unwrap();
let mut buf_reader = BufReader::new(file);
let mut contents = String::new();
buf_reader.read_to_string(&mut contents).unwrap();
contents
}
#[test] #[test]
fn ifdef_undefined() { fn ifdef_undefined() {
let (ret, _) = preprocess( let (ret, _) = preprocess(
@ -872,14 +883,7 @@ mod tests {
.unwrap(); .unwrap();
assert_eq!( assert_eq!(
ret.text(), ret.text(),
r##"module and_op (a, b, c); testfile_contents("expected/ifdef_undefined")
output a;
input b, c;
and a1 (a,b,c);
endmodule
"##
); );
assert_eq!( assert_eq!(
ret.origin(10).unwrap().0, ret.origin(10).unwrap().0,
@ -904,14 +908,7 @@ endmodule
.unwrap(); .unwrap();
assert_eq!( assert_eq!(
ret.text(), ret.text(),
r##"module and_op (a, b, c); testfile_contents("expected/ifdef_predefined")
output a;
input b, c;
wire a = b & c;
endmodule
"##
) )
} }
@ -928,15 +925,7 @@ endmodule
.unwrap(); .unwrap();
assert_eq!( assert_eq!(
ret.text(), ret.text(),
r##"module and_op (a, b, c); testfile_contents("expected/include_origin")
output a;
input b, c;
and a1 (a,b,c);
endmodule
"##
); );
assert_eq!( assert_eq!(
ret.origin(10).unwrap().0, ret.origin(10).unwrap().0,
@ -968,10 +957,7 @@ endmodule
.unwrap(); .unwrap();
assert_eq!( assert_eq!(
ret.text(), ret.text(),
r##"module and_op (a, b, c); testfile_contents("expected/ignore_include")
endmodule
"##
); );
} }
@ -987,16 +973,7 @@ endmodule
.unwrap(); .unwrap();
assert_eq!( assert_eq!(
ret.text(), ret.text(),
r##"`define connect(NAME, INDEX = 0) \ testfile_contents("expected/macro_parameters_defaultvalue")
assign NAME``_``INDEX``__x = NAME[INDEX].x; \
assign NAME``_``INDEX``__y = NAME[INDEX].y;
module a ();
assign a_0__x = a[0].x;
assign a_0__y = a[0].y; assign a_1__x = a[1].x;
assign a_1__y = a[1].y; endmodule
"##
); );
} }
@ -1012,24 +989,7 @@ module a ();
.unwrap(); .unwrap();
assert_eq!( assert_eq!(
ret.text(), ret.text(),
r##"`define disp(clk, exp, msg) \ testfile_contents("expected/macro_parameters_multiline")
always @(posedge clk) begin \
if (!(exp)) begin \
$display msg; \
end \
end \
module a ();
always @(posedge clk) begin
if (!(!(a[i].b && c[i]))) begin
$display ("xxx(()[]]{}}}", a[i].b, c[i]);
end
end
;
endmodule
"##
); );
} }
@ -1045,17 +1005,7 @@ endmodule
.unwrap(); .unwrap();
assert_eq!( assert_eq!(
ret.text(), ret.text(),
r##"module a; testfile_contents("expected/macro_parameters_dependent")
`define HI Hello
`define LO "`HI, world"
`define H(x) "Hello, x"
initial begin
$display("`HI, world");
$display("`HI, world" );
$display("Hello, x" );
end
endmodule
"##
); );
} }
@ -1071,14 +1021,7 @@ endmodule
.unwrap(); .unwrap();
assert_eq!( assert_eq!(
ret.text(), ret.text(),
r##"`define msg(x,y) `"x: `\`"y`\`"`" testfile_contents("expected/macro_string_literal")
module a;
initial begin
$display("left side: \"right side\"" );
end
endmodule
"##
); );
} }
@ -1145,13 +1088,7 @@ endmodule
.unwrap(); .unwrap();
assert_eq!( assert_eq!(
ret.text(), ret.text(),
r##"module a; testfile_contents("expected/macro_LINE")
initial begin
if (3 == 0) begin
end
end
endmodule
"##
); );
} }
@ -1167,10 +1104,7 @@ endmodule
.unwrap(); .unwrap();
assert_eq!( assert_eq!(
ret.text(), ret.text(),
r##"module a; testfile_contents("expected/escaped_identifier")
reg \`~!-_=+\|[]{};:'"",./<>? ;
endmodule
"##
); );
} }
@ -1186,10 +1120,7 @@ endmodule
.unwrap(); .unwrap();
assert_eq!( assert_eq!(
ret.text(), ret.text(),
r##"`define NAME 42 // Comment testfile_contents("expected/macro_with_comment")
interface foo #(WIDTH = 42 ) ();
endinterface
"##
); );
} }
@ -1205,12 +1136,7 @@ endinterface
.unwrap(); .unwrap();
assert_eq!( assert_eq!(
ret.text(), ret.text(),
r##"module A; testfile_contents("expected/ifdef_nested")
wire a = 1'b0;
endmodule
"##
); );
} }
@ -1226,11 +1152,7 @@ endmodule
.unwrap(); .unwrap();
assert_eq!( assert_eq!(
ret.text(), ret.text(),
r##"`define MOD_INST u_mysubmod testfile_contents("expected/macro_usage_sameline")
module mymod;
mysubmod u_mysubmod() ;
endmodule
"##
); );
} }
@ -1246,17 +1168,7 @@ endmodule
.unwrap(); .unwrap();
assert_eq!( assert_eq!(
ret.text(), ret.text(),
r##"module a; testfile_contents("expected/macro_backslash")
`define HELLO0 "HELLO"
`define \HELLO1 "HELLO"
initial begin
$display("HELLO" );
$display("HELLO" );
$display("HELLO" );
$display("HELLO" );
end
endmodule
"##
); );
} }
@ -1272,15 +1184,7 @@ endmodule
.unwrap(); .unwrap();
assert_eq!( assert_eq!(
ret.text(), ret.text(),
r##"`define A \ testfile_contents("expected/macro_multiline")
initial begin // comment \
end
module test();
initial begin
end endmodule
"##
); );
} }
@ -1296,12 +1200,7 @@ initial begin
.unwrap(); .unwrap();
assert_eq!( assert_eq!(
ret.text(), ret.text(),
r##"// pragma translate_off testfile_contents("expected/ifndef_undefined")
module A;
endmodule
// pragma translate_on
"##
); );
} }
@ -1318,15 +1217,7 @@ endmodule
.unwrap(); .unwrap();
assert_eq!( assert_eq!(
ret.text(), ret.text(),
r##"module and_op (a, b, c); testfile_contents("expected/whitespace_include_with_comment")
output a;
input b, c;
and a1 (a,b,c);
// comment
endmodule
"##
); );
assert_eq!( assert_eq!(
ret.origin(10).unwrap().0, ret.origin(10).unwrap().0,
@ -1358,16 +1249,7 @@ endmodule
.unwrap(); .unwrap();
assert_eq!( assert_eq!(
ret.text(), ret.text(),
r##"module and_op (a, b, c); testfile_contents("expected/whitespace_include")
// a
output a;
input b, c;
and a1 (a,b,c);
endmodule
"##
); );
assert_eq!( assert_eq!(
ret.origin(10).unwrap().0, ret.origin(10).unwrap().0,
@ -1401,24 +1283,7 @@ endmodule
.unwrap(); .unwrap();
assert_eq!( assert_eq!(
ret.text(), ret.text(),
r##"//top testfile_contents("expected/whitespace_directives")
`resetall
`timescale 10 us / 100 ns
`default_nettype wire
//first
`default_nettype none//middle
//last
`unconnected_drive pull0
`unconnected_drive pull1
`nounconnected_drive
`celldefine
`endcelldefine
`pragma foo
`pragma foo bar
`line 5 "foo" 0
`begin_keywords "1800-2017"
`end_keywords
"##
); );
} }
} }

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@ -0,0 +1,3 @@
module a;
reg \`~!-_=+\|[]{};:'"",./<>? ;
endmodule

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@ -0,0 +1,5 @@
module A;
wire a = 1'b0;
endmodule

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@ -0,0 +1,7 @@
module and_op (a, b, c);
output a;
input b, c;
wire a = b & c;
endmodule

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@ -0,0 +1,7 @@
module and_op (a, b, c);
output a;
input b, c;
and a1 (a,b,c);
endmodule

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@ -0,0 +1,5 @@
// pragma translate_off
module A;
endmodule
// pragma translate_on

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@ -0,0 +1,3 @@
module and_op (a, b, c);
endmodule

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@ -0,0 +1,8 @@
module and_op (a, b, c);
output a;
input b, c;
and a1 (a,b,c);
endmodule

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@ -0,0 +1,6 @@
module a;
initial begin
if (3 == 0) begin
end
end
endmodule

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@ -0,0 +1,10 @@
module a;
`define HELLO0 "HELLO"
`define \HELLO1 "HELLO"
initial begin
$display("HELLO" );
$display("HELLO" );
$display("HELLO" );
$display("HELLO" );
end
endmodule

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@ -0,0 +1,8 @@
`define A \
initial begin // comment \
end
module test();
initial begin
end endmodule

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@ -0,0 +1,9 @@
`define connect(NAME, INDEX = 0) \
assign NAME``_``INDEX``__x = NAME[INDEX].x; \
assign NAME``_``INDEX``__y = NAME[INDEX].y;
module a ();
assign a_0__x = a[0].x;
assign a_0__y = a[0].y; assign a_1__x = a[1].x;
assign a_1__y = a[1].y; endmodule

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@ -0,0 +1,10 @@
module a;
`define HI Hello
`define LO "`HI, world"
`define H(x) "Hello, x"
initial begin
$display("`HI, world");
$display("`HI, world" );
$display("Hello, x" );
end
endmodule

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@ -0,0 +1,17 @@
`define disp(clk, exp, msg) \
always @(posedge clk) begin \
if (!(exp)) begin \
$display msg; \
end \
end \
module a ();
always @(posedge clk) begin
if (!(!(a[i].b && c[i]))) begin
$display ("xxx(()[]]{}}}", a[i].b, c[i]);
end
end
;
endmodule

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@ -0,0 +1,7 @@
`define msg(x,y) `"x: `\`"y`\`"`"
module a;
initial begin
$display("left side: \"right side\"" );
end
endmodule

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@ -0,0 +1,4 @@
`define MOD_INST u_mysubmod
module mymod;
mysubmod u_mysubmod() ;
endmodule

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@ -0,0 +1,3 @@
`define NAME 42 // Comment
interface foo #(WIDTH = 42 ) ();
endinterface

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@ -0,0 +1,17 @@
//top
`resetall
`timescale 10 us / 100 ns
`default_nettype wire
//first
`default_nettype none//middle
//last
`unconnected_drive pull0
`unconnected_drive pull1
`nounconnected_drive
`celldefine
`endcelldefine
`pragma foo
`pragma foo bar
`line 5 "foo" 0
`begin_keywords "1800-2017"
`end_keywords

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@ -0,0 +1,9 @@
module and_op (a, b, c);
// a
output a;
input b, c;
and a1 (a,b,c);
endmodule

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@ -0,0 +1,8 @@
module and_op (a, b, c);
output a;
input b, c;
and a1 (a,b,c);
// comment
endmodule