diff --git a/CHANGELOG.md b/CHANGELOG.md index 88c72b2..3cfa2c2 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -2,6 +2,7 @@ ## [Unreleased](https://github.com/dalance/sv-parser/compare/v0.4.19...Unreleased) - ReleaseDate +* [Fixed] parser priority about specify * [Fixed] escaped_ideitifier including `` ` `` * [Fixed] time_literal spacing diff --git a/sv-parser-parser/src/specify_section/system_timing_check_command_arguments.rs b/sv-parser-parser/src/specify_section/system_timing_check_command_arguments.rs index 51f6c3c..90c1e67 100644 --- a/sv-parser-parser/src/specify_section/system_timing_check_command_arguments.rs +++ b/sv-parser-parser/src/specify_section/system_timing_check_command_arguments.rs @@ -27,10 +27,10 @@ pub(crate) fn data_event(s: Span) -> IResult { #[packrat_parser] pub(crate) fn delayed_data(s: Span) -> IResult { alt(( + delayed_data_with_mintypmax, map(terminal_identifier, |x| { DelayedData::TerminalIdentifier(Box::new(x)) }), - delayed_data_with_mintypmax, ))(s) } @@ -49,10 +49,10 @@ pub(crate) fn delayed_data_with_mintypmax(s: Span) -> IResult #[packrat_parser] pub(crate) fn delayed_reference(s: Span) -> IResult { alt(( + delayed_reference_with_mintypmax, map(terminal_identifier, |x| { DelayedReference::TerminalIdentifier(Box::new(x)) }), - delayed_reference_with_mintypmax, ))(s) } diff --git a/sv-parser-parser/src/specify_section/system_timing_check_event_definitions.rs b/sv-parser-parser/src/specify_section/system_timing_check_event_definitions.rs index 566fea6..6dcdda8 100644 --- a/sv-parser-parser/src/specify_section/system_timing_check_event_definitions.rs +++ b/sv-parser-parser/src/specify_section/system_timing_check_event_definitions.rs @@ -30,12 +30,12 @@ pub(crate) fn timing_check_event_control(s: Span) -> IResult? ; endmodule"##, Ok((_, _)) ); + test!( + source_text, + r##"module test(); specify $setuphold(posedge A &&& B, BL_0 , 0, 0, C,,,D, BL_X[0]); endspecify endmodule"##, + Ok((_, _)) + ); + test!( + source_text, + r##"module test(); specify $setup(posedge CSB, edge[01,0x,x1,1x] CL, tps, a); endspecify endmodule"##, + Ok((_, _)) + ); } }