18 lines
320 B
Systemverilog
18 lines
320 B
Systemverilog
`define disp(clk, exp, msg) \
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always @(posedge clk) begin \
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if (!(exp)) begin \
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$display msg; \
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end \
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end \
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module a ();
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always @(posedge clk) begin
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if (!(!(a[i].b && c[i]))) begin
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$display ("xxx(()[]]{}}}", a[i].b, c[i]);
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end
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end
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;
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endmodule
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