24 lines
724 B
Systemverilog
24 lines
724 B
Systemverilog
// Macro with parameters with usage spread over multiple lines.
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// Final line of macro is line14.
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// Argument value `clk` is equal to its name.
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// Argument value of exp contains matching brackets and parentheses.
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// Bracketed value of msg is required to avoid being parsed as a parameterized
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// macro instead of argumnts to $display.
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// NOTE: Trailing whitespace is not exercised here, i.e. continuations
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// immediately follow non-whitespace.
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`define disp(clk, exp, msg)\
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always @(posedge clk)\
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if (exp) begin\
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$display msg;\
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end\
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module M ();
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always @(posedge clk)
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if (!(a[i].b && c[i])) begin
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$display ("xxx(()[]]{}}}", a[i].b, c[i]);
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end
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; // NOTE: Semi-colon is unnecessary.
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endmodule
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