31 lines
718 B
Systemverilog
31 lines
718 B
Systemverilog
// __LINE__ = `__LINE__
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`ifdef __LINE__
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// This block SHOULD be emitted from the preprocessor.
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`elsif UNDEFINED
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// NOT emitted.
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`endif
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`ifndef __LINE__
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// This block should NOT be emitted from the preprocessor.
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// However, following (conditional) definition should make it through the
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// preprocessor parsing stage without error.
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`define __LINE__ -1
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`elsif UNDEFINED
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// Emitted instead.
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`endif
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// The following define should have no effect.
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`define __LINE__ -2
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// The following undef should have no effect.
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`undef __LINE__
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module M;
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initial
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if (`__LINE__ == 28) // Should be "26 == 28".
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$display("PASS");
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else if (`__LINE__ == 28) // Should be "28 == 28".
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$display("FAIL");
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endmodule
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