16 lines
387 B
Systemverilog
16 lines
387 B
Systemverilog
/* IEEE1800-2017 Clause 22.5.1 page 677
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* NOTE: Illegal cases are not included in this testcase.
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*/
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`define D(x,y) initial $display("start", x , y, "end");
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module m;
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initial begin
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$display("start", "msg1" , "msg2", "end");
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$display("start", " msg1" , , "end");
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$display("start", , "msg2 ", "end");
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$display("start", , , "end");
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$display("start", , , "end");
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end
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endmodule
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