11 lines
186 B
Systemverilog
11 lines
186 B
Systemverilog
`define connect(NAME, INDEX = 0) \
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assign NAME``_``INDEX``__x = NAME[INDEX].x; \
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assign NAME``_``INDEX``__y = NAME[INDEX].y;
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module a ();
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`connect(a)
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`connect(a, 1)
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endmodule
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