18 lines
199 B
Systemverilog
18 lines
199 B
Systemverilog
// it's for test
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`ifndef ABCD
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`define ABCD
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package my_package;
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import uvm_pkg::*;
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import internal_pkg::*;
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// include
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`include "test21.sv"
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endpackage : my_package
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`endif |