da6157952e
- Illustration of https://github.com/dalance/svlint/issues/77 - That's the same as https://github.com/dalance/sv-parser/issues/48 - A,B show what doesn't work, vaguely defined on page 680. - C,D show what does work, using example on page 680.
10 lines
180 B
Systemverilog
10 lines
180 B
Systemverilog
// Based on last example of IEEE1800-2017 Clause 22.5.1, page 680.
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`define APPEND_SVH(path) `"path.svh`"
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module and_op (a, b, c);
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output a;
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input b, c;
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and a1 (a,b,c);
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endmodule
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