26 lines
543 B
Systemverilog
26 lines
543 B
Systemverilog
/* IEEE1800-2017 Clause 22.5.1 page 678
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* NOTE: Illegal cases are not included in this testcase.
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* NOTE: Use of EMPTY is suggested on page 679
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*/
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`define MACRO1(a=5,b="B",c) $display(a,,b,,c);
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`define MACRO2(a=5, b, c="C") $display(a,,b,,c);
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`define MACRO3(a=5, b=0, c="C") $display(a,,b,,c);
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`define EMPTY
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module m;
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initial begin
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$display(5,,2,,3);
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$display(1,,"B",,3);
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$display(5,,2,,);
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$display(1,,,,3);
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$display(5,,2,,"C");
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$display(5,,2,,"C");
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$display(1,,0,,"C");
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$display(5,,0,,"C");
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$display(,,,,);
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end
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endmodule
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