15 lines
170 B
Systemverilog
15 lines
170 B
Systemverilog
module A;
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`ifdef OPT_1
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//wire a = 1'b1;
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`else
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wire a = 1'b0;
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`endif
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`ifdef DEBUG
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`ifdef OPT_2
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//wire b = 1'b1;
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`else
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wire b = 1'b0;
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`endif
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`endif
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endmodule
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