4 lines
52 B
Systemverilog
4 lines
52 B
Systemverilog
module a;
|
|
reg \`~!-_=+\|[]{};:'"",./<>? ;
|
|
endmodule
|
module a;
|
|
reg \`~!-_=+\|[]{};:'"",./<>? ;
|
|
endmodule
|