17 lines
248 B
Systemverilog
17 lines
248 B
Systemverilog
`define disp(clk, exp, msg) \
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always @(posedge clk) begin \
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if (!(exp)) begin \
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$display msg; \
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end \
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end \
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module a ();
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`disp(
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clk,
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!(a[i].b && c[i]),
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("xxx(()[]]{}}}", a[i].b, c[i])
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);
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endmodule
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