14 lines
820 B
Systemverilog
14 lines
820 B
Systemverilog
// IEEE1800-2017 Clause 22.10
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// The directives `celldefine and `endcelldefine tag modules as cell modules.
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// Cells are used by certain PLI routines and may be useful for applications
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// such as delay calculations. It is advisable to pair each `celldefine with an
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// `endcelldefine, but it is not required. The latest occurrence of either
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// directive in the source controls whether modules are tagged as cell modules.
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// More than one of these pairs may appear in a single source description.
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// These directives may appear anywhere in the source description, but it is
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// recommended that the directives be specified outside any design elements.
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// The `resetall directive includes the effects of a `endcelldefine directive.
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`celldefine
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`endcelldefine
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// This file should be emitted from the preprocessor unchanged.
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