35 lines
1.9 KiB
Systemverilog
35 lines
1.9 KiB
Systemverilog
// IEEE1800-2017 Clause 22.12
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// The `line compiler directive can be used to specify the original source code
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// line number and file name.
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// This allows the location in the original file to be maintained if another
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// process modifies the source. After the new line number and file name are
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// specified, the compiler can correctly refer to the original source location.
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// However, a tool is not required to produce `line directives. These
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// directives are not intended to be inserted manually into the code, although
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// they can be.
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// The compiler shall maintain the current line number and file name of the
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// file being compiled. The `line directive shall set the line number and file
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// name of the following line to those specified in the directive.
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// The directive can be specified anywhere within the SystemVerilog source
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// description. However, only white space may appear on the same line as the
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// `line directive. Comments are not allowed on the same line as a `line
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// directive. All parameters in the `line directive are required. The results
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// of this directive are not affected by the `resetall directive.
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//
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// The number parameter shall be a positive integer that specifies the new line
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// number of the following text line. The filename parameter shall be a string
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// literal that is treated as the new name of the file. The filename can also
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// be a full or relative path name. The level parameter shall be 0, 1, or 2.
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// The value 1 indicates that the following line is the first line after an
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// include file has been entered. The value 2 indicates that the following
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// line is the first line after an include file has been exited. The value
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// 0 indicates any other line.
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`line 3 "orig.v" 2
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// This line is line 3 of orig.v after exiting include file
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`line 999 "foo.sv" 2
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`line 888 "foo.sv" 1
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`line 777 "foo.sv" 0
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// This file should be emitted from the preprocessor unchanged.
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