9 lines
217 B
Systemverilog
9 lines
217 B
Systemverilog
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`begin_keywords "1800-2005"
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module m2 ();
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// "logic" IS a reserved keyword in IEEE1800-2005.
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// This module should pass both the preprocessor, but NOT the main parser.
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reg [63:0] logic;
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endmodule
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`end_keywords
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