11 lines
156 B
Systemverilog
11 lines
156 B
Systemverilog
/* IEEE1800-2017 Clause 22.5.1 page 680
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*/
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`define msg(x,y) `"x: `\`"y`\`"`"
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module a;
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initial begin
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$display("left side: \"right side\"");
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end
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endmodule
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