310 lines
15 KiB
VHDL
310 lines
15 KiB
VHDL
-- -----------------------------------------------------------------
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--
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-- Copyright 2019 IEEE P1076 WG Authors
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--
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-- See the LICENSE file distributed with this work for copyright and
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-- licensing information and the AUTHORS file.
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--
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-- This file to you under the Apache License, Version 2.0 (the "License").
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-- You may obtain a copy of the License at
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--
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-- http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
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-- implied. See the License for the specific language governing
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-- permissions and limitations under the License.
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--
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-- Title : Standard multivalue logic package
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-- : (STD_LOGIC_1164 package declaration)
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-- :
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-- Library : This package shall be compiled into a library
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-- : symbolically named IEEE.
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-- :
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-- Developers: IEEE model standards group (PAR 1164),
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-- : Accellera VHDL-TC, and IEEE P1076 Working Group
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-- :
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-- Purpose : This packages defines a standard for designers
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-- : to use in describing the interconnection data types
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-- : used in vhdl modeling.
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-- :
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-- Limitation: The logic system defined in this package may
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-- : be insufficient for modeling switched transistors,
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-- : since such a requirement is out of the scope of this
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-- : effort. Furthermore, mathematics, primitives,
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-- : timing standards, etc. are considered orthogonal
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-- : issues as it relates to this package and are therefore
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-- : beyond the scope of this effort.
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-- :
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-- Note : This package may be modified to include additional data
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-- : required by tools, but it must in no way change the
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-- : external interfaces or simulation behavior of the
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-- : description. It is permissible to add comments and/or
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-- : attributes to the package declarations, but not to change
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-- : or delete any original lines of the package declaration.
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-- : The package body may be changed only in accordance with
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-- : the terms of Clause 16 of this standard.
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-- :
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-- --------------------------------------------------------------------
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-- $Revision: 1228 $
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-- $Date: 2008-04-30 10:04:53 +0930 (Wed, 30 Apr 2008) $
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-- --------------------------------------------------------------------
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use STD.TEXTIO.all;
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package std_logic_1164 is
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-------------------------------------------------------------------
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-- logic state system (unresolved)
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-------------------------------------------------------------------
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type STD_ULOGIC is ( 'U', -- Uninitialized
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'X', -- Forcing Unknown
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'0', -- Forcing 0
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'1', -- Forcing 1
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'Z', -- High Impedance
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'W', -- Weak Unknown
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'L', -- Weak 0
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'H', -- Weak 1
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'-' -- Don't care
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);
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-------------------------------------------------------------------
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-- unconstrained array of std_ulogic for use with the resolution function
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-- and for use in declaring signal arrays of unresolved elements
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-------------------------------------------------------------------
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type STD_ULOGIC_VECTOR is array (NATURAL range <>) of STD_ULOGIC;
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-------------------------------------------------------------------
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-- resolution function
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-------------------------------------------------------------------
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function resolved (s : STD_ULOGIC_VECTOR) return STD_ULOGIC;
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-------------------------------------------------------------------
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-- logic state system (resolved)
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-------------------------------------------------------------------
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subtype STD_LOGIC is resolved STD_ULOGIC;
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-------------------------------------------------------------------
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-- unconstrained array of resolved std_ulogic for use in declaring
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-- signal arrays of resolved elements
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-------------------------------------------------------------------
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subtype STD_LOGIC_VECTOR is (resolved) STD_ULOGIC_VECTOR;
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-------------------------------------------------------------------
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-- common subtypes
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-------------------------------------------------------------------
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subtype X01 is resolved STD_ULOGIC range 'X' to '1'; -- ('X','0','1')
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subtype X01Z is resolved STD_ULOGIC range 'X' to 'Z'; -- ('X','0','1','Z')
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subtype UX01 is resolved STD_ULOGIC range 'U' to '1'; -- ('U','X','0','1')
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subtype UX01Z is resolved STD_ULOGIC range 'U' to 'Z'; -- ('U','X','0','1','Z')
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-------------------------------------------------------------------
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-- overloaded logical operators
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-------------------------------------------------------------------
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function "and" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01;
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function "nand" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01;
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function "or" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01;
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function "nor" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01;
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function "xor" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01;
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function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01;
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function "not" (l : STD_ULOGIC) return UX01;
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-------------------------------------------------------------------
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-- vectorized overloaded logical operators
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-------------------------------------------------------------------
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function "and" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
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function "nand" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
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function "or" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
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function "nor" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
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function "xor" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
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function "xnor" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
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function "not" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
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function "and" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
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function "and" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
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function "nand" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
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function "nand" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
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function "or" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
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function "or" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
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function "nor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
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function "nor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
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function "xor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
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function "xor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
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function "xnor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
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function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
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function "and" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
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function "nand" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
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function "or" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
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function "nor" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
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function "xor" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
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function "xnor" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
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-------------------------------------------------------------------
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-- shift operators
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-------------------------------------------------------------------
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function "sll" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
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function "srl" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
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function "rol" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
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function "ror" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
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-------------------------------------------------------------------
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-- conversion functions
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-------------------------------------------------------------------
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function To_bit (s : STD_ULOGIC; xmap : BIT := '0') return BIT;
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function To_bitvector (s : STD_ULOGIC_VECTOR; xmap : BIT := '0') return BIT_VECTOR;
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function To_StdULogic (b : BIT) return STD_ULOGIC;
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function To_StdLogicVector (b : BIT_VECTOR) return STD_LOGIC_VECTOR;
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function To_StdLogicVector (s : STD_ULOGIC_VECTOR) return STD_LOGIC_VECTOR;
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function To_StdULogicVector (b : BIT_VECTOR) return STD_ULOGIC_VECTOR;
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function To_StdULogicVector (s : STD_LOGIC_VECTOR) return STD_ULOGIC_VECTOR;
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alias To_Bit_Vector is
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To_bitvector[STD_ULOGIC_VECTOR, BIT return BIT_VECTOR];
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alias To_BV is
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To_bitvector[STD_ULOGIC_VECTOR, BIT return BIT_VECTOR];
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alias To_Std_Logic_Vector is
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To_StdLogicVector[BIT_VECTOR return STD_LOGIC_VECTOR];
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alias To_SLV is
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To_StdLogicVector[BIT_VECTOR return STD_LOGIC_VECTOR];
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alias To_Std_Logic_Vector is
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To_StdLogicVector[STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR];
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alias To_SLV is
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To_StdLogicVector[STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR];
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alias To_Std_ULogic_Vector is
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To_StdULogicVector[BIT_VECTOR return STD_ULOGIC_VECTOR];
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alias To_SULV is
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To_StdULogicVector[BIT_VECTOR return STD_ULOGIC_VECTOR];
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alias To_Std_ULogic_Vector is
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To_StdULogicVector[STD_LOGIC_VECTOR return STD_ULOGIC_VECTOR];
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alias To_SULV is
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To_StdULogicVector[STD_LOGIC_VECTOR return STD_ULOGIC_VECTOR];
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-------------------------------------------------------------------
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-- strength strippers and type convertors
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-------------------------------------------------------------------
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function TO_01 (s : STD_ULOGIC_VECTOR; xmap : STD_ULOGIC := '0')
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return STD_ULOGIC_VECTOR;
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function TO_01 (s : STD_ULOGIC; xmap : STD_ULOGIC := '0')
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return STD_ULOGIC;
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function TO_01 (s : BIT_VECTOR; xmap : STD_ULOGIC := '0')
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return STD_ULOGIC_VECTOR;
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function TO_01 (s : BIT; xmap : STD_ULOGIC := '0')
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return STD_ULOGIC;
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function To_X01 (s : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
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function To_X01 (s : STD_ULOGIC) return X01;
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function To_X01 (b : BIT_VECTOR) return STD_ULOGIC_VECTOR;
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function To_X01 (b : BIT) return X01;
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function To_X01Z (s : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
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function To_X01Z (s : STD_ULOGIC) return X01Z;
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function To_X01Z (b : BIT_VECTOR) return STD_ULOGIC_VECTOR;
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function To_X01Z (b : BIT) return X01Z;
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function To_UX01 (s : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
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function To_UX01 (s : STD_ULOGIC) return UX01;
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function To_UX01 (b : BIT_VECTOR) return STD_ULOGIC_VECTOR;
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function To_UX01 (b : BIT) return UX01;
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function "??" (l : STD_ULOGIC) return BOOLEAN;
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-------------------------------------------------------------------
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-- edge detection
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-------------------------------------------------------------------
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function rising_edge (signal s : STD_ULOGIC) return BOOLEAN;
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function falling_edge (signal s : STD_ULOGIC) return BOOLEAN;
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-------------------------------------------------------------------
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-- object contains an unknown
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-------------------------------------------------------------------
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function Is_X (s : STD_ULOGIC_VECTOR) return BOOLEAN;
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function Is_X (s : STD_ULOGIC) return BOOLEAN;
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-------------------------------------------------------------------
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-- matching relational operators
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-------------------------------------------------------------------
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-- the following operations are predefined
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-- function "?=" (l, r : STD_ULOGIC) return STD_ULOGIC;
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-- function "?=" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC;
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-- function "?/=" (l, r : STD_ULOGIC) return STD_ULOGIC;
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-- function "?/=" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC;
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-- function "?<" (l, r : STD_ULOGIC) return STD_ULOGIC;
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-- function "?<=" (l, r : STD_ULOGIC) return STD_ULOGIC;
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-- function "?>" (l, r : STD_ULOGIC) return STD_ULOGIC;
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-- function "?>=" (l, r : STD_ULOGIC) return STD_ULOGIC;
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-------------------------------------------------------------------
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-- string conversion and write operations
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-------------------------------------------------------------------
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-- the following operations are predefined
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-- function TO_STRING (value : STD_ULOGIC) return STRING;
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-- function TO_STRING (value : STD_ULOGIC_VECTOR) return STRING;
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-- explicitly defined operations
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alias TO_BSTRING is TO_STRING [STD_ULOGIC_VECTOR return STRING];
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alias TO_BINARY_STRING is TO_STRING [STD_ULOGIC_VECTOR return STRING];
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function TO_OSTRING (VALUE : STD_ULOGIC_VECTOR) return STRING;
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alias TO_OCTAL_STRING is TO_OSTRING [STD_ULOGIC_VECTOR return STRING];
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function TO_HSTRING (VALUE : STD_ULOGIC_VECTOR) return STRING;
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alias TO_HEX_STRING is TO_HSTRING [STD_ULOGIC_VECTOR return STRING];
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procedure READ (L : inout LINE; VALUE : out STD_ULOGIC; GOOD : out BOOLEAN);
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procedure READ (L : inout LINE; VALUE : out STD_ULOGIC);
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procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
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procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
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procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC;
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JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
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procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
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JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
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alias BREAD is READ [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
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alias BREAD is READ [LINE, STD_ULOGIC_VECTOR];
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alias BINARY_READ is READ [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
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alias BINARY_READ is READ [LINE, STD_ULOGIC_VECTOR];
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procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
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procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
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alias OCTAL_READ is OREAD [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
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alias OCTAL_READ is OREAD [LINE, STD_ULOGIC_VECTOR];
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procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
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procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
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alias HEX_READ is HREAD [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
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alias HEX_READ is HREAD [LINE, STD_ULOGIC_VECTOR];
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alias BWRITE is WRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
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alias BINARY_WRITE is WRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
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procedure OWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
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JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
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alias OCTAL_WRITE is OWRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
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procedure HWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
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JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
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alias HEX_WRITE is HWRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
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end package std_logic_1164;
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