44 lines
1.3 KiB
VHDL
44 lines
1.3 KiB
VHDL
-- Nearly useless stub, it's here to support genericmap.vhd
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LIBRARY IEEE;
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USE IEEE.std_logic_1164.all;
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USE IEEE.numeric_std.all;
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entity dsp is generic(
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rst_val : std_logic := '0';
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thing_size: integer := 51;
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bus_width : integer := 24);
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port(
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-- Inputs
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clk, rstn : in std_logic;
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en, start : in std_logic;
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param : in std_logic_vector(7 downto 0);
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addr : in std_logic_vector(2 downto 0);
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din : in std_logic_vector(bus_width-1 downto 0);
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we : in std_logic;
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memdin : out std_logic_vector(13 downto 0);
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-- Outputs
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dout : out std_logic_vector(bus_width-1 downto 0);
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memaddr : out std_logic_vector(5 downto 0);
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memdout : out std_logic_vector(13 downto 0)
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);
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end;
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this is a bug statement :D
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architecture rtl of dsp is
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signal foo : std_logic;
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signal sr : std_logic_vector(63 downto 0);
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signal iparam : integer;
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begin
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iparam <= to_integer(unsigned(param));
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process(clk) begin
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-- dout <= std_logic_vector(to_unsigned(1,bus_width));
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if rising_edge(clk) then
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if we = '1' then
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sr <= sr(thing_size-bus_width-1 downto 0) & din;
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end if;
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dout <= sr(iparam*bus_width+bus_width-1 downto iparam*bus_width);
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end if;
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end process;
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end rtl;
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