add something in lsp linter test

.vscode/property.json

@@ -4,7 +4,7 @@
 		"PL": "template"
 	},
 	"soc": {
-		"core": "cortexM3"
+		"core": "none"
 	},
 	"enableShowLog": false,
 	"device": "none"

Verilog/dependence_test/parent.v

@@ -17,18 +17,22 @@ module Main (
     output Qus, Qs, `main
 );
 
-dependence_1 u_dependence_1(
+initial begin
+    $display("hello world");
+end
+
+dependence_1 u_dependence_1_1(
     .a(a),
     .b(b),
     .c(c),
     .Result(Qus)
 );
 
-dependence_2 u_dependence_2(
+dependence_1 u_dependence_1_2(
     .a(a),
     .b(b),
     .c(c),
-    .Q(Qs)
+    .Result(Qus)
 );
 
 dependence_3 u_dependence_3(
@@ -38,6 +42,15 @@ dependence_3 u_dependence_3(
     .Q(Qs)
 );
 
+adwadawdwa
+
+// dependence_3 u_dependence_3(
+//     .a(a),
+//     .b(b),
+//     .c(c),
+//     .Q(Qs)
+// );
+
 endmodule
 
 
@@ -66,4 +79,4 @@ endmodule
     { name: "clk3", wave: "nhNhplPl" },
     { name: "clk4", wave: "xlh.L.Hx" },
 ]}
-*/
+*/

lsp/linter/child_1.v

@@ -0,0 +1,17 @@
+module dependence_1 (
+    // this is a test
+    input a, b, c,
+    // a test
+    output Result       // balabalabala for result
+);
+
+    // a & b | ((b & c) & (b | c))
+    // &=*, |=+               AB + BC(B+C)
+    // Distribute             AB + BBC + BCC
+    // Simplify AA = A        AB + BC + BC
+    // Simplify A + A = A     AB + BC
+    // Factor                 B(A+C)
+
+    assign Result = a & (b | c);
+
+endmodule

lsp/linter/child_2.v

@@ -0,0 +1,8 @@
+module dependence_2 (
+    input a, b, c,
+    output Q 
+);
+
+  assign Q = a & b | ((b & c) & (b | c));
+
+endmodule

lsp/linter/clk.vhd

@@ -0,0 +1,36 @@
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.all;
+entity clk is port( reset, preset, qreset, sysclk, dsysclk, esysclk : in std_logic;
+                     ival : in std_logic_vector(31 downto 0)
+                     );
+end clk;
+architecture rtl of clk is
+  signal foo : std_logic_vector(10+3 downto 0);
+  signal baz : std_logic_vector(2 downto 0);
+  signal egg : std_logic_vector(4 to 7-1);
+begin
+  pfoo: process(reset, sysclk)
+  begin
+    if( reset /= '0' ) then
+      foo <= (others => '1');
+    elsif( sysclk'event and sysclk = '1' ) then
+      foo <= ival(31 downto 31-(10+3));
+    end if;
+  end process;
+  pbaz: process(preset, dsysclk)
+  begin
+    if( preset /= '1' ) then
+      baz <= (others => '0');
+    elsif( dsysclk'event and dsysclk = '0' ) then
+      baz <= ival(2 downto 0);
+    end if;
+  end process;
+  pegg: process(qreset, esysclk)
+  begin
+    if( qreset /= '1' ) then
+      egg <= (others => '0');
+    elsif( esysclk'event and esysclk = '0' ) then
+      egg <= ival(6 downto 4);
+    end if;
+  end process;
+end rtl;

lsp/linter/dsp.vhd

@@ -0,0 +1,43 @@
+-- Nearly useless stub, it's here to support genericmap.vhd
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.all;
+USE IEEE.numeric_std.all;
+
+entity dsp is generic(
+  rst_val   : std_logic := '0';
+  thing_size: integer   := 51;
+  bus_width : integer   := 24);
+    port(
+      -- Inputs
+      clk, rstn : in std_logic;
+      en, start : in std_logic;
+      param     : in std_logic_vector(7 downto 0);
+      addr      : in std_logic_vector(2 downto 0);
+      din       : in std_logic_vector(bus_width-1 downto 0);
+      we        : in std_logic;
+      memdin    : out std_logic_vector(13 downto 0);
+      -- Outputs
+      dout      : out std_logic_vector(bus_width-1 downto 0);
+      memaddr   : out std_logic_vector(5 downto 0);
+      memdout   : out std_logic_vector(13 downto 0)
+      );
+end;
+
+this is a bug statement :D
+
+architecture rtl of dsp is
+    signal foo : std_logic;
+    signal sr  : std_logic_vector(63 downto 0);
+    signal iparam : integer;
+begin
+    iparam <= to_integer(unsigned(param));
+    process(clk) begin
+       -- dout <= std_logic_vector(to_unsigned(1,bus_width));
+       if rising_edge(clk) then
+           if we = '1' then
+              sr <= sr(thing_size-bus_width-1 downto 0) & din;
+           end if;
+           dout <= sr(iparam*bus_width+bus_width-1 downto iparam*bus_width);
+       end if;
+    end process;
+end rtl;

lsp/linter/head_1.v

@@ -0,0 +1,23 @@
+`define cow 34
+
+module dependence_1 (
+    input port_a, port_b, port_c,
+    output out_q
+);
+    // a & b | ((b & c) & (b | c))
+    // &=*, |=+               AB + BC(B+C)
+    // Distribute             AB + BBC + BCC
+    // Simplify AA = A        AB + BC + BC
+    // Simplify A + A = A     AB + BC
+    // Factor                 B(A+C)
+
+    assign out_q = port_b & (port_a | port_c);
+endmodule
+
+
+module test_1 (
+    input port_a, port_b,
+    output Q 
+);
+    assign Q = port_b & port_a;
+endmodule

lsp/linter/hello.v

@@ -0,0 +1,6 @@
+module hello;
+    initial begin
+        $display("hello world");
+        $finish;
+    end
+endmodule

lsp/linter/main.js

@@ -0,0 +1,39 @@
+const childProcess = require("child_process");
+
+remove_files = ["xvlog.pb", "xvhdl.pb"]
+remove_folders = ["xsim.dir"]
+
+/**
+ * 
+ * @param {string} file 
+ * @param {string[]} args
+ * @returns {Promise<{ stdout: string, stderr: string }>} 
+ */
+async function easyExec(file, args) {
+    const allArguments = [file, ...args];
+    const command = allArguments.join(' ');
+
+    const p = new Promise( ( resolve, _ ) => {
+        childProcess.exec(command, ( _, stdout, stderr ) => {
+            resolve({ stdout, stderr });
+        });
+    });
+
+    return p;
+}
+
+
+async function linter_vlog(path) {
+    let command = `xvlog ${path} --nolog`;
+
+    const { stdout, stderr } = await easyExec('C:/modeltech64_10.4/win64/vlog.exe', [path, '--nolog']);
+    console.log(stdout);
+    for (const line of stdout.split('\n')) {
+        if (line.startsWith('ERROR')) {
+            const tokens = line.split(/:?\s*(?:\[|\])\s*/);
+            console.log(tokens);
+        }
+    }
+}
+
+linter_vlog("./parent.v")

lsp/linter/parent.v

@@ -0,0 +1,81 @@
+/* 
+ * EN: A simple demo to test search order of dependence
+ *     current file -> macro include -> whole project
+ *     expect dependence_1 from child_1.v (macro include)
+ *     expect dependence_2 from child_2.v (whole project)
+ *     cannot find dependence_3 `main
+ */
+
+`include "child_1.v"
+`include "child_2.v"
+`define main out
+
+module Main (
+    // Main input
+    input a, b, c,
+    // Main output
+    output Qus, Qs, `main
+);
+
+initial begin
+    $display("hello world");
+end
+
+dependence_1 u_dependence_1_1(
+    .a(a),
+    .b(b),
+    .c(c),
+    .Result(Qus)
+);
+
+dependence_1 u_dependence_1_2(
+    .a(a),
+    .b(b),
+    .c(c),
+    .Result(Qus)
+);
+
+dependence_3 u_dependence_3(
+    .a(a),
+    .b(b),
+    .c(c),
+    .Q(Qs)
+);
+
+adawdwa
+// dependence_3 u_dependence_3(
+//     .a(a),
+//     .b(b),
+//     .c(c),
+//     .Q(Qs)
+// );
+
+endmodule
+
+
+/* @wavedrom this is wavedrom demo1
+{
+    signal : [
+        { name: "clk",  wave: "p......" },
+        { name: "bus",  wave: "x.34.5x", data: "head body tail" },
+        { name: "wire", wave: "0.1..0." }
+    ]
+}
+*/
+
+
+/* @wavedrom this is wavedrom demo2
+{ 
+    signal: [
+    { name: "pclk", wave: "p......." },
+    { name: "Pclk", wave: "P......." },
+    { name: "nclk", wave: "n......." },
+    { name: "Nclk", wave: "N......." },
+    {},
+    { name: "clk0", wave: "phnlPHNL" },
+    { name: "clk1", wave: "xhlhLHl." },
+    { name: "clk2", wave: "hpHplnLn" },
+    { name: "clk3", wave: "nhNhplPl" },
+    { name: "clk4", wave: "xlh.L.Hx" },
+]}
+*/

lsp/linter/work/_info

@@ -0,0 +1,50 @@
+m255
+K4
+z2
+13
+!s112 1.1
+!i10d 8192
+!i10e 25
+!i10f 100
+cModel Technology
+Z0 dC:/Users/11934/Project/Digital-IDE/Digital-Test/lsp/linter
+vdependence_1
+Z1 !s110 1700576438
+!i10b 1
+!s100 1L3L]>oO5UNbT`JWk8I2F1
+IIgLED8NdRzGhBY_234<1k2
+Z2 VDg1SIo80bB@j0V0VzS_@n1
+R0
+Z3 w1696688297
+8child_1.v
+Fchild_1.v
+L0 1
+Z4 OL;L;10.4;61
+r1
+!s85 0
+31
+Z5 !s108 1700576438.165000
+Z6 !s107 child_2.v|child_1.v|.\parent.v|
+Z7 !s90 .\parent.v|-quiet|-nologo|
+!i113 0
+Z8 o-quiet -nologo -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact
+vdependence_2
+R1
+!i10b 1
+!s100 LMOKj0lWZZRTkT2OVHa543
+Ibh;z<<=?EQaGZPfGf:Fh52
+R2
+R0
+R3
+8child_2.v
+Fchild_2.v
+L0 1
+R4
+r1
+!s85 0
+31
+R5
+R6
+R7
+!i113 0
+R8

lsp/linter/work/_vmake

@@ -0,0 +1,4 @@
+m255
+K4
+z0
+cModel Technology

lsp/linter/xsim.dir/work/work.rlx

@@ -0,0 +1,8 @@
+0.6
+2018.3
+Dec  7 2018
+00:33:28
+C:/Users/11934/Project/Digital-IDE/Digital-Test/lsp/linter/child_1.v,1696688297,verilog,,,,dependence_1,,,,,,,,
+C:/Users/11934/Project/Digital-IDE/Digital-Test/lsp/linter/child_2.v,1696688297,verilog,,,,dependence_2,,,,,,,,
+C:/Users/11934/Project/Digital-IDE/Digital-Test/lsp/linter/dsp.vhd,1692686802,vhdl,,,,dsp,,,,,,,,
+C:/Users/11934/Project/Digital-IDE/Digital-Test/lsp/linter/parent.v,1700548652,verilog,,,C:/Users/11934/Project/Digital-IDE/Digital-Test/lsp/linter/child_1.v;C:/Users/11934/Project/Digital-IDE/Digital-Test/lsp/linter/child_2.v,Main,,,,,,,,

lsp/linter/xvhdl.log

@@ -0,0 +1 @@
+ERROR: [XSIM 43-3273] No HDL file(s) specified.

markdown/clkdiv/index.md

@@ -0,0 +1,29 @@
+# clkdiv
+## Basic Info
+- 3 params, 0 ports 
+- top module √ 
+
+## params
+no params info
+
+## ports
+| name | type | width | description |
+| :--- | :--- | :--- | :--- |
+| clk50 | input | 1 | |
+| rst_n | input | 1 | |
+| clkout | output | 1 | |
+
+## Dependency
+no Dependencies info
+
+
+
+
+<br><div align=center><img src="./figure/wavedrom-5.svg"></img></div><br><br>
+
+
+
+
+<br><div align=center><img src="./figure/wavedrom-6.svg"></img></div><br><br>
+
+

prj/simulation/icarus/out.vvp

@@ -0,0 +1,25 @@
+#! /c/Source/iverilog-install/bin/vvp
+:ivl_version "12.0 (devel)" "(s20150603-1110-g18392a46)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision + 0;
+:vpi_module "C:\iverilog\lib\ivl\system.vpi";
+:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
+:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
+:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
+:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
+:vpi_module "C:\iverilog\lib\ivl\v2009.vpi";
+S_000001e5c16a3530 .scope package, "$unit" "$unit" 2 1;
+ .timescale 0 0;
+S_000001e5c16a36c0 .scope module, "hello" "hello" 3 1;
+ .timescale 0 0;
+    .scope S_000001e5c16a36c0;
+T_0 ;
+    %vpi_call/w 3 4 "$display", "hello world" {0 0 0};
+    %end;
+    .thread T_0;
+# The file index is used to find the file name in the following table.
+:file_names 4;
+    "N/A";
+    "<interactive>";
+    "-";
+    "c:/Users/11934/Project/Digital-IDE/Digital-Test/user/src/hello.v";

scripts/.vscode/property.json

@@ -6,12 +6,6 @@
 	"soc": {
 		"core": "none"
 	},
-    "arch": {
-        "hardware": {
-            "sim": "./",
-            "src": "./"
-        }
-    },
 	"enableShowLog": false,
 	"device": "none"
 }

scripts/test.vhd

@@ -0,0 +1 @@
+    

suite/extension.test.ts

@@ -1,15 +0,0 @@
-import * as assert from 'assert';
-
-// You can import and use all API from the 'vscode' module
-// as well as import your extension to test it
-import * as vscode from 'vscode';
-// import * as myExtension from '../../extension';
-
-suite('Extension Test Suite', () => {
-	vscode.window.showInformationMessage('Start all tests.');
-
-	test('Sample test', () => {
-		assert.strictEqual(-1, [1, 2, 3].indexOf(5));
-		assert.strictEqual(-1, [1, 2, 3].indexOf(0));
-	});
-});

suite/index.ts

@@ -1,38 +0,0 @@
-import * as path from 'path';
-import * as Mocha from 'mocha';
-import * as glob from 'glob';
-
-export function run(): Promise<void> {
-	// Create the mocha test
-	const mocha = new Mocha({
-		ui: 'tdd',
-		color: true
-	});
-
-	const testsRoot = path.resolve(__dirname, '..');
-
-	return new Promise((c, e) => {
-		glob('**/**.test.js', { cwd: testsRoot }, (err, files) => {
-			if (err) {
-				return e(err);
-			}
-
-			// Add files to the test suite
-			files.forEach(f => mocha.addFile(path.resolve(testsRoot, f)));
-
-			try {
-				// Run the mocha test
-				mocha.run(failures => {
-					if (failures > 0) {
-						e(new Error(`${failures} tests failed.`));
-					} else {
-						c();
-					}
-				});
-			} catch (err) {
-				console.error(err);
-				e(err);
-			}
-		});
-	});
-}

tcl/top.xdc

@@ -0,0 +1,6 @@
+set_property PACKAGE PIN W30[get_ports R3_A2]
+set_property PACKAGE PIN V27[get_ports TTT14]
+set_property PACKAGE PIN W28[get_ports TTT12]
+set_property PACKAGE_ PIN W25[get_ports TTT10]
+set_property PACKAGE_ PIN W26[get_ports TTT11]
+set_property PACKAGE PIN U25[get_ports TTT_CLK1] 

user/Hardware/sim/testbench.v

@@ -1,51 +0,0 @@
-module testbench();
-
-parameter DATA_WIDTH = 32;
-parameter ADDR_WIDTH = 32;
-parameter MAIN_FRE   = 100; //unit MHz
-reg                   sys_clk = 0;
-reg                   sys_rst = 1;
-reg [DATA_WIDTH-1:0]  data = 0;
-reg [ADDR_WIDTH-1:0]  addr = 0;
-
-always begin
-    #(500/MAIN_FRE) sys_clk = ~sys_clk;
-end
-
-always begin
-    #50 sys_rst = 0;
-end
-
-always @(posedge sys_clk) begin
-    if (sys_rst) 
-        addr = 0;
-    else      
-        addr = addr + 1;
-end
-always @(posedge sys_clk) begin
-    if (sys_rst) 
-        data = 0;
-    else      
-        data = data + 1;
-end
-
-//Instance 
-// outports wire
-wire   	outp;
-
-mux2to1 u_mux2to1(
-	.a    	( a     ),
-	.b    	( b     ),
-	.sel  	( sel   ),
-	.outp 	( outp  )
-);
-
-
-
-initial begin            
-    $dumpfile("wave.vcd");        
-    $dumpvars(0, testbench);    
-    #50000 $finish;
-end
-
-endmodule  //TOP

user/Hardware/src/clkdiv.v

@@ -1,29 +0,0 @@
-module clkdiv(
-    input clk50,
-    input rst_n,
-    output reg clkout
-);
-    reg [15:0] cnt;
-    always @(posedge clk50 or negedge rst_n)
-    begin
-        if(!rst_n)
-        begin
-            cnt <= 16'b0;
-            clkout <= 1'b0;
-        end
-        else if(cnt == 16'd162) 
-        begin
-            clkout <= 1'b1;
-            cnt <= cnt + 16'd1;
-        end
-            else if(cnt == 16'd325) 
-        begin
-            clkout <= 1'b0;
-            cnt <= 16'd0;
-        end
-            else 
-        begin
-            cnt <= cnt + 16'd1;
-        end
-    end
-endmodule

user/Hardware/src/hello.v

@@ -1,33 +0,0 @@
-// VHDL code for a 2-to-1 multiplexer
-
-module mux2to1(
-        input wire a,
-        input wire b,
-        input wire sel,
-        output wire outp
-    );
-
-    // outports wire
-wire [XY_BITS-1:0] 	x_o;
-wire [XY_BITS-1:0] 	y_o;
-wire [PH_BITS-1:0] 	phase_out;
-wire               	valid_out;
-
-Cordic u_Cordic(
-	.clk       	( clk        ),
-	.RST       	( RST        ),
-	.x_i       	( x_i        ),
-	.y_i       	( y_i        ),
-	.phase_in  	( phase_in   ),
-	.x_o       	( x_o        ),
-	.y_o       	( y_o        ),
-	.phase_out 	( phase_out  ),
-	.valid_in  	( valid_in   ),
-	.valid_out 	( valid_out  )
-);
-
-
-
-    assign outp = sel == 1'b0 ? a : b;
-
-endmodule

user/src/Cordic.v

@@ -2,11 +2,12 @@
 
 
 `include "mult_module.v"
+`define ITER_RAW 32
 
 module Cordic #(
 	parameter XY_BITS      = 12,
 	parameter PH_BITS      = 32,
-	parameter ITERATIONS   = 32,
+	parameter ITERATIONS   = `ITER_RAW,
 	parameter CORDIC_STYLE = "ROTATE",
 	parameter PHASE_ACC    = "ON"
 )(

user/src/clkdiv.v

@@ -0,0 +1,56 @@
+module clkdiv(
+    input clk50,
+    input rst_n,
+    output reg clkout
+);
+    reg [15:0] cnt;
+    always @(posedge clk50 or negedge rst_n)
+    begin
+        if(!rst_n)
+        begin
+            cnt <= 16'b0;
+            clkout <= 1'b0;
+        end
+        else if(cnt == 16'd162)
+        begin
+            clkout <= 1'b1;
+            cnt <= cnt + 16'd1;
+        end
+            else if(cnt == 16'd325) 
+        begin
+            clkout <= 1'b0;
+            cnt <= 16'd0;
+        end
+            else 
+        begin
+            cnt <= cnt + 16'd1;
+        end
+    end
+endmodule
+
+/* @wavedrom this is wavedrom demo1
+{
+    signal : [
+        { name: "clk",  wave: "p......" },
+        { name: "bus",  wave: "x.34.5x", data: "head body tail" },
+        { name: "wire", wave: "0.1..0." }
+    ]
+}
+*/
+
+
+/* @wavedrom this is wavedrom demo2
+{ 
+    signal: [
+    { name: "pclk", wave: "p......." },
+    { name: "Pclk", wave: "P......." },
+    { name: "nclk", wave: "n......." },
+    { name: "Nclk", wave: "N......." },
+    {},
+    { name: "clk0", wave: "phnlPHNL" },
+    { name: "clk1", wave: "xhlhLHl." },
+    { name: "clk2", wave: "hpHplnLn" },
+    { name: "clk3", wave: "nhNhplPl" },
+    { name: "clk4", wave: "xlh.L.Hx" },
+]}
+*/

user/src/generate.v

@@ -0,0 +1,7 @@
+module led (
+    input      key,  // key in
+    output     led   // led out
+);
+    assign led = ~key;
+    
+endmodule //led

user/src/hello.v

@@ -0,0 +1,7 @@
+module hello ();
+
+    initial begin
+        $display("hello world");
+    end
+    
+endmodule //hello