82 lines
1.5 KiB
Verilog
82 lines
1.5 KiB
Verilog
/*
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* EN: A simple demo to test search order of dependence
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* current file -> macro include -> whole project
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* expect dependence_1 from child_1.v (macro include)
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* expect dependence_2 from child_2.v (whole project)
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* cannot find dependence_3 `main
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*/
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`include "child_1.v"
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`include "child_2.v"
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`define main out
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module Main (
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// Main input
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input a, b, c,
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// Main output
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output Qus, Qs, `main
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);
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initial begin
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$display("hello world");
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end
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dependence_1 u_dependence_1_1(
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.a(a),
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.b(b),
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.c(c),
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.Result(Qus)
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);
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dependence_1 u_dependence_1_2(
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.a(a),
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.b(b),
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.c(c),
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.Result(Qus)
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);
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dependence_3 u_dependence_3(
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.a(a),
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.b(b),
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.c(c),
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.Q(Qs)
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);
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adawdwa
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// dependence_3 u_dependence_3(
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// .a(a),
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// .b(b),
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// .c(c),
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// .Q(Qs)
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// );
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endmodule
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/* @wavedrom this is wavedrom demo1
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{
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signal : [
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{ name: "clk", wave: "p......" },
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{ name: "bus", wave: "x.34.5x", data: "head body tail" },
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{ name: "wire", wave: "0.1..0." }
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]
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}
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*/
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/* @wavedrom this is wavedrom demo2
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{
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signal: [
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{ name: "pclk", wave: "p......." },
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{ name: "Pclk", wave: "P......." },
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{ name: "nclk", wave: "n......." },
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{ name: "Nclk", wave: "N......." },
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{},
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{ name: "clk0", wave: "phnlPHNL" },
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{ name: "clk1", wave: "xhlhLHl." },
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{ name: "clk2", wave: "hpHplnLn" },
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{ name: "clk3", wave: "nhNhplPl" },
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{ name: "clk4", wave: "xlh.L.Hx" },
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]}
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*/
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