51 lines
823 B
Verilog
51 lines
823 B
Verilog
module testbench();
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parameter DATA_WIDTH = 32;
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parameter ADDR_WIDTH = 32;
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parameter MAIN_FRE = 100; //unit MHz
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reg sys_clk = 0;
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reg sys_rst = 1;
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reg [DATA_WIDTH-1:0] data = 0;
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reg [ADDR_WIDTH-1:0] addr = 0;
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always begin
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#(500/MAIN_FRE) sys_clk = ~sys_clk;
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end
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always begin
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#50 sys_rst = 0;
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end
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always @(posedge sys_clk) begin
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if (sys_rst)
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addr = 0;
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else
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addr = addr + 1;
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end
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always @(posedge sys_clk) begin
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if (sys_rst)
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data = 0;
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else
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data = data + 1;
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end
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//Instance
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// outports wire
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wire [8:0] c;
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SimpleAdd_1 u_SimpleAdd_1(
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.a ( a ),
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.b ( b ),
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.c ( c )
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);
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initial begin
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$dumpfile("wave.vcd");
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$dumpvars(0, testbench);
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#50000 $finish;
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end
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endmodule //TOP
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