kirigaya/Digital-Test
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

update

Browse Source
This commit is contained in:
锦恢 2023-08-24 11:58:55 +08:00
parent e7698f933d
commit 52c550bdea
58 changed files with 3359 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
.vscode/property.json vendored Normal file
View File

@ -0,0 +1,11 @@
{
"toolChain": "xilinx",
"prjName": {
"PL": "template"
},
"soc": {
"core": "cortexM3"
},
"enableShowLog": false,
"device": "none"
}

18
README.md
View File

@ -1,2 +1,18 @@
# Digital-Test
test space for Digital IDE extension
默认property.json:
```json
{
"toolChain": "xilinx",
"prjName": {
"PL": "template"
},
"soc": {
"core": "cortexM3"
},
"enableShowLog": false,
"device": "none"
}
```

11
manager/.vscode/property.json vendored Normal file
View File

@ -0,0 +1,11 @@
{
"toolChain": "xilinx",
"prjName": {
"PL": "template"
},
"soc": {
"core": "none"
},
"enableShowLog": false,
"device": "none"
}

6
manager/user/src/hello.v Normal file
View File

@ -0,0 +1,6 @@
module hello(
input clk, reset,
output value
);
endmodule

17
monitor/.vscode/property.json vendored Normal file
View File

@ -0,0 +1,17 @@
{
"toolChain": "xilinx",
"prjName": {
"PL": "template"
},
"soc": {
"core": "none"
},
"enableShowLog": false,
"device": "none",
"arch": {
"hardware": {
"src": "./src1",
"sim": "./sim1"
}
}
}

50
monitor/sim1/testbench.v Normal file
View File

@ -0,0 +1,50 @@
module testbench();
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 32;
parameter MAIN_FRE = 100; //unit MHz
reg sys_clk = 0;
reg sys_rst = 1;
reg [DATA_WIDTH-1:0] data = 0;
reg [ADDR_WIDTH-1:0] addr = 0;
always begin
#(500/MAIN_FRE) sys_clk = ~sys_clk;
end
always begin
#50 sys_rst = 0;
end
always @(posedge sys_clk) begin
if (sys_rst)
addr = 0;
else
addr = addr + 1;
end
always @(posedge sys_clk) begin
if (sys_rst)
data = 0;
else
data = data + 1;
end
//Instance
// outports wire
wire [8:0] c;
SimpleAdd_1 u_SimpleAdd_1(
.a ( a ),
.b ( b ),
.c ( c )
);
initial begin
$dumpfile("wave.vcd");
$dumpvars(0, testbench);
#50000 $finish;
end
endmodule //TOP

11
monitor/src1/add.v Normal file
View File

@ -0,0 +1,11 @@
module SimpleAdd_1(
input [8:0] a, b,
output [8:0] c
);
assign c = a + b;
endmodule //SimpleAdd

9
monitor/src2/add.v Normal file
View File

@ -0,0 +1,9 @@
module SimpleAdd_2(
input [7:0] a, b,
output [7:0] c
);
assign c = a + b;
endmodule //SimpleAdd

15
suite/extension.test.ts Normal file
View File

@ -0,0 +1,15 @@
import * as assert from 'assert';
// You can import and use all API from the 'vscode' module
// as well as import your extension to test it
import * as vscode from 'vscode';
// import * as myExtension from '../../extension';
suite('Extension Test Suite', () => {
vscode.window.showInformationMessage('Start all tests.');
test('Sample test', () => {
assert.strictEqual(-1, [1, 2, 3].indexOf(5));
assert.strictEqual(-1, [1, 2, 3].indexOf(0));
});
});

38
suite/index.ts Normal file
View File

@ -0,0 +1,38 @@
import * as path from 'path';
import * as Mocha from 'mocha';
import * as glob from 'glob';
export function run(): Promise<void> {
// Create the mocha test
const mocha = new Mocha({
ui: 'tdd',
color: true
});
const testsRoot = path.resolve(__dirname, '..');
return new Promise((c, e) => {
glob('**/**.test.js', { cwd: testsRoot }, (err, files) => {
if (err) {
return e(err);
}
// Add files to the test suite
files.forEach(f => mocha.addFile(path.resolve(testsRoot, f)));
try {
// Run the mocha test
mocha.run(failures => {
if (failures > 0) {
e(new Error(`${failures} tests failed.`));
} else {
c();
}
});
} catch (err) {
console.error(err);
e(err);
}
});
});
}

9
tcl/timing.xdc Normal file
View File

@ -0,0 +1,9 @@
create_debug_core u_ila_0 ila
set_property ALL_PROBE_SAME_MU true
set_property C_ADV_TRIGGER true
set_property C_EN_STRG_QUAL true
set_property C_INPUT_PIPE_STAGES true
set_property C_TRIGIN_EN false
set_property C_TRIGOUT_EN false
set_property port_width
connect_debug_port u_ila_0/clk

51
user/Hardware/sim/testbench.v Normal file
View File

@ -0,0 +1,51 @@
module testbench();
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 32;
parameter MAIN_FRE = 100; //unit MHz
reg sys_clk = 0;
reg sys_rst = 1;
reg [DATA_WIDTH-1:0] data = 0;
reg [ADDR_WIDTH-1:0] addr = 0;
always begin
#(500/MAIN_FRE) sys_clk = ~sys_clk;
end
always begin
#50 sys_rst = 0;
end
always @(posedge sys_clk) begin
if (sys_rst)
addr = 0;
else
addr = addr + 1;
end
always @(posedge sys_clk) begin
if (sys_rst)
data = 0;
else
data = data + 1;
end
//Instance
// outports wire
wire outp;
mux2to1 u_mux2to1(
.a ( a ),
.b ( b ),
.sel ( sel ),
.outp ( outp )
);
initial begin
$dumpfile("wave.vcd");
$dumpvars(0, testbench);
#50000 $finish;
end
endmodule //TOP

265
user/Hardware/src/Cordic.v Normal file
View File

@ -0,0 +1,265 @@
`timescale 1ns / 1ps
`include "mult_module.v"
module Cordic #(
parameter XY_BITS = 12,
parameter PH_BITS = 32,
parameter ITERATIONS = 32,
parameter CORDIC_STYLE = "ROTATE",
parameter PHASE_ACC = "ON"
)(
input clk,
input RST,
input signed [XY_BITS-1:0] x_i,
input signed [XY_BITS-1:0] y_i,
input signed [PH_BITS-1:0] phase_in,
output signed [XY_BITS-1:0] x_o,
output signed [XY_BITS-1:0] y_o,
output signed [PH_BITS-1:0] phase_out,
input valid_in,
output valid_out
);
localparam [XY_BITS-1:0] K_COS = (0.607252935 * 2**(XY_BITS-1))-2;
/*
//360°--2^16,phase_in = 16bits (input [15:0] phase_in)
//1°--2^16/360
*/
function [PH_BITS-1:0] tanangle;
input [4:0] i;
begin
case (i)
5'b00000: tanangle = (32'h20000000 >> (32 - PH_BITS)); //tan = 1/2^1 = 1/2
5'b00001: tanangle = (32'h12e4051e >> (32 - PH_BITS)); //tan = 1/2^2 = 1/4
5'b00010: tanangle = (32'h09fb385b >> (32 - PH_BITS)); //tan = 1/2^3 = 1/8
5'b00011: tanangle = (32'h051111d4 >> (32 - PH_BITS)); //tan = 1/2^4 = 1/16
5'b00100: tanangle = (32'h028b0d43 >> (32 - PH_BITS)); //tan = 1/2^5 = 1/32
5'b00101: tanangle = (32'h0145d7e1 >> (32 - PH_BITS)); //tan = 1/2^6 = 1/64
5'b00110: tanangle = (32'h00a2f61e >> (32 - PH_BITS)); //tan = 1/2^7 = 1/128
5'b00111: tanangle = (32'h00517c55 >> (32 - PH_BITS)); //tan = 1/2^8 = 1/256
5'b01000: tanangle = (32'h0028be53 >> (32 - PH_BITS)); //tan = 1/2^9 = 1/512
5'b01001: tanangle = (32'h00145f2f >> (32 - PH_BITS)); //tan = 1/2^10 = 1/1024
5'b01010: tanangle = (32'h000a2f98 >> (32 - PH_BITS)); //tan = 1/2^11 = 1/2048
5'b01011: tanangle = (32'h000517cc >> (32 - PH_BITS)); //tan = 1/2^12 = 1/4096
5'b01100: tanangle = (32'h00028be6 >> (32 - PH_BITS)); //tan = 1/2^13 = 1/8192
5'b01101: tanangle = (32'h000145f3 >> (32 - PH_BITS)); //tan = 1/2^14 = 1/16384
5'b01110: tanangle = (32'h0000a2fa >> (32 - PH_BITS)); //tan = 1/2^15 = 1/32768
5'b01111: tanangle = (32'h0000517d >> (32 - PH_BITS)); //tan = 1/2^16 = 1/65536
5'b10000: tanangle = (32'h000028be >> (32 - PH_BITS)); //tan = 1/2^17 = 1/131072
5'b10001: tanangle = (32'h0000145f >> (32 - PH_BITS)); //tan = 1/2^18 = 1/262144
5'b10010: tanangle = (32'h00000a30 >> (32 - PH_BITS)); //tan = 1/2^19 = 1/524288
5'b10011: tanangle = (32'h00000518 >> (32 - PH_BITS)); //tan = 1/2^20 = 1/1048576
5'b10100: tanangle = (32'h0000028c >> (32 - PH_BITS)); //tan = 1/2^21 = 1/2097152
5'b10101: tanangle = (32'h00000146 >> (32 - PH_BITS)); //tan = 1/2^22 = 1/4194304
5'b10110: tanangle = (32'h000000a3 >> (32 - PH_BITS)); //tan = 1/2^23 = 1/8388608
5'b10111: tanangle = (32'h00000051 >> (32 - PH_BITS)); //tan = 1/2^24 = 1/16777216
5'b11000: tanangle = (32'h00000029 >> (32 - PH_BITS)); //tan = 1/2^25 = 1/33554432
5'b11001: tanangle = (32'h00000014 >> (32 - PH_BITS)); //tan = 1/2^26 = 1/67108864
5'b11010: tanangle = (32'h0000000a >> (32 - PH_BITS)); //tan = 1/2^27 = 1/134217728
5'b11011: tanangle = (32'h00000005 >> (32 - PH_BITS)); //tan = 1/2^28 = 1/268435456
5'b11100: tanangle = (32'h00000003 >> (32 - PH_BITS)); //tan = 1/2^29 = 1/536870912
5'b11101: tanangle = (32'h00000001 >> (32 - PH_BITS)); //tan = 1/2^30 = 1/1073741824
5'b11110: tanangle = (32'h00000001 >> (32 - PH_BITS)); //tan = 1/2^31 = 1/2147483648
5'b11111: tanangle = (32'h00000000 >> (32 - PH_BITS)); //tan = 1/2^32 = 1/4294967296
endcase
end
endfunction
reg [1:0] data_in_buff [ITERATIONS:0];
reg signed [XY_BITS-1:0] x [ITERATIONS:0];
reg signed [XY_BITS-1:0] y [ITERATIONS:0];
reg signed [PH_BITS-1:0] z [ITERATIONS:0];
integer m;
initial begin
for (m = 0; m<=ITERATIONS; m=m+1) begin
x[m] = 0;
end
end
integer n;
initial begin
for (n = 0; n<=ITERATIONS; n=n+1) begin
y[n] = 0;
end
end
integer s;
initial begin
for (s = 0; s<=ITERATIONS; s=s+1) begin
z[s] = 0;
end
end
integer k;
initial begin
for (k = 0; k<=ITERATIONS; k=k+1) begin
data_in_buff[k] = 0;
end
end
genvar i;
generate for(i=0;i<ITERATIONS;i=i+1) begin : CORDIC
always @ (posedge clk) begin
if (RST) begin
x[i+1] <= 0;
y[i+1] <= 0;
z[i+1] <= 0;
end
else begin
if (CORDIC_STYLE == "ROTATE") begin
if (z[i] < 0) begin
x[i+1] <= x[i] + (y[i]>>>i);
y[i+1] <= y[i] - (x[i]>>>i);
z[i+1] <= z[i] + tanangle(i);
end
else begin
x[i+1] <= x[i] - (y[i]>>>i);
y[i+1] <= y[i] + (x[i]>>>i);
z[i+1] <= z[i] - tanangle(i);
end
end
else if(CORDIC_STYLE == "VECTOR") begin
if (y[i] > 0) begin
x[i+1] <= x[i] + (y[i]>>>i);
y[i+1] <= y[i] - (x[i]>>>i);
z[i+1] <= z[i] + tanangle(i);
end else begin
x[i+1] <= x[i] - (y[i]>>>i);
y[i+1] <= y[i] + (x[i]>>>i);
z[i+1] <= z[i] - tanangle(i);
end
end
end
end
always @ (posedge clk) begin
data_in_buff[i+1] <= data_in_buff[i];
end
end
endgenerate
generate if (CORDIC_STYLE == "ROTATE") begin : IQ_Gen
reg [PH_BITS - 1 : 0] Phase_input = 0;
if (PHASE_ACC == "ON") begin
reg [PH_BITS - 1 : 0] addr_r0 = 0;
always @(posedge clk) begin
addr_r0 <= addr_r0 + phase_in;
end
always @(posedge clk) begin
Phase_input <= addr_r0;
end
end
else if (PHASE_ACC == "OFF") begin
always @(posedge clk) begin
Phase_input <= phase_in;
end
end
always @(posedge clk) begin
if(valid_in & (~RST)) begin
x[0] <= K_COS;
y[0] <= 0;
z[0] <= Phase_input[PH_BITS - 3 : 0];
data_in_buff[0] <= Phase_input[PH_BITS - 1 : PH_BITS - 2];
end
else begin
x[0] <= 0;
y[0] <= 0;
z[0] <= 0;
data_in_buff[0] <= 0;
end
end
reg signed [XY_BITS-1:0] cos = 0;
reg signed [XY_BITS-1:0] sin = 0;
always @ (posedge clk) begin
case(data_in_buff[ITERATIONS])
2'b00:begin //if the phase is in first quadrant,the sin(X)=sin(A),cos(X)=cos(A)
cos <= x[ITERATIONS];
sin <= y[ITERATIONS];
end
2'b01:begin //if the phase is in second quadrant,the sin(X)=sin(A+90)=cosA,cos(X)=cos(A+90)=-sinA
cos <= ~(y[ITERATIONS]) + 1'b1;//-sin
sin <= x[ITERATIONS];//cos
end
2'b10:begin //if the phase is in third quadrant,the sin(X)=sin(A+180)=-sinA,cos(X)=cos(A+180)=-cosA
cos <= ~(x[ITERATIONS]) + 1'b1;//-cos
sin <= ~(y[ITERATIONS]) + 1'b1;//-sin
end
2'b11:begin //if the phase is in forth quadrant,the sin(X)=sin(A+270)=-cosA,cos(X)=cos(A+270)=sinA
cos <= y[ITERATIONS];//sin
sin <= ~(x[ITERATIONS]) + 1'b1;//-cos
end
endcase
end
assign x_o = cos;
assign y_o = sin;
assign phase_out = z[ITERATIONS];
end
endgenerate
generate if (CORDIC_STYLE == "VECTOR") begin : Demodule_Gen
localparam signed [PH_BITS-1:0] PHASE_COE = (2**(PH_BITS-2)) - 1;
//localparam MODUIUS_COE = ;
always @(posedge clk) begin
if(valid_in & (~RST)) begin
case ({x_i[XY_BITS-1],y_i[XY_BITS-1]})
2'b00 : begin x[0] <= {x_i[XY_BITS-1],x_i[XY_BITS-1:1]};
y[0] <= {y_i[XY_BITS-1],y_i[XY_BITS-1:1]}; end
2'b01 : begin x[0] <= {x_i[XY_BITS-1],x_i[XY_BITS-1:1]};
y[0] <= {y_i[XY_BITS-1],y_i[XY_BITS-1:1]}; end
2'b10 : begin x[0] <= {y_i[XY_BITS-1],y_i[XY_BITS-1:1]};
y[0] <= -{x_i[XY_BITS-1],x_i[XY_BITS-1:1]}; end
2'b11 : begin x[0] <= -{y_i[XY_BITS-1],y_i[XY_BITS-1:1]};
y[0] <= {x_i[XY_BITS-1],x_i[XY_BITS-1:1]}; end
default : begin x[0] <= {x_i[XY_BITS-1],x_i[XY_BITS-1:1]};
y[0] <= {y_i[XY_BITS-1],y_i[XY_BITS-1:1]}; end
endcase
z[0] <= phase_in;
data_in_buff[0] <= {x_i[XY_BITS-1],y_i[XY_BITS-1]};
end
else begin
x[0] <= 0;
y[0] <= 0;
z[0] <= 0;
data_in_buff[0] <= 0;
end
end
reg [XY_BITS*2-1:0] Modulus = 0;
wire [XY_BITS*2-1:0] Modulus_buf;
reg signed [PH_BITS - 1:0] phase_r = 0;
always @ (posedge clk) begin
case(data_in_buff[ITERATIONS])
2'b00:begin phase_r <= $signed(z[ITERATIONS]); end
2'b01:begin phase_r <= $signed(z[ITERATIONS]); end
2'b10:begin phase_r <= $signed(z[ITERATIONS]) + $signed(PHASE_COE); end
2'b11:begin phase_r <= $signed(z[ITERATIONS]) - $signed(PHASE_COE); end
endcase
Modulus[XY_BITS:0] <= x[ITERATIONS];
end
assign Modulus_buf = (Modulus * 32'd39797)>>15;
assign x_o = Modulus_buf[XY_BITS-1:0];
assign y_o = y[ITERATIONS];
assign phase_out = phase_r;
end
endgenerate
reg [ITERATIONS+1:0] v = 0;
always @ (posedge clk) begin
if (RST)
v <= 0;
else begin
v <= v << 1;
v[0] <= valid_in;
end
end
assign valid_out = v[ITERATIONS+1];
endmodule

29
user/Hardware/src/clkdiv.v Normal file
View File

@ -0,0 +1,29 @@
module clkdiv(
input clk50,
input rst_n,
output reg clkout
);
reg [15:0] cnt;
always @(posedge clk50 or negedge rst_n)
begin
if(!rst_n)
begin
cnt <= 16'b0;
clkout <= 1'b0;
end
else if(cnt == 16'd162)
begin
clkout <= 1'b1;
cnt <= cnt + 16'd1;
end
else if(cnt == 16'd325)
begin
clkout <= 1'b0;
cnt <= 16'd0;
end
else
begin
cnt <= cnt + 16'd1;
end
end
endmodule

58
user/Hardware/src/fsm_test.v Normal file
View File

@ -0,0 +1,58 @@
module fsm_test(
input clock,
input reset,
input [2 : 0] req_0,
input [2 : 0] req_1,
output reg [2 : 0] gnt_0,
output reg [2 : 0] gnt_1
);
reg [2:0] state;
parameter IDLE = 3'h1;
parameter GNT0 = 3'd2;
parameter GNT1 = 3'b100;
always @ (posedge clock) begin : FSM
if (reset == 1'b1) begin
state <= #1 IDLE;
gnt_0 <= 0;
gnt_1 <= 0;
end
else
case(state)
IDLE :
if (req_0 == 1'b1) begin
state <= #1 GNT0;
gnt_0 <= 1;
end
else if (req_1 == 1'b1) begin
gnt_1 <= 1;
state <= #1 GNT1;
end
else begin
state <= #1 IDLE; //example comment
end
GNT0 :
if (req_0 == 1'b1) begin
state <= #1 GNT0;
end
else begin
gnt_0 <= 0;
state <= #1 IDLE;
end
GNT1 :
if (req_1 == 1'b1) begin
state <= #1 GNT1;
end
else begin
gnt_1 <= 0;
state <= #1 IDLE;
end
default :
state <= #1 IDLE;
endcase
end
endmodule //module_name

33
user/Hardware/src/hello.v Normal file
View File

@ -0,0 +1,33 @@
// VHDL code for a 2-to-1 multiplexer
module mux2to1(
input wire a,
input wire b,
input wire sel,
output wire outp
);
// outports wire
wire [XY_BITS-1:0] x_o;
wire [XY_BITS-1:0] y_o;
wire [PH_BITS-1:0] phase_out;
wire valid_out;
Cordic u_Cordic(
.clk ( clk ),
.RST ( RST ),
.x_i ( x_i ),
.y_i ( y_i ),
.phase_in ( phase_in ),
.x_o ( x_o ),
.y_o ( y_o ),
.phase_out ( phase_out ),
.valid_in ( valid_in ),
.valid_out ( valid_out )
);
assign outp = sel == 1'b0 ? a : b;
endmodule

14
user/Hardware/src/hello.vhd Normal file
View File

@ -0,0 +1,14 @@
-- VHDL code for a 2-to-1 multiplexer
library IEEE;
use IEEE.std_logic_1164.all;
entity mux2to1 is
port(a, b : in std_logic;
sel : in std_logic;
outp : out std_logic);
end mux2to1;
architecture behavioral of mux2to1 is
begin
outp <= a when sel = '0' else b;
end behavioral;

80
user/Hardware/src/mult_module.v Normal file
View File

@ -0,0 +1,80 @@
// template
module template #(
parameter INPUT_WIDTH = 12,
parameter OUTPUT_WIDTH = 12
)(
input [INPUT_WIDTH
- 1 : 0]data_in,
output reg clk_in = (INPUT_WIDTH -
OUTPUT_WIDTH) ,
clk=9'hd0,
input rst_n, RST,
output [OUTPUT_WIDTH - 1 : 0] data_out
);
endmodule //template
module test # (
parameter INPUT_WIDTH = 12,
parameter OUTPUT_WIDTH = 12
)(
input clk_in,
input rst_n,
input [INPUT_WIDTH - 1 : 0] data_in ,
input [3:2] dasta_ff,
output reg signed [OUTPUT_WIDTH - 1 : 0] data_out,
output reg signed [OUTPUT_WIDTH - 1 : 0] data_ff
);
wire valid_out;
Cordic #(
.XY_BITS ( 12 ),
.PH_BITS ( 32 ),
.ITERATIONS ( 32 ),
.CORDIC_STYLE ( "ROTATE" ),
.PHASE_ACC ( "ON" ))
u_Cordic(
//input
.clk_in ( clk_in ),
.RST ( RST ),
.x_i ( x_i ),
.y_i ( y_i ),
.phase_in ( phase_in ),
.valid_in ( valid_in ),
//output
.x_o ( x_o ),
.y_o ( y_o ),
.phase_out ( phase_out ),
.valid_out ( valid_out )
//inout
);
wire [3 : 0] count_high;
wire [3 : 0] count_low;
wire over;
template u_template(
//input
.clk ( clk ),
.data ( data ),
.en ( en ),
.load ( load ),
.rst ( rst ),
.switch ( switch ),
//output
.count_high ( count_high ),
.count_low ( count_low ),
.over ( over )
//inout
);
endmodule //test

34
user/Hardware/src/netlist_test.v Normal file
View File

@ -0,0 +1,34 @@
// borrowed with some modifications from
// http://www.ee.ed.ac.uk/~gerard/Teach/Verilog/manual/Example/lrgeEx2/cooley.html
module up3down5(clock, data_in, up, down, carry_out, borrow_out, count_out, parity_out);
input [8:0] data_in;
input clock, up, down;
output reg [8:0] count_out;
output reg carry_out, borrow_out, parity_out;
reg [9:0] cnt_up, cnt_dn;
reg [8:0] count_nxt;
always @(posedge clock)
begin
cnt_dn = count_out - 3'b 101;
cnt_up = count_out + 2'b 11;
case ({up,down})
2'b 00 : count_nxt = data_in;
2'b 01 : count_nxt = cnt_dn;
2'b 10 : count_nxt = cnt_up;
2'b 11 : count_nxt = count_out;
default : count_nxt = 9'bX;
endcase
parity_out <= ^count_nxt;
carry_out <= up & cnt_up[9];
borrow_out <= down & cnt_dn[9];
count_out <= count_nxt;
end
endmodule

15
vhdl/Scientific.vhd Normal file
View File

@ -0,0 +1,15 @@
library IEEE;
use IEEE.std_logic_1164.all;
entity Scientific is
generic (
exp1: integer := 25e6;
exp2: integer := 25E6;
exp3: real := 25.0e6;
exp4: real := 50.0e+3;
exp5: real := 50.0e-3
);
port(
clk : in std_logic
);
end Scientific;

16
vhdl/based.vhd Normal file
View File

@ -0,0 +1,16 @@
library IEEE;
use IEEE.std_logic_1164.all;
entity based is port (sysclk : in std_logic);
end based;
architecture rtl of based is
signal foo, foo1, foo2, foo8, foo10, foo11, foo16 : integer;
begin
foo <= 123;
foo1 <= 123_456;
foo2 <= 2#00101101110111#;
foo8 <= 8#0177362#;
foo10 <= 10#01234#;
--foo11<= 11#01234#;
foo16 <= 16#12af#;
end rtl;

467
vhdl/bigfile.vhd Normal file
View File

@ -0,0 +1,467 @@
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- CONNECTIVITY DEFINITION
entity bigfile is
port (
-- from external pins
sysclk : in std_logic;
g_zaq_in : in std_logic_vector(31 downto 0);
g_aux : in std_logic_vector(31 downto 0);
scanb : in std_logic;
g_wrb : in std_logic;
g_rdb : in std_logic;
g_noop_clr : in std_logic_vector(31 downto 0);
swe_ed : in std_logic;
swe_lv : in std_logic;
din : in std_logic_vector(63 downto 0);
g_dout_w0x0f : in std_logic_vector(4 downto 0);
n9_bit_write : in std_logic;
-- from reset_gen block
reset : in std_logic;
alu_u : in std_logic_vector(31 downto 0);
debct_ping : in std_logic;
g_sys_in : out std_logic_vector(31 downto 0);
g_zaq_in_rst_hold : out std_logic_vector(31 downto 0);
g_zaq_hhh_enb : out std_logic_vector(31 downto 0);
g_zaq_out : out std_logic_vector(31 downto 0);
g_dout : out std_logic_vector(31 downto 0);
g_zaq_ctl : out std_logic_vector(31 downto 0);
g_zaq_qaz_hb : out std_logic_vector(31 downto 0);
g_zaq_qaz_lb : out std_logic_vector(31 downto 0);
gwerth : out std_logic_vector(31 downto 0);
g_noop : out std_logic_vector(31 downto 0);
g_vector : out std_logic_vector(8*32-1 downto 0);
swe_qaz1 : out std_logic_vector(31 downto 0)
);
end bigfile;
-- IMPLEMENTATION
architecture rtl of bigfile is
-- constants
constant g_t_klim_w0x0f : std_logic_vector(4 downto 0) := "00000";
constant g_t_u_w0x0f : std_logic_vector(4 downto 0) := "00001";
constant g_t_l_w0x0f : std_logic_vector(4 downto 0) := "00010";
constant g_t_hhh_l_w0x0f : std_logic_vector(4 downto 0) := "00011";
constant g_t_jkl_sink_l_w0x0f : std_logic_vector(4 downto 0) := "00100";
constant g_secondary_t_l_w0x0f : std_logic_vector(4 downto 0) := "00101";
constant g_style_c_l_w0x0f : std_logic_vector(4 downto 0) := "00110";
constant g_e_z_w0x0f : std_logic_vector(4 downto 0) := "00111";
constant g_n_both_qbars_l_w0x0f : std_logic_vector(4 downto 0) := "01000";
constant g_style_vfr_w0x0f : std_logic_vector(4 downto 0) := "01001";
constant g_style_klim_w0x0f : std_logic_vector(4 downto 0) := "01010";
constant g_unklimed_style_vfr_w0x0f : std_logic_vector(4 downto 0) := "01011";
constant g_style_t_y_w0x0f : std_logic_vector(4 downto 0) := "01100";
constant g_n_l_w0x0f : std_logic_vector(4 downto 0) := "01101";
constant g_n_vfr_w0x0f : std_logic_vector(4 downto 0) := "01110";
constant g_e_n_r_w0x0f : std_logic_vector(4 downto 0) := "01111";
constant g_n_r_bne_w0x0f : std_logic_vector(4 downto 0) := "10000";
constant g_n_div_rebeq_w0x0f : std_logic_vector(4 downto 0) := "10001";
constant g_alu_l_w0x0f : std_logic_vector(4 downto 0) := "10010";
constant g_t_qaz_mult_low_w0x0f : std_logic_vector(4 downto 0) := "10011";
constant g_t_qaz_mult_high_w0x0f : std_logic_vector(4 downto 0) := "10100";
constant gwerthernal_style_u_w0x0f : std_logic_vector(4 downto 0) := "10101";
constant gwerthernal_style_l_w0x0f : std_logic_vector(4 downto 0) := "10110";
constant g_style_main_reset_hold_w0x0f : std_logic_vector(4 downto 0) := "10111";
-- comment
signal g_t_klim_dout : std_logic_vector(31 downto 0);
signal g_t_u_dout : std_logic_vector(31 downto 0);
signal g_t_l_dout : std_logic_vector(31 downto 0);
signal g_t_hhh_l_dout : std_logic_vector(31 downto 0);
signal g_t_jkl_sink_l_dout : std_logic_vector(31 downto 0);
signal g_secondary_t_l_dout : std_logic_vector(31 downto 0);
signal g_style_c_l_dout : std_logic_vector(3 downto 0); -- not used
signal g_e_z_dout : std_logic_vector(31 downto 0);
signal g_n_both_qbars_l_dout : std_logic_vector(31 downto 0);
signal g_style_vfr_dout : std_logic_vector(31 downto 0);
signal g_style_klim_dout : std_logic_vector(31 downto 0);
signal g_unklimed_style_vfr_dout : std_logic_vector(31 downto 0);
signal g_style_t_y_dout : std_logic_vector(31 downto 0);
signal g_n_l_dout : std_logic_vector(31 downto 0);
signal g_n_vfr_dout : std_logic_vector(31 downto 0);
signal g_e_n_r_dout : std_logic_vector(31 downto 0);
signal g_n_r_bne_dout : std_logic;
signal g_n_div_rebeq_dout : std_logic_vector(31 downto 0);
signal g_alu_l_dout : std_logic_vector(31 downto 0);
signal g_t_qaz_mult_low_dout : std_logic_vector(31 downto 0);
signal g_t_qaz_mult_high_dout : std_logic_vector(31 downto 0);
signal gwerthernal_style_u_dout : std_logic_vector(31 downto 0);
signal gwerthernal_style_l_dout : std_logic_vector(31 downto 0);
signal g_style_main_reset_hold_dout : std_logic_vector(31 downto 0);
-- other
signal q_g_zaq_in : std_logic_vector(31 downto 0);
signal q2_g_zaq_in : std_logic_vector(31 downto 0);
signal q3_g_zaq_in : std_logic_vector(31 downto 0);
signal q_g_zaq_in_cd : std_logic_vector(3 downto 0);
signal q_g_style_vfr_dout : std_logic_vector(31 downto 0);
signal q_g_unzq : std_logic_vector(3 downto 0);
signal g_n_active : std_logic_vector(31 downto 0);
-- inter
signal g_zaq_in_y : std_logic_vector(31 downto 0);
signal g_zaq_in_y_no_dout : std_logic_vector(31 downto 0);
signal g_zaq_out_i : std_logic_vector(31 downto 0);
signal g_zaq_ctl_i : std_logic_vector(31 downto 0);
signal g_sys_in_i : std_logic_vector(31 downto 0);
signal g_sys_in_ii : std_logic_vector(31 downto 0);
signal g_dout_i : std_logic_vector(31 downto 0);
begin
-- qaz out
g_zaq_out_i <=
-- if secondary
(g_secondary_t_l_dout and (g_aux xor g_style_t_y_dout)) or
-- if alu
(g_alu_l_dout and alu_u and not g_secondary_t_l_dout) or
-- otherwise
(not g_alu_l_dout and not g_secondary_t_l_dout and g_t_u_dout);
-- Changed
g_zaq_out <= g_zaq_out_i and not g_t_jkl_sink_l_dout;
-- qaz
-- JLB
g_zaq_ctl_i <= not((g_t_l_dout and not g_t_jkl_sink_l_dout) or
(g_t_l_dout and g_t_jkl_sink_l_dout and not g_zaq_out_i));
-- mux
--vnavigatoroff
g_zaq_ctl <= g_zaq_ctl_i when scanb = '1' else "00000000000000000000000000000000";
--vnavigatoron
g_zaq_hhh_enb <= not(g_t_hhh_l_dout);
g_zaq_qaz_hb <= g_t_qaz_mult_high_dout;
g_zaq_qaz_lb <= g_t_qaz_mult_low_dout;
-- Dout
g_dout_i <= g_t_klim_dout and g_style_klim_dout when g_dout_w0x0f = g_t_klim_w0x0f else
g_t_u_dout and g_style_klim_dout when g_dout_w0x0f = g_t_u_w0x0f else
g_t_l_dout and g_style_klim_dout when g_dout_w0x0f = g_t_l_w0x0f else
g_t_hhh_l_dout and g_style_klim_dout when g_dout_w0x0f = g_t_hhh_l_w0x0f else
g_t_jkl_sink_l_dout and g_style_klim_dout when g_dout_w0x0f = g_t_jkl_sink_l_w0x0f else
g_secondary_t_l_dout and g_style_klim_dout when g_dout_w0x0f = g_secondary_t_l_w0x0f else
("0000000000000000000000000000" & g_style_c_l_dout) and g_style_klim_dout when g_dout_w0x0f = g_style_c_l_w0x0f else
g_e_z_dout when g_dout_w0x0f = g_e_z_w0x0f else
g_n_both_qbars_l_dout when g_dout_w0x0f = g_n_both_qbars_l_w0x0f else
g_style_vfr_dout and g_style_klim_dout when g_dout_w0x0f = g_style_vfr_w0x0f else
g_style_klim_dout when g_dout_w0x0f = g_style_klim_w0x0f else
g_unklimed_style_vfr_dout when g_dout_w0x0f = g_unklimed_style_vfr_w0x0f else
g_style_t_y_dout and g_style_klim_dout when g_dout_w0x0f = g_style_t_y_w0x0f else
g_n_l_dout when g_dout_w0x0f = g_n_l_w0x0f else
g_n_vfr_dout when g_dout_w0x0f = g_n_vfr_w0x0f else
g_e_n_r_dout when g_dout_w0x0f = g_e_n_r_w0x0f else
("0000000000000000000000000000000" & g_n_r_bne_dout) when g_dout_w0x0f = g_n_r_bne_w0x0f else
g_n_div_rebeq_dout when g_dout_w0x0f = g_n_div_rebeq_w0x0f else
g_alu_l_dout and g_style_klim_dout when g_dout_w0x0f = g_alu_l_w0x0f else
g_t_qaz_mult_low_dout and g_style_klim_dout when g_dout_w0x0f = g_t_qaz_mult_low_w0x0f else
g_t_qaz_mult_high_dout and g_style_klim_dout when g_dout_w0x0f = g_t_qaz_mult_high_w0x0f else
gwerthernal_style_u_dout and g_style_klim_dout when g_dout_w0x0f = gwerthernal_style_u_w0x0f else
g_style_main_reset_hold_dout and g_style_klim_dout when g_dout_w0x0f = g_style_main_reset_hold_w0x0f else
gwerthernal_style_l_dout and g_style_klim_dout when g_dout_w0x0f = gwerthernal_style_l_w0x0f else
"00000000000000000000000000000000";
g_dout <= g_dout_i when g_rdb = '0' else (others => '1');
-- this can be used to use zzz1
g_style_main_reset_hold_dout_proc :
process(sysclk)
begin
if( sysclk'event and sysclk = '1' ) then
if( scanb = '1' ) then
if( reset = '1' ) then
g_style_main_reset_hold_dout <= g_zaq_in;
end if;
--vnavigatoroff
else
g_style_main_reset_hold_dout <= q2_g_zaq_in;
end if;
--vnavigatoron
end if;
end process;
-- qaz
g_zaq_in_rst_hold <= g_style_main_reset_hold_dout;
-- Din
g_doutister_proc :
process(reset, sysclk)
variable g_dout_w0x0f_v : std_logic_vector(4 downto 0);
variable i : integer;
variable j : integer;
begin
if( reset /= '0' ) then
g_t_klim_dout <= (others => '0');
g_t_u_dout <= (others => '0');
g_t_l_dout <= (others => '0');
g_t_hhh_l_dout <= (others => '0');
g_t_jkl_sink_l_dout <= (others => '0');
g_secondary_t_l_dout <= (others => '0');
g_style_c_l_dout <= (others => '0');
g_e_z_dout <= (others => '0');
g_n_both_qbars_l_dout <= (others => '0');
g_style_klim_dout <= (others => '0');
g_style_t_y_dout <= (others => '0');
g_n_l_dout <= (others => '0');
g_e_n_r_dout <= (others => '0');
g_n_r_bne_dout <= '0';
g_n_div_rebeq_dout <= (others => '1');
g_alu_l_dout <= (others => '0');
g_t_qaz_mult_low_dout <= (others => '1'); -- NOTE Low
g_t_qaz_mult_high_dout <= (others => '0');
gwerthernal_style_u_dout <= (others => '0');
gwerthernal_style_l_dout <= (others => '0');
elsif( sysclk'event and sysclk = '1' ) then
-- clear
g_n_div_rebeq_dout <= g_n_div_rebeq_dout and not g_noop_clr;
if( g_wrb = '0' ) then
-- because we now...
for i in 0 to 1 loop
if( i = 0 ) then
g_dout_w0x0f_v := g_dout_w0x0f;
elsif( i = 1 ) then
if( n9_bit_write = '1' ) then
-- set
g_dout_w0x0f_v := g_dout_w0x0f(4 downto 1) & '1';
end if;
--vnavigatoroff
else
-- not possible but added for code coverage's sake
end if;
--vnavigatoron
case g_dout_w0x0f_v is
when g_t_klim_w0x0f => g_t_klim_dout <= din(i*32+31 downto i*32);
when g_t_u_w0x0f =>
-- output klim
for j in 0 to 31 loop
if( (g_t_klim_dout(j) = '0' and n9_bit_write = '0') or ( din(j) = '0' and n9_bit_write = '1')) then
g_t_u_dout(j) <= din(32*i+j);
end if;
end loop;
when g_t_l_w0x0f => g_t_l_dout <= din(i*32+31 downto i*32);
when g_t_hhh_l_w0x0f => g_t_hhh_l_dout <= din(i*32+31 downto i*32);
when g_t_jkl_sink_l_w0x0f => g_t_jkl_sink_l_dout <= din(i*32+31 downto i*32);
when g_secondary_t_l_w0x0f => g_secondary_t_l_dout <= din(i*32+31 downto i*32);
when g_style_c_l_w0x0f => g_style_c_l_dout(3 downto 0) <= din(3+i*32 downto i*32);
when g_e_z_w0x0f => g_e_z_dout <= din(i*32+31 downto i*32);
when g_n_both_qbars_l_w0x0f => g_n_both_qbars_l_dout <= din(i*32+31 downto i*32);
when g_style_vfr_w0x0f => null; -- read-only register
when g_style_klim_w0x0f => g_style_klim_dout <= din(i*32+31 downto i*32);
when g_unklimed_style_vfr_w0x0f => null; -- read-only register
when g_style_t_y_w0x0f => g_style_t_y_dout <= din(i*32+31 downto i*32);
when g_n_l_w0x0f => g_n_l_dout <= din(i*32+31 downto i*32);
when g_n_vfr_w0x0f => null; -- writes
when g_e_n_r_w0x0f => g_e_n_r_dout <= din(i*32+31 downto i*32);
when g_n_r_bne_w0x0f => g_n_r_bne_dout <= din(i*32);
when g_n_div_rebeq_w0x0f => g_n_div_rebeq_dout <= din(i*32+31 downto i*32) or
g_n_div_rebeq_dout; -- a '1' writes
when g_alu_l_w0x0f => g_alu_l_dout <= din(i*32+31 downto i*32);
when g_t_qaz_mult_low_w0x0f => g_t_qaz_mult_low_dout <= din(i*32+31 downto i*32);
when g_t_qaz_mult_high_w0x0f => g_t_qaz_mult_high_dout <= din(i*32+31 downto i*32);
when gwerthernal_style_u_w0x0f => gwerthernal_style_u_dout <= din(i*32+31 downto i*32);
when gwerthernal_style_l_w0x0f => gwerthernal_style_l_dout <= din(i*32+31 downto i*32);
--vnavigatoroff
when others => null;
--vnavigatoron
end case;
end loop;
end if;
end if;
end process;
-- sample
g_zaq_in_sample_proc :
process(reset, sysclk)
begin
if( reset /= '0' ) then
q_g_zaq_in <= (others => '0');
q2_g_zaq_in <= (others => '0');
q3_g_zaq_in <= (others => '0');
elsif( sysclk'event and sysclk = '1' ) then
q_g_zaq_in <= g_zaq_in;
q2_g_zaq_in <= q_g_zaq_in;
q3_g_zaq_in <= g_zaq_in_y;
end if;
end process;
-- vfr register
g_unklimed_style_vfr_dout <= q2_g_zaq_in;
-- switch
g_zaq_in_y <= g_style_t_y_dout xor q2_g_zaq_in;
-- qaz
g_style_vfr_dout <= -- top 2
(g_zaq_in_y(31 downto 4) &
-- FSM
(( g_style_c_l_dout(3 downto 0) and q_g_zaq_in_cd) or
-- otherwise just use
(not g_style_c_l_dout(3 downto 0) and g_zaq_in_y(3 downto 0))));
-- in scan mode
g_zaq_in_y_no_dout <= (g_style_t_y_dout xor g_zaq_in) when scanb = '1'
--vnavigatoroff
else g_style_t_y_dout;
--vnavigatoron
g_sys_in_i <= (-- top 28
(g_zaq_in_y_no_dout(31 downto 4) &
-- is enabled
(( g_style_c_l_dout(3 downto 0) and q_g_zaq_in_cd) or
-- otherwise just use
(not g_style_c_l_dout(3 downto 0) and g_zaq_in_y_no_dout(3 downto 0)))));
g_sys_in_ii <= (g_sys_in_i and not gwerthernal_style_l_dout) or (gwerthernal_style_u_dout and gwerthernal_style_l_dout );
g_sys_in <= g_sys_in_ii;
lpq_proc :
process(reset, sysclk)
variable i : integer;
begin
if( reset /= '0' ) then
q_g_zaq_in_cd <= (others => '0');
q_g_unzq <= (others => '1');
elsif( sysclk'event and sysclk = '1' ) then
-- sample
if( debct_ping = '1') then
-- taken
for i in 0 to 3 loop
if( g_zaq_in_y(i) /= q3_g_zaq_in(i) ) then
q_g_unzq(i) <= '1';
else
if( q_g_unzq(i) = '0' ) then
q_g_zaq_in_cd(i) <= g_zaq_in_y(i);
else
q_g_unzq(i) <= '0';
end if;
end if;
end loop;
else
for i in 0 to 3 loop
if( g_zaq_in_y(i) /= q3_g_zaq_in(i) ) then
q_g_unzq(i) <= '1';
end if;
end loop;
end if;
end if;
end process;
-- generate lqqs
sample_forwerth_proc :
process(reset, sysclk)
begin
if( reset /= '0' ) then
q_g_style_vfr_dout <= (others => '0');
elsif( sysclk'event and sysclk = '1' ) then
if( scanb = '1' ) then
q_g_style_vfr_dout <= g_style_vfr_dout;
--vnavigatoroff
else
-- in scan
q_g_style_vfr_dout <= g_style_vfr_dout or (g_zaq_out_i(31 downto 17) & "0" & g_zaq_out_i(15 downto 1) & "0") or g_zaq_ctl_i or g_sys_in_ii;
end if;
--vnavigatoron
end if;
end process;
-- generate
g_n_active <= -- 1 to 0
(((q_g_style_vfr_dout and not g_style_vfr_dout) or
-- get this
(not q_g_style_vfr_dout and g_style_vfr_dout and
g_n_both_qbars_l_dout))) and
-- must be
g_n_l_dout;
-- check for lqq active and set lqq vfr register
-- also clear
n_proc :
process(reset, sysclk)
variable i : integer;
begin
if( reset /= '0' ) then
g_n_vfr_dout <= (others => '0');
gwerth <= (others => '0');
elsif( sysclk'event and sysclk = '1' ) then
for i in 0 to 31 loop
-- lqq
-- vfr matches
if( g_n_active(i) = '1' ) then
gwerth(i) <= '1';
if( g_e_z_dout(i) = '1' ) then
-- lqq
g_n_vfr_dout(i) <= '1';
else
g_n_vfr_dout(i) <= q_g_style_vfr_dout(i);
end if;
else
-- clear
if( g_e_z_dout(i) = '0' ) then
g_n_vfr_dout(i) <= q_g_style_vfr_dout(i); -- default always assign
-- in both
if( g_n_both_qbars_l_dout(i) = '1' or g_style_vfr_dout(i) = '1') then
gwerth(i) <= '0';
end if;
else
-- write
if( g_wrb = '0' and g_dout_w0x0f = g_n_vfr_w0x0f and din(i) = '1' ) then
gwerth(i) <= '0';
g_n_vfr_dout(i) <= '0';
end if;
end if;
end if;
end loop;
end if;
end process;
----
-- Create the Lqq
createwerth_vec_proc :
process( g_n_r_bne_dout, g_e_n_r_dout)
variable imod8, idiv8 : integer;
variable i : integer;
begin
for i in 0 to 31 loop
imod8 := i mod 8;
idiv8 := i / 8;
if( g_n_r_bne_dout = '0' ) then
-- non-unique
g_vector(8*i+7 downto 8*i) <= g_e_n_r_dout(8*idiv8+7 downto 8*idiv8);
else
-- unique
if( imod8 = 0 ) then
g_vector(8*i+7 downto 8*i) <= g_e_n_r_dout(8*idiv8+7 downto 8*idiv8);
else
g_vector(8*i+7 downto 8*i) <= std_logic_vector( unsigned(g_e_n_r_dout(8*idiv8+7 downto 8*idiv8)) +
to_unsigned(imod8, 8));
end if;
end if;
end loop;
end process;
----
-- Qaz
g_noop <= g_n_div_rebeq_dout;
create_g_ack_bne_proc :
process( swe_ed,swe_lv,g_e_z_dout)
variable i : integer;
begin
for i in 0 to 31 loop
if( g_e_z_dout(i) = '1') then
swe_qaz1(i) <= swe_ed;
else
swe_qaz1(i) <= swe_lv;
end if;
end loop;
end process;
end rtl;

36
vhdl/clk.vhd Normal file
View File

@ -0,0 +1,36 @@
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
entity clk is port( reset, preset, qreset, sysclk, dsysclk, esysclk : in std_logic;
ival : in std_logic_vector(31 downto 0)
);
end clk;
architecture rtl of clk is
signal foo : std_logic_vector(10+3 downto 0);
signal baz : std_logic_vector(2 downto 0);
signal egg : std_logic_vector(4 to 7-1);
begin
pfoo: process(reset, sysclk)
begin
if( reset /= '0' ) then
foo <= (others => '1');
elsif( sysclk'event and sysclk = '1' ) then
foo <= ival(31 downto 31-(10+3));
end if;
end process;
pbaz: process(preset, dsysclk)
begin
if( preset /= '1' ) then
baz <= (others => '0');
elsif( dsysclk'event and dsysclk = '0' ) then
baz <= ival(2 downto 0);
end if;
end process;
pegg: process(qreset, esysclk)
begin
if( qreset /= '1' ) then
egg <= (others => '0');
elsif( esysclk'event and esysclk = '0' ) then
egg <= ival(6 downto 4);
end if;
end process;
end rtl;

344
vhdl/counters.vhd Normal file
View File

@ -0,0 +1,344 @@
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counters is
port(
sysclk : in std_logic;
foo_card : in std_logic;
wfoo0_baz : in std_logic;
wfoo0_blrb : in std_logic;
wfoo0_zz1pb : in std_logic;
wfoo0_turn : in std_logic_vector(31 downto 0);
debct_baz : in std_logic;
debct_blrb : in std_logic;
debct_zz1pb : in std_logic;
debct_bar : in std_logic;
debct_turn : in std_logic_vector(31 downto 0);
Z0_bar : in std_logic;
Z0_baz : in std_logic;
Z0_blrb : in std_logic;
Z0_zz1pb : in std_logic;
Z0_turn : in std_logic_vector(31 downto 0);
Y1_bar : in std_logic;
Y1_baz : in std_logic;
Y1_blrb : in std_logic;
Y1_zz1pb : in std_logic;
Y1_turn : in std_logic_vector(31 downto 0);
X2_bar : in std_logic;
X2_baz : in std_logic;
X2_blrb : in std_logic;
X2_zz1pb : in std_logic;
X2_turn : in std_logic_vector(31 downto 0);
W3_bar : in std_logic;
W3_baz : in std_logic;
W3_blrb : in std_logic;
W3_zz1pb : in std_logic;
W3_turn : in std_logic_vector(31 downto 0);
-- to engine block
Z0_cwm : out std_logic;
Z0 : out std_logic_vector(31 downto 0);
Y1_cwm : out std_logic;
Y1 : out std_logic_vector(31 downto 0);
X2_cwm : out std_logic;
X2 : out std_logic_vector(31 downto 0);
W3_cwm : out std_logic;
W3 : out std_logic_vector(31 downto 0);
wfoo0_cwm : out std_logic;
wfoo0_llwln : out std_logic_vector(31 downto 0);
debct_cwm : out std_logic;
debct_pull : out std_logic;
debct : out std_logic_vector(31 downto 0);
wdfilecardA2P : out std_logic
);
end counters;
architecture rtl of counters is
signal wfoo0_llwln_var : unsigned(31 downto 0);
signal debct_var : unsigned(31 downto 0);
signal Z0_var : unsigned(31 downto 0);
signal Y1_var : unsigned(31 downto 0);
signal X2_var : unsigned(31 downto 0);
signal W3_var : unsigned(31 downto 0);
signal main_wfoo0_cwm : std_logic;
signal do_q3p_Z0 : std_logic;
signal do_q3p_Y1 : std_logic;
signal do_q3p_X2 : std_logic;
signal do_q3p_W3 : std_logic;
signal do_q3p_wfoo0 : std_logic;
signal do_q3p_debct : std_logic;
signal Z0_cwm_i : std_logic;
signal Y1_cwm_i : std_logic;
signal X2_cwm_i : std_logic;
signal W3_cwm_i : std_logic;
signal debct_cwm_i : std_logic;
signal file_card_i : std_logic;
signal do_file_card_i : std_logic;
signal prev_do_file_card : std_logic;
begin
-----
-- form the outputs
wfoo0_llwln <= std_logic_vector(wfoo0_llwln_var);
debct <= std_logic_vector(debct_var);
Z0 <= std_logic_vector(Z0_var);
Y1 <= std_logic_vector(Y1_var);
X2 <= std_logic_vector(X2_var);
W3 <= std_logic_vector(W3_var);
Z0_cwm <= Z0_cwm_i;
Y1_cwm <= Y1_cwm_i;
X2_cwm <= X2_cwm_i;
W3_cwm <= W3_cwm_i;
debct_cwm <= debct_cwm_i;
wdfilecardA2P <= do_file_card_i;
LLWLNS :
process(foo_card, sysclk)
begin
if foo_card = '1' then
wfoo0_llwln_var <= (others => '0');
debct_var <= (others => '0');
Z0_var <= (others => '0');
Y1_var <= (others => '0');
X2_var <= (others => '0');
W3_var <= (others => '0');
wfoo0_cwm <= '0';
debct_cwm_i <= '0';
debct_pull <= '0';
Z0_cwm_i <= '0';
Y1_cwm_i <= '0';
X2_cwm_i <= '0';
W3_cwm_i <= '0';
main_wfoo0_cwm <= '0';
file_card_i <= '0';
do_q3p_wfoo0 <= '0';
do_file_card_i <= '0';
prev_do_file_card <= '0';
do_q3p_Z0 <= '0';
do_q3p_Y1 <= '0';
do_q3p_X2 <= '0';
do_q3p_W3 <= '0';
do_q3p_debct <= '0';
else
if sysclk'event and sysclk = '1' then
-- pull
debct_pull <= '0';
do_file_card_i <= '0';
----
-- wfoo0
if wfoo0_baz = '1' then
wfoo0_llwln_var <= unsigned(wfoo0_turn);
main_wfoo0_cwm <= '0';
if wfoo0_llwln_var = "00000000000000000000000000000000" then
do_q3p_wfoo0 <= '0';
else
do_q3p_wfoo0 <= '1';
end if;
else
if do_q3p_wfoo0 = '1' and wfoo0_blrb = '1' then
wfoo0_llwln_var <= wfoo0_llwln_var - 1;
if (wfoo0_llwln_var = "00000000000000000000000000000000") then
wfoo0_llwln_var <= unsigned(wfoo0_turn);
if main_wfoo0_cwm = '0' then
wfoo0_cwm <= '1';
main_wfoo0_cwm <= '1';
else
do_file_card_i <= '1';
do_q3p_wfoo0 <= '0';
end if;
end if;
end if;
end if;
if wfoo0_zz1pb = '0' then
wfoo0_cwm <= '0';
end if;
if Z0_baz = '1' then -- counter Baz
Z0_var <= unsigned(Z0_turn);
if Z0_turn = "00000000000000000000000000000000" then
do_q3p_Z0 <= '0';
else
do_q3p_Z0 <= '1';
end if;
else
if do_q3p_Z0 = '1' and Z0_blrb = '1' then
if Z0_bar = '0' then
if Z0_cwm_i = '0' then
if do_q3p_Z0 = '1' then
Z0_var <= Z0_var - 1;
if (Z0_var = "00000000000000000000000000000001") then
Z0_cwm_i <= '1';
do_q3p_Z0 <= '0';
end if;
end if;
end if;
else
Z0_var <= Z0_var - 1;
if (Z0_var = "00000000000000000000000000000000") then
Z0_cwm_i <= '1';
Z0_var <= unsigned(Z0_turn);
end if;
end if; -- Z0_bar
end if;
end if; -- Z0_blrb
if Z0_zz1pb = '0' then
Z0_cwm_i <= '0';
end if;
if Y1_baz = '1' then -- counter Baz
Y1_var <= unsigned(Y1_turn);
if Y1_turn = "00000000000000000000000000000000" then
do_q3p_Y1 <= '0';
else
do_q3p_Y1 <= '1';
end if;
elsif do_q3p_Y1 = '1' and Y1_blrb = '1' then
if Y1_bar = '0' then
if Y1_cwm_i = '0' then
if do_q3p_Y1 = '1' then
Y1_var <= Y1_var - 1;
if (Y1_var = "00000000000000000000000000000001") then
Y1_cwm_i <= '1';
do_q3p_Y1 <= '0';
end if;
end if;
end if;
else
Y1_var <= Y1_var - 1;
if (Y1_var = "00000000000000000000000000000000") then
Y1_cwm_i <= '1';
Y1_var <= unsigned(Y1_turn);
end if;
end if; -- Y1_bar
end if; -- Y1_blrb
if Y1_zz1pb = '0' then
Y1_cwm_i <= '0';
end if;
if X2_baz = '1' then -- counter Baz
X2_var <= unsigned(X2_turn);
if X2_turn = "00000000000000000000000000000000" then
do_q3p_X2 <= '0';
else
do_q3p_X2 <= '1';
end if;
elsif do_q3p_X2 = '1' and X2_blrb = '1' then
if X2_bar = '0' then
if X2_cwm_i = '0' then
if do_q3p_X2 = '1' then
X2_var <= X2_var - 1;
if (X2_var = "00000000000000000000000000000001") then
X2_cwm_i <= '1';
do_q3p_X2 <= '0';
end if;
end if;
end if;
else
X2_var <= X2_var - 1;
if (X2_var = "00000000000000000000000000000000") then --{
X2_cwm_i <= '1';
X2_var <= unsigned(X2_turn);
end if;
end if; --X2_bar
end if; -- X2_blrb
if X2_zz1pb = '0' then
X2_cwm_i <= '0';
end if;
if W3_baz = '1' then -- counter Baz
W3_var <= unsigned(W3_turn);
if W3_turn = "00000000000000000000000000000000" then
do_q3p_W3 <= '0';
else
do_q3p_W3 <= '1';
end if;
elsif do_q3p_W3 = '1' and W3_blrb = '1' then
if W3_bar = '0' then
if W3_cwm_i = '0'then
if do_q3p_W3 = '1' then
W3_var <= W3_var - 1;
if (W3_var = "00000000000000000000000000000001") then
W3_cwm_i <= '1';
do_q3p_W3 <= '0';
end if;
end if;
end if;
else
W3_var <= W3_var - 1;
if (W3_var = "00000000000000000000000000000000") then --{
W3_cwm_i <= '1';
W3_var <= unsigned(W3_turn);
end if;
end if; -- W3_bar
end if; -- W3_blrb
if W3_zz1pb = '0' then
W3_cwm_i <= '0';
end if;
if debct_baz = '1' then -- counter Baz
debct_var <= unsigned(debct_turn);
if debct_turn = "00000000000000000000000000000000" then
do_q3p_debct <= '0';
else
do_q3p_debct <= '1';
end if;
elsif do_q3p_debct = '1' and debct_blrb = '1' then
if debct_bar = '0' then
if debct_cwm_i = '0'then
if do_q3p_debct = '1' then
debct_var <= debct_var - 1;
if (debct_var = "00000000000000000000000000000001") then
debct_cwm_i <= '1';
debct_pull <= '1';
do_q3p_debct <= '0';
end if;
end if;
end if;
else
---- T
-- Continue
debct_var <= debct_var - 1;
-- ending
if (debct_var = "00000000000000000000000000000000") then --{
debct_cwm_i <= '1';
debct_pull <= '1';
debct_var <= unsigned(debct_turn);
end if;
end if; -- debct_bar
end if; -- debct_blrb
-- comment
if debct_zz1pb = '0' then
debct_cwm_i <= '0';
end if;
end if;
end if;
end process;
end rtl;

41
vhdl/dsp.vhd Normal file
View File

@ -0,0 +1,41 @@
-- Nearly useless stub, it's here to support genericmap.vhd
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
entity dsp is generic(
rst_val : std_logic := '0';
thing_size: integer := 51;
bus_width : integer := 24);
port(
-- Inputs
clk, rstn : in std_logic;
en, start : in std_logic;
param : in std_logic_vector(7 downto 0);
addr : in std_logic_vector(2 downto 0);
din : in std_logic_vector(bus_width-1 downto 0);
we : in std_logic;
memdin : out std_logic_vector(13 downto 0);
-- Outputs
dout : out std_logic_vector(bus_width-1 downto 0);
memaddr : out std_logic_vector(5 downto 0);
memdout : out std_logic_vector(13 downto 0)
);
end;
architecture rtl of dsp is
signal foo : std_logic;
signal sr : std_logic_vector(63 downto 0);
signal iparam : integer;
begin
iparam <= to_integer(unsigned(param));
process(clk) begin
-- dout <= std_logic_vector(to_unsigned(1,bus_width));
if rising_edge(clk) then
if we = '1' then
sr <= sr(thing_size-bus_width-1 downto 0) & din;
end if;
dout <= sr(iparam*bus_width+bus_width-1 downto iparam*bus_width);
end if;
end process;
end rtl;

46
vhdl/expr.vhd Normal file
View File

@ -0,0 +1,46 @@
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity expr is
generic(SIZE: positive:=2**8-1);
port(reset, sysclk, ival : in std_logic);
end expr;
architecture rtl of expr is
constant SIZE_OF : positive:=2**8-1;
signal foo : std_logic_vector(13 downto 0);
signal baz : std_logic_vector(2 downto 0);
signal bam : std_logic_vector(22 downto 0);
signal out_i : std_logic_vector(5 downto 3);
signal input_status : std_logic_vector(8 downto 0);
signal enable, debug, aux, outy, dv, value : std_logic;
signal expo : std_logic_vector(2**3-1 downto 0);
begin
-- drive input status
input_status <= -- top bits
(foo(9 downto 4) &
(( (baz(2 downto 0) and foo(3 downto 0)) or
(not baz(2 downto 0) and bam(3 downto 0)))));
-- drive based on foo
out_i(4) <=
-- if secondary enabl is set then drive aux out
(enable and (aux xor outy)) or
-- if debug is enabled
(debug and dv and not enable) or
-- otherwise we drive reg
(not debug and not enable and value);
-- not drive
pfoo: process(reset, sysclk)
begin
if( reset /= '0' ) then
foo <= (others => '0');
elsif( sysclk'event and sysclk = '0' ) then
foo(3*(2-1)) <= baz(1*(1+2)-2);
bam(foo'range) <= foo;
end if;
end process;
expo <= std_logic_vector(to_unsigned(2**4, 2**8));
end rtl;

202
vhdl/fifo.vhd Normal file
View File

@ -0,0 +1,202 @@
---------------------------------------------------------------------
-- Filename: gh_fifo_async16_sr.vhd
--
-- Description:
-- an Asynchronous FIFO
--
-- Copyright (c) 2006 by George Huber
-- an OpenCores.org Project
-- free to use, but see documentation for conditions
--
-- Revision History:
-- Revision Date Author Comment
-- -------- ---------- --------- -----------
-- 1.0 12/17/06 h lefevre Initial revision
--
--------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
USE ieee.numeric_std.all;
entity fifo is
GENERIC (data_width: INTEGER :=8 ); -- size of data bus
port (
clk_WR : in STD_LOGIC; -- write clock
clk_RD : in STD_LOGIC; -- read clock
rst : in STD_LOGIC; -- resets counters
srst : in STD_LOGIC:='0'; -- resets counters (sync with clk_WR)
WR : in STD_LOGIC; -- write control
RD : in STD_LOGIC; -- read control
D : in STD_LOGIC_VECTOR (data_width-1 downto 0);
Q : out STD_LOGIC_VECTOR (data_width-1 downto 0);
empty : out STD_LOGIC;
full : out STD_LOGIC);
end entity;
architecture rtl of fifo is
type ram_mem_type is array (15 downto 0)
of STD_LOGIC_VECTOR (data_width-1 downto 0);
signal ram_mem : ram_mem_type;
signal iempty : STD_LOGIC;
signal ifull : STD_LOGIC;
signal add_WR_CE : std_logic;
signal add_WR : std_logic_vector(4 downto 0); -- 4 bits are used to address MEM
signal add_WR_GC : std_logic_vector(4 downto 0); -- 5 bits are used to compare
signal n_add_WR : std_logic_vector(4 downto 0); -- for empty, full flags
signal add_WR_RS : std_logic_vector(4 downto 0); -- synced to read clk
signal add_RD_CE : std_logic;
signal add_RD : std_logic_vector(4 downto 0);
signal add_RD_GC : std_logic_vector(4 downto 0);
signal add_RD_GCwc : std_logic_vector(4 downto 0);
signal n_add_RD : std_logic_vector(4 downto 0);
signal add_RD_WS : std_logic_vector(4 downto 0); -- synced to write clk
signal srst_w : STD_LOGIC;
signal isrst_w : STD_LOGIC;
signal srst_r : STD_LOGIC;
signal isrst_r : STD_LOGIC;
begin
--------------------------------------------
------- memory -----------------------------
--------------------------------------------
process (clk_WR)
begin
if (rising_edge(clk_WR)) then
if ((WR = '1') and (ifull = '0')) then
--ram_mem(to_integer(unsigned(add_WR(3 downto 0)))) <= D;
end if;
end if;
end process;
--Q <= ram_mem(to_integer(unsigned(add_RD(3 downto 0))));
-----------------------------------------
----- Write address counter -------------
-----------------------------------------
add_WR_CE <= '0' when (ifull = '1') else
'0' when (WR = '0') else
'1';
n_add_WR <= std_logic_vector(unsigned(add_WR) + x"1");
process (clk_WR,rst)
begin
if (rst = '1') then
add_WR <= (others => '0');
add_RD_WS <= "11000";
add_WR_GC <= (others => '0');
elsif (rising_edge(clk_WR)) then
add_RD_WS <= add_RD_GCwc;
if (srst_w = '1') then
add_WR <= (others => '0');
add_WR_GC <= (others => '0');
elsif (add_WR_CE = '1') then
add_WR <= n_add_WR;
add_WR_GC(0) <= n_add_WR(0) xor n_add_WR(1);
add_WR_GC(1) <= n_add_WR(1) xor n_add_WR(2);
add_WR_GC(2) <= n_add_WR(2) xor n_add_WR(3);
add_WR_GC(3) <= n_add_WR(3) xor n_add_WR(4);
add_WR_GC(4) <= n_add_WR(4);
else
add_WR <= add_WR;
add_WR_GC <= add_WR_GC;
end if;
end if;
end process;
full <= ifull;
ifull <= '0' when (iempty = '1') else -- just in case add_RD_WS is reset to "00000"
'0' when (add_RD_WS /= add_WR_GC) else ---- instend of "11000"
'1';
-----------------------------------------
----- Read address counter --------------
-----------------------------------------
add_RD_CE <= '0' when (iempty = '1') else
'0' when (RD = '0') else
'1';
n_add_RD <= std_logic_vector(unsigned(add_RD) + x"1");
process (clk_RD,rst)
begin
if (rst = '1') then
add_RD <= (others => '0');
add_WR_RS <= (others => '0');
add_RD_GC <= (others => '0');
add_RD_GCwc <= "11000";
elsif (rising_edge(clk_RD)) then
add_WR_RS <= add_WR_GC;
if (srst_r = '1') then
add_RD <= (others => '0');
add_RD_GC <= (others => '0');
add_RD_GCwc <= "11000";
elsif (add_RD_CE = '1') then
add_RD <= n_add_RD;
add_RD_GC(0) <= n_add_RD(0) xor n_add_RD(1);
add_RD_GC(1) <= n_add_RD(1) xor n_add_RD(2);
add_RD_GC(2) <= n_add_RD(2) xor n_add_RD(3);
add_RD_GC(3) <= n_add_RD(3) xor n_add_RD(4);
add_RD_GC(4) <= n_add_RD(4);
add_RD_GCwc(0) <= n_add_RD(0) xor n_add_RD(1);
add_RD_GCwc(1) <= n_add_RD(1) xor n_add_RD(2);
add_RD_GCwc(2) <= n_add_RD(2) xor n_add_RD(3);
add_RD_GCwc(3) <= n_add_RD(3) xor (not n_add_RD(4));
add_RD_GCwc(4) <= (not n_add_RD(4));
else
add_RD <= add_RD;
add_RD_GC <= add_RD_GC;
add_RD_GCwc <= add_RD_GCwc;
end if;
end if;
end process;
empty <= iempty;
iempty <= '1' when (add_WR_RS = add_RD_GC) else
'0';
----------------------------------
--- sync rest stuff --------------
--- srst is sync with clk_WR -----
--- srst_r is sync with clk_RD ---
----------------------------------
process (clk_WR,rst)
begin
if (rst = '1') then
srst_w <= '0';
isrst_r <= '0';
elsif (rising_edge(clk_WR)) then
isrst_r <= srst_r;
if (srst = '1') then
srst_w <= '1';
elsif (isrst_r = '1') then
srst_w <= '0';
end if;
end if;
end process;
process (clk_RD,rst)
begin
if (rst = '1') then
srst_r <= '0';
isrst_w <= '0';
elsif (rising_edge(clk_RD)) then
isrst_w <= srst_w;
if (isrst_w = '1') then
srst_r <= '1';
else
srst_r <= '0';
end if;
end if;
end process;
end architecture;

52
vhdl/forgen.vhd Normal file
View File

@ -0,0 +1,52 @@
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
entity forgen is
generic(
bus_width : integer := 15;
TOP_GP2 : integer:= 0
);
port(
sysclk, reset, wrb : in std_logic;
din : in std_logic_vector(bus_width downto 0);
rdout: out std_logic_vector(bus_width downto 0)
);
end forgen;
architecture rtl of forgen is
component wbit1 -- register bit default 1
port(
clk : in std_logic;
wrb : in std_logic;
reset : in std_logic;
enb : in std_logic;
din : in std_logic;
dout : out std_logic);
end component;
signal regSelect : std_logic_vector(bus_width * 2 downto 0);
begin
-----------------------------------------------------
-- Reg : GP 2
-- Active : 32
-- Type : RW
-----------------------------------------------------
reg_gp2 : for bitnum in 0 to bus_width generate
wbit1_inst : wbit1
PORT MAP(
clk => sysclk,
wrb => wrb,
reset => reset,
enb => regSelect(TOP_GP2),
din => din(bitnum),
dout => rdout(bitnum)
);
end generate;
process(sysclk) begin
if sysclk'event and sysclk = '1' then
regSelect(1) <= '1';
end if;
end process;
end rtl;

37
vhdl/forloop.vhd Normal file
View File

@ -0,0 +1,37 @@
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity forloop is port(
reset, sysclk : in std_logic
);
end forloop;
architecture rtl of forloop is
signal selection : std_logic;
signal egg_timer : std_logic_vector(6 downto 0);
begin
TIMERS :
process(reset, sysclk)
variable timer_var : integer;
variable a, i, j, k : integer;
variable zz5 : std_logic_vector(31 downto 0);
variable zz : std_logic_vector(511 downto 0);
begin
if reset = '1' then
selection <= '1';
timer_var := 2;
egg_timer <= (others => '0');
elsif sysclk'event and sysclk = '1' then
-- pulse only lasts for once cycle
selection <= '0';
egg_timer <= (others => '1');
for i in 0 to j*k loop
a := a + i;
for k in a-9 downto -14 loop
zz5 := zz(31+k downto k);
end loop; -- k
end loop; -- i
end if;
end process;
end rtl;

0
vhdl/formatter_vhdl.vhd Normal file
View File

105
vhdl/genericmap.vhd Normal file
View File

@ -0,0 +1,105 @@
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
entity genericmap is
generic(
rst_val : std_logic := '0';
thing_size: integer := 201 rem 2;
bus_width : integer := 201 mod 32);
port(
clk, rstn : in std_logic;
en, start_dec : in std_logic;
addr : in std_logic_vector(2 downto 0);
din : in std_logic_vector(25 downto 0);
we : in std_logic;
pixel_in : in std_logic_vector(7 downto 0);
pix_req : in std_logic;
bip : in std_logic;
a, b : in std_logic_vector(7 downto 0);
c, load : in std_logic_vector(7 downto 0);
pack : in std_logic_vector(6 downto 0);
base : in std_logic_vector(2 downto 0);
qtd : in std_logic_vector(21 downto 0);
-- Outputs
dout : out std_logic_vector(25 downto 0);
pixel_out : out std_logic_vector(7 downto 0);
pixel_valid : out std_logic;
code : out std_logic_vector(9 downto 0);
complex : out std_logic_vector(23 downto 0);
eno : out std_logic
);
end genericmap;
architecture rtl of genericmap is
component dsp
generic(
rst_val : std_logic := '0';
thing_size: integer := 201;
bus_width : integer := 24);
port(
-- Inputs
clk, rstn : in std_logic;
en, start : in std_logic;
param : in std_logic_vector(7 downto 0);
addr : in std_logic_vector(2 downto 0);
din : in std_logic_vector(bus_width-1 downto 0);
we : in std_logic;
memdin : out std_logic_vector(13 downto 0);
-- Outputs
dout : out std_logic_vector(bus_width-1 downto 0);
memaddr : out std_logic_vector(5 downto 0);
memdout : out std_logic_vector(13 downto 0)
);
end component;
signal param : std_logic_vector(7 downto 0);
signal selection : std_logic;
signal start, enf : std_logic; -- Start and enable signals
signal memdin : std_logic_vector(13 downto 0);
signal memaddr : std_logic_vector(5 downto 0);
signal memdout : std_logic_vector(13 downto 0);
signal colour : std_logic_vector(1 downto 0);
begin
dsp_inst0 : dsp
-- default bus_width is 24
port map(
-- Inputs
clk => clk,
rstn => rstn,
en => '1',
start => '0',
param => X"42",
addr => "101",
din => "000100010001000100010001",
we => '0',
-- Outputs
dout => dout(23 downto 0),
memaddr => memaddr,
memdout => memdout
);
dsp_inst1 : dsp
generic map(
rst_val => '1',
bus_width => 16)
port map(
-- Inputs
clk => clk,
rstn => rstn,
en => '1',
start => '0',
param => X"42",
addr => "101",
din => "0001000100010001",
we => '0',
-- Outputs
dout => dout(15 downto 0),
memaddr => memaddr,
memdout => memdout
);
signextend_inst2 : entity work.signextend
port map (
i => "0000000000000000",
o => open
);
end rtl;

26
vhdl/ifchain.vhd Normal file
View File

@ -0,0 +1,26 @@
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
entity ifchain is port(
clk, rstn : in std_logic
);
end ifchain;
architecture rtl of ifchain is
type t is array (3 downto 0) of std_logic_vector(31 downto 0);
signal a : std_logic_vector(3 downto 0);
signal b : std_logic_vector(3 downto 0);
signal status : std_logic;
signal c : t;
begin
process(clk) begin
if clk'event and clk = '1' then
if b(1) & a(3 downto 2) = "001" then
status <= '1';
c(0) <= x"FFFFFFFF";
end if;
end if;
end process;
end rtl;

36
vhdl/ifchain2.vhd Normal file
View File

@ -0,0 +1,36 @@
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
entity ifchain2 is port(
clk, rstn : in std_logic;
enable: in std_logic;
result: out std_logic
);
end ifchain2;
architecture rtl of ifchain2 is
signal counter : unsigned(3 downto 0);
constant CLK_DIV_VAL : unsigned(3 downto 0) := to_unsigned(11,4);
begin
clk_src : process(clk, rstn) is
begin
if (rstn = '0') then
counter <= (others => '0');
result <= '0';
elsif (rising_edge(clk)) then -- Divide by 2 by default
if (enable = '1') then
if (counter = 0) then
counter <= CLK_DIV_VAL;
result <= '1';
else
counter <= counter - 1;
result <= '0';
end if; -- counter
end if; -- enable
end if; -- clk, rst_n
end process clk_src;
assert (counter < CLK_DIV_VAL) report "test case" severity error;
end rtl;

36
vhdl/mem.vhd Normal file
View File

@ -0,0 +1,36 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mem is
generic(
addr_width : integer := 6;
bus_width : integer := 14
);
port (
clk : in std_logic;
rstn : in std_logic; -- not implemented
en : in std_logic;
cs : in std_logic; -- not implemented
addr : in unsigned(addr_width-1 downto 0);
din : in unsigned(bus_width-1 downto 0);
dout : out unsigned(bus_width-1 downto 0)
);
end entity;
architecture rtl of mem is
signal al : unsigned(addr_width-1 downto 0) := X"00";
type mem_Type is array (255 downto 0) of unsigned(bus_width-1 downto 0);
signal mem : mem_Type;
begin
dout <= mem(to_integer(al));
process (clk) is
begin
if rising_edge(clk) then
al <= addr;
if en = '1' then
mem(to_integer(addr)) <= din;
end if;
end if;
end process;
end architecture;

85
vhdl/operators.vhd Normal file
View File

@ -0,0 +1,85 @@
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity operators is
generic (
g_and : std_logic_vector(1 downto 0) := "11" and "10";
g_or : std_logic_vector(1 downto 0) := "11" or "10";
g_nand : std_logic_vector(1 downto 0) := "11" nand "10";
g_nor : std_logic_vector(1 downto 0) := "11" nor "10";
g_xor : std_logic_vector(1 downto 0) := "11" xor "10";
g_xnor : std_logic_vector(1 downto 0) := "11" xnor "10";
g_not : std_logic_vector(1 downto 0) := not "10"
);
port (
clk_i : in std_logic
);
end entity operators;
architecture rtl of operators is
constant c_and : std_logic_vector(1 downto 0) := "11" and "10";
constant c_or : std_logic_vector(1 downto 0) := "11" or "10";
constant c_nand : std_logic_vector(1 downto 0) := "11" nand "10";
constant c_nor : std_logic_vector(1 downto 0) := "11" nor "10";
constant c_xor : std_logic_vector(1 downto 0) := "11" xor "10";
constant c_xnor : std_logic_vector(1 downto 0) := "11" xnor "10";
constant c_not : std_logic_vector(1 downto 0) := not "10";
signal s_op1 : std_logic_vector(1 downto 0);
signal s_op2 : std_logic_vector(1 downto 0);
signal s_res : std_logic_vector(1 downto 0);
signal s_int : integer;
signal s_sig : signed(7 downto 0);
signal s_uns : unsigned(7 downto 0);
begin
test_i: process(clk_i)
variable v_op1 : std_logic_vector(1 downto 0);
variable v_op2 : std_logic_vector(1 downto 0);
variable v_res : std_logic_vector(1 downto 0);
begin
if rising_edge(clk_i) then
if
(s_op1="11" and s_op2="00") or
(s_op1="11" or s_op2="00") or
(s_op1="11" nand s_op2="00") or
(s_op1="11" nor s_op2="00") or
(not (s_op1="11"))
then
s_res <= s_op1 and s_op2;
s_res <= s_op1 or s_op2;
v_res := v_op1 nand v_op2;
v_res := v_op1 nor v_op2;
s_res <= s_op1 xor s_op2;
v_res := v_op1 xnor v_op2;
s_res <= not s_op1;
s_int <= abs(s_int);
s_sig <= abs(s_sig);
s_sig <= s_sig sll 2;
s_sig <= s_sig srl to_integer(s_sig);
s_uns <= s_uns sll to_integer(s_uns);
s_uns <= s_uns srl 9;
s_sig <= shift_left(s_sig,2);
s_sig <= shift_right(s_sig,to_integer(s_sig));
-- s_uns <= s_uns ror 3; -- Not yet implemented
-- s_uns <= s_uns rol to_integer(s_uns); -- Not yet implemented
-- s_uns <= rotate_right(s_uns,3); -- Not yet implemented
-- s_uns <= rotate_left(s_uns,to_integer(s_uns)); -- Not yet implemented
s_sig <= s_sig rem s_int;
s_sig <= s_sig mod s_int;
end if;
if
s_sig = signed(s_uns) or unsigned(s_sig) /= s_uns or s_sig < "101010101" or
s_sig <= signed(s_uns) or unsigned(s_sig) > s_uns or s_sig >= "00000101"
then
s_sig <= s_sig + s_sig;
s_sig <= s_sig - s_sig;
s_sig <= s_sig * s_sig;
s_sig <= s_sig / s_sig;
s_sig <= s_sig(7 downto 4) & "10" & signed(s_uns(1 downto 0));
s_int <= 2 ** 3;
end if;
end if;
end process test_i;
end architecture rtl;

32
vhdl/partselect.vhd Normal file
View File

@ -0,0 +1,32 @@
library IEEE;
use IEEE.std_logic_1164.all;
entity partselect is
port(
clk_i : in std_logic
);
end entity partselect;
architecture rtl of partselect is
signal big_sig : std_logic_vector(31 downto 0);
signal lit_sig : std_logic_vector(0 to 31);
signal i : integer:=8;
begin
test_i: process(clk_i)
variable big_var : std_logic_vector(31 downto 0);
variable lit_var : std_logic_vector(0 to 31);
variable j : integer;
begin
if rising_edge(clk_i) then
big_sig(31 downto 24) <= big_sig(7 downto 0);
big_var(31 downto 24) := big_var(7 downto 0);
lit_sig(i*3 to i*3+7) <= lit_sig(0 to 7);
lit_var(j*3 to j*3+8) := lit_var(j*0 to 8+j*0);
--
big_sig(i*3+8 downto i*3) <= big_sig(8 downto 0);
big_var(j*3+8 downto j*3) := big_var(j*0+8 downto j*0);
end if;
end process test_i;
end architecture rtl;

17
vhdl/signextend.vhd Normal file
View File

@ -0,0 +1,17 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity signextend is
port(
i : in std_logic_vector(15 downto 0);
o : out std_logic_vector(31 downto 0)
);
end entity signextend;
architecture behavior of signextend is
begin
o(31 downto 24) <= (others => '0');
o(23 downto 16) <= (others => i(15));
o(15 downto 0) <= i;
end architecture behavior;

191
vhdl/test.vhd Normal file
View File

@ -0,0 +1,191 @@
-- Project: VHDL to Verilog RTL translation
-- Revision: 1.0
-- Date of last Revision: February 27 2001
-- Designer: Vincenzo Liguori
-- vhd2vl test file
-- This VHDL file exercises vhd2vl
LIBRARY IEEE;
USE IEEE.std_logic_1164.all, IEEE.numeric_std.all;
entity test is port(
-- Inputs
clk, rstn : in std_logic;
en, start_dec : in std_logic;
addr : in std_logic_vector(2 downto 0);
din : in std_logic_vector(25 downto 0);
we : in std_logic;
pixel_in : in std_logic_vector(7 downto 0);
pix_req : in std_logic;
config1, bip : in std_logic;
a, b : in std_logic_vector(7 downto 0);
c, load : in std_logic_vector(7 downto 0);
pack : in std_logic_vector(6 downto 0);
base : in std_logic_vector(2 downto 0);
qtd : in std_logic_vector(21 downto 0);
-- Outputs
dout : out std_logic_vector(23 downto 0);
pixel_out : out std_logic_vector(7 downto 0);
pixel_valid : out std_logic;
code : out std_logic_vector(9 downto 0);
code1 : out std_logic_vector(9 downto 0);
complex : out std_logic_vector(23 downto 0);
eno : out std_logic
);
end test;
architecture rtl of test is
-- Components declarations are ignored by vhd2vl
-- but they are still parsed
component dsp port(
-- Inputs
clk, rstn : in std_logic;
en, start : in std_logic;
param : in std_logic_vector(7 downto 0);
addr : in std_logic_vector(2 downto 0);
din : in std_logic_vector(23 downto 0);
we : in std_logic;
memdin : out std_logic_vector(13 downto 0);
-- Outputs
dout : out std_logic_vector(23 downto 0);
memaddr : out std_logic_vector(5 downto 0);
memdout : out std_logic_vector(13 downto 0)
);
end component;
component mem port(
-- Inputs
clk, rstn : in std_logic;
en : in std_logic;
cs : in std_logic;
addr : in std_logic_vector(5 downto 0);
din : in std_logic_vector(13 downto 0);
-- Outputs
dout : out std_logic_vector(13 downto 0)
);
end component;
type state is (red, green, blue, yellow);
signal status : state;
constant PARAM1 : std_logic_vector(7 downto 0):="01101101";
constant PARAM2 : std_logic_vector(7 downto 0):="11001101";
constant PARAM3 : std_logic_vector(7 downto 0):="00010111";
signal param : std_logic_vector(7 downto 0);
signal selection : std_logic := '0';
signal start, enf : std_logic; -- Start and enable signals
signal memdin : std_logic_vector(13 downto 0);
signal memaddr : std_logic_vector(5 downto 0);
signal memdout : std_logic_vector(13 downto 0);
signal colour : std_logic_vector(1 downto 0);
begin
param <= PARAM1 when config1 = '1' else PARAM2 when status = green else PARAM3;
-- Synchronously process
process(clk) begin
if clk'event and clk = '1' then
pixel_out <= pixel_in xor "11001100";
end if;
end process;
-- Synchronous process
process(clk) begin
if rising_edge(clk) then
case status is
when red => colour <= "00";
when green => colour <= B"01";
when blue => colour <= "10";
when others => colour <= "11";
end case;
end if;
end process;
-- Synchronous process with asynch reset
process(clk,rstn) begin
if rstn = '0' then
status <= red;
elsif rising_edge(clk) then
case status is
when red =>
if pix_req = '1' then
status <= green;
end if;
when green =>
if a(3) = '1' then
start <= start_dec;
status <= blue;
elsif (b(5) & a(3 downto 2)) = "001" then
status <= yellow;
end if;
when blue =>
status <= yellow;
when others =>
start <= '0';
status <= red;
end case;
end if;
end process;
-- Example of with statement
with memaddr(2 downto 0) select
code(9 downto 2) <= "110" & pack(6 downto 2) when "000" | "110",
"11100010" when "101",
(others => '1') when "010",
(others => '0') when "011",
std_logic_vector(unsigned(a) + unsigned(b)) when others;
code1(1 downto 0) <= a(6 downto 5) xor (a(4) & b(6));
-- Asynch process
decode : process(we, addr, config1, bip) begin
if we = '1' then
if addr(2 downto 0) = "100" then
selection <= '1';
elsif (b & a) = a & b and bip = '0' then
selection <= config1;
else
selection <= '1';
end if;
else
selection <= '0';
end if;
end process decode;
-- Components instantiation
dsp_inst : dsp port map(
-- Inputs
clk => clk,
rstn => rstn,
en => en,
start => start,
param => param,
addr => addr,
din => din(23 downto 0),
we => we,
memdin => memdin,
-- Outputs
dout => dout,
memaddr => memaddr,
memdout => memdout
);
dsp_mem : mem port map(
-- Inputs
clk => clk,
rstn => rstn,
en => en,
cs => selection,
addr => memaddr,
din => memdout,
-- Outputs
dout => memdin
);
complex <= enf & (std_logic_vector("110" * unsigned(load))) & qtd(3 downto 0) & base & "11001";
enf <= '1' when c < "1000111" else '0';
eno <= enf;
end rtl;

74
vhdl/todo.vhd Normal file
View File

@ -0,0 +1,74 @@
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity todo is
generic(
INBYLEVEL : boolean:=FALSE
);
port (
clk_i : in std_logic;
data_i : in std_logic_vector(7 downto 0);
data_o : out std_logic_vector(7 downto 0)
);
end todo;
architecture rtl of todo is
type mem_type is array (0 to 255) of integer;
signal mem : mem_type;
signal int : integer;
signal uns : unsigned(7 downto 0);
constant BYTES : positive:=4;
constant WIDTH : positive:=BYTES*8;
signal index : natural range 0 to BYTES-1;
signal comma : std_logic_vector(BYTES*3-1 downto 0);
-- (others => (others => '0')) must be replaced by an initial block with a for
-- or something similar.
--type ff_array is array (0 to 255) of std_logic_vector(7 downto 0);
--signal data_r : ff_array :=(others => (others => '0'));
begin
--**************************************************************************
-- Wrong translations
--**************************************************************************
--
test_i: process(clk_i)
-- iverilog: variable declaration assignments are only allowed at the module level.
variable i : integer:=8;
begin
for i in 0 to 7 loop
if i=4 then
exit; -- iverilog: error: malformed statement
end if;
end loop;
end process test_i;
-- indexed part-select not applied
do_boundary: process (clk_i)
begin
if rising_edge(clk_i) then
for i in 0 to BYTES-1 loop
if comma(BYTES*2+i-1 downto BYTES+i)=comma(3 downto 0) then
index <= i;
end if;
end loop;
end if;
end process;
comma <= comma(BYTES+index-1 downto index);
--**************************************************************************
-- Translations which abort with syntax error (uncomment to test)
--**************************************************************************
-- Concatenation in port assignament fail
-- uns <= "0000" & X"1"; -- It is supported
-- dut1_i: entity work.signextend
-- port map (
-- i => "00000000" & X"11", -- But here fail
-- o => open
-- );
-- Unsupported generate with boolean?
-- in_by_level:
-- if INBYLEVEL generate
-- int <= 9;
-- end generate in_by_level;
end rtl;

21
vhdl/wbit1.vhd Normal file
View File

@ -0,0 +1,21 @@
-- Nearly useless stub, it's here to support generate.vhd
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
entity wbit1 is
port(
clk : in std_logic;
wrb : in std_logic;
reset : in std_logic;
enb : in std_logic;
din : in std_logic;
dout : out std_logic);
end;
architecture rtl of wbit1 is
signal foo : std_logic;
begin
process(clk) begin
dout <= '1';
end process;
end rtl;

27
vhdl/whileloop.vhd Normal file
View File

@ -0,0 +1,27 @@
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity whileloop is port(
A : in integer;
Z : out std_logic_vector(3 downto 0)
);
end whileloop;
architecture rtl of whileloop is
begin
process (A)
variable I : integer range 0 to 4;
begin
Z <= "0000";
I := 0;
while (I <= 3) loop
if (A = I) then
Z(I) <= '1';
end if;
I := I + 1;
end loop;
end process;
end rtl;

34
vhdl/withselect.vhd Normal file
View File

@ -0,0 +1,34 @@
LIBRARY IEEE;
USE IEEE.std_logic_1164.all, IEEE.numeric_std.all;
entity withselect is
generic(
dog_width : std_logic_vector(7 downto 0) := "10101100";
bus_width : integer := 32
);
port( reset, sysclk : in std_logic;
a, b, enf, load, qtd, base: in std_logic_vector(bus_width downto 0)
);
end withselect;
architecture rtl of withselect is
signal foo : std_logic_vector(1+1 downto 0);
signal code,code1: std_logic_vector(9 downto 0);
signal egg : std_logic_vector(324 to 401);
signal baz : std_logic_vector(bus_width*3-1 to bus_width*4);
signal complex : std_logic_vector(31 downto 0);
begin
-- Example of with statement
with foo(2 downto 0) select
code(9 downto 2) <= "110" & egg(325 to 329) when "000" | "110",
"11100010" when "101",
(others => '1') when "010",
(others => '0') when "011",
std_logic_vector(unsigned(a) + unsigned(b)) when others;
code1(1 downto 0) <= a(6 downto 5) xor (a(4) & b(6));
foo <= (others => '0');
egg <= (others => '0');
baz <= (others => '1');
complex <= enf & (std_logic_vector("110" * unsigned(load))) & qtd(3 downto 0) & base & "11001";
end rtl;

17
vlog/dependence_test/.vscode/property.json vendored Normal file
View File

@ -0,0 +1,17 @@
{
"toolChain": "xilinx",
"prjName": {
"PL": "template"
},
"soc": {
"core": "none"
},
"arch": {
"hardware": {
"sim": "./",
"src": "./"
}
},
"enableShowLog": false,
"device": "none"
}

17
vlog/dependence_test/child_1.v Normal file
View File

@ -0,0 +1,17 @@
module dependence_1 (
// this is a test
input a, b, c,
// a test
output Result // balabalabala for result
);
// a & b | ((b & c) & (b | c))
// &=*, |=+ AB + BC(B+C)
// Distribute AB + BBC + BCC
// Simplify AA = A AB + BC + BC
// Simplify A + A = A AB + BC
// Factor B(A+C)
assign Result = a & (b | c);
endmodule

8
vlog/dependence_test/child_2.v Normal file
View File

@ -0,0 +1,8 @@
module dependence_2 (
input a, b, c,
output Q
);
assign Q = a & b | ((b & c) & (b | c));
endmodule

23
vlog/dependence_test/head_1.v Normal file
View File

@ -0,0 +1,23 @@
`define cow 34
module dependence_1 (
input port_a, port_b, port_c,
output out_q
);
// a & b | ((b & c) & (b | c))
// &=*, |=+ AB + BC(B+C)
// Distribute AB + BBC + BCC
// Simplify AA = A AB + BC + BC
// Simplify A + A = A AB + BC
// Factor B(A+C)
assign out_q = port_b & (port_a | port_c);
endmodule
module test_1 (
input port_a, port_b,
output Q
);
assign Q = port_b & port_a;
endmodule

6
vlog/dependence_test/hello.v Normal file
View File

@ -0,0 +1,6 @@
module hello;
initial begin
$display("hello world");
$finish;
end
endmodule

69
vlog/dependence_test/parent.v Normal file
View File

@ -0,0 +1,69 @@
/*
* EN: A simple demo to test search order of dependence
* current file -> macro include -> whole project
* expect dependence_1 from child_1.v (macro include)
* expect dependence_2 from child_2.v (whole project)
* cannot find dependence_3 `main
*/
`include "child_1.v"
`include "child_2.v"
`define main out
module Main (
// Main input
input a, b, c,
// Main output
output Qus, Qs, `main
);
dependence_1 u_dependence_1(
.a(a),
.b(b),
.c(c),
.Result(Qus)
);
dependence_2 u_dependence_2(
.a(a),
.b(b),
.c(c),
.Q(Qs)
);
dependence_3 u_dependence_3(
.a(a),
.b(b),
.c(c),
.Q(Qs)
);
endmodule
/* @wavedrom this is wavedrom demo1
{
signal : [
{ name: "clk", wave: "p......" },
{ name: "bus", wave: "x.34.5x", data: "head body tail" },
{ name: "wire", wave: "0.1..0." }
]
}
*/
/* @wavedrom this is wavedrom demo2
{
signal: [
{ name: "pclk", wave: "p......." },
{ name: "Pclk", wave: "P......." },
{ name: "nclk", wave: "n......." },
{ name: "Nclk", wave: "N......." },
{},
{ name: "clk0", wave: "phnlPHNL" },
{ name: "clk1", wave: "xhlhLHl." },
{ name: "clk2", wave: "hpHplnLn" },
{ name: "clk3", wave: "nhNhplPl" },
{ name: "clk4", wave: "xlh.L.Hx" },
]}
*/

BIN
vlog/dependence_test/pdf/parent.pdf Normal file
View File

Binary file not shown.

10
vlog/dependence_test/readme_cn.md Normal file
View File

@ -0,0 +1,10 @@
# dependence_test 文件夹
用于测试依赖检测
在vlog中分有两种依赖形式
1. 分module文件依赖，该依赖取决于解释器的自动检索。
【注】: 在存在同名module的时候很大程度上会导致依赖出错，因此不建议使用同名module，或者在同名的时 候使用 `include 依赖方式
2. 使用 include 引用文件的方式进行模块间的依赖，该方式可以精确定位依赖项。
【注】: 在使用 `include 依赖方式时该插件会自动去除对于include文件中有同名的其他文件。

26
vlog/dependence_test/simulation/icarus/out.vvp Normal file
View File

@ -0,0 +1,26 @@
#! /c/Source/iverilog-install/bin/vvp
:ivl_version "12.0 (devel)" "(s20150603-1110-g18392a46)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "C:\iverilog\lib\ivl\system.vpi";
:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
:vpi_module "C:\iverilog\lib\ivl\v2009.vpi";
S_0000023701252df0 .scope package, "$unit" "$unit" 2 1;
.timescale 0 0;
S_0000023701252f80 .scope module, "hello" "hello" 3 1;
.timescale 0 0;
.scope S_0000023701252f80;
T_0 ;
%vpi_call/w 3 3 "$display", "hello world" {0 0 0};
%vpi_call/w 3 4 "$finish" {0 0 0};
%end;
.thread T_0;
# The file index is used to find the file name in the following table.
:file_names 4;
"N/A";
"<interactive>";
"-";
"e:/Project/Digial-IDE/digital-ide/src/test/vlog/dependence_test/hello.v";

11
vlog/formatter_test/formatter_test.v Normal file
View File

@ -0,0 +1,11 @@
module formatter_vlog #(
parameter INPUT_WIDTH = 12,
parameter OUTPUT_WIDTH = 12
) (
input clk_in,
input rst_n,
input [INPUT_WIDTH - 1 : 0]data_in,
output [OUTPUT_WIDTH - 1 : 0]data_out
);
reg [3:0] cnt; always @(posedge clk_in or posedge rst_n) begin if(rst_n) begin cnt<=4'h0; end else begin cnt<=cnt+4'h1; end end endmodule //module_name

58
vlog/fsm_test/fsm_test.v Normal file
View File

@ -0,0 +1,58 @@
module fsm_test(
input clock,
input reset,
input [2 : 0] req_0,
input [2 : 0] req_1,
output reg [2 : 0] gnt_0,
output reg [2 : 0] gnt_1
);
reg [2:0] state;
parameter IDLE = 3'h1;
parameter GNT0 = 3'd2;
parameter GNT1 = 3'b100;
always @ (posedge clock) begin : FSM
if (reset == 1'b1) begin
state <= #1 IDLE;
gnt_0 <= 0;
gnt_1 <= 0;
end
else
case(state)
IDLE :
if (req_0 == 1'b1) begin
state <= #1 GNT0;
gnt_0 <= 1;
end
else if (req_1 == 1'b1) begin
gnt_1 <= 1;
state <= #1 GNT1;
end
else begin
state <= #1 IDLE; //example comment
end
GNT0 :
if (req_0 == 1'b1) begin
state <= #1 GNT0;
end
else begin
gnt_0 <= 0;
state <= #1 IDLE;
end
GNT1 :
if (req_1 == 1'b1) begin
state <= #1 GNT1;
end
else begin
gnt_1 <= 0;
state <= #1 IDLE;
end
default :
state <= #1 IDLE;
endcase
end
endmodule //module_name

33
vlog/netlist_test/netlist_test.v Normal file
View File

@ -0,0 +1,33 @@
// borrowed with some modifications from
// http://www.ee.ed.ac.uk/~gerard/Teach/Verilog/manual/Example/lrgeEx2/cooley.html
module up3down5(clock, data_in, up, down, carry_out, borrow_out, count_out, parity_out);
input [8:0] data_in;
input clock, up, down;
output reg [8:0] count_out;
output reg carry_out, borrow_out, parity_out;
reg [9:0] cnt_up, cnt_dn;
reg [8:0] count_nxt;
always @(posedge clock)
begin
cnt_dn = count_out - 3'b 101;
cnt_up = count_out + 2'b 11;
case ({up,down})
2'b 00 : count_nxt = data_in;
2'b 01 : count_nxt = cnt_dn;
2'b 10 : count_nxt = cnt_up;
2'b 11 : count_nxt = count_out;
default : count_nxt = 9'bX;
endcase
parity_out <= ^count_nxt;
carry_out <= up & cnt_up[9];
borrow_out <= down & cnt_dn[9];
count_out <= count_nxt;
end
endmodule

257
vlog/parse_test/Cordic.v Normal file
View File

@ -0,0 +1,257 @@
`timescale 1ns / 1ps
module Cordic #(
parameter XY_BITS = 12,
parameter PH_BITS = 32,
parameter ITERATIONS = 32,
parameter CORDIC_STYLE = "ROTATE",
parameter PHASE_ACC = "ON"
)(
input clk,
input RST,
input signed [XY_BITS-1:0] x_i,
input signed [XY_BITS-1:0] y_i,
input signed [PH_BITS-1:0] phase_in,
input valid_in,
output valid_out,
output signed [XY_BITS-1:0] x_o,
output signed [XY_BITS-1:0] y_o,
output signed [PH_BITS-1:0] phase_out
);
localparam [XY_BITS-1:0] K_COS = (0.607252935 * 2**(XY_BITS-1))-2;
/*
//360°--2^16,phase_in = 16bits (input [15:0] phase_in)
//1°--2^16/360
*/
function [PH_BITS-1:0] tanangle;
input [4:0] i;
begin
case (i)
5'b00000: tanangle = (32'h20000000 >> (32 - PH_BITS)); //tan = 1/2^1 = 1/2
5'b00001: tanangle = (32'h12e4051e >> (32 - PH_BITS)); //tan = 1/2^2 = 1/4
5'b00010: tanangle = (32'h09fb385b >> (32 - PH_BITS)); //tan = 1/2^3 = 1/8
5'b00011: tanangle = (32'h051111d4 >> (32 - PH_BITS)); //tan = 1/2^4 = 1/16
5'b00100: tanangle = (32'h028b0d43 >> (32 - PH_BITS)); //tan = 1/2^5 = 1/32
5'b00101: tanangle = (32'h0145d7e1 >> (32 - PH_BITS)); //tan = 1/2^6 = 1/64
5'b00110: tanangle = (32'h00a2f61e >> (32 - PH_BITS)); //tan = 1/2^7 = 1/128
5'b00111: tanangle = (32'h00517c55 >> (32 - PH_BITS)); //tan = 1/2^8 = 1/256
5'b01000: tanangle = (32'h0028be53 >> (32 - PH_BITS)); //tan = 1/2^9 = 1/512
5'b01001: tanangle = (32'h00145f2f >> (32 - PH_BITS)); //tan = 1/2^10 = 1/1024
5'b01010: tanangle = (32'h000a2f98 >> (32 - PH_BITS)); //tan = 1/2^11 = 1/2048
5'b01011: tanangle = (32'h000517cc >> (32 - PH_BITS)); //tan = 1/2^12 = 1/4096
5'b01100: tanangle = (32'h00028be6 >> (32 - PH_BITS)); //tan = 1/2^13 = 1/8192
5'b01101: tanangle = (32'h000145f3 >> (32 - PH_BITS)); //tan = 1/2^14 = 1/16384
5'b01110: tanangle = (32'h0000a2fa >> (32 - PH_BITS)); //tan = 1/2^15 = 1/32768
5'b01111: tanangle = (32'h0000517d >> (32 - PH_BITS)); //tan = 1/2^16 = 1/65536
5'b10000: tanangle = (32'h000028be >> (32 - PH_BITS)); //tan = 1/2^17 = 1/131072
5'b10001: tanangle = (32'h0000145f >> (32 - PH_BITS)); //tan = 1/2^18 = 1/262144
5'b10010: tanangle = (32'h00000a30 >> (32 - PH_BITS)); //tan = 1/2^19 = 1/524288
5'b10011: tanangle = (32'h00000518 >> (32 - PH_BITS)); //tan = 1/2^20 = 1/1048576
5'b10100: tanangle = (32'h0000028c >> (32 - PH_BITS)); //tan = 1/2^21 = 1/2097152
5'b10101: tanangle = (32'h00000146 >> (32 - PH_BITS)); //tan = 1/2^22 = 1/4194304
5'b10110: tanangle = (32'h000000a3 >> (32 - PH_BITS)); //tan = 1/2^23 = 1/8388608
5'b10111: tanangle = (32'h00000051 >> (32 - PH_BITS)); //tan = 1/2^24 = 1/16777216
5'b11000: tanangle = (32'h00000029 >> (32 - PH_BITS)); //tan = 1/2^25 = 1/33554432
5'b11001: tanangle = (32'h00000014 >> (32 - PH_BITS)); //tan = 1/2^26 = 1/67108864
5'b11010: tanangle = (32'h0000000a >> (32 - PH_BITS)); //tan = 1/2^27 = 1/134217728
5'b11011: tanangle = (32'h00000005 >> (32 - PH_BITS)); //tan = 1/2^28 = 1/268435456
5'b11100: tanangle = (32'h00000003 >> (32 - PH_BITS)); //tan = 1/2^29 = 1/536870912
5'b11101: tanangle = (32'h00000001 >> (32 - PH_BITS)); //tan = 1/2^30 = 1/1073741824
5'b11110: tanangle = (32'h00000001 >> (32 - PH_BITS)); //tan = 1/2^31 = 1/2147483648
5'b11111: tanangle = (32'h00000000 >> (32 - PH_BITS)); //tan = 1/2^32 = 1/4294967296
endcase
end
endfunction
reg [1:0] data_in_buff [ITERATIONS:0];
reg signed [XY_BITS-1:0] x [ITERATIONS:0];
reg signed [XY_BITS-1:0] y [ITERATIONS:0];
reg signed [PH_BITS-1:0] z [ITERATIONS:0];
integer m;
initial begin
for (m = 0; m<=ITERATIONS; m=m+1) begin
x[m] = 0;
end
end
integer n;
initial begin
for (n = 0; n<=ITERATIONS; n=n+1) begin
y[n] = 0;
end
end
integer s;
initial begin
for (s = 0; s<=ITERATIONS; s=s+1) begin
z[s] = 0;
end
end
integer k;
initial begin
for (k = 0; k<=ITERATIONS; k=k+1) begin
data_in_buff[k] = 0;
end
end
genvar i;
generate for(i=0;i<ITERATIONS;i=i+1) begin : CORDIC
always @ (posedge clk) begin
if (RST) begin
x[i+1] <= 0;
y[i+1] <= 0;
z[i+1] <= 0;
end
else begin
if (CORDIC_STYLE == "ROTATE") begin
if (z[i] < 0) begin
x[i+1] <= x[i] + (y[i]>>>i);
y[i+1] <= y[i] - (x[i]>>>i);
z[i+1] <= z[i] + tanangle(i);
end
else begin
x[i+1] <= x[i] - (y[i]>>>i);
y[i+1] <= y[i] + (x[i]>>>i);
z[i+1] <= z[i] - tanangle(i);
end
end
else if(CORDIC_STYLE == "VECTOR") begin
if (y[i] > 0) begin
x[i+1] <= x[i] + (y[i]>>>i);
y[i+1] <= y[i] - (x[i]>>>i);
z[i+1] <= z[i] + tanangle(i);
end else begin
x[i+1] <= x[i] - (y[i]>>>i);
y[i+1] <= y[i] + (x[i]>>>i);
z[i+1] <= z[i] - tanangle(i);
end
end
end
end
always @ (posedge clk) begin
data_in_buff[i+1] <= data_in_buff[i];
end
end
endgenerate
generate if (CORDIC_STYLE == "ROTATE") begin : IQ_Gen
reg [PH_BITS - 1 : 0] Phase_input = 0;
if (PHASE_ACC == "ON") begin
reg [PH_BITS - 1 : 0] addr_r0 = 0;
always @(posedge clk) begin
addr_r0 <= addr_r0 + phase_in;
end
always @(posedge clk) begin
Phase_input <= addr_r0;
end
end
else if (PHASE_ACC == "OFF") begin
always @(posedge clk) begin
Phase_input <= phase_in;
end
end
always @(posedge clk) begin
if(valid_in & (~RST)) begin
x[0] <= K_COS;
y[0] <= 0;
z[0] <= Phase_input[PH_BITS - 3 : 0];
data_in_buff[0] <= Phase_input[PH_BITS - 1 : PH_BITS - 2];
end
else begin
x[0] <= 0;
y[0] <= 0;
z[0] <= 0;
data_in_buff[0] <= 0;
end
end
reg signed [XY_BITS-1:0] cos = 0;
reg signed [XY_BITS-1:0] sin = 0;
always @ (posedge clk) begin
case(data_in_buff[ITERATIONS])
2'b00:begin //if the phase is in first quadrant,the sin(X)=sin(A),cos(X)=cos(A)
cos <= x[ITERATIONS];
sin <= y[ITERATIONS];
end
2'b01:begin //if the phase is in second quadrant,the sin(X)=sin(A+90)=cosA,cos(X)=cos(A+90)=-sinA
cos <= ~(y[ITERATIONS]) + 1'b1;//-sin
sin <= x[ITERATIONS];//cos
end
2'b10:begin //if the phase is in third quadrant,the sin(X)=sin(A+180)=-sinA,cos(X)=cos(A+180)=-cosA
cos <= ~(x[ITERATIONS]) + 1'b1;//-cos
sin <= ~(y[ITERATIONS]) + 1'b1;//-sin
end
2'b11:begin //if the phase is in forth quadrant,the sin(X)=sin(A+270)=-cosA,cos(X)=cos(A+270)=sinA
cos <= y[ITERATIONS];//sin
sin <= ~(x[ITERATIONS]) + 1'b1;//-cos
end
endcase
end
assign x_o = cos;
assign y_o = sin;
assign phase_out = z[ITERATIONS];
end
endgenerate
generate if (CORDIC_STYLE == "VECTOR") begin : Demodule_Gen
localparam signed [PH_BITS-1:0] PHASE_COE = (2**(PH_BITS-2)) - 1;
//localparam MODUIUS_COE = ;
always @(posedge clk) begin
if(valid_in & (~RST)) begin
case ({x_i[XY_BITS-1],y_i[XY_BITS-1]})
2'b00 : begin x[0] <= {x_i[XY_BITS-1],x_i[XY_BITS-1:1]};
y[0] <= {y_i[XY_BITS-1],y_i[XY_BITS-1:1]}; end
2'b01 : begin x[0] <= {x_i[XY_BITS-1],x_i[XY_BITS-1:1]};
y[0] <= {y_i[XY_BITS-1],y_i[XY_BITS-1:1]}; end
2'b10 : begin x[0] <= {y_i[XY_BITS-1],y_i[XY_BITS-1:1]};
y[0] <= -{x_i[XY_BITS-1],x_i[XY_BITS-1:1]}; end
2'b11 : begin x[0] <= -{y_i[XY_BITS-1],y_i[XY_BITS-1:1]};
y[0] <= {x_i[XY_BITS-1],x_i[XY_BITS-1:1]}; end
default : begin x[0] <= {x_i[XY_BITS-1],x_i[XY_BITS-1:1]};
y[0] <= {y_i[XY_BITS-1],y_i[XY_BITS-1:1]}; end
endcase
z[0] <= phase_in;
data_in_buff[0] <= {x_i[XY_BITS-1],y_i[XY_BITS-1]};
end
else begin
x[0] <= 0;
y[0] <= 0;
z[0] <= 0;
data_in_buff[0] <= 0;
end
end
reg [XY_BITS*2-1:0] Modulus = 0;
wire [XY_BITS*2-1:0] Modulus_buf;
reg signed [PH_BITS - 1:0] phase_r = 0;
always @ (posedge clk) begin
case(data_in_buff[ITERATIONS])
2'b00:begin phase_r <= $signed(z[ITERATIONS]); end
2'b01:begin phase_r <= $signed(z[ITERATIONS]); end
2'b10:begin phase_r <= $signed(z[ITERATIONS]) + $signed(PHASE_COE); end
2'b11:begin phase_r <= $signed(z[ITERATIONS]) - $signed(PHASE_COE); end
endcase
Modulus[XY_BITS:0] <= x[ITERATIONS];
end
assign Modulus_buf = (Modulus * 32'd39797)>>15;
assign x_o = Modulus_buf[XY_BITS-1:0];
assign y_o = y[ITERATIONS];
assign phase_out = phase_r;
end
endgenerate
reg [ITERATIONS+1:0] v = 0;
always @ (posedge clk) begin
if (RST)
v <= 0;
else begin
v <= v << 1;
v[0] <= valid_in;
end
end
assign valid_out = v[ITERATIONS+1];
endmodule

11
vlog/parse_test/instance_test.v Normal file
View File

@ -0,0 +1,11 @@
`include "./Cordic.v"
module instance_test (
input input_a,
input input_b,
output output_c
);
assign output_c = input_a & input_b;
endmodule

80
vlog/parse_test/mult_module.v Normal file
View File

@ -0,0 +1,80 @@
// template
module template #(
parameter INPUT_WIDTH = 12,
parameter OUTPUT_WIDTH = 12
)(
input [INPUT_WIDTH
- 1 : 0]data_in,
output reg clk_in = (INPUT_WIDTH -
OUTPUT_WIDTH) ,
clk=9'hd0,
input rst_n, RST,
output [OUTPUT_WIDTH - 1 : 0] data_out
);
endmodule //template
module test # (
parameter INPUT_WIDTH = 12,
parameter OUTPUT_WIDTH = 12
)(
input clk_in,
input rst_n,
input [INPUT_WIDTH - 1 : 0] data_in ,
input [3:2] dasta_ff,
output reg signed [OUTPUT_WIDTH - 1 : 0] data_out,
output reg signed [OUTPUT_WIDTH - 1 : 0] data_ff
);
wire valid_out;
Cordic #(
.XY_BITS ( 12 ),
.PH_BITS ( 32 ),
.ITERATIONS ( 32 ),
.CORDIC_STYLE ( "ROTATE" ),
.PHASE_ACC ( "ON" ))
u_Cordic(
//input
.clk_in ( clk_in ),
.RST ( RST ),
.x_i ( x_i ),
.y_i ( y_i ),
.phase_in ( phase_in ),
.valid_in ( valid_in ),
//output
.x_o ( x_o ),
.y_o ( y_o ),
.phase_out ( phase_out ),
.valid_out ( valid_out )
//inout
);
wire [3 : 0] count_high;
wire [3 : 0] count_low;
wire over;
template u_template(
//input
.clk ( clk ),
.data ( data ),
.en ( en ),
.load ( load ),
.rst ( rst ),
.switch ( switch ),
//output
.count_high ( count_high ),
.count_low ( count_low ),
.over ( over )
//inout
);
endmodule //test

35
vlog/wavedrom_test/sample.v Normal file
View File

@ -0,0 +1,35 @@
module dependence_1 (
input a, b, c,
output Q
);
// a & b | ((b & c) & (b | c))
// &=*, |=+ AB + BC(B+C)
// Distribute AB + BBC + BCC
// Simplify AA = A AB + BC + BC
// Simplify A + A = A AB + BC
// Factor B(A+C)
assign Q = a & (b | c);
endmodule
`include "adwada"
`define main dwwds
`define ada wss
/*
*/
`main
module dependence_2 (
input a, b, c,
output Q
);
assign Q = a & b | ((b & c) & (b | c));
endmodule