81 lines
2.3 KiB
Verilog
81 lines
2.3 KiB
Verilog
// template
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module template #(
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parameter INPUT_WIDTH = 12,
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parameter OUTPUT_WIDTH = 12
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)(
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input [INPUT_WIDTH
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- 1 : 0]data_in,
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output reg clk_in = (INPUT_WIDTH -
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OUTPUT_WIDTH) ,
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clk=9'hd0,
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input rst_n, RST,
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output [OUTPUT_WIDTH - 1 : 0] data_out
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);
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endmodule //template
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module test # (
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parameter INPUT_WIDTH = 12,
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parameter OUTPUT_WIDTH = 12
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)(
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input clk_in,
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input rst_n,
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input [INPUT_WIDTH - 1 : 0] data_in ,
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input [3:2] dasta_ff,
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output reg signed [OUTPUT_WIDTH - 1 : 0] data_out,
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output reg signed [OUTPUT_WIDTH - 1 : 0] data_ff
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);
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wire valid_out;
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Cordic #(
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.XY_BITS ( 12 ),
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.PH_BITS ( 32 ),
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.ITERATIONS ( 32 ),
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.CORDIC_STYLE ( "ROTATE" ),
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.PHASE_ACC ( "ON" ))
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u_Cordic(
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//input
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.clk_in ( clk_in ),
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.RST ( RST ),
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.x_i ( x_i ),
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.y_i ( y_i ),
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.phase_in ( phase_in ),
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.valid_in ( valid_in ),
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//output
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.x_o ( x_o ),
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.y_o ( y_o ),
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.phase_out ( phase_out ),
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.valid_out ( valid_out )
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//inout
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);
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wire [3 : 0] count_high;
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wire [3 : 0] count_low;
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wire over;
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template u_template(
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//input
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.clk ( clk ),
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.data ( data ),
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.en ( en ),
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.load ( load ),
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.rst ( rst ),
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.switch ( switch ),
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//output
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.count_high ( count_high ),
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.count_low ( count_low ),
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.over ( over )
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//inout
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);
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endmodule //test
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