38 lines
932 B
VHDL
38 lines
932 B
VHDL
library IEEE;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity forloop is port(
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reset, sysclk : in std_logic
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);
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end forloop;
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architecture rtl of forloop is
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signal selection : std_logic;
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signal egg_timer : std_logic_vector(6 downto 0);
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begin
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TIMERS :
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process(reset, sysclk)
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variable timer_var : integer;
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variable a, i, j, k : integer;
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variable zz5 : std_logic_vector(31 downto 0);
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variable zz : std_logic_vector(511 downto 0);
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begin
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if reset = '1' then
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selection <= '1';
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timer_var := 2;
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egg_timer <= (others => '0');
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elsif sysclk'event and sysclk = '1' then
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-- pulse only lasts for once cycle
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selection <= '0';
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egg_timer <= (others => '1');
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for i in 0 to j*k loop
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a := a + i;
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for k in a-9 downto -14 loop
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zz5 := zz(31+k downto k);
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end loop; -- k
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end loop; -- i
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end if;
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end process;
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end rtl;
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