47 lines
1.4 KiB
VHDL
47 lines
1.4 KiB
VHDL
library IEEE;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity expr is
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generic(SIZE: positive:=2**8-1);
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port(reset, sysclk, ival : in std_logic);
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end expr;
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architecture rtl of expr is
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constant SIZE_OF : positive:=2**8-1;
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signal foo : std_logic_vector(13 downto 0);
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signal baz : std_logic_vector(2 downto 0);
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signal bam : std_logic_vector(22 downto 0);
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signal out_i : std_logic_vector(5 downto 3);
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signal input_status : std_logic_vector(8 downto 0);
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signal enable, debug, aux, outy, dv, value : std_logic;
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signal expo : std_logic_vector(2**3-1 downto 0);
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begin
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-- drive input status
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input_status <= -- top bits
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(foo(9 downto 4) &
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(( (baz(2 downto 0) and foo(3 downto 0)) or
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(not baz(2 downto 0) and bam(3 downto 0)))));
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-- drive based on foo
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out_i(4) <=
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-- if secondary enabl is set then drive aux out
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(enable and (aux xor outy)) or
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-- if debug is enabled
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(debug and dv and not enable) or
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-- otherwise we drive reg
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(not debug and not enable and value);
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-- not drive
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pfoo: process(reset, sysclk)
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begin
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if( reset /= '0' ) then
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foo <= (others => '0');
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elsif( sysclk'event and sysclk = '0' ) then
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foo(3*(2-1)) <= baz(1*(1+2)-2);
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bam(foo'range) <= foo;
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end if;
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end process;
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expo <= std_logic_vector(to_unsigned(2**4, 2**8));
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end rtl;
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