16 lines
378 B
VHDL
16 lines
378 B
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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entity based is port (sysclk : in std_logic);
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end based;
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architecture rtl of based is
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signal foo, foo1, foo2, foo8, foo10, foo11, foo16 : integer;
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begin
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foo <= 123;
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foo1 <= 123_456;
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foo2 <= 2#00101101110111#;
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foo8 <= 8#0177362#;
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foo10 <= 10#01234#;
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--foo11<= 11#01234#;
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foo16 <= 16#12af#;
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end rtl; |