14 lines
293 B
VHDL
14 lines
293 B
VHDL
-- VHDL code for a 2-to-1 multiplexer
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity mux2to1 is
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port(a, b : in std_logic;
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sel : in std_logic;
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outp : out std_logic);
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end mux2to1;
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architecture behavioral of mux2to1 is
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begin
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outp <= a when sel = '0' else b;
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end behavioral; |