11 lines
389 B
Verilog
11 lines
389 B
Verilog
module formatter_vlog #(
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parameter INPUT_WIDTH = 12,
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parameter OUTPUT_WIDTH = 12
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) (
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input clk_in,
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input rst_n,
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input [INPUT_WIDTH - 1 : 0]data_in,
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output [OUTPUT_WIDTH - 1 : 0]data_out
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);
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reg [3:0] cnt; always @(posedge clk_in or posedge rst_n) begin if(rst_n) begin cnt<=4'h0; end else begin cnt<=cnt+4'h1; end end endmodule //module_name
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