53 lines
1.2 KiB
VHDL
53 lines
1.2 KiB
VHDL
LIBRARY IEEE;
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USE IEEE.std_logic_1164.all;
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entity forgen is
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generic(
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bus_width : integer := 15;
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TOP_GP2 : integer:= 0
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);
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port(
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sysclk, reset, wrb : in std_logic;
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din : in std_logic_vector(bus_width downto 0);
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rdout: out std_logic_vector(bus_width downto 0)
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);
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end forgen;
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architecture rtl of forgen is
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component wbit1 -- register bit default 1
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port(
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clk : in std_logic;
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wrb : in std_logic;
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reset : in std_logic;
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enb : in std_logic;
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din : in std_logic;
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dout : out std_logic);
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end component;
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signal regSelect : std_logic_vector(bus_width * 2 downto 0);
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begin
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-----------------------------------------------------
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-- Reg : GP 2
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-- Active : 32
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-- Type : RW
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-----------------------------------------------------
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reg_gp2 : for bitnum in 0 to bus_width generate
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wbit1_inst : wbit1
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PORT MAP(
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clk => sysclk,
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wrb => wrb,
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reset => reset,
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enb => regSelect(TOP_GP2),
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din => din(bitnum),
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dout => rdout(bitnum)
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);
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end generate;
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process(sysclk) begin
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if sysclk'event and sysclk = '1' then
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regSelect(1) <= '1';
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end if;
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end process;
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end rtl;
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