59 lines
1.5 KiB
Verilog
59 lines
1.5 KiB
Verilog
module fsm_test(
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input clock,
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input reset,
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input [2 : 0] req_0,
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input [2 : 0] req_1,
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output reg [2 : 0] gnt_0,
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output reg [2 : 0] gnt_1
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);
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reg [2:0] state;
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parameter IDLE = 3'h1;
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parameter GNT0 = 3'd2;
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parameter GNT1 = 3'b100;
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always @ (posedge clock) begin : FSM
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if (reset == 1'b1) begin
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state <= #1 IDLE;
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gnt_0 <= 0;
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gnt_1 <= 0;
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end
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else
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case(state)
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IDLE :
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if (req_0 == 1'b1) begin
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state <= #1 GNT0;
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gnt_0 <= 1;
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end
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else if (req_1 == 1'b1) begin
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gnt_1 <= 1;
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state <= #1 GNT1;
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end
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else begin
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state <= #1 IDLE; //example comment
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end
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GNT0 :
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if (req_0 == 1'b1) begin
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state <= #1 GNT0;
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end
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else begin
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gnt_0 <= 0;
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state <= #1 IDLE;
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end
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GNT1 :
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if (req_1 == 1'b1) begin
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state <= #1 GNT1;
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end
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else begin
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gnt_1 <= 0;
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state <= #1 IDLE;
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end
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default :
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state <= #1 IDLE;
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endcase
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end
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endmodule //module_name
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