37 lines
867 B
VHDL
37 lines
867 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity mem is
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generic(
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addr_width : integer := 6;
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bus_width : integer := 14
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);
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port (
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clk : in std_logic;
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rstn : in std_logic; -- not implemented
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en : in std_logic;
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cs : in std_logic; -- not implemented
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addr : in unsigned(addr_width-1 downto 0);
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din : in unsigned(bus_width-1 downto 0);
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dout : out unsigned(bus_width-1 downto 0)
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);
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end entity;
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architecture rtl of mem is
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signal al : unsigned(addr_width-1 downto 0) := X"00";
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type mem_Type is array (255 downto 0) of unsigned(bus_width-1 downto 0);
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signal mem : mem_Type;
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begin
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dout <= mem(to_integer(al));
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process (clk) is
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begin
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if rising_edge(clk) then
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al <= addr;
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if en = '1' then
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mem(to_integer(addr)) <= din;
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end if;
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end if;
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end process;
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end architecture;
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