33 lines
926 B
VHDL
33 lines
926 B
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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entity partselect is
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port(
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clk_i : in std_logic
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);
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end entity partselect;
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architecture rtl of partselect is
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signal big_sig : std_logic_vector(31 downto 0);
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signal lit_sig : std_logic_vector(0 to 31);
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signal i : integer:=8;
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begin
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test_i: process(clk_i)
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variable big_var : std_logic_vector(31 downto 0);
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variable lit_var : std_logic_vector(0 to 31);
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variable j : integer;
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begin
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if rising_edge(clk_i) then
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big_sig(31 downto 24) <= big_sig(7 downto 0);
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big_var(31 downto 24) := big_var(7 downto 0);
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lit_sig(i*3 to i*3+7) <= lit_sig(0 to 7);
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lit_var(j*3 to j*3+8) := lit_var(j*0 to 8+j*0);
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--
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big_sig(i*3+8 downto i*3) <= big_sig(8 downto 0);
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big_var(j*3+8 downto j*3) := big_var(j*0+8 downto j*0);
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end if;
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end process test_i;
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end architecture rtl;
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