22 lines
441 B
VHDL
22 lines
441 B
VHDL
-- Nearly useless stub, it's here to support generate.vhd
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LIBRARY IEEE;
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USE IEEE.std_logic_1164.all;
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entity wbit1 is
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port(
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clk : in std_logic;
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wrb : in std_logic;
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reset : in std_logic;
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enb : in std_logic;
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din : in std_logic;
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dout : out std_logic);
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end;
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architecture rtl of wbit1 is
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signal foo : std_logic;
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begin
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process(clk) begin
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dout <= '1';
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end process;
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end rtl;
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