35 lines
1.2 KiB
VHDL
35 lines
1.2 KiB
VHDL
LIBRARY IEEE;
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USE IEEE.std_logic_1164.all, IEEE.numeric_std.all;
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entity withselect is
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generic(
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dog_width : std_logic_vector(7 downto 0) := "10101100";
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bus_width : integer := 32
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);
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port( reset, sysclk : in std_logic;
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a, b, enf, load, qtd, base: in std_logic_vector(bus_width downto 0)
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);
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end withselect;
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architecture rtl of withselect is
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signal foo : std_logic_vector(1+1 downto 0);
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signal code,code1: std_logic_vector(9 downto 0);
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signal egg : std_logic_vector(324 to 401);
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signal baz : std_logic_vector(bus_width*3-1 to bus_width*4);
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signal complex : std_logic_vector(31 downto 0);
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begin
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-- Example of with statement
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with foo(2 downto 0) select
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code(9 downto 2) <= "110" & egg(325 to 329) when "000" | "110",
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"11100010" when "101",
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(others => '1') when "010",
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(others => '0') when "011",
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std_logic_vector(unsigned(a) + unsigned(b)) when others;
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code1(1 downto 0) <= a(6 downto 5) xor (a(4) & b(6));
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foo <= (others => '0');
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egg <= (others => '0');
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baz <= (others => '1');
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complex <= enf & (std_logic_vector("110" * unsigned(load))) & qtd(3 downto 0) & base & "11001";
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end rtl;
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