16 lines
292 B
VHDL
16 lines
292 B
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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entity Scientific is
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generic (
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exp1: integer := 25e6;
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exp2: integer := 25E6;
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exp3: real := 25.0e6;
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exp4: real := 50.0e+3;
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exp5: real := 50.0e-3
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);
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port(
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clk : in std_logic
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);
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end Scientific;
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