37 lines
1.0 KiB
VHDL
37 lines
1.0 KiB
VHDL
LIBRARY IEEE;
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USE IEEE.std_logic_1164.all;
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entity clk is port( reset, preset, qreset, sysclk, dsysclk, esysclk : in std_logic;
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ival : in std_logic_vector(31 downto 0)
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);
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end clk;
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architecture rtl of clk is
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signal foo : std_logic_vector(10+3 downto 0);
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signal baz : std_logic_vector(2 downto 0);
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signal egg : std_logic_vector(4 to 7-1);
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begin
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pfoo: process(reset, sysclk)
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begin
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if( reset /= '0' ) then
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foo <= (others => '1');
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elsif( sysclk'event and sysclk = '1' ) then
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foo <= ival(31 downto 31-(10+3));
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end if;
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end process;
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pbaz: process(preset, dsysclk)
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begin
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if( preset /= '1' ) then
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baz <= (others => '0');
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elsif( dsysclk'event and dsysclk = '0' ) then
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baz <= ival(2 downto 0);
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end if;
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end process;
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pegg: process(qreset, esysclk)
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begin
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if( qreset /= '1' ) then
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egg <= (others => '0');
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elsif( esysclk'event and esysclk = '0' ) then
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egg <= ival(6 downto 4);
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end if;
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end process;
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end rtl;
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