27 lines
553 B
VHDL
27 lines
553 B
VHDL
LIBRARY IEEE;
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USE IEEE.std_logic_1164.all;
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entity ifchain is port(
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clk, rstn : in std_logic
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);
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end ifchain;
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architecture rtl of ifchain is
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type t is array (3 downto 0) of std_logic_vector(31 downto 0);
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signal a : std_logic_vector(3 downto 0);
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signal b : std_logic_vector(3 downto 0);
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signal status : std_logic;
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signal c : t;
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begin
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process(clk) begin
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if clk'event and clk = '1' then
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if b(1) & a(3 downto 2) = "001" then
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status <= '1';
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c(0) <= x"FFFFFFFF";
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end if;
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end if;
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end process;
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end rtl;
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