37 lines
923 B
VHDL
37 lines
923 B
VHDL
LIBRARY IEEE;
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USE IEEE.std_logic_1164.all;
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USE IEEE.numeric_std.all;
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entity ifchain2 is port(
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clk, rstn : in std_logic;
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enable: in std_logic;
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result: out std_logic
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);
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end ifchain2;
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architecture rtl of ifchain2 is
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signal counter : unsigned(3 downto 0);
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constant CLK_DIV_VAL : unsigned(3 downto 0) := to_unsigned(11,4);
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begin
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clk_src : process(clk, rstn) is
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begin
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if (rstn = '0') then
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counter <= (others => '0');
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result <= '0';
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elsif (rising_edge(clk)) then -- Divide by 2 by default
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if (enable = '1') then
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if (counter = 0) then
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counter <= CLK_DIV_VAL;
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result <= '1';
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else
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counter <= counter - 1;
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result <= '0';
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end if; -- counter
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end if; -- enable
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end if; -- clk, rst_n
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end process clk_src;
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assert (counter < CLK_DIV_VAL) report "test case" severity error;
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end rtl;
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